201216160 六、發明說明： 【發明所屬之技#f領域】 [0001] 本發明涉及一種電腦系統及電腦系統的開機方法，尤其 涉及一種具有至少兩個BIOS (Basic Input-Output System *基本輸入輸出系統）記憶體的電腦系統及電腦 系統的開機方法。 【先前技術】 [0002] BIOS存儲有電腦等電子設備在出廠時寫在其主板上記憶 體（Memory)中的程式*該程式是主板上的動體（ O Firmware )，作為硬體與作業系統間相互溝通的橋樑， 通過B10 S可設定電子設備的系統操作機制與硬體的相關 參數*該BIOS中主要存放與電腦相關且重要的基本輸入 輸出程式、系統資訊設置、開機自我測試（POST)和系 統啟動開機程式（Bootstrap)等。而BIOS通常存儲於 對應的BIOS記憶體内，當電腦開機時，中央處理器 (Central processing unit, .CPU)即調用BIOS 記憶 體内存儲的相關程式，並依次執行該調用出來的程式。 〇 然，當BIOS記憶體内存儲的相關程式因病毒侵害發生缺 損或毁壞時，使用者無法自動恢復BIOS記憶體内存儲的 程式，該電腦系統將無法正常運行，或者下次使用時， 該電腦系統將無法啟動，而需要將該主機送回出廠處進 行維修，或者更換一塊新的主板，使用不便。 【發明内容】 [0003] 鑒於以上内容，有必要提供一種能夠自動恢復BIOS記憶 體内存儲的程式的電腦系統。 099134988 表單編號A0101 第3頁/共16頁 0992061071-0 201216160 [0004] 另，還有必要提供一種電腦系統的開機方法。 [0005] 種％腦系統，包括CPU、基板管理控制器、主Bi〇s記憶 體及輔BIOS記憶體，輔BIOS記憶體内存儲有與主bi〇Sb 隐體内存儲的相同的BIOS程式，cpu調用並運行主 記憶體内存儲的程式，CPU運行調用的程式過程中向基板 B理控制發送回饋訊號，用以指示B I 程式的正常運 行基板管理控制器根據接收到的回饋訊號，判斷是否 需要將輔BIOS記憶體内存儲的程式覆蓋主BI〇s記憶體内 存健的程式，以恢復主BI:〇S記憶體内存儲的程式，cpu再 調用並運行恢復後的主B10 S記憶體内存儲的程式。 [0006] 一種電腦系統的開機方法’其包括以下步驟：提供一種 電腦系統，包括基板管理控制器、主BI〇s記憶體、輔 BIOSs己憶體及CPU，基板管理控制器包括核心晶片及BMc 5己憶體，主BIOS記憶體與輔BIOS記憶體内儲存有相同的 程式’ CPU調用並運行主BIOS記憶體内存儲的程式時，依 次向核心晶片發送第一回饋訊號、第二回饋訊號與第三 回饋訊號，核心晶片對應第一丨回饋訊號、第二回饋訊號 及第三回饋訊號分別預設有對應的時間間隔；CPU調用並 運行主BIOS記憶體内存儲的程式，並向核心晶片發送回 饋訊號；核心晶片判斷是否超過預設的時間間隔仍未接 收到對應的回饋訊號；及若超過預設的時間間隔仍未接 收到對應的回饋訊號，核心晶片利用輔BIOS記憶體内存 儲的程式恢復主BIOS記憶體内存儲的程式，並返回至CPU 調用並運行主BIOS記憶體内存儲的程式，並向核心晶片 發送回饋訊號這一步驟。 099134988 表單蝙號A0101 第4頁/共16頁 0992061071-0 201216160 [0007]本發明電腦系統，其通過基板管理控制器檢測Cpu從主 BIOS記憶體内調用的程式是否運行正常，若檢測到異常 ’及時利用辅BIOS記憶體内存儲的程式恢復主BIOS記憶 體内存儲的程式，而無須人工手動恢復81〇3程式，使用 方便，且有效保證電腦系統正常開機、運行。 【實施方式】 [0008] Ο [0009]201216160 VI. Description of the Invention: [Technical Fields of the Invention] [0001] The present invention relates to a computer system and a computer system booting method, and more particularly to a BIOS (Basic Input-Output System * Basic Input Output System) The computer system of the memory and the boot method of the computer system. [Prior Art] [0002] The BIOS stores a program written on the memory of a motherboard such as a computer such as a computer. * The program is a firmware on the motherboard (O Firmware) as a hardware and operating system. Bridges that communicate with each other, through B10 S can set the system operation mechanism of electronic equipment and hardware related parameters. * The BIOS mainly stores computer-related and important basic input and output programs, system information settings, and power-on self-test (POST). And the system starts the boot program (Bootstrap) and so on. The BIOS is usually stored in the corresponding BIOS memory. When the computer is turned on, the Central Processing Unit (.CPU) calls the relevant program stored in the BIOS memory and executes the called program in turn. Suddenly, when the relevant program stored in the BIOS memory is damaged or destroyed due to virus damage, the user cannot automatically restore the program stored in the BIOS memory, the computer system will not operate normally, or the computer will be used the next time. The system will not be able to start, but the host needs to be sent back to the factory for repair, or a new motherboard can be replaced, which is inconvenient to use. SUMMARY OF THE INVENTION [0003] In view of the above, it is necessary to provide a computer system capable of automatically restoring a program stored in a BIOS memory. 099134988 Form No. A0101 Page 3 of 16 0992061071-0 201216160 [0004] In addition, it is necessary to provide a boot method for the computer system. [0005] The % brain system includes a CPU, a substrate management controller, a main Bi〇s memory, and a secondary BIOS memory, and the secondary BIOS memory stores the same BIOS program stored in the main bi〇Sb. The cpu calls and runs the program stored in the main memory, and the CPU runs the called program to send a feedback signal to the substrate B control to indicate the normal operation of the BI program. The baseboard management controller determines whether it needs to be based on the received feedback signal. The program stored in the secondary BIOS memory overwrites the main BI〇s memory memory to restore the program stored in the main BI:〇S memory, and the cpu calls and runs the restored main B10 S memory storage. Program. [0006] A computer system booting method includes the following steps: providing a computer system including a substrate management controller, a main BI〇s memory, a secondary BIOS, and a CPU, and the substrate management controller includes a core chip and a BMc 5 Recall, the main BIOS memory and the secondary BIOS memory store the same program 'CPU call and run the program stored in the main BIOS memory, in turn send the first feedback signal, the second feedback signal to the core chip and The third feedback signal, the core chip corresponding to the first feedback signal, the second feedback signal and the third feedback signal are respectively preset with corresponding time intervals; the CPU calls and runs the program stored in the main BIOS memory, and sends the program to the core chip. The feedback signal is received; the core chip determines whether the corresponding feedback signal has not been received after the preset time interval; and if the corresponding feedback signal is not received after the preset time interval, the core chip uses the program stored in the secondary BIOS memory. Restore the program stored in the main BIOS memory, and return to the CPU to call and run the program stored in the main BIOS memory, and The core chip sends a feedback signal step. 099134988 Form bat number A0101 Page 4 / Total 16 page 0992061071-0 201216160 [0007] The computer system of the present invention detects whether the program called by the CPU from the main BIOS memory is normal through the baseboard management controller, and if an abnormality is detected' Timely use the program stored in the secondary BIOS memory to restore the program stored in the main BIOS memory, without manual manual recovery of the 81〇3 program, convenient to use, and effectively ensure that the computer system is normally turned on and running. [Embodiment] [0008] Ο [0009]
請參考圖1，本發明電腦系統1〇〇包括基板管理控制器 (Baseboard Management Controller ， BMC)l〇 、主 BIOS記憶體30、輔BIOS記馋體4〇及CPU60。主BIOS記憶 體30與輔BIOS記憶體40内均儲存有相同的BIOS程式， CPU60調用主BIOS記憶體30内儲存的程式，.並運行調用 的程式’同時向基板管理控制器10發送指示BI0S程式正 常運行的回饋訊號，基板管理控制器1〇根據接收到的回 饋訊號，判斷是否需要將輔BIOS記憶體40内存儲的程式 覆蓋主BIOS s己憶體30内存儲的程式’以恢復主Bl〇s記情 體30内存儲的程式。 ' ~ 基板管理控制器10内設有梭心畢片11及BMC記憶體13。 該核心晶片11選擇性的連接至主BIOS記憶體30與辅Bl〇s 記憶體40。當核心晶片11連接至輔BIOS記憶體40時，核 心晶片11將讀取輔BIOS記憶體40内存儲的程式，並存错 於BMC記憶體13内。當核心晶片11連接至主BIOS記憶體 30内時，核心晶片11將BMC記憶體13内存儲的裎式寫入 主BIOS記憶體30内，以恢復主BIOS記憶體30内存倚的程 式。該核心晶片11還連接至CPU60，接收CPU60發送的1 號，並對應CPU60發送的訊號預設有時間間隔《若該 099134988 表單編號A0101 第5頁/共16頁 0"2〇61〇71,〇 201216160 晶片11超過預設的時間間隔仍未接收到CPU60發送的對應 的訊號’核心晶片11將實現輔^㈨記憶體4〇内存儲的程 式後盖主BIOS6己憶體30内存儲的輕式。於本發明實施方 式中’該基板管理控制器1〇内還設有連接至CpU6〇的通信 接口 15 ’以實現與CPU60的通信。 [0010] 於本發明實施方式中’主BIOS記憶體30與輔BIOS記憶體 40内存儲的程式相同，且主bios記憶體30内存儲的程式 供CPU60調用’以通過CPU60運行其内存儲的程式，輔 BIOS記憶體40内存儲的程式用以恢復主BIOS記憶體30内 .... ... ......； 存儲的程式。該主BIOS記憶體30與輔BIOS記憶體40内均 儲存有BIOS初始化、BIOS設置以及系統引導三大模組的 程式。 [0011] 於本發明實施方式中，電腦系統100還包括連接至核心晶 片11的開關模組50，該開關模組50具有初始狀態以及應 急狀態兩種狀態’並在核心晶片11的控制下於上述兩種 狀態下切換。於本發明實施方式中，該開關模組50為多 路類比開關組，包括第一開關51、第二開關53及第三開 關5 5。第一開關51連接至主B10S記憶體30與核心晶片11 ，並在核心晶片11的控制下選擇的連接至CPU60或者第二 開關53。第二開關53連接至第三開關55與核心晶片π， 並在核心晶片11的控制下選擇的連接至輔BIOS記憶體40 或者第一開關51。第三開關5 5連接至核心晶片11，並在 核心晶片11的控制下選擇的連接至BMC記憶體1 3或者第二 開關5 3。當開關模組5 0處於初始狀態時，第一開關51將 主BIOS記憶體30連接至CPU60，供CPU60調用主BIOS記 099134988 表單編號A0101 第6頁/共16頁 0992061071-0 201216160 憶體30内存儲的程式’此時第二開關53斷開與輔bios記 憶體40連接，第三開關55斷開與BMC記憶體13連接。當 開關模組50處於應急狀態時’第三開關55將連接至第二 開關53 ’以通過第二開關53連接至辅^〇5記憶體4〇，以 便核心晶片11讀取輔B10S記憶體4 〇内存儲的程式，並將 其存儲於BMC s己憶體13内。然後該核心晶片11再控制第三 開關55將BMC記憶體13通過第三開關、第二開關53及 第一開關51連接至主BIOS記憶體3〇，以將BMC記憶體13 内存儲的程式覆蓋主BIOS記憶體3〇内存儲的程式。Referring to FIG. 1, the computer system 1 of the present invention includes a Baseboard Management Controller (BMC), a main BIOS memory 30, a secondary BIOS, and a CPU 60. The main BIOS memory 30 and the secondary BIOS memory 40 both store the same BIOS program, and the CPU 60 calls the program stored in the main BIOS memory 30, and runs the called program 'to send the instruction BIOS program to the substrate management controller 10 at the same time. The normal operation feedback signal, the substrate management controller 1 determines, according to the received feedback signal, whether the program stored in the secondary BIOS memory 40 needs to be overwritten by the program stored in the main BIOS s memory 30 to restore the main B1. s The program stored in the modal 30. The substrate management controller 10 is provided with a bobbin sheet 11 and a BMC memory 13. The core wafer 11 is selectively coupled to the main BIOS memory 30 and the secondary Bls memory 40. When the core chip 11 is connected to the secondary BIOS memory 40, the core wafer 11 reads the program stored in the secondary BIOS memory 40 and stores it in the BMC memory 13. When the core chip 11 is connected to the main BIOS memory 30, the core chip 11 writes the 存储 stored in the BMC memory 13 into the main BIOS memory 30 to restore the memory of the main BIOS memory 30. The core chip 11 is also connected to the CPU 60, receives the number 1 sent by the CPU 60, and corresponds to the signal pre-set time interval sent by the CPU 60. "If the 099134988 form number A0101 page 5 / a total of 16 pages 0" 2〇61〇71, 〇 201216160 The wafer 11 has not received the corresponding signal sent by the CPU 60 for more than a preset time interval. The core chip 11 will realize the light stored in the program stored in the secondary memory 6 of the secondary memory. In the embodiment of the present invention, the base station management controller 1 is also provided with a communication interface 15' connected to the CpU6's to implement communication with the CPU 60. [0010] In the embodiment of the present invention, the main BIOS memory 30 is the same as the program stored in the secondary BIOS memory 40, and the program stored in the main bios memory 30 is called by the CPU 60 to run the program stored in the CPU 60. The program stored in the auxiliary BIOS memory 40 is used to restore the main BIOS memory 30................ The stored program. Both the main BIOS memory 30 and the secondary BIOS memory 40 store programs for BIOS initialization, BIOS setup, and system booting. [0011] In the embodiment of the present invention, the computer system 100 further includes a switch module 50 connected to the core wafer 11, the switch module 50 having two states of an initial state and an emergency state, and under the control of the core wafer 11 Switch between the above two states. In the embodiment of the present invention, the switch module 50 is a multi-channel analog switch group, and includes a first switch 51, a second switch 53, and a third switch 55. The first switch 51 is connected to the main B10S memory 30 and the core wafer 11, and is selectively connected to the CPU 60 or the second switch 53 under the control of the core wafer 11. The second switch 53 is connected to the third switch 55 and the core wafer π, and is selectively connected to the secondary BIOS memory 40 or the first switch 51 under the control of the core wafer 11. The third switch 55 is connected to the core wafer 11 and is selectively connected to the BMC memory 13 or the second switch 53 under the control of the core wafer 11. When the switch module 50 is in the initial state, the first switch 51 connects the main BIOS memory 30 to the CPU 60 for the CPU 60 to call the main BIOS record 099134988 Form No. A0101 Page 6 / Total 16 Page 0992061071-0 201216160 Recall within the body 30 The stored program 'At this time, the second switch 53 is disconnected from the auxiliary bios memory 40, and the third switch 55 is disconnected from the BMC memory 13. When the switch module 50 is in an emergency state, the 'third switch 55 will be connected to the second switch 53' to be connected to the auxiliary memory 4 through the second switch 53, so that the core wafer 11 reads the auxiliary B10S memory 4 The program stored in the file is stored in the BMC s memory file 13. Then, the core chip 11 controls the third switch 55 to connect the BMC memory 13 to the main BIOS memory 3 through the third switch, the second switch 53, and the first switch 51 to overwrite the program stored in the BMC memory 13. The program stored in the main BIOS memory.
[0012] CPU60調用並運行主BIOS記憶體30内存儲的程式，且運 行過程中’CPU60還不斷向基板管理控制器1〇發送回饋訊 號，以便基板管理控制器10判斷ΒΙ〇》程式是否正常運行 。於本發明實施方式中，由於主81〇3記憶體3〇内存儲的 BIOS程式包括BIOS初始化、Bl〇s設置以及系統引導三大 模組的程式，是以CPU60運行每广模組程今的過程中均會 向基板管理控制器10發送不同的回饋訊號。具體為：CPU Q 運行完ΒΙ〇ΜΛ始化這_模組後，向基板管理控制器10發 送第一回饋sfl號，CPU於運行Bios設置過程中，每隔預設 的時間間隔均向基板管理控制器1〇發送第二回饋訊號； B10S完成系統引導後，CPU60向基板管理控制器1 〇發送 第三回饋訊號。另，若用戶未進入BIOS設置，貝JCPU60 將不會運行BIOS設置這一模組，相應的CPU6〇也不會向 基板管理控制器10發送第二回館訊號。 [0013] 於本發明實施方式中’基板管理控制器1〇對應第一自饋 訊號、第二回饋訊號與第三回饋訊號分別預設一第—時 099134988 表單編號A0101 第7頁/共16頁 0992061071-0 201216160 間間隔第二時間間隔與第三時間間隔。若基板管理控制 器1 〇自開啟直至預設的第一時間間隔仍未接收到第一回 饋訊號，或者接收第一回饋訊號後超過三個及以上的第 二時間間隔仍未接收到第二回饋訊號，同時也未接收到 第三回饋訊號，基板管理控制器10將判斷CPU運行BIOS 程式時異常，將實現輔BIOS記憶體40内存儲的程式覆蓋 主BIOS記憶體30存儲的程式。 [0014] 於本發明實施方式中，該電腦系統100還包括南橋晶片70 。南橋晶片70用以建立CPU60與基板管理控制器10及主 BIOS記憶體30之間的連接。具體為：南橋晶片70通過通 信接口 15實現CPU60與核心晶片11之間的通信，並通過 第一開關51實現CPU60與主BIOS30之間的通信，以便 CPU60調用主BIOS30内存儲的程式。 [0015] 請一併參閱圖2，該電腦系統100開機時，其包括以下步 驟： [0016] S1 :啟動電腦系統100内的各組件。 [0017] S2 : CPU60調用並運行主BIOS記憶體30内存儲的程式， 並向核心晶片11發送回饋訊號。於本步驟中，CPU60運行 每一階段的程式均分別向核心晶片11發送不同的回饋訊 號。 [0018] S3 :核心晶片11判斷是否超過預設的時間間隔仍未接收 到對應的回饋訊號。具體為，核心晶片11判斷自開機後 是否超過預設的第一時間間隔仍未接收到第一回饋訊號 ，或者接收第一回饋訊號後超過三個及以上的第二時間 099134988 表單編號A0101 第8頁/共16頁 0992061071-0 201216160 [0019] 間隔仍未接收到第二回饋訊號，同時也未接收到第=回 饋訊號，若否，說明未超時，則進入步驟S4，若是，戈 明調用並運行的61卯程式出現異常，將進入步驟％。 S4 .核心晶片11判斷接收到的回饋訊號類型。若接收到 的回饋訊號為第一回饋訊號或者第二回饋訊號，列返回 梦驟S3 ’若接收到的回饋訊號為第三回饋訊號，則社束 。因為若核心晶片11接收到第三回馈訊號，說明CPU60已 運行元系統引導部分程式，相應的電腦系統1 〇 〇正常開機 〇 〇 [0020] S5 :核心晶片11讀取輔BIOS記憶體40内存儲的程式，並 將其存儲於BMC記憶體13内。 [0021] S6 :核心晶片11將BMC記憶體13内存儲的程式覆蓋主 BIOS記憶體30内存儲的程式，並返回至步驟S2。具體為 :核心晶片11將BMC記憶體13内存儲的程式覆蓋主biOS 記憶體30内已破損的程式，從而恢復主BIOS記憶體3〇内 存儲的程式。 〇 η [0022] 於本發明實施方式中，步驟仍與86中’核心晶片11將控 制開關模組50進入應急狀態’而完成步驟S5與S6後，核 心晶片11將控制開關模組50恢復至初始狀態。 [0023] 本發明電腦系統1〇〇，其通過基板管理控制器10檢測 CPU60從主BIOS記憶體30内調用的程式是否運行正常， 若檢測到異常，及時利用輔BI0S記憶體40内存儲的程式 恢復主BIOS記憶體30内存儲的程式’而無須人工手動恢 復BIOS程式，使用方便，且有效保證電腦系統正常開機 099134988 表單編號A0101 第9頁/共16頁 0992061071-0 201216160 、運行。 [0024] 综上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0025] 圖1是本發明實施方式電腦系統的功能框圖。 [0026] 圖2是圖1所示電腦系統開機的方法流程圖。 【主要元件符號說明】 [0027] 電腦系統：1 0 0 [0028] 基板管理控制器：10 [0029] 核心晶片：11 [0030] BMC記憶體：13 [0031] 通信接口 ： 15 [0032] 主BIOS記憶體：30 [0033] 輔BIOS記憶體：40 [0034] 開關模組：50 [0035] 第一開關：51 [0036] 第二開關：53 [0037] 第三開關：55 [0038] CPU ： 60 099134988 表單編號A0101 第10頁/共16頁 0992061071-0 201216160 [0039] 南橋晶片：70 〇[0012] The CPU 60 calls and runs the program stored in the main BIOS memory 30, and during the running process, the CPU 60 continuously sends a feedback signal to the substrate management controller 1 to enable the baseboard management controller 10 to determine whether the program is running normally. . In the embodiment of the present invention, since the BIOS program stored in the main 81〇3 memory 3 includes BIOS initialization, Bls setting, and system booting three modules, the CPU 60 runs every wide module. Different feedback signals are sent to the substrate management controller 10 during the process. Specifically, after the CPU Q runs the initialization module, the first feedback sfl number is sent to the substrate management controller 10, and the CPU manages the substrate every preset time interval during the running Bios setting process. The controller 1 transmits a second feedback signal; after the B10S completes the system boot, the CPU 60 sends a third feedback signal to the baseboard management controller 1 . In addition, if the user does not enter the BIOS setting, the JCPU60 will not run the BIOS setup module, and the corresponding CPU6 will not send the second logback signal to the baseboard management controller 10. [0013] In the embodiment of the present invention, the substrate management controller 1 corresponding to the first self-feed signal, the second feedback signal, and the third feedback signal respectively preset a first time - 099134988 form number A0101 page 7 / total 16 pages 0992061071-0 201216160 Interval Second time interval and third time interval. If the substrate management controller 1 does not receive the first feedback signal until the preset first time interval, or does not receive the second feedback after the first time feedback signal exceeds three or more second time intervals The signal does not receive the third feedback signal, and the baseboard management controller 10 determines that the CPU is running the BIOS program abnormally, and implements the program stored in the secondary BIOS memory 40 to overwrite the program stored in the main BIOS memory 30. [0014] In the embodiment of the present invention, the computer system 100 further includes a south bridge wafer 70. The south bridge wafer 70 is used to establish a connection between the CPU 60 and the substrate management controller 10 and the main BIOS memory 30. Specifically, the south bridge chip 70 realizes communication between the CPU 60 and the core chip 11 through the communication interface 15, and realizes communication between the CPU 60 and the main BIOS 30 through the first switch 51, so that the CPU 60 calls the program stored in the main BIOS 30. [0015] Please refer to FIG. 2 together. When the computer system 100 is powered on, it includes the following steps: [0016] S1: Start each component in the computer system 100. [0017] S2: The CPU 60 calls and runs the program stored in the main BIOS memory 30, and sends a feedback signal to the core wafer 11. In this step, the CPU 60 runs each stage of the program to send different feedback signals to the core chip 11, respectively. [0018] S3: The core chip 11 determines whether the corresponding feedback signal has not been received for more than a preset time interval. Specifically, the core chip 11 determines whether the first feedback signal has not been received after the preset first time interval, or more than three or more times after receiving the first feedback signal. 099134988 Form No. A0101 No. 8 Page / Total 16 pages 0992061071-0 201216160 [0019] The second feedback signal has not been received yet, and the == feedback signal has not been received. If not, it means that it has not timed out, then it goes to step S4, and if so, Gemin calls And the 61卯 program that runs is abnormal and will go to step %. S4. The core chip 11 determines the type of feedback signal received. If the received feedback signal is the first feedback signal or the second feedback signal, the column returns to the dream S3 ’. If the received feedback signal is the third feedback signal, the community is bundled. Because if the core chip 11 receives the third feedback signal, the CPU 60 has run the meta system boot part program, and the corresponding computer system 1 is normally turned on. [0020] S5: The core chip 11 reads the auxiliary BIOS memory 40 for storage. The program is stored in the BMC memory 13. [0021] S6: The core wafer 11 overwrites the program stored in the main BIOS memory 30 with the program stored in the BMC memory 13, and returns to step S2. Specifically, the core chip 11 overwrites the program stored in the BMC memory 13 with the program stored in the main biOS memory 30, thereby restoring the program stored in the main BIOS memory 3. In the embodiment of the present invention, after the steps S5 and S6 are completed, the core wafer 11 restores the control switch module 50 to the core chip 11 after the step S5 and S6 are completed. Initial state. [0023] The computer system of the present invention detects whether the program called from the main BIOS memory 30 by the CPU 60 is operating normally by the substrate management controller 10. If an abnormality is detected, the program stored in the secondary BIOS memory 40 is used in time. Restore the program stored in the main BIOS memory 30 without manual manual recovery of the BIOS program, easy to use, and effectively ensure that the computer system is normally turned on 099134988 Form No. A0101 Page 9 / Total 16 Page 0992061071-0 201216160, run. [0024] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0025] FIG. 1 is a functional block diagram of a computer system according to an embodiment of the present invention. 2 is a flow chart of a method for booting the computer system shown in FIG. 1. [Main component symbol description] [0027] Computer system: 1 0 0 [0028] Baseboard management controller: 10 [0029] Core chip: 11 [0030] BMC memory: 13 [0031] Communication interface: 15 [0032] Main BIOS Memory: 30 [0033] Secondary BIOS Memory: 40 [0034] Switch Module: 50 [0035] First Switch: 51 [0036] Second Switch: 53 [0037] Third Switch: 55 [0038] CPU : 60 099134988 Form No. A0101 Page 10 / Total 16 Page 0992061071-0 201216160 [0039] South Bridge Wafer: 70 〇
099134988 表單編號A0101099134988 Form number A0101
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