201214576 AU0911054 35600twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電晶體及其製造方法，且特別是 有關於一種薄膜電晶體及其製造方法。 【先前技術】 近來環保意識抬頭，具有低消耗功率、空間利用效率 佳、無骑、高畫質等優越特性的平面顯示面板_此卿 panels)已成為市場线。常見的平峨示^包括液晶顯示201214576 AU0911054 35600twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to an electro-optical crystal and a method of manufacturing the same, and more particularly to a thin film transistor and a method of manufacturing the same. [Prior Art] Recently, the environmental awareness has risen, and the flat display panel with low power consumption, good space utilization efficiency, no riding, high image quality, etc. has become a market line. Common flat display ^ including liquid crystal display
器(liquid crystal displays)、電漿顯示器(plasma 卿咖）、 有機電激發光顯示器（electr〇iuminescent出印丨㈣等。以目 前最為普及騎晶顯示ϋ為例，其主要是㈣膜電晶體陣 列基板、彩色濾光基板以及夾於二者之間的液晶層所構 ^在習知的薄膜電晶體陣列基板上，多採用非晶石夕㈣) 薄膜電晶體或低溫多晶梦薄膜電晶體作為各個子晝素的切 換元件。近年來，[有研究指Λ氧化物半導體(〇佩 second論Γ)薄膜電晶體相較於非晶石夕薄膜電晶體，具有 較南的載子移動率(mGbilit)〇，而氧化物半導體薄膜電晶體 相較於低溫多㈣薄膜電晶體，則具有較佳的臨界電壓 (threshold voltage，Vth).^ ^ 〇 0,b , + ^ 電晶體有潛力成為下—代平面顯示器之關鍵元件。 在習知的氧化物半導體薄獏電晶體中，1 f二會受到紫外光照射(例峨 外在认）而產生偏移，進而影響職化物半導體薄膜電 201214576 …， * A 054 35600twf.doc/n 晶體的電性，因此已有習知技術提出採用具有紫外光遮蔽 效果之氧化鈦(TiOx)作為閘絕緣層或保護層之材質，以避 免氧化物通道層之臨界電壓偏移的問題。閘絕緣層或保護 層是全面性地覆蓋於薄膜電晶體陣列基板上。 圖1A至圖1F為習知氧化物半導體薄膜電晶體之製造 流程剖面示意圖。請依序參考圖1A至圖1F，首先於基板 100上形成閘極102，如圖1A所示。接著，於基板1〇〇上 形成閘絕緣層104以覆蓋閘極102,如圖1B所示，。然後， 於閘絕緣層104上形成通道層丨〇6，如圖1C所示。接著， 於基板100上依序形成材料層1〇8與金屬層11〇，並覆蓋 通道層106’如圖1D所示。然後，圖案化金屬層11〇以形 成源極SI#以及汲極D，並暴露出部份材料層1〇8，如圖m 所示。接著，對暴露出的部份材料層！〇8進行氧化(〇xidati〇n) 以形成-紫外光遮_案1G8a，如圖1F所示。此紫外光遮 蔽圖案108a位於通道層1〇6上，當有紫外光入射時可對通 道層1〇6形成保護作用，使通道層106不易受到紫外光之 影響，進較得氧化物轉體薄膜電晶體之電性維持穩定。 然而，在習知的氧化物半導體薄膜電晶體製程中^ 往因為材料層1G8的厚度過厚而導致被源極S與沒極D 所暴露出的部份材料層⑽未能被完全地氧化(如圖㈣ 不）’進而造成氧化物半導體薄膜電晶體發生漏電流或其 =不、右為避免上述問題而降低材料層i。 膜厚、 Ϊ導===性㈣細;祕會變差，而導致氧二 丰賴電曰曰體之良率不佳。承上述，如何兼顧氧化物 201214576 AU〇y 11054 35600twf.doc/n 實為研發者所欲解 半導體薄膜電晶體之電性以及其良率 決的問題之一。 【發明内容】 膜電晶體之量產 本發明提供一種薄膜電晶體，其具有穩定之電性。 本發明提供一種薄膜電晶體的製造方法，其有助於薄(liquid crystal displays), plasma display (plasma), organic electroluminescent display (electr〇iuminescent printing 丨 (4), etc.. The most popular riding crystal display ϋ as an example, which is mainly (four) membrane transistor array The substrate, the color filter substrate, and the liquid crystal layer sandwiched therebetween are formed on a conventional thin film transistor array substrate, and an amorphous (4) thin film transistor or a low temperature polycrystalline dream thin film transistor is often used as the substrate. The switching element of each sub-tenk. In recent years, [there is a study that the oxide semiconductor (〇佩second Γ) thin film transistor has a souther carrier mobility (mGbilit) 〇, and an oxide semiconductor film compared to an amorphous slab transistor. Compared with low temperature (four) thin film transistors, the transistor has a better threshold voltage (Vth). ^ ^ 〇 0, b , + ^ The transistor has the potential to become a key component of the lower-generation flat panel display. In a conventional oxide semiconductor thin germanium transistor, 1 f 2 is exposed to ultraviolet light (except for external recognition), which causes an offset, thereby affecting the semiconductor film power 201214576 ..., * A 054 35600twf.doc/ n The electrical properties of the crystal. Therefore, it has been proposed in the prior art to use titanium oxide (TiOx) having an ultraviolet shielding effect as a material for the gate insulating layer or the protective layer to avoid the problem of the threshold voltage shift of the oxide channel layer. The gate insulating layer or protective layer is entirely overlying the thin film transistor array substrate. 1A to 1F are schematic cross-sectional views showing a manufacturing process of a conventional oxide semiconductor thin film transistor. Referring to FIG. 1A to FIG. 1F in sequence, a gate 102 is first formed on the substrate 100 as shown in FIG. 1A. Next, a gate insulating layer 104 is formed on the substrate 1 to cover the gate 102 as shown in Fig. 1B. Then, a channel layer 丨〇6 is formed on the gate insulating layer 104 as shown in FIG. 1C. Next, a material layer 1〇8 and a metal layer 11〇 are sequentially formed on the substrate 100, and the channel layer 106' is covered as shown in FIG. 1D. Then, the metal layer 11 is patterned to form the source electrode SI# and the drain electrode D, and a portion of the material layer 1〇8 is exposed, as shown in Fig. m. Then, on the exposed part of the material layer! 〇8 is oxidized (〇xidati〇n) to form - ultraviolet light-mask 1G8a, as shown in Fig. 1F. The ultraviolet light shielding pattern 108a is located on the channel layer 1〇6, and can protect the channel layer 1〇6 when ultraviolet light is incident, so that the channel layer 106 is not easily affected by ultraviolet light, and the oxide conversion film is obtained. The electrical properties of the transistor remain stable. However, in the conventional oxide semiconductor thin film transistor process, the portion of the material layer (10) exposed by the source S and the gate D is not completely oxidized because the thickness of the material layer 1G8 is too thick ( As shown in Fig. 4 (not), the oxide semiconductor thin film transistor is caused to leak current or it is not, and the material layer i is lowered to avoid the above problem. The film thickness, Ϊ conduction === sex (four) fine; the secret will be worse, resulting in poor yield of oxygen bismuth. In view of the above, how to balance oxides 201214576 AU〇y 11054 35600twf.doc/n is one of the problems that developers need to solve for the electrical properties of semiconductor thin film transistors and their yield. SUMMARY OF THE INVENTION The present invention provides a thin film transistor having stable electrical properties. The invention provides a method for manufacturing a thin film transistor, which contributes to thin
本發明提供一種薄膜電晶體的製造方法，其包括：於 基板上形朗極。接著，於紐上形朗崎層以覆蓋問 極。然後，於閘絕緣層上形成彼此電性絕緣之源極與沒極。 =後，於閘極上方之閘絕緣層上形成氧化物半導體層以覆 蓋閘絕緣層、源極與汲極。接著，於氧化物半導體層上形 成材料層。然後，薄化材料層。之後，令材料層氧^以於 ^化物半導體層上形成紫外光遮蔽材料層。最後，圖案化 紫外光遮蔽材料層以及氧化物半導體層以形成氧化物通道 層與紫外光遮蔽圖案，其中氧化物通道層覆蓋源極之部分 區域與没極之部分區域，而紫外光遮蔽圖案位於氧化物通 道層上。 本發明提供一種薄膜電晶體，其包括閘極、閉絕緣 層、源極、汲極、氧化物通道層以及紫外光遮蔽圖案。其 中’閘絕緣層覆蓋閘極。源極與汲極配置於閘絕緣層上且 彼此電性絕緣。氧化物通道層配置於閘絕緣層、源極以及 沒極上。紫外光遮蔽圖案位於氧化物通道層上，且紫外光 遮蔽圖案僅覆蓋氧化物通道層，未覆蓋氧化物通道層之側 201214576 ς *·—-. 054 35600twf.doc/n 在本發明的一實施例中，前述之氧化物半導體層之材 質包括氧化銦鎵鋅PGZO)、氧化銦辞(IZ〇)、氧化銦鎵 PGO)、氧化錫(ZnO)，氧化鎘.氧化鍺(2Cd〇.Ge〇2)或氧化 鎳始(NiCo2〇4)。 在本發明的一實施例中，前述之材料層之材質包括 鈦、石夕、鋁或鋅》 在本發明的一實施例中，前述之紫外光遮蔽材料層之 材質包括氧化鈦(TiOx)、富矽氧化矽(Si_rich Si〇x)、氧化 矽(SiOx)、氧化鋁(Ai〇x)或氧化鋅(Ζη〇χ)。 在本發明的一實施例中，前述之氧化鈦(Ti〇x)包括一 氧化鈦(Ti〇)、二氧化鈦(Ti〇2)、五氧化三鈦(Ti3〇5)、一氧 化二鈦(Ti2〇)。 在本發明的一實施例中，前述之材料層的厚度介於25 埃至500埃之間，薄化後之材料層的厚度約為介於1〇埃至 150埃之間，而紫外光遮蔽材料層之厚度介於2〇埃至3⑻ 埃之間。 ' 在本發明的一實施例中，前述之材料層的厚度介於5〇 埃至150埃之間，薄化後之材料層的厚度約為介於埃至 100埃之間’而紫外光遮蔽材料層之厚度介於50埃至2〇〇 埃之間β ' 在本發明的一實施例中，前述之圖案化紫外光遮蔽材 料層以及氧化物半導體層的方法包括：以乾蝕刻製程移除 部分紫外光遮蔽材料層以形成紫外光遮蔽圖案，之後，以 濕钱刻製程移除未被紫外光遮蔽圖案覆蓋之氧化物丰導 層以形成氧化物通道層。 201214576 AU〇yil054 35600tvvf.doc/n 在本發明的一實施例中’前述之形成紫外光遮蔽圖案 的方法包括利用六氟化硫(SF6)對紫外光遮蔽材料層進行 等向性钱刻。 在本發明的一實施例中，前述之紫外光遮蔽材料層之 厚度介於20埃至300埃之間。 本發明之薄膜電晶體具有穩定的電氣特性，且本發明 之製造方法與現有製程相容，有利於薄膜電晶體之量產。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 ，2A至圖為本實施例之薄膜電晶體製造流程剖 面不意圖。首先，請參照圖2A，於基板上形一閑極 2。在本實施例巾，基板細的材質例如為玻璃、石英、 =口物不透光/反射材料(如導電材料、晶圓、陶究 疋其它合適的材料。在本實施例中，閘極2G2之材料 你丨1疋使用金屬材料。然’本發明不限於此，在其他實施 金屬之材料也可以使用其他導電材料，如合金、 化物V:厶凰2物、金屬材料的氧化物、金屬材料的氮氧 物或疋金屬材料與其它導材料的堆疊層。 請2B，於基板·上全面性地形成問絕 之二202。在本實施例中，_緣層_ 無機介電材料（如氧切、—、氮氧化 —一種材料的堆疊層）、有機介電材料或上述 2〇1214576ϋ54 35600twf.doc/n 有機與無機介電材料之組合。 接著請參照圖2C，於閘絕緣層204上形成源極s，與 汲極D’。源極S’與汲極D，係彼此電性絕緣，並且覆蓋於 部分的閘絕緣層204上。本實施例之源極s’與汲極d，分別 位於部分的閘極202之上。在本實施例中，源極s，與汲極 D之材料一般是使用金屬材料。然，本發明不限於此在 其他實施例中，源極S’與汲極D，之材料也可以使用其他導 電材料，如合金、金屬材料的氮化物、金屬材料的氧化物、 金屬材料的氮氧化物或是金屬材料與其它導電材料的堆疊 層。 接著請參照圖2D，於閘極202上方之閘絕緣層2〇4 上形成氧化物半導體層206以覆蓋部分的閘絕緣層2〇4、 源極S與沒極D’。在本實施例中，氧化物半導體層 之材料例如為氧化銦鎵鋅(IGZO)、氧化銦鋅(IZ〇)、氧化銦 鎵(IGO)、氧化錫(ZnO)、氧化鎘、氧化鍺(2Cd〇.Ge〇2)、 氧化鎳録(NiC〇2〇4)或其他適當材料，但本發明不以此為限。 接著凊參照圖2E，於氧化物半導體層2〇6上全面性地 形成材料層208。本實施例之材料層2〇8的厚度G例如是 介於25埃至500埃之間，而材料層2〇8的厚度G較佳是 介於50埃至150埃之間。值得一提的是，由於材料層2〇8 的厚度G不低於25埃’因此材料層2〇8不易出現膜厚均 勻性不佳的情況。在本實施例中，材料層观之材質例如 為鈦、梦、IS、鋅或其他適當金屬材料，但本發明不以此 為限。值得注意的是，材料層2G8之材質必須是氧化後具 備紫外光遮蔽功能之材質。 201214576 auwi i054 35600twf.doc/n 接著請參照圖2F，對材料層鹰進行薄化製程， 化製程可以是姓刻製程、化學機械研磨製程仰啦㈣ Mechanical Polishing，CMP)或其他能約減少材料層2〇8之 厚度的難。在本實施射，薄化後之材制⑽厚产d 例如是介於10埃至15G埃之間，而薄化後之材料層^ 的厚度d較佳是介於25埃至刚埃之i在本實施例中， 薄化材料層2G8的方法例如為利用六氟化硫(SF6)對材料 層208進行等向性蝕刻以使其厚度G減少。然，本發明不 限於此，在其他可行實關巾，亦可细其 化材料層208。 得 接著請參照圖2G ’使材料層2〇8氧化以於氧化物半 導體層206上形成紫外光遮蔽材料層島。在本實施例 中’紫外光遮蔽材料層208a之厚度d，例如是介於2〇埃至 300埃之間，而紫外光遮蔽材料層2〇8a之厚度y較佳是介 =0埃至200埃之間。值得一提的是，因為在材料層施 被氧化之前，材料層駕的厚度已經被減少& d，所 化後之材料層208十分容易被氧化，而形成一氧化完全且 組成穩定之紫外光遮蔽材料層烏。在本實施例中， 光遮蔽材料層208a之材質例如為氧化鈦(Ti〇x)、富石夕氧化 石夕(Si-rich SiOx)、氧切(Si〇x)、氧化雖1〇χ)、氧化辞 (ZnOx)或其他適當材料。其中，氧化鈦(Ti〇x)包括一氧 化鈦⑽）、二氧化鈦⑽2)、五氧化三鈦(Ή迎）、一氧化 二鈦(Τι20)，但本發明不以此為限。 接者請參照圖2Η’圖案化紫外光遮蔽材料層職及 氧化物半導體層206以分別形成氧化物通道層施與紫外 201214576 -J4 35600twf.doc/n 光遮蔽圖案208b。其中，氧化物通道層206a覆蓋源極§， 之部分區域與沒極D’之部分區域’而紫外光遮蔽圖案2〇8b 位於氧化物通道層206a上。在本實施例中，圖案化紫外光 遮蔽材料層208a的方法例如是先利用乾钱刻製程移除部 分紫外光遮蔽材料層208a以形成紫外光遮蔽圖案2〇8b， 或者是利用六氟化硫(SF6)對紫外光遮蔽材料層2〇8a進行 等向性蝕刻以形成紫外光遮蔽圖案208b。在本實施例中， 圖案化氧化物半導體層206的方法例如為利用濕姓刻製程. 移除未被紫外光遮蔽圖案208b覆蓋之氧化物半導體層2〇6 以形成氧化物通道層206a。然，本發明之氧化物通道層 2〇6a與紫外光遮蔽圖案208b的形成方法不限於上述，在 其他可行的實施例中，亦可利用其他適當方法圖案化紫外 光遮蔽材料層208a以及氧化物半導體層206。 從圖2H可知，由於紫外光遮蔽圖案2〇8b不與源極s， 與汲極D’直接接觸，因此紫外光遮蔽圖案2〇8b不容易導 致習知的漏電流現象。 在完成紫外光遮蔽圖案208b以及氧化物通道層2〇6a 的製作之後，便完成了本實施例之薄膜電晶體之製作。 由圖2H可清楚得知，本實施例之薄膜電晶體包括間 極202、閘絕緣層204、源極s，、錄D，、氧化物通道層 206a及紫外光遮蔽圖案2〇8b’其中閘絕緣層2〇4覆蓋閘極 202，源極S’與汲極D’配置於閘絕緣層2〇4上且彼此電性 絕緣，氧化物通道層206a配置於部份閘絕緣層2〇4、邙俨 源極S’以及部紐極D，上。此外，料光遮蔽圖案^b 配置於氧化物通道層206a上。 10 201214576The present invention provides a method of fabricating a thin film transistor, comprising: forming a ridge on a substrate. Next, the upper layer is formed on the ridge to cover the question. Then, a source and a gate which are electrically insulated from each other are formed on the gate insulating layer. After the oxide semiconductor layer is formed on the gate insulating layer above the gate to cover the gate insulating layer, the source and the drain. Next, a material layer is formed on the oxide semiconductor layer. Then, the material layer is thinned. Thereafter, the material layer is made to form an ultraviolet light shielding material layer on the chemical semiconductor layer. Finally, the ultraviolet light shielding material layer and the oxide semiconductor layer are patterned to form an oxide channel layer and an ultraviolet light shielding pattern, wherein the oxide channel layer covers a partial region of the source and a portion of the electrodeless region, and the ultraviolet light shielding pattern is located On the oxide channel layer. The present invention provides a thin film transistor comprising a gate, a closed insulating layer, a source, a drain, an oxide channel layer, and an ultraviolet light shielding pattern. The 'gate insulation layer covers the gate. The source and the drain are disposed on the gate insulating layer and electrically insulated from each other. The oxide channel layer is disposed on the gate insulating layer, the source, and the gate. The ultraviolet light shielding pattern is located on the oxide channel layer, and the ultraviolet light shielding pattern covers only the oxide channel layer, and the side of the oxide channel layer is not covered 201214576 ς *·--. 054 35600 twf.doc/n In an implementation of the present invention In the example, the material of the oxide semiconductor layer includes indium gallium zinc oxide (PGZO), indium oxide (IZ〇), indium gallium oxide (PGO), tin oxide (ZnO), cadmium oxide, and cerium oxide (2Cd〇.Ge〇). 2) or the beginning of nickel oxide (NiCo2〇4). In an embodiment of the invention, the material of the material layer comprises titanium, stellite, aluminum or zinc. In an embodiment of the invention, the material of the ultraviolet shielding material layer comprises titanium oxide (TiOx), Anthracene-rich cerium oxide (Si_rich Si〇x), cerium oxide (SiOx), aluminum oxide (Ai〇x) or zinc oxide (Ζη〇χ). In an embodiment of the invention, the titanium oxide (Ti〇x) comprises titanium oxide (Ti〇), titanium dioxide (Ti〇2), titanium trioxide (Ti3〇5), and titanium oxide (Ti2). 〇). In an embodiment of the invention, the thickness of the material layer is between 25 angstroms and 500 angstroms, and the thickness of the thinned material layer is between about 1 angstrom and 150 angstroms, and the ultraviolet light is shielded. The thickness of the material layer is between 2 angstroms and 3 (8) angstroms. In an embodiment of the invention, the thickness of the material layer is between 5 Å and 150 Å, and the thickness of the thinned material layer is between about angstrom and 100 angstroms. The thickness of the material layer is between 50 Å and 2 Å. In an embodiment of the invention, the method for patterning the ultraviolet light shielding material layer and the oxide semiconductor layer includes: removing by a dry etching process A portion of the ultraviolet light shielding material layer is formed to form an ultraviolet light shielding pattern, and then the oxide diffusion layer not covered by the ultraviolet light shielding pattern is removed by a wet etching process to form an oxide channel layer. 201214576 AU〇yil054 35600tvvf.doc/n In an embodiment of the invention, the aforementioned method of forming an ultraviolet light shielding pattern comprises performing an isotropic burn on a layer of the ultraviolet light shielding material using sulfur hexafluoride (SF6). In an embodiment of the invention, the thickness of the ultraviolet light shielding material layer is between 20 angstroms and 300 angstroms. The thin film transistor of the present invention has stable electrical characteristics, and the manufacturing method of the present invention is compatible with the prior art process, which is advantageous for mass production of the thin film transistor. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] 2A to Fig. is a schematic cross-sectional view showing a manufacturing process of the thin film transistor of the present embodiment. First, referring to FIG. 2A, a dummy pole 2 is formed on the substrate. In the towel of the embodiment, the material of the substrate is, for example, glass, quartz, or opaque/reflective material (such as conductive material, wafer, ceramics, other suitable materials. In this embodiment, the gate 2G2 The material of the material is used by you. However, the invention is not limited thereto, and other conductive materials such as alloys, compounds V: phoenix 2, oxides of metal materials, metal materials may be used for materials of other metal implementations. a layer of oxynitride or bismuth metal material and other conductive materials. 2B, comprehensively formed on the substrate · 202. In this embodiment, _ edge layer _ inorganic dielectric material (such as oxygen Cutting, -, oxynitridation - a layer of a material), an organic dielectric material or a combination of the above 2, 1214, 576, 54, 35, 600 twf.doc / n organic and inorganic dielectric materials. Referring now to Figure 2C, formed on the gate insulating layer 204 The source s, and the drain D'. The source S' and the drain D are electrically insulated from each other and cover a portion of the gate insulating layer 204. The source s' and the drain d of the embodiment respectively Located above a portion of the gate 202. In this embodiment The material of the source s and the drain D is generally a metal material. However, the invention is not limited thereto. In other embodiments, the source S' and the drain D may be made of other conductive materials such as an alloy. a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials. Referring next to FIG. 2D, on the gate insulating layer 2〇4 above the gate 202 The oxide semiconductor layer 206 is formed to cover a portion of the gate insulating layer 2〇4, the source S and the gate D′. In the embodiment, the material of the oxide semiconductor layer is, for example, indium gallium zinc oxide (IGZO) or indium oxide. Zinc (IZ〇), indium gallium oxide (IGO), tin oxide (ZnO), cadmium oxide, antimony oxide (2Cd〇.Ge〇2), nickel oxide (NiC〇2〇4) or other suitable materials, but The invention is not limited thereto. Next, referring to FIG. 2E, the material layer 208 is formed integrally on the oxide semiconductor layer 2〇6. The thickness G of the material layer 2〇8 of the present embodiment is, for example, 25 Å to 500 Å. Between the angstroms, the thickness G of the material layer 2 〇 8 is preferably between 50 angstroms and 150 angstroms. Therefore, since the thickness G of the material layer 2〇8 is not less than 25 angstroms, the material layer 2〇8 is less likely to have a poor uniformity of the film thickness. In the embodiment, the material of the material layer is, for example, titanium. Dream, IS, zinc or other suitable metal materials, but the invention is not limited thereto. It is worth noting that the material of the material layer 2G8 must be a material with ultraviolet light shielding after oxidation. 201214576 auwi i054 35600twf.doc/n Then, referring to FIG. 2F, the material layer eagle is thinned, and the process can be a process of surname engraving, mechanical polishing, or other reduction of the thickness of the material layer 2〇8. In the present embodiment, the thinned material (10) thick product d is, for example, between 10 angstroms and 15 angstroms, and the thickness d of the thinned material layer is preferably between 25 angstroms and angstroms. In the present embodiment, the method of thinning the material layer 2G8 is, for example, isotropic etching of the material layer 208 with sulfur hexafluoride (SF6) to reduce the thickness G thereof. However, the present invention is not limited thereto, and the material layer 208 may be finely formed in other feasible real towels. Next, please refer to Fig. 2G' to oxidize the material layer 2〇8 to form an ultraviolet light shielding material layer island on the oxide semiconductor layer 206. In the present embodiment, the thickness d of the ultraviolet shielding material layer 208a is, for example, between 2 Å and 300 Å, and the thickness y of the ultraviolet shielding material layer 2 〇 8a is preferably =0 Å to 200 Å. Between the ang. It is worth mentioning that because the thickness of the material layer has been reduced before the material layer is oxidized & d, the material layer 208 is easily oxidized to form a completely oxidized and stable ultraviolet light. The masking material layer is black. In the present embodiment, the material of the light shielding material layer 208a is, for example, titanium oxide (Ti〇x), Si-rich SiOx, oxygen-cut (Si〇x), and oxidation. Oxidation (ZnOx) or other suitable material. Among them, titanium oxide (Ti〇x) includes titanium oxide (10)), titanium oxide (10) 2), trititanium pentoxide, and titanium oxide, but the invention is not limited thereto. Referring to FIG. 2Η, the patterned ultraviolet shielding material layer and the oxide semiconductor layer 206 are respectively formed to form an oxide channel layer to be applied to the ultraviolet 201214576-J4 35600 twf.doc/n light shielding pattern 208b. Wherein, the oxide channel layer 206a covers a portion of the source §, and a portion of the region of the gate D', and the ultraviolet light shielding pattern 2〇8b is located on the oxide channel layer 206a. In this embodiment, the method for patterning the ultraviolet light shielding material layer 208a is, for example, first removing a portion of the ultraviolet light shielding material layer 208a by using a dry etching process to form an ultraviolet light shielding pattern 2〇8b, or using sulfur hexafluoride. (SF6) Anisotropic etching is performed on the ultraviolet light shielding material layer 2A8a to form an ultraviolet light shielding pattern 208b. In the present embodiment, the method of patterning the oxide semiconductor layer 206 is, for example, using a wet etching process. The oxide semiconductor layer 2〇6 not covered by the ultraviolet light shielding pattern 208b is removed to form the oxide channel layer 206a. The method for forming the oxide channel layer 2〇6a and the ultraviolet light shielding pattern 208b of the present invention is not limited to the above. In other feasible embodiments, the ultraviolet light shielding material layer 208a and the oxide may be patterned by other suitable methods. Semiconductor layer 206. As is apparent from Fig. 2H, since the ultraviolet light shielding pattern 2〇8b is not in direct contact with the source s and the drain D', the ultraviolet light shielding pattern 2〇8b does not easily cause a conventional leakage current phenomenon. After the fabrication of the ultraviolet light shielding pattern 208b and the oxide channel layer 2〇6a is completed, the fabrication of the thin film transistor of the present embodiment is completed. It can be clearly seen from FIG. 2H that the thin film transistor of the present embodiment includes the interpole 202, the gate insulating layer 204, the source s, the recording D, the oxide channel layer 206a, and the ultraviolet shielding pattern 2〇8b'. The insulating layer 2〇4 covers the gate 202, the source S′ and the drain D′ are disposed on the gate insulating layer 2〇4 and electrically insulated from each other, and the oxide channel layer 206a is disposed on the partial gate insulating layer 2〇4,邙俨 source S' and the part of the pole D, on. Further, the material light shielding pattern ^b is disposed on the oxide channel layer 206a. 10 201214576
Auuyix^54 35600twf.doc/n 需特別注意的是’紫外光遮蔽圖案208b僅覆蓋氧化 物通道層206a’而未覆蓋氧化物通道層之側壁2〇6t^在本 實施例中，紫外光遮蔽圖案2〇8b可有效地吸收外界的紫外 光二以保護位於其下之氧化物通道層2〇6a，因此本實施例 之薄膜電晶體不易受到外界的紫外光的影響而具有穩定的 電性。 綜上所述，本發明先形成一厚度較厚的材料層，使此Auuyix^54 35600twf.doc/n It is to be noted that the 'ultraviolet light shielding pattern 208b covers only the oxide channel layer 206a' and does not cover the sidewall of the oxide channel layer. In this embodiment, the ultraviolet light shielding pattern 2〇8b can effectively absorb the external ultraviolet light 2 to protect the underlying oxide channel layer 2〇6a. Therefore, the thin film transistor of the present embodiment is not easily affected by external ultraviolet light and has stable electrical properties. In summary, the present invention first forms a thicker layer of material to make this
材料^不易發生膜厚均勻性不佳關題，之後，再將此材 料層薄化’以使薄化後之材料層可於後續的製程中被氧化 而形成-氧化完全且組成穩定之料光遮㈣料層。前述 之紫外光賴材料層可降低料光對於氧化物通道層 響。 " 雖然本發明已以實施例揭露如上，然其並非用以 本發明，任何所倾術躺巾具有通f知識者，在 本發明之精神和範圍内，當可作些許之更動 發明之保護範圍當視_之申請專利範_=為^本 【圖式簡單說明】 知的氧化物铸體_電晶體製造 圖1A至圖1F為習 流程剖面示意圖。 實施例之薄膜電晶體製 圖2A至圖2H為本發明之— 造流程剖面示意圖。 薄膜電晶體剖面示意 圖2H為本發明之一實施例之 圖0 11 201214576^ 35600twf.doc/n 【主要元件符號說明】 100、200 :基板 102、202 :閘極 104、204 :閘絕緣層 106 :通道層 108、208 :材料層 108a、208 a :紫外光遮蔽材料層 110 :金屬層 206 :氧化物半導體層 206a :氧化物通道層 206b :側壁 208b :紫外光遮蔽圖案 S、S，：源極 D、D，：汲極 G、d、d’ ：厚度The material ^ is not prone to poor film thickness uniformity, and then the material layer is thinned 'so that the thinned material layer can be oxidized in a subsequent process to form - complete oxidation and stable composition Cover (four) material layer. The aforementioned layer of ultraviolet light raying material can reduce the layering of the material to the oxide channel. <Although the present invention has been disclosed above by way of example, it is not intended to be used in the present invention, and any of the draped drapes has the knowledge of the invention, and it is possible to make some modifications of the invention within the spirit and scope of the present invention. Scope of application _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Thin Film Transistor of the Embodiment FIG. 2A to FIG. 2H are schematic cross-sectional views showing the manufacturing process of the present invention. 2H is a schematic diagram of a thin film transistor. FIG. 1 is an embodiment of the present invention. FIG. 0 11 201214576^35600twf.doc/n [Description of main components] 100, 200: substrate 102, 202: gate 104, 204: gate insulating layer 106: Channel layer 108, 208: material layer 108a, 208a: ultraviolet light shielding material layer 110: metal layer 206: oxide semiconductor layer 206a: oxide channel layer 206b: sidewall 208b: ultraviolet light shielding pattern S, S, source D, D,: bungee G, d, d': thickness