201205437 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種伺服器系統。 【先前技術】 [0002] 先前之伺服器系統内大多有基板管理晶片（Baseboard Management Chip-BMC)，可以對伺服器進行管控、監 視。BMC自帶有一個嵌入式之軟體系統。在主機死機時， BMC仍然可以以自帶之軟體系統進行工作。先前之伺服器 系統死機之原因大多係由於基本輸入輸出系統（Bas i c Input Output System-BIOS)之崩潰或錯誤。此種狀 態下，雖然BMC可以保持運作並且監視到BIOS崩潰之情況 並加以記錄，但係對於B10 S之崩潰狀況只能袖手旁觀， 無能為力。 【發明内容】 [0003] 有鑒於此，有必要提供一種在伺服器死機之情況下仍可 對BIOS進行更新之伺服器系統。 [0004] 一種伺服器系統，其包括一個基板管理晶片（BMC)、一 個基本輸入輸出系統（BIOS)及一個智慧型平臺管理介 面（IPMI)。所述BMC包括一個第一片選訊號輸出端、一 個第一資料更新輸出端及一輸入控制端。所述IPMI包括 一個輸出控制端，所述BIOS包括一個片選訊號輸入端及 一個資料更新輸入端。所述伺服器系統進一步包括一個 雙工器。所述雙工器包括一個第一輸入端及一個資料更 新輸出端。所述雙工器之第一輸入端電性連接至所述BMC 之第一資料更新輸出端，所述雙工器之資料更新輸出端 099123443 表單編號A0101 第4頁/共15頁 0992041309-0 201205437 [0005] Ο [0006] ❹ _7] 099123443 電性連接至所述BIOS之資料更新輸入端。所述ΙΡΜΙ之輸 出控制端電性連接至所述BMC之輸入控制端❶所述BIOS之 片選訊號輸入端電性連接至所述BMC之第一片選訊號輸出 嶸。 相較於先前技術，當伺服器系統死機時，所述IPMI之輸 出控制端輸出一控制訊號至所述BMC之輸入控制端，以控 制所述BMC之第一片選訊號輸出端輸出一個片選訊號至所 述Bios之片選訊號輸入端’同時，所述BMC之第一資料更 新輪出端輸出一個更新訊號至所述雙工器之第一輸入端 ’並藉由所述雙；器之資料更新輪出端輪出至所述BI0S 之資料更新輸入端，以對所述bios進行資料更新。因此 ’本發明之伺服器系統在伺服器死機之情況下仍可藉由 BMC對BIOS進行更新。 【實施方式】 下面將結合附圖對本發明實施方式作進一步之詳細說明 .... !. 〇 .. 請參閱圖1 ’本發明提供之伺服器系統100，其包括一個 基板管理晶片（Baseboard Management Chip-BMC) 10、一個BMC記憶體20、一個基本輸入輸出系統（Basic Input Output System-BIOS) 30、一個智慧型平臺管 理介面（11^611丄叾6111?1以【0〇111|[&11&莒61116111：111- t erf ace-1 PM I ) 40、一個雙工器50及一個南橋晶片60 〇 戶斤述BMC 1 0用於對所述飼服器系統1 〇 〇中之各項設備（例 如中央處理器、硬碟裝置、電源供應器、網路連接設置 表單编號A0101 苐5頁/共15頁 0992041309-0 [0008] 201205437 等）進行管控及監視，其可獨立運行不必受控於作業系 統。所述BMC10包括一個第一片選訊號輸出端丨丨、一個第 二片選訊號輸出端12、一個第一資料更新輸出端11{)及— 輸入控制端112。 [0009] 所述BMC記憶體20用於記錄所述BMC1〇管控及監視到之所 述伺服益系統1 0 0中之各項設備之運行情況。當所述伺服 器系統100發生錯誤時，所述BMC記憶體20會記錄該事件 曰誌，例如，所述BIOS之崩潰之時間及原由。所述BMC記 憶體20包括一個第一片選訊號輸入端21及一個第一資料 更新輸入端22。所述第一片選訊號輸入端21電性連接至 所述BMC1 0之第二片選訊號輸出端12。所述第一資料更新 輸入端22電性連接至所述BMC10之第一資料更新輪出端 110 ° [0010] 所述BIOS30用於保存所述伺服器系統100之基本輸入輪 出之程式、系統設置資訊、開機上電自檢程式和系統啟 動自舉程式。所述BIOS30g括一個片選訊號輸入端31及 一個資料更新输入端32。所述片選訊號輸入端31電性連 接至所述BMC10之第一片選訊號輸出端11。 [0011] 所述IPMI40用於控制所述MC10之第一片選訊號輸出端 11或第二片選訊號輸出端12輸出片選訊號。所述ipm 140 包括一個輸出控制端41，所述輸出控制端41電性連接至 所述BMC10之輸入控制端112。 [0012] 所述雙工器50包括一個第一輸入端51、一個第二輸入端 52及一個資料更新輸出端53。所述第一輸入端51電性連 099123443 表單編號A0101 第6頁/共15頁 0992041309-0 201205437 [0013] [0014] Ο ο 接至所述BMC10之第〆資料更新輸出端110。所述資料更 新輸出端53電性連接矣所述30之資料更新輸入端32 所述南橋晶片60包括〆個第二資料更新輸出端61用於輸 出一個更新驅動訊號。所述第二資料更新輸出端61電性 連接至所述雙工器50之第二輸入端52。 請參閱圖2，為所述伺脈器系統1 00之第一工作狀態示意 圖。當正常更新所述祠服器系統1〇〇時’所述IPMI40之 輸出控制端41輸出一控制訊號至所述BMC1 0之輸入控制端 ........ . ... 112，以控制所述BMC10之第二片選訊號輸出端12輸出一 個片選訊號至所述BMC記憶體20之第一片選訊號輸入端21 ，所述BMC10之第一資料更新輸出端110輸出一個更新訊 號至所述第一資料更新輸入端22，以對所述BMC記憶體20 進行資料更新《而此時，所述南橋晶片之第二資料更 新輸出端61輸出一個更新驅動訊號至所述雙工器50之第 二輸入端52，並藉由所述雙工器50之資料更新輸出端53 輸出至所述BIOS30之所述資料更新輸入端32，以對所述 BIOS30進行資料更新.所述第二資料更新輸出端61電性 連接至所述雙工器50之第二輸入端52。 [0015] 二參閱囷3，當伺服器系統1〇〇死機時，所述南橋晶片60 停止工作。此時，所述IPMI4〇之輸出控制端41輸出一控 099123443 制訊號至所述BMC1〇之輸入控制端112，以控制所述 〇之第一片選訊號輪出端^輸出—個片選訊號至所述 次30之片選訊號輪入端31。同時，所述贏1〇之第一 貝料更新輸出端11〇輪出一個更新訊 表單編號A0101 第7頁/共15頁 號至所述雙工器50之 0992041309-0 201205437 第一輸入端51，並藉由所述雙工器50之資料更新輸出端 53輸出至所述BIOS30之所述資料更新輸入端32，以對所 述BIOS30進行資料更新。 [0016] 綜上所述，本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本 案技藝之人士爰依本發明之精神所作之等效修飾或變化 ，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0017] 圖1為本發明實施方式提供之伺服器系統之功能單元圖； [0018] 圖2為圖1之伺服器系統之第一工作狀態示意圖； [0019] 圖3為圖1之伺服器系統之第二工作狀態示意圖。 【主要元件符號說明】 [0020] 伺服器系統：1 0 0 [0021] BMC ： 10 [0022] BMC記憶體：20 [0023] BIOS ： 30 [0024] IPMI : 40 [0025] 雙工器：5 0 [0026] 南橋晶片：60 [0027] 第一片選訊號輸出端：1 1 [0028] 第二片選訊號輸出端：12 099123443 表單編號A0101 第8頁/共15頁 0992041309-0 110201205437201205437 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a server system. [Prior Art] [0002] Most of the previous server systems have a Baseboard Management Chip (BMC) that can be used for management and monitoring of the server. BMC comes with an embedded software system. When the host crashes, the BMC can still work with its own software system. The reason for the previous server system crash is mostly due to the crash or error of the Basic Input Output System (BIOS). In this state, although the BMC can keep running and monitor the BIOS crash and record it, it can only stand by and watch the collapse of the B10 S. SUMMARY OF THE INVENTION [0003] In view of the above, it is necessary to provide a server system that can still update the BIOS in the event of a server crash. A server system includes a substrate management chip (BMC), a basic input/output system (BIOS), and a smart platform management interface (IPMI). The BMC includes a first chip selection output, a first data update output, and an input control. The IPMI includes an output control terminal, and the BIOS includes a chip select signal input and a data update input. The server system further includes a duplexer. The duplexer includes a first input and a data update output. The first input end of the duplexer is electrically connected to the first data update output end of the BMC, and the data update output end of the duplexer is 099123443. Form No. A0101 Page 4 / Total 15 Page 0992041309-0 201205437 [0005] ❹ _7] 099123443 is electrically connected to the data update input of the BIOS. The output control terminal of the BMC is electrically connected to the input control terminal of the BMC, and the chip select signal input end of the BIOS is electrically connected to the first chip select signal output port of the BMC. Compared with the prior art, when the server system is dead, the output control terminal of the IPMI outputs a control signal to the input control end of the BMC to control the output of the first chip selection signal output of the BMC. Signaling to the chip select signal input end of the Bios, at the same time, the first data update round output end of the BMC outputs an update signal to the first input end of the duplexer and by the dual device The data update round is rotated out to the data update input of the BI0S to update the data of the bios. Therefore, the server system of the present invention can still update the BIOS by the BMC in the event of a server crash. [Embodiment] Hereinafter, embodiments of the present invention will be further described in detail with reference to the accompanying drawings.. Please refer to FIG. 1 'The server system 100 provided by the present invention includes a substrate management chip (Baseboard Management) Chip-BMC) 10. A BMC memory 20, a Basic Input Output System (BIOS) 30, a smart platform management interface (11^611丄叾6111?1 with [0〇111|[& ; 11 & 莒 61116111: 111- t erf ace-1 PM I ) 40, a duplexer 50 and a south bridge wafer 60 〇 斤 B BMC 1 0 for each of the feeding machine system 1 Equipment (such as central processing unit, hard disk device, power supply, network connection setting form number A0101 苐 5 pages / 15 pages 0992041309-0 [0008] 201205437, etc.) for control and monitoring, which can be operated independently Controlled by the operating system. The BMC 10 includes a first chip select signal output port, a second chip select signal output terminal 12, a first data update output terminal 11{), and an input control terminal 112. [0009] The BMC memory 20 is configured to record the operation of each device in the servo benefit system 100 that is controlled and monitored by the BMC1. When an error occurs in the server system 100, the BMC memory 20 records the event, for example, the time and cause of the BIOS crash. The BMC memory 20 includes a first chip select input 21 and a first data update input 22. The first chip select signal input terminal 21 is electrically connected to the second chip select signal output terminal 12 of the BMC 10. The first data update input terminal 22 is electrically connected to the first data update round-trip terminal 110 of the BMC 10. [0010] The BIOS 30 is configured to save a basic input round-off program and system of the server system 100. Set up information, power-on self-test and system bootloader. The BIOS 30g includes a chip select signal input terminal 31 and a data update input terminal 32. The chip select signal input terminal 31 is electrically connected to the first chip select signal output terminal 11 of the BMC 10. [0011] The IPMI 40 is configured to control the first chip select signal output terminal 11 or the second chip select signal output terminal 12 of the MC 10 to output a chip select signal. The ipm 140 includes an output control terminal 41, and the output control terminal 41 is electrically connected to the input control terminal 112 of the BMC 10. [0012] The duplexer 50 includes a first input terminal 51, a second input terminal 52, and a data update output terminal 53. The first input end 51 is electrically connected to the 099123443 form number A0101 page 6 / 15 pages 0992041309-0 201205437 [0014] [0014] ο ο connected to the second data update output end 110 of the BMC 10. The data update output 53 is electrically connected to the data update input 32 of the 30. The south bridge chip 60 includes a second data update output 61 for outputting an update drive signal. The second data update output 61 is electrically connected to the second input 52 of the duplexer 50. Please refer to FIG. 2, which is a schematic diagram of the first working state of the servo system 100. When the server system 1 is normally updated, the output control terminal 41 of the IPMI 40 outputs a control signal to the input control terminal of the BMC1 0. The second chip select signal output terminal 12 of the BMC 10 outputs a chip select signal to the first chip select signal input terminal 21 of the BMC memory 20, and the first data update output terminal 110 of the BMC 10 outputs an update signal. Up to the first data update input terminal 22 to perform data update on the BMC memory 20. At this time, the second data update output end 61 of the south bridge chip outputs an update drive signal to the duplexer. The second input terminal 52 of the 50 is output to the data update input terminal 32 of the BIOS 30 by the data update output terminal 53 of the duplexer 50 to update the BIOS 30. The second The data update output 61 is electrically connected to the second input 52 of the duplexer 50. [0015] Referring to FIG. 3, when the server system 1 crashes, the south bridge wafer 60 stops operating. At this time, the output control terminal 41 of the IPMI4 outputs a control signal of 099123443 to the input control terminal 112 of the BMC1, to control the output of the first chip selection signal of the first chip. Up to the 30th chip selection signal wheel entry terminal 31. At the same time, the first beast update output terminal 11 of the win 1 turns out an update form number A0101 page 7 / 15 pages to the duplexer 50 0992041309-0 201205437 first input 51 And outputting to the data update input terminal 32 of the BIOS 30 by the data update output terminal 53 of the duplexer 50 to perform data update on the BIOS 30. [0016] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the present invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIG. 1 is a functional unit diagram of a server system according to an embodiment of the present invention; [0018] FIG. 2 is a first operational state diagram of the server system of FIG. 1; [0019] FIG. It is a schematic diagram of the second working state of the server system of FIG. [Main component symbol description] [0020] Servo system: 1 0 0 [0021] BMC : 10 [0022] BMC memory: 20 [0023] BIOS : 30 [0024] IPMI : 40 [0025] Duplexer: 5 0 [0026] South Bridge Chip: 60 [0027] The first selection signal output: 1 1 [0028] The second selection signal output: 12 099123443 Form No. A0101 Page 8 / Total 15 Page 0992041309-0 110201205437
[0029] 第一資料更新輸出端： [0030] 輸入控制端：112 [0031] 第一片選訊號輸入端： [0032] 第一資料更新輸入端： [0033] 片選訊號輸入端： 31 [0034] 資料更新輸入端： 32 [0035] 輸出控制端：41 [0036] 第一輸入端：51 [0037] 第二輸入端：52 [0038] 資料更新輸出端： 53 [0039] 第二資料更新輸出端： 21 22 61[0029] The first data update output: [0030] Input control terminal: 112 [0031] The first chip selection signal input terminal: [0032] The first data update input terminal: [0033] Chip select signal input terminal: 31 [ 0034] Data update input: 32 [0035] Output control: 41 [0036] First input: 51 [0037] Second input: 52 [0038] Data update output: 53 [0039] Second data update Output: 21 22 61
099123443 表單編號A0101 第9頁/共15頁 0992041309-0099123443 Form No. A0101 Page 9 of 15 0992041309-0