201203817 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電源供應器與以及抑制電源供應器之輪出 電壓波動(ripple)的方法。 【先前技術】 電源供應器為一種電源管理裝置，用來轉換電源，以提供電源 給電子裝置或是元件。因為轉換效率以及成品大小考量，目前許多 家用電子產品多以切換式電源供應器(switched_m〇de ρ〇· supply ’ SMPS)，希望產生—輸出紐，來對好產品供電。而輪 出電壓是否穩定，往往是SMPS的性能重點。 為了減小單-頻率之電磁波干擾(EMI)，SMps 一般會設計有抖 =eq=ltolng陶能，使其功彻嶋作鮮，能夠隨著 寺間的，化’而緩慢的且週期性的變化於—很小的範圍内。 如果SMPS在每^^力^事實上是跟操作贿目_。譬如說， 之妗屮、對輸出所提供的能量為W，那SMps 化的輸出辨往彳^7^~為固定倾時’這樣隨著頻率變 SMPS的穩絲現。 4電壓的波動(ripple) ’因而降低了 【發明内容】 一時脈產生器用以產生— 本發明實施例提供—種電源供應器 201203817 時脈信號以及-三角波信號。該三驗錢 頻產生器用以提供—抖_號予該時脈產“ 抖 率…補償電路依據輸出電源狀態，以產生—補償信^=頻 不同之-第-狀態以及—第二狀態。當該抖頻作藏古於^於 號時，該補償電路操作於該第-狀態，當該抖_^=角波信 信號，該補償電路操作於該第二狀態。 -角波 本發明實施例提供-種抑制電源供應器之輪出電壓波 法。提供-抖頻信號，控制—三角波信號之—時脈頻率。比較 _號以及該三角波信號，喊生—比較結果。依據槪較结果， 使-補償電路切·二操錄態。魏，依魏電源供應 器之輸出電壓’產生一補償信號。 【實施方式】 第1圖為一依據本發明實施的電源供應器60，具有返馳式架構 (flybacktopology)。橋式整流器62整流了交流電源Vac，提供^入 • 電源Vin至變壓器64。開關72短路(d〇se)時，變壓器64的一次側 繞組LP儲能；開路(open)時，變壓器64的二次側繞組“透過整流 器66釋能至負載電容(load capacitor)69以建立輸出電源ν〇υτ。誤差 放大裔(error amplifier)68比較輸出電源V〇ut的電壓血目標電壓 Vtarget ’並在一補償端產生補償信號COM。控制器76依據補償信 5虎COM以及電流彳貞測彳§彳虎CS .，以控制信號GATE控制開關72。 €流偵測信號CS反應流經一次側繞組LP的電感電流。補償信號 COM可以決定電源供應器60的能量輸出。 201203817 隨著各個國豕的供電系統規格不同，輸入電源〜可能是.⑽伏 特 伏特中的一個相當尚的電壓。在-實施例中，控制器76 是一單晶^體電路。在另一實施例中，控制器76與開關72共同 形成在一單晶片積體電路中。 在控制器76中’抖頻產生器90提供抖頻信號JTR予時脈產生 器100,用來控制時脈產生器刚所輸出的時脈信號CLK以及三角 波信號RAMP的時脈頻率fcLK。時脈產生器也比較了三角波信 號RAMP與抖頻信號取，然後輸出比較結果脱。處理器％則 依據電流偵測信號CS、補償信號COM、時脈信號CLK以及比較結 果H/L，來產生控制信號GATE控制開關。 第2圖顯示有第1圖中的時脈產生器100與抖頻產生器90。抖 頻信號皿由抖頻產生器90所產生，為一具有很慢頻帮如說 侧2)的三角波。抖頻信號JTR導致波形產生器1〇2所產生時齡 就CLK以及三角波信號_之時脈頻率f似緩慢變化於，響如 60KHZ到70KHZ之間。比較器1〇4比較抖頻信號皿以及三 角波信號RAMP，而輸出比較結果H/L。 第3醜示三纽錢_、時脈錢clk、細節现、 以及比較結果H/L之間的時序關係。當三角波信號_於上升/ 伸寺’時脈信號CLK為邏輯的”^。如同第㈣所示意的噶 考細言號皿的上升或下降，三角波信號罐p與時脈信號似 之《頻率W也隨之上升或下降。比較結果肌為邏輯的，雷， 時’表示抖齡號高/低於三肖波錢議？。 第4圖顯示第i财的處理器74與誤差放大器紹。誤差放大 201203817 态68有一光耦合器(photo-coup㈣280與一補償電容282。處理器％ 中，依據輸出電源νουτ的電壓，補償電路201會產生補償信號c〇M 與相對的補償信號C0M2。比較器204則比較了補償信號c〇M2與 電流偵測信號CS。邏輯處理器206依據比較器2〇4之輸出與時脈信 號CLK，產生控制信號GATE。補償信號COM大致決定了電流偵 測信號cs的峰值’所以大約決定了 一次開關循環（c外⑹中， 一次側繞組Ls的輸出能量。 如同第4圖所示，補償電路201有電阻模組2〇2、二極體214、 電阻208以及電阻2! 〇。電阻模组2〇2祕於操作電源vcc與補償 電容282之間，受控於比較結果h/l，可以操作於兩種狀態。譬如 說’當比較結果H/L為邏輯”1”時，電阻模組2〇2操作於一第一狀態， 具有-較高等效電阻；當比較結果亂為邏輯，，〇，，時，電阻模組L 操作於一第二狀態，具有有一較低等效電阻。 第5a與5b圖例示了兩種不同的電阻模組，都可以適用於第* 圖中的電阻模組2G2。每«45b_具有兩電阻以及一開關。 在第5a ®中，當開關被比較結果亂所短路⑽㈣時，電阻迎的 電阻對電阻模組2G2a的等效阻值就不會有任何影響。類似的，在第 5b圖中田開關被比較結果h/l所開路(〇㈣時，電阻3⑽的電阻 對電阻模組202b的等效阻值就不會有任何影響。 從一個開關循環來看，雖然電阻模組2〇2的等效電阻可能切換 在較高與較低等效電阻之間，因為補償電容撕所提供她皮效、 果’所以電阻模組2〇2可以視為有一個平均電阻，由電峰且2〇2 提供較高與較低等效f阻之日销_岭定令說，在第3圖中， 201203817 所以電 電阻模組 在開關循環C1中，比較結果h/l在邏輯，，〇，，的時間比較久，” 阻模組2〇2在較低等效電阻的時間比較久，因此 -個比較低辭物且。同理伽相_和中 有 202有一個比較高的平均電阻。 在同樣的輸出電鮮晴之電壓下，比較⑽平均電阻合導致比 較高的補償信號C0M，以及二次織組^較高輸出能㈣。比 較結果H/L在邏輯，，〇，，的時間比較久，意味著比較低之時脈頻率 CLK如同第3圖之開關猶環C1所例示。只要設計得當，每個開關 週期的輸出功率p=w*w就可以大約是個常數，不受抖頻之頻率 變化影響，使得輸出f源VQUT^ 轉穩定。 口口第6圖顯示有可適驗第i圖中的時脈產生器i〇〇a與抖頻產生 器:0。跟第5圖中的時脈產生器謂不一樣的，第6圖中的時脈產 生器100a中’抖頻信號JTR沒有直接連接到波形產生器腿，且 比較結果H/L有連接到波形產生器1〇2a。 第7圖為第6圖之三角波信號ramp、時脈信號CLK、抖頻信 號JTR、以及比較結果h/l之間的時序關係。第7圖之時脈信號 CLK、抖頻信號JTR、以及比較結果亂跟第3圖大致相同，不再 重述'然而，跟第3圖不同的，第3圖中三角波信號腿^的每個 上升#又與母個下降^又都疋大約斜率固定的一直線，在一開關循環 中，第7圖中二角波k號RAMP則可能會有斜率不同的二上升段與 二下降段。如同第7圖所示，間關循環C3中，上升段服斜率高於 上升段SR ’下降段FF斜率尚於下降段sf。比較結果肌大致控 制三角波信號RAMP的上升段或是下降段的斜率。在一個實施例， 201203817 比較結果H/L為邏輯”0”時，三角波信號RAjyjp的上升與下降斜率 大致會產出的時脈頻率fCLK* 60kHz ;比較結果H/L為邏輯”Γ，時， 上升與下降斜率大财產㈣報頻料Lj7GkHz。如果在一個 開關循環中，比較結果H/L有決大部分時間是邏輯”Γ，，則時脈信號 CLK的時脈頻率fCLK，可預期的，會是介於6〇k〜7〇ωζ之間，但比 較靠近70kHz的一個值。 以上貫把例雖然以返驰式架構(flyback topology)的電源供應5| 為例，但是，本發明並不限於此，也可以適用於其他架構之電源供 應器4如5兒，降壓式轉換器(buck converter)或是昇壓式轉換5| ” (booster) ° 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖顯示了一個電源路徑管理控制器。 讓"第2圖顯示本發明一實施例之時脈產生器與抖頻產生器 第3圖顯不本發明一實施例之三角波信號、時脈信號、抖頻信號、 以及比較結果H/L之間的時序圖。 第4圖顯示本發明貫施例之處理器與誤差放大器 第5a圖顯示本發明一實施例之電阻模組 第5b圖顯示本發明一實施例之電阻模組 第6圖顯示本發明一實施例之時脈產生器與抖頻產生器 第7圖顯示本發明一實施例之三角波信號、時脈信號、抖頻彳古號、 201203817 以及比較結果H/L之間的時序圖。 【主要元件符號說明】 60 電源供應器 62 橋式整流器 64 變壓器 66 整流器 68 誤差放大器 69 負載電容 72 開關 74 處理器 76 控制器 90 抖頻產生器 100 、 100a 時脈產生器 102 、 102a 波形產生器 104 比較器 201 補償電路 202、202a、202b 電阻模組 204 比較器 206 邏輯處理器 208、210、302、304 電阻 214 二極體201203817 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a power supply and a method of suppressing the voltage fluctuation of the power supply. [Prior Art] A power supply is a power management device for converting a power supply to supply power to an electronic device or component. Because of the conversion efficiency and the size of the finished product, many household electronic products currently use a switched power supply (switched_m〇de ρ〇· supply ’ SMPS), and it is desirable to generate an output button to supply power to the good product. Whether the voltage is stable or not is often the focus of SMPS performance. In order to reduce the single-frequency electromagnetic interference (EMI), SMps is generally designed to have shake = eq = ltolng pottery, which makes it work well and can be slow and periodic with the temple. Change in - a small range. If the SMPS is in every ^^ force ^ is actually with the operation of the bribe _. For example, after the energy supplied to the output is W, the output of the SMps is determined as 彳^7^~ is a fixed tilting state. 4 Voltage fluctuations are thus reduced. SUMMARY OF THE INVENTION A clock generator is used to generate a power supply 201203817 clock signal and a triangular wave signal. The three money detectors are used to provide a jitter signal to the clock generator. The "shake rate...compensation circuit is based on the output power state to generate - the compensation signal = the frequency difference - the - state and the second state. The compensating circuit operates in the first state when the frequency hopping is hidden in the first state, and the compensating circuit operates in the second state when the shaking signal is _^= angular wave signal. - Angular wave embodiment of the present invention Providing a method for suppressing the voltage of the power supply from the power supply. Providing a frequency-jittering signal, controlling the frequency of the triangular wave signal, the clock frequency, comparing the _ number and the triangular wave signal, and shouting the result of the comparison. - Compensating circuit cutting and second recording. Wei, Yi Wei power supply output voltage 'generates a compensation signal. [Embodiment] FIG. 1 is a power supply 60 according to the implementation of the present invention, with a flyback architecture (flybacktopology) The bridge rectifier 62 rectifies the AC power supply Vac to provide power supply Vin to the transformer 64. When the switch 72 is short-circuited (d〇se), the primary side winding LP of the transformer 64 stores energy; when open (open), Secondary winding of transformer 64" The rectifier 66 is discharged to a load capacitor 69 to establish an output supply ν 〇υ τ. The error amplifier 68 compares the voltage blood target voltage Vtarget ' of the output power supply V〇ut and generates a compensation signal COM at a compensation end. The controller 76 controls the switch 72 with the control signal GATE based on the compensation signal 5 and the current test. The flow detection signal CS reacts through the inductor current of the primary side winding LP. The compensation signal COM can determine the energy output of the power supply 60. 201203817 With the different power supply system specifications for each country, the input power supply ~ may be a fairly high voltage in .10 volts. In an embodiment, controller 76 is a single crystal circuit. In another embodiment, controller 76 and switch 72 are co-formed in a single wafer integrated circuit. In the controller 76, the frequency hopping generator 90 provides a frequency hopping signal JTR to the clock generator 100 for controlling the clock signal CLK just output by the clock generator and the clock frequency fcLK of the triangular wave signal RAMP. The clock generator also compares the triangular wave signal RAMP with the frequency-jitter signal, and then outputs the comparison result. The processor % generates a control signal GATE control switch based on the current detection signal CS, the compensation signal COM, the clock signal CLK, and the comparison result H/L. Fig. 2 shows the clock generator 100 and the frequency hopping generator 90 in Fig. 1. The dither signal is generated by the frequency hopping generator 90 as a triangular wave having a very slow frequency side, such as side 2). The frequency-jittering signal JTR causes the waveform generator 1〇2 to generate a aging time and the clock frequency f of the triangular wave signal _ seems to change slowly, such as between 60KHZ and 70KHZ. The comparator 1〇4 compares the frequency-jitter signal and the triangular-wave signal RAMP, and outputs a comparison result H/L. The third ugly shows the timing relationship between the three new money _, the clock money clk, the detail present, and the comparison result H/L. When the triangular wave signal _ is rising / stretching the temple' clock signal CLK is logical "^. As shown in the fourth (4), the rise or fall of the reference number, the triangular wave signal tank p and the clock signal are similar to the frequency W It also rises or falls. The result of the comparison is that the muscle is logical, and the Ray's time indicates that the peak age is higher/lower than the three Xiaobo money. Figure 4 shows the processor 74 and the error amplifier of the first money. Amplifying 201203817 state 68 has a photocoupler (photo-coup (four) 280 and a compensation capacitor 282. In processor %, according to the voltage of the output power source νουτ, the compensation circuit 201 generates a compensation signal c〇M and a relative compensation signal C0M2. The compensation signal c〇M2 and the current detection signal CS are compared. The logic processor 206 generates a control signal GATE according to the output of the comparator 2〇4 and the clock signal CLK. The compensation signal COM substantially determines the current detection signal cs. The peak value is thus determined approximately once in the switching cycle (outer (6), the output energy of the primary side winding Ls. As shown in Fig. 4, the compensation circuit 201 has the resistance module 2〇2, the diode 214, the resistor 208, and the resistor. 2! The resistor module 2〇2 is secret between the operating power source vcc and the compensation capacitor 282, and is controlled by the comparison result h/l, and can be operated in two states. For example, when the comparison result H/L is logic "1" The resistor module 2〇2 operates in a first state and has a higher equivalent resistance; when the comparison result is chaotic, logic, 电阻,, the resistor module L operates in a second state, having a lower level The 5a and 5b diagrams illustrate two different resistor modules, both of which can be applied to the resistor module 2G2 in Figure *. Each «45b_ has two resistors and one switch. In the 5a ®, when When the switch is short-circuited by the comparison result (10) (4), the resistance of the resistor will have no effect on the equivalent resistance of the resistor module 2G2a. Similarly, in Figure 5b, the field switch is opened by the comparison result h/l (〇 (4) When the resistance of the resistor 3 (10) has no effect on the equivalent resistance of the resistor module 202b. From the perspective of one switching cycle, although the equivalent resistance of the resistor module 2〇2 may be switched between higher and lower. Between the equivalent resistance, because the compensation capacitor tears provide her skin effect, fruit 'so The resistor module 2〇2 can be regarded as having an average resistance, which is provided by the electric peak and 2〇2 for the higher and lower equivalent f resistance. _ Lingding Order, in Fig. 3, 201203817 In the switching cycle C1, the comparison result h/l is longer in logic, 〇, ,, and longer, the resistance module 2〇2 is longer in the lower equivalent resistance time, so a relatively low relic And the same gamma phase _ and 202 have a higher average resistance. Under the same output voltage, the comparison (10) average resistance results in a higher compensation signal C0M, and the secondary woven group is higher. The output can be (4). The comparison result H/L is longer in logic, 〇, ,, meaning that the lower clock frequency CLK is exemplified as the switch of Figure 3, C1. As long as it is properly designed, the output power p=w*w of each switching cycle can be approximately constant and is not affected by the frequency variation of the frequency hopping, so that the output f source VQUT^ is stable. Figure 6 of the mouth shows the clock generator i〇〇a and the frequency-jitter generator in the i-th picture: 0. Unlike the clock generator in Fig. 5, the frequency-jitter signal JTR in the clock generator 100a in Fig. 6 is not directly connected to the waveform generator leg, and the comparison result H/L is connected to the waveform. Generator 1〇2a. Fig. 7 is a timing relationship between the triangular wave signal ramp, the clock signal CLK, the dither signal JTR, and the comparison result h/l of Fig. 6. The clock signal CLK, the frequency-jittering signal JTR, and the comparison result in FIG. 7 are substantially the same as in FIG. 3, and will not be repeated. However, unlike FIG. 3, each of the triangle wave signal legs in FIG. Rising # and descending with the parent ^ are both straight lines with a fixed slope. In a switching cycle, the two-wave k-th RAMP in Figure 7 may have two rising and two falling segments with different slopes. As shown in Fig. 7, in the interval C3, the rising section service slope is higher than the rising section SR'. The falling section FF slope is still in the falling section sf. The comparison result muscle roughly controls the slope of the rising or falling section of the triangular wave signal RAMP. In one embodiment, when the comparison result H/L of the 201203817 is logic "0", the rising and falling slopes of the triangular wave signal RAjyjp approximately produce a clock frequency fCLK*60 kHz; the comparison result H/L is logic "Γ, when The rising and falling slopes have a large property (4) The frequency of the material is Lj7GkHz. If the comparison result H/L has a logic for most of the time in a switching cycle, the clock frequency fCLK of the clock signal CLK can be expected. It will be between 6〇k~7〇ωζ, but it is closer to a value of 70kHz. The above example is an example of a power supply 5| of a flyback topology. However, the present invention is not limited thereto, and may be applied to a power supply 4 of other architectures such as a buck converter. (buck converter) or boost converter 5|" (booster) ° The above is only a preferred embodiment of the present invention, and all the equivalent changes and modifications made in accordance with the scope of the present invention should belong to the present invention. Scope of the Invention [Simplified Schematic Description] Fig. 1 shows a power path management controller. Let Fig 2 show a clock generator and a frequency hopping generator according to an embodiment of the present invention. A timing diagram between a triangular wave signal, a clock signal, a frequency hopping signal, and a comparison result H/L according to an embodiment of the present invention. FIG. 4 is a diagram showing a processor and an error amplifier according to a fifth embodiment of the present invention. FIG. 5B shows a resistor module according to an embodiment of the present invention. FIG. 6 shows a clock generator and a frequency-jitter generator according to an embodiment of the present invention. FIG. 7 shows a triangular wave according to an embodiment of the present invention. Signal, clock signal, Timing diagram between frequency, 201203817 and comparison result H/L. [Main component symbol description] 60 Power supply 62 Bridge rectifier 64 Transformer 66 Rectifier 68 Error amplifier 69 Load capacitance 72 Switch 74 Processor 76 Controller 90 frequency hop generator 100, 100a clock generator 102, 102a waveform generator 104 comparator 201 compensation circuit 202, 202a, 202b resistor module 204 comparator 206 logic processor 208, 210, 302, 304 resistor 214 diode body
10 20120381710 201203817
280 光柄合器(photo-coupler) 282 補償電容 CLK 時脈信號 COM、COM2 補償信號 CS 電流偵測信號 Cl、C2、C3 開關循環 fcLK 時脈頻率 FR、SR 上升段 FF、SF 下降段 GATE 控制信號 H/L 比較結果 JTR 抖頻信號 LP 一次側繞組 Ls 二次側繞組 RAMP 三角波信號 Vac 交流電源 vcc 操作電源 Vtn 輸入電源 V〇UT 輸出電源 ViARGET 目標電壓 11280 light-handle 282 compensation capacitor CLK clock signal COM, COM2 compensation signal CS current detection signal Cl, C2, C3 switching cycle fcLK clock frequency FR, SR rising segment FF, SF falling segment GATE control Signal H/L Comparison result JTR Frequency-hopping signal LP Primary side winding Ls Secondary side winding RAMP Triangle wave signal Vac AC power supply vcc Operation power supply Vtn Input power supply V〇UT Output power supply ViARGET Target voltage 11