201203480 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種矽基基板，且特別是有關於一種具有 非對稱結構之f夕基基板及其製作方法。 【先前技術】 目刖，S知石夕基基板（siHc〇n based substrate)通常是遵 循傳統線路基板之對稱設計準則進行料製作，因而為對稱 (symmetric)結構。也就是說，習知矽基基板之矽基材之相 對兩側之堆疊線路結構與介電層材料是大致相同的。 一般在矽基基板應用於電子産品的實際使用過程中，矽基 材-側之堆疊線路結構係用於與電子元件電性連接，另一側之 堆疊線路結構係用於封裝時與電路板電性連接 功能日趨多樣化，料基板之佈線密度亦趨向·度化發^ 如果按照傳統線路基板之對稱設計準則，不僅石夕基材一側用於 與電子元件電性連接之堆疊線路結構需要高材 芯眚電路板電性連接之堆疊線路結心^ 路結構並不需要如此高的佈線密= Γ=;:Γ封裝時與電路板電性連接=二 ί製作完成，而目前許多封裝礙的設備和製程 尚無法元成過尚佈線密度之製作。 【發明内容】 (:二二==:基板；=對稱 201203480 為達上述優點，本發明提出一種矽基基板，包括矽晶圓、 第一線路基板以及第二線路基板。矽晶圓具有第一表面以及與 第一表面相對之第二表面，並具有至少，穿孔貫通第一表面 與第二表面。第一線路基板設置於矽晶圓之第一表面，並由多 層第一介電層以及多層第一導電線路層交替疊合而成。第二線 路基板設置於矽晶圓之第二表面，並由多層第二介電層以及多 層第一導電線路層交替疊合而成。其中，至少一石夕穿孔分別電 性連接第一線路基板中位於最下層之第一導電線路層與第二 線路基板中位於最上層之第二導電線路層，且第一導電7線路層 之佈線密度大於第二導電線路層之佈線密度。 在本發明之一實施例中，上述之第一線路基板採用晶圓級 半導體製程製作完成。 ，本發明之一實施例中’上述之矽基基板更包括第一保護 層覆蓋第一線路基板，及第二保護層覆蓋第二線路基板。 在本發明之一實施例中，上述之第一線路基板更包括凸塊 金屬層（under bump metallization，UBM )形成於第一線路基 板之第一開口中，電性連接於第一導電線路層。 在本發明之一實施例中’上述之第一線路基板更包括複數 被動元件與第一導電線路層電連接。 為達上述優點，本發明提出一種矽基基板，包括矽晶圓、 第一線路基板以及第二線路基板。矽晶圓具有第一表面以及與 第一表面相對之第二表面，並具有至少一矽穿孔貫通第一表面 與第二表面。第一線路基板設置於矽晶圓之第一表面，並由多 層第一介電層以及多層第一導電線路層交替疊合而成。第二線 路基板設置於矽晶圓之第二表面，並由多層第二介電層以及多 層第二導電線路層交替疊合而成。其中，至少一矽穿孔分別電 201203480 性連接第一線路基板中位於最下層之第一導電線路層與第二 線路基板t位於最上層之第二導電線路層。且這些第一導介電 層包括無機材料，這些第二介電層包括有機材料。 在本發明之一實施例中，上述之無機材料包括矽氧化物、 矽氮化物或矽基材料。 在本發明之一實施例t，上述之有機材料包括聚亞醯胺或 苯環丁烯。 為達上述優點，本發明提出一種矽基基板之製作方法其 首先提供矽晶圓，此矽晶圓具有第一表面以及與第一表面相對 之第二表面。然後，採用晶圓級半導體製程於矽晶圓之第一表 面形成多層第一介電層以及多層第一導電線路層，這些第一介 電層與第-導電線路層交替疊合形成第一線路基板。接著，於 石夕晶圓中形成至少-石夕穿孔貫通第一表面與第二表面，石夕穿孔 電性連接至第一線路基板中位於最下層之第一導電線路層。之 後’於石夕晶圓之第二表面形成多層第二介電層以及多層第二導 電線路層，這些第二介電層與第二導電線路層交替疊合形成第 二線路基板’且第二線路基板中位於最上層之第二導電線路層 #電性連接於石夕穿孔。其中這些第一導電線路層之佈線密度大^ 這些第二導電線路層之佈線密度。 在本發明之-實施例中，上述之魏基板之製作方法於形 成至少-石夕穿孔之前，更包括進行晶圓薄化製程。晶圓薄化製 程係首先研磨石夕晶圓之第二表面，形成研磨表面，然後钱刻研 磨表面。 在本發明之一實施例中’上述之形成至少一石夕穿孔貫通第 -表面與第二表面，係首細成至少—通孔貫通碎晶圓之第一 表面與第二表面，且暴露出第一線路基板之部分第一導電線路 201203480 層。然後，形成絕緣層，以覆蓋矽晶圓之第二表面以及通孔之 側壁。之後，形成導電層於絕緣層上及通孔中，以形成多個電 連接第一線路基板及第二線路基板之導電通路。 在本發明之一實施例中，上述之第一介電層包括無機材 料，且第二介電層包括有機材料。 在本發明之一實施例中’上述之矽基基板之製作方法更包 括形成第一保護層，覆蓋第一線路基板。201203480 VI. Description of the Invention: [Technical Field] The present invention relates to a ruthenium-based substrate, and more particularly to an HF substrate having an asymmetric structure and a method of fabricating the same. [Prior Art] It is seen that the SiHc〇n based substrate is usually fabricated in accordance with the symmetrical design criteria of the conventional circuit substrate, and thus is a symmetric structure. That is to say, the stacked wiring structures on the opposite sides of the germanium substrate of the conventional germanium substrate are substantially the same as the dielectric layer material. Generally, in the actual use of the ruthenium-based substrate for electronic products, the stack-side structure of the 矽 substrate-side is used for electrical connection with the electronic components, and the stacked circuit structure on the other side is used for packaging and circuit board. The connection function is increasingly diversified, and the wiring density of the material substrate tends to be higher. If the symmetrical design criteria of the conventional circuit substrate are used, not only the stack circuit structure for electrically connecting the electronic components to the side of the stone substrate is required. The core structure of the core board is electrically connected to the stacking circuit. The circuit structure does not need such a high wiring density. Γ=;: 电The electrical connection with the board when the package is mounted = 2 制作 is completed, and many packages are currently blocked. Equipment and processes have not yet been able to produce excessive wiring density. SUMMARY OF THE INVENTION (: 22 ==: substrate; = symmetrical 201203480 To achieve the above advantages, the present invention provides a ruthenium-based substrate comprising a ruthenium wafer, a first circuit substrate, and a second circuit substrate. a surface and a second surface opposite to the first surface, and having at least a through hole penetrating the first surface and the second surface. The first circuit substrate is disposed on the first surface of the germanium wafer and is composed of a plurality of first dielectric layers and a plurality of layers The first conductive circuit layer is alternately stacked. The second circuit substrate is disposed on the second surface of the germanium wafer, and is formed by alternately stacking a plurality of second dielectric layers and a plurality of first conductive circuit layers. The first through-holes are respectively electrically connected to the first conductive circuit layer located in the lowermost layer of the first circuit substrate and the second conductive circuit layer located in the uppermost layer of the second circuit substrate, and the wiring density of the first conductive 7-line layer is greater than the second conductive The wiring density of the circuit layer. In one embodiment of the present invention, the first circuit substrate is fabricated by a wafer level semiconductor process. In an embodiment of the present invention, The base substrate further includes a first protective layer covering the first circuit substrate, and a second protective layer covering the second circuit substrate. In an embodiment of the invention, the first circuit substrate further includes a bump metal layer (under bump metallization) The UBM is formed in the first opening of the first circuit substrate and electrically connected to the first conductive circuit layer. In an embodiment of the invention, the first circuit substrate further includes a plurality of passive components and the first conductive circuit. In order to achieve the above advantages, the present invention provides a germanium-based substrate including a germanium wafer, a first wiring substrate, and a second wiring substrate. The germanium wafer has a first surface and a second surface opposite to the first surface. And having at least one turn through the first surface and the second surface. The first circuit substrate is disposed on the first surface of the germanium wafer, and is formed by alternately stacking the plurality of first dielectric layers and the plurality of first conductive circuit layers. The second circuit substrate is disposed on the second surface of the germanium wafer, and is formed by alternately laminating a plurality of second dielectric layers and a plurality of second conductive circuit layers, wherein at least one of the perforations The second conductive circuit layer located at the lowermost layer of the first circuit substrate and the second circuit substrate t are disposed on the second conductive circuit layer of the first circuit substrate, and the first conductive dielectric layers include inorganic materials, and the second The dielectric layer comprises an organic material. In one embodiment of the invention, the inorganic material comprises a cerium oxide, a cerium nitride or a cerium based material. In one embodiment of the invention, the organic material comprises polyarylene In order to achieve the above advantages, the present invention provides a method for fabricating a germanium-based substrate which first provides a germanium wafer having a first surface and a second surface opposite the first surface. A first level dielectric layer and a plurality of first conductive circuit layers are formed on the first surface of the germanium wafer by a wafer level semiconductor process, and the first dielectric layer and the first conductive circuit layer are alternately stacked to form a first circuit substrate. Then, at least the stone is pierced through the first surface and the second surface in the Shixi wafer, and the through hole is electrically connected to the first conductive layer in the lowermost layer of the first circuit substrate. Then forming a plurality of second dielectric layers and a plurality of second conductive wiring layers on the second surface of the Shi Xi wafer, the second dielectric layers and the second conductive wiring layers are alternately stacked to form a second wiring substrate 'and a second The second conductive circuit layer # located in the uppermost layer of the circuit substrate is electrically connected to the stone-shaped perforation. Wherein the wiring density of the first conductive circuit layers is greater than the wiring density of the second conductive circuit layers. In the embodiment of the present invention, the method for fabricating the above-mentioned Wei substrate further includes performing a wafer thinning process before forming at least a shi-shi. The wafer thinning process first grinds the second surface of the Shi Xi wafer to form an abrasive surface, and then grinds the surface. In one embodiment of the present invention, the at least one of the above-mentioned formations penetrates through the first surface and the second surface, and the first portion is formed into at least a through hole penetrating through the first surface and the second surface of the chip, and the first surface is exposed. A portion of the first conductive line 201203480 of a circuit substrate. Then, an insulating layer is formed to cover the second surface of the germanium wafer and the sidewalls of the via. Thereafter, a conductive layer is formed on the insulating layer and in the via hole to form a plurality of conductive paths electrically connecting the first circuit substrate and the second circuit substrate. In one embodiment of the invention, the first dielectric layer comprises an inorganic material and the second dielectric layer comprises an organic material. In an embodiment of the invention, the method for fabricating the above-described ruthenium-based substrate further includes forming a first protective layer covering the first circuit substrate.
在本發明之一實施例中，上述之矽基基板之製作方法更包 括.形成第一開口於第一線路基板中，以暴露出部分第一導電 線路層，以及形成凸塊金屬層於第一開口中，電性連接於第一 導電線路層。 ' 在本發明之-實施例中，上述之石夕基基板之製作方法更包 括形成第二保護層，覆蓋第二線路基板。 在本發明之-實施财，上述之德基板之製作方法更包 括形成複數被動元件於第一線路基板中。 本么明之石夕基基板及其製作方法，由於位於石夕晶圓相對兩 側之第-線路基板與第二線路基板之導路層之佈線密度 或者位於石夕晶圓相對兩側之第—線路基板與第二線路基 ΐ層材料不同，而具有非對稱結構。此碎基基板可以根 合理安排佈線’使得用於與電子元件電性連接 :可：於:與電路板電性連接之第二線路基板電i 作第二介電層’不僅可以滿足製作不同佈線 在度之第—導電、祕層與第二導電祕狀需要。 201203480 懂，和其他目的、特徵和優點能更明顯易 “較佳實關’並配合所附®式，作詳細說明如下。 【實施方式】 ^閱圖1A至圖1L，圖1A至圖 例之t基基板ι〇之製作方法的流程剖面示意圖。 第-圖1A ’首先，提供石夕晶圓刚。石夕晶圓剛具有 第一表面102以及與第一表自1〇2相對之第二表面1〇4。 之第清ίΓ圖1β ’然後’採用晶圓級半導體製程於發晶圓議 多層第—介電層112以及多層第一導電線 成i-㈣其/電層112與第—導電線路層114交替疊合形 =第-線路基板11()。由於採用晶圓級半導體製程，第一導電 ，層114之佈線密度可以達到毫微米級(奈米級）。第一導 括無機材料。無機材料包括矽氧化物、矽氮化物 或矽基材料等，但並不以此為限。 在製作第—線路基板UG之過程中，更包括形成複 數被動7G件（圖未不）於第一線路基板11〇中。 請參照圖1C，之後，形成第—保護層12G，覆蓋第一線 路基板110 4 了實現第一線路基板11〇與其他電子元件例如 積體電路之凸塊（bump)電性連接，於第—保護層120形成 之後，更可包括形成凸塊金屬層（under bump metallization， UBM) 115之步驟。在本實施例中，首先，如圖ic所示形 成第-開口 122於第-線路基板11G中，例如移除部分第一保 護層120以及對應之第一介電層112中’以暴露出部分第一導 電線路層114。域第—開σ 122之方法可採用黃光或钱刻製 程，在此不予詳述。然後，如圖1D所示，在第一開口 122中 形成凸塊金屬層115，使得凸塊金屬層115位於第一開口 122 201203480 之側壁以^第-開Π 122暴露出的部分第 上，並延侧-祕㈣〇外，從m 層m之電性連接。凸塊金屬層u 可』二電線： (Cu)、鎳（Ni)、金（Au)或其、7為欽（Tl)、銅 ν, ^ « 1Λ 、、’且δ。值得注意的是，形 成第-保4層m以及凸塊金屬層115之 線路基板130製作完成後進行。 』隹後、只弟In an embodiment of the present invention, the method for fabricating the ruthenium-based substrate further includes: forming a first opening in the first circuit substrate to expose a portion of the first conductive circuit layer, and forming a bump metal layer on the first The opening is electrically connected to the first conductive circuit layer. In the embodiment of the present invention, the method for fabricating the above-described base substrate further includes forming a second protective layer covering the second circuit substrate. In the method of the present invention, the method for fabricating the substrate described above further includes forming a plurality of passive components in the first circuit substrate. The illuminating substrate of the present invention and the manufacturing method thereof are based on the wiring density of the guiding layer of the first-line substrate and the second circuit substrate on opposite sides of the Shixi wafer or on the opposite sides of the Shixi wafer. The circuit substrate is different from the second line base layer material and has an asymmetric structure. The ground substrate can be properly arranged to be electrically connected to the electronic component: the second circuit substrate electrically connected to the circuit board can be used as a second dielectric layer to meet different wiring requirements. In the first degree - conductive, secret layer and second conductive secrets are needed. 201203480 understands, and other purposes, features and advantages can be more obvious and "better" and with the attached ® formula, as detailed below. [Embodiment] Read Figure 1A to Figure 1L, Figure 1A to Figure t A schematic cross-sectional view of a method for fabricating a base substrate ι. Figure 1A 'First, a stone wafer is provided. The stone wafer has a first surface 102 and a second surface opposite to the first surface from the first surface. 1〇4. The first clear figure 1β 'then' uses a wafer level semiconductor process to issue a multilayer dielectric-dielectric layer 112 and a plurality of first conductive lines into i-(d)/electric layer 112 and first-conducting The circuit layers 114 are alternately stacked = the first-substrate substrate 11 (). Due to the wafer level semiconductor process, the first conductive, layer 114 wiring density can reach nanometer order (nano). The inorganic material includes cerium oxide, cerium nitride or cerium-based material, but is not limited thereto. In the process of fabricating the first circuit substrate UG, it also includes forming a plurality of passive 7G parts (not shown). In a circuit board 11 请. Please refer to FIG. 1C, and then form the first The protective layer 12G covers the first circuit substrate 110 to realize electrical connection between the first circuit substrate 11 and other electronic components, such as integrated circuits. After the first protective layer 120 is formed, the protective layer 12G may further comprise a bump. Step of the bump metallization (UBM) 115. In this embodiment, first, the first opening 122 is formed in the first-line substrate 11G as shown in FIG. 1c, for example, a portion of the first protective layer 120 is removed. And corresponding to the first dielectric layer 112 to expose a portion of the first conductive circuit layer 114. The method of domain-opening σ 122 can adopt a yellow light or a money engraving process, which will not be described in detail herein. As shown in FIG. 1D, a bump metal layer 115 is formed in the first opening 122 such that the bump metal layer 115 is located on the sidewall of the first opening 122 201203480 with the portion exposed by the opening-opening 122, and the side is secreted. (4) Outside the ,, the electrical connection from the m layer m. The bump metal layer u can be two wires: (Cu), nickel (Ni), gold (Au) or its 7 is Qin (Tl), copper ν, ^ « 1 Λ , , ' and δ. It is worth noting that the fourth layer 4 and the bump metal layer 115 are formed. After the circuit board 130 is completed, it is carried out.
接著，於石夕晶圓励之第二表面1〇4可選擇性地進行晶圓 薄化製程’以將碎晶圓刚縮減至適當的厚度。請配合參照圖 1D與圖1E在晶圓薄化製程中，首先，研磨石夕晶圓削之第 二表面104’以形成研磨表面（圖未示）。研磨碎晶圓⑽的 方法，例如是利用銑削（mining)、磨削（grinding)或研磨 (polishing)等方法。然後，蝕刻矽晶圓1〇〇之研磨表面，從而 獲知經薄化之石夕晶圓100’。經薄化之石夕晶圓1〇〇,具有與第一 表面102相對之第二表面104,。 請參照圖1F至圖II，之後，於矽晶圓1〇〇中形成至少一 矽穿孔20貫通第一表面1〇2與第二表面1〇4。本實施例中， 由於選擇進行了晶圓薄化製程，因此係於薄化之矽晶圓100, 中形成矽穿孔20貫通第一表面1〇2與經薄化之第二表面1〇4，。 具體地’形成矽穿孔20貫通第一表面1〇2與第二表面104, 之方法’請先參照圖1F，形成通孔22貫通矽晶圓之第一表面 與經薄化之矽晶圓1〇〇，之第二表面ι〇4，，且暴露出第一線 路基板110中位於最下層之部分第一導電線路層114。然後， 於矽晶圓100’之第二表面104,形成絕緣層24,以覆蓋經薄化 之石夕晶圓100’之第二表面104’以及通孔22之侧壁。本實施例 中，係以先沈積後蝕刻之方式形成絕緣層24，請參照圖1G， 先於石夕晶圓100,之第二表面104,順應性地化學氣相沈積絕緣 201203480 材料’覆蓋經薄化之石夕晶圓100’之第二表面104,、部分第一 導電線路層114以及通孔22之側壁。之後，請參照圖iH，姓 刻移除位於部分第一導電線路層114上的絕緣材料，從而形成 絕緣層24。本實施例中，絕緣材料為二氧化矽（Si02)。請參 照圖II ’絕緣層24形成之後’再將導電材料填入通孔22中，Then, the wafer thinning process can be selectively performed on the second surface 1〇4 of the Shixi wafer to reduce the shredded wafer to a proper thickness. Referring to FIG. 1D and FIG. 1E, in the wafer thinning process, first, the second surface 104' of the lithographic wafer is ground to form an abrasive surface (not shown). The method of grinding the wafer (10) is, for example, a method of mining, grinding, or polishing. Then, the polished surface of the wafer 1 is etched to obtain the thinned silicon wafer 100'. The thinned silicon wafer has a second surface 104 opposite the first surface 102. Referring to FIG. 1F to FIG. II, at least one of the through holes 20 is formed in the tantalum wafer 1 through the first surface 1〇2 and the second surface 1〇4. In this embodiment, since the wafer thinning process is selected, the tantalum perforation 20 is formed in the thinned wafer 100, and the first surface 1〇2 and the thinned second surface 1〇4 are formed. . Specifically, the method of forming the through-holes 20 through the first surface 1〇2 and the second surface 104 is as follows. Referring first to FIG. 1F, the through-holes 22 are formed through the first surface of the wafer and the thinned wafer 1 Then, the second surface ι 4, and exposing a portion of the first conductive substrate layer 114 located in the lowermost layer of the first circuit substrate 110. Then, on the second surface 104 of the wafer 100', an insulating layer 24 is formed to cover the second surface 104' of the thinned wafer 100' and the sidewalls of the via 22. In this embodiment, the insulating layer 24 is formed by first depositing and etching. Referring to FIG. 1G, prior to the second surface 104 of the Shixi wafer 100, the chemical vapor deposition insulating 201203480 material is covered. The second surface 104 of the thinned silicon wafer 100', a portion of the first conductive wiring layer 114, and sidewalls of the via 22 are formed. Thereafter, referring to Fig. iH, the insulating material on the portion of the first conductive wiring layer 114 is removed by the last name to form the insulating layer 24. In this embodiment, the insulating material is cerium oxide (SiO 2 ). Referring to FIG. II 'after the formation of the insulating layer 24', the conductive material is filled into the through hole 22,
开>成石夕穿孔（through silicon via，TSV ) 20，以使矽穿孔20電 f生連接至第一線路基板11〇中位於最下層之第一導電線路層 114。本實施例中，為簡化製程，可形成導電層26於絕緣層 24上並填入通孔22中，導電層26可作為後續第二線路基板 130之第二導電線路層134之一，並可採用電鍍的方法形成， 在此不予詳述。在其他實施例中，亦可先形成電鍍種子層（未 圖示)於通孔22中，電鑛種子層的材料例如是鈦或銅，再採用 電錢法將導電材料填人通孔巾，形^^穿孔2〇。 繼之，請參照圖1J，於絕緣層24上形成多層第二介電層 132以及夕層第二導電線路層134，第二介電層132與第二導 134交替疊合形成第二線路基板13()。且第二線路基The through silicon via (TSV) 20 is opened to electrically connect the via hole 20 to the first conductive line layer 114 located at the lowermost layer of the first circuit substrate 11A. In this embodiment, in order to simplify the process, the conductive layer 26 may be formed on the insulating layer 24 and filled in the through hole 22, and the conductive layer 26 may serve as one of the second conductive circuit layers 134 of the subsequent second circuit substrate 130, and It is formed by electroplating and will not be described in detail here. In other embodiments, a plating seed layer (not shown) may be formed in the through hole 22, and the material of the electric ore seed layer is, for example, titanium or copper, and the conductive material is filled into the through-hole towel by the electric money method. Shape ^^ perforation 2〇. Then, referring to FIG. 1J, a plurality of second dielectric layers 132 and a second conductive circuit layer 134 are formed on the insulating layer 24. The second dielectric layer 132 and the second conductive layer 134 are alternately stacked to form a second circuit substrate. 13(). Second line base
連接於上層之第二導電線路層134 (導電層26)電性 層134;之係錄。其中’第二線路基板130之第二導電線路 i路㈣ΐί錢騎米級，例如銅線路線距可為3微米，鎳 採用-般的線;^t導電線路層114之佈線密i ’因此可 括無機材料。裝階段製作完成。第二介電層132包 等，但並不以此、=料包括石夕氧化物、石夕氮化物或石夕基材料 接著’請參昭_】τ, 路基板12〇，以俘t1K，形成第二保護層140，覆蓋第二線 味邊暴露於第二線路基板130外的第二導電線 201203480 路層134 ^第二保護層140例如為綠漆或者防焊漆。之後，在 本實施例中，如圖1K所示，形成第二開口 142於第二保護層 140中，例如移除部分第二保護層14〇以暴露出部分第二導電 線路層134，從而使得第二導電線路層134可實現與電路板的 電性連接。形成第二開口 142之方法可採用黃光或蝕刻製程， 在此不予詳述。此外，為了使第二導電線路層134與電路板有 更好的連接，請參照圖1L，還可形成導電層15〇於第二保護 層140上，並填入第二開口 142中，以使導電層15〇電連接於 位於最下層之第二導電線路層134。導電層150可採用電鍍或 沈積的方法形成，在此不予詳述。導電層15〇係用以與電路板 電性連接。請繼續參照圖1L，即為由上述方法製作完成石夕基 基板10。具體地，矽基基板10包括矽晶圓1〇〇，、第一線路基 板110以及第二線路基板13〇β矽晶圓1〇〇’具有貫通第一表面 102與第二表面104,之石夕穿孔2〇β第一線路基板u〇設置於石夕 晶圓100,之第一表面102,並由多層第一介電層112以及多層 第-導電線路層114交替疊合而成。第二線路基板13〇設置於 矽晶圓1〇〇,之第二表面104,，並由多層第二介電層132以及 鲁多層第二導電線路層134交替疊合而成。石夕穿孔2〇分別電性 連接第-線路基板11〇中位於最下層之第一導電線路層114與 第二線路基板13G中位於最上層之第二導電線路層134。且第 -導電線路層m之佈線密度Α於第二導電線路層134之佈線 密度：此外’第-介電層112與第二介電層132包括無機材料。 請參照圖2，繪示本發明第二實施例之石夕基基板i〇a。石夕 基基板10a與石夕基絲1〇結構基本上相似，區別在於第一介 電層112包括無機材料，而第二介電層ma包括有機材料。 無機材料包括石夕氧化物、石夕氮化物或石夕基材料，有機材料包括 201203480 電=:以:為限。第一導電線路層114 之材質需求合理佈設。例如第-導電線路層U::=: J層 大於或等於第二導電線路層134之佈線密度。力線迷、度可 優點知上舰，本㈣之魏基㈣錢作方法至少具有以下 1.由於位於梦晶圓相對兩側之第—線路 1之ΐ電線路層之佈線密度不同，或者位於矽晶圓相;、L路 基板與第二線路基板之介電層材料不同，= 於與⑽綱線，使得用 电丨王遝接之第一線路基板之第一導Connected to the upper second conductive wiring layer 134 (conductive layer 26) electrical layer 134; Wherein the second conductive substrate i of the second circuit substrate 130 (four) ΐ 钱 money riding meters, for example, the copper line line spacing can be 3 microns, nickel uses a general line; ^ t conductive circuit layer 114 wiring dense i 'so Including inorganic materials. The loading stage is completed. The second dielectric layer 132 is packaged, etc., but does not include, the material includes a stone oxide, a stone nitride or a stone base material, followed by 'see _ τ, τ, the substrate 12 〇, to capture t1K, The second protective layer 140 is formed to cover the second conductive line 201203480, the second protective layer 140 is exposed to the second wiring substrate 130. The second protective layer 140 is, for example, green paint or solder resist. Thereafter, in the present embodiment, as shown in FIG. 1K, a second opening 142 is formed in the second protective layer 140, for example, a portion of the second protective layer 14 is removed to expose a portion of the second conductive wiring layer 134, thereby The second conductive circuit layer 134 can be electrically connected to the circuit board. The method of forming the second opening 142 may employ a yellow light or etching process, which will not be described in detail herein. In addition, in order to make the second conductive circuit layer 134 have a better connection with the circuit board, referring to FIG. 1L, a conductive layer 15 may be formed on the second protective layer 140 and filled in the second opening 142, so that The conductive layer 15 is electrically connected to the second conductive wiring layer 134 located at the lowermost layer. The conductive layer 150 may be formed by plating or deposition, and will not be described in detail herein. The conductive layer 15 is used to electrically connect to the circuit board. Referring to Fig. 1L, the scotch substrate 10 is completed by the above method. Specifically, the ruthenium-based substrate 10 includes a ruthenium wafer 1 〇〇, and the first circuit substrate 110 and the second circuit substrate 13 〇β矽 wafer 1 〇〇' have a stone penetrating the first surface 102 and the second surface 104. The first via substrate 2 is disposed on the first surface 102 of the Shihua wafer 100, and is formed by alternately laminating a plurality of first dielectric layers 112 and a plurality of first conductive layer 114. The second circuit substrate 13 is disposed on the second wafer 104, and is formed by alternately laminating a plurality of second dielectric layers 132 and a plurality of second conductive wiring layers 134. The shixi through holes 2 are electrically connected to the second conductive circuit layer 134 located at the uppermost layer among the first conductive circuit layer 114 located at the lowermost layer and the second circuit substrate 13G. Further, the wiring density of the first conductive layer m is smaller than the wiring density of the second conductive wiring layer 134: Further, the 'first dielectric layer 112 and the second dielectric layer 132 include inorganic materials. Referring to FIG. 2, a stone base substrate i〇a according to a second embodiment of the present invention is illustrated. The stone base substrate 10a is substantially similar to the stone base structure, except that the first dielectric layer 112 includes an inorganic material and the second dielectric layer ma includes an organic material. Inorganic materials include Shi Xi oxide, Shi Xi nitride or Shi Xi base materials, and organic materials include 201203480 electricity =: limited to: . The material requirements of the first conductive circuit layer 114 are reasonably arranged. For example, the first conductive layer U::=: J layer is greater than or equal to the wiring density of the second conductive wiring layer 134. The force line fan, the degree can be known to the ship, the (four) Weiji (four) money method has at least the following 1. Because the first line on the opposite side of the dream wafer - line 1 of the electrical circuit layer wiring density is different, or located矽 wafer phase; the L-channel substrate is different from the dielectric layer material of the second circuit substrate, and is the first guide of the first circuit substrate connected to the (10) line.
程製作’可比用於與電路板電性連接之C 節約i作成!線路層具有較高之佈線密度，並還有助於 3.第一線路基板採用無機材料製作 電層，滿足‘作不= 線路層與第二導電線路層之需要。 本發明已以較佳實施例揭露如上，然:其並非用以限定 内，當可作^此動技血藝^，在不脫離本發明之精神和範圍 附之申請專準因此本發明之保護範圍當視後 【圖式簡單說明】 … 作方圖為本發明第-實施例之石夕基基板之製 圖2繪示為本發明第二實施例之梦基基板剖面示意圖。 201203480 【主要元件符號說明】 10、10a :矽基基板 100、100’ ：矽晶圓 102 :第一表面 104、104’ ：第二表面 110 :第一線路基板 112 :第一介電層 114 :第一導電線路層 115 :凸塊金屬層 120 :第一保護層 122 :第一開口 130 :第二線路基板 132、132a :第二介電層 134 :第二導電線路層 140 :第二保護層 142 :第二開口 150 :導電層 20 :矽穿孔 22 :通孔 24 :絕緣層 26 :導電層The process can be compared with the C used for electrical connection with the circuit board to save i! The circuit layer has a higher wiring density, and also contributes to 3. The first circuit substrate is made of inorganic material to make an electric layer, which satisfies 'do not= The need for a circuit layer and a second conductive circuit layer. The present invention has been disclosed in the above preferred embodiments. However, it is not intended to limit the scope of the invention, and the present invention may be applied without departing from the spirit and scope of the invention. 2 is a schematic view of the base substrate of the second embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the base substrate of the second embodiment of the present invention. 201203480 [Description of main component symbols] 10, 10a: 矽 base substrate 100, 100': 矽 wafer 102: first surface 104, 104': second surface 110: first circuit substrate 112: first dielectric layer 114: First conductive wiring layer 115: bump metal layer 120: first protective layer 122: first opening 130: second wiring substrate 132, 132a: second dielectric layer 134: second conductive wiring layer 140: second protective layer 142: second opening 150: conductive layer 20: tantalum perforation 22: through hole 24: insulating layer 26: conductive layer