TW201201327A - Semiconductor storage device and manufacturing method thereof - Google Patents
Semiconductor storage device and manufacturing method thereof Download PDFInfo
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- TW201201327A TW201201327A TW100104972A TW100104972A TW201201327A TW 201201327 A TW201201327 A TW 201201327A TW 100104972 A TW100104972 A TW 100104972A TW 100104972 A TW100104972 A TW 100104972A TW 201201327 A TW201201327 A TW 201201327A
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Abstract
Description
201201327 六、發明說明： 【發明所屬之技術領域】 本實施形態通常係關於一種半導體記憶裝置及其製造方 法。 • 本申請案主張2010年2月15日申請之曰本專利申請案 • 20^-30350號及2010年9月30日申請之日本專利申請案 2010-222469號之優先權，該等日本專利申請案之全文援 用於本申請案中。 【先前技術】 近年來，作為行動電話或個人電腦等電子機器之記憶裝 置’多用使用有NAND(反及閘）型快閃記憶體等記憶元件 之半導體記憶裝置。作為電子機器中使用之半導體記憶裝 置，可例示記憶卡（半導體記憶卡）。 於半導體記憶裝置中，半導體記憶體晶片或控制器201201327 VI. Description of the Invention: TECHNICAL FIELD This embodiment relates to a semiconductor memory device and a method of manufacturing the same. The present application claims the priority of Japanese Patent Application No. 2010-222469, filed on Feb. 15, 2010, which is hereby incorporated by reference. The full text of the case is used in this application. [Prior Art] In recent years, as a memory device for an electronic device such as a mobile phone or a personal computer, a semiconductor memory device using a memory element such as a NAND (anti-gate) type flash memory has been used. As a semiconductor memory device used in an electronic device, a memory card (semiconductor memory card) can be exemplified. In a semiconductor memory device, a semiconductor memory chip or controller
導體晶片之電極係應用線結合而與配線基板之連接 連接’進而以覆蓋半導體晶片整體之方式^以樹脂密封。The electrodes of the conductor wafer are bonded to the wiring substrate by application of a wire, and are further sealed with a resin so as to cover the entire semiconductor wafer.
連接， 於此種半導體記憶裝置之使用之普及中，半導體記則 置之製造成本之拍J制朮陆A H ,.. I54062.doc 201201327 造成本之抑制效果易於受到限定 【發明内容】 本發明提供-種可抑制有機基板之使用I而實現製造成 本之抑制之半導體記憶裝置及其製造方法。 根據實施形態，可提供一種半導體記憶裝置，其包含： 有機基板，其係於一面設置有外部連接端子，且單片化成 與》又置有外連接端子之區域大致相同之平面形狀，·導線 架，其具有對有機基板相對地定位之載置區域；及半導體 記憶體晶片，其係接著於載置區域。 根據另實施態樣，可提供一種半導體記憶裝置之製造 方法，其係將形成有外部連接端子之有機基板單片化成與 形成有上述外部連接端子之區域大致相同之平面形狀，將 具有載置區域之導線架之一部分對上述有機基板相對地定 位，且於上述載置區域配置半導體記憶體晶片。 根據本發明，可抑制有機基板之使用量而實現製造成本 之抑制。 【實施方式】 以下，參照隨附圖式對實施形態之半導體記憶裝置及其 製造方法進行詳細說明^再者，本發明並不藉由該等實施 形態而受到限定。又，說明中之導線架無需為42合金或a 等導電性材料，為非導電性之材料亦可達成相同之目的。 圖1係表示第1實施形態之半導體記憶裝置之外觀之平面 圖。圖2係表示圖丨所示之半導體記憶裝置之外觀之仰視 圖。圖3係模式性地表示圖！所示之半導體記憶裝置之内部 154062.doc 201201327 構成之圖。圖4係表示沿圖1所示之半導體記憶裝置之a 線之剖面構造之橫剖面圖。半導體記憶裝置1〇例如為微 SD(Secure Digita卜安全數位）卡（註冊商標）。 半導體記憶裝置10包含有機基板1丨、導線架13、半導體 記憶體晶片15、控制器晶片16、電子零件17、及樹脂模具 部1 8而構成。如圖1、2所示，半導體記憶裝置丨〇以使外部 連接端子19露出於底面側之狀態，將其外周由樹脂模具部 18所覆蓋。 有機基板11係於例如絕緣性樹脂基板之内部或表面設置 有配線網者，且兼作元件搭載基板及端子形成基板。作為 此種有機基板11，係使用印刷配線板，該印刷配線板使用 有玻璃-環氧樹脂或BT樹脂（雙馬來醢亞胺-三嗪樹脂）等。 雖省略詳細之圖示，但存在有機基板丨〗為多層構造，且對 應各層使用之材料不同之情形。 圖5係有機基板丨丨之仰視圖。於有機基板n之底面（一 面）1 la設置有包含金屬層之外部連接端子19。外部連接端 子19成為半導體記憶裝置1G之輸人輸出端子β機基板^ 單片化成與設置有外部連接端子19之區域s大致相同之平 面形狀。 有機基板11之上表面llb(另-面）成為搭載控制器晶片16 及電子零件17之搭載面。因此，有機基板"之上表面川 之面積較控制器晶片16及電子零件17之自上表面觀察之面 積更大。有機基板U為多層構造，且具有形成有内部配線 之配線層。於有機基板W上表面m形成有複數個連接 154062.doc 201201327 墊（未圖示）。連接墊與外部連接端子19之間、或連接墊間 之間，經由形成於有機基板丨丨之配線層之内部配線（亦包 含通孔等）而電性連接。藉由將半導體記憶體晶片15及控 制器晶片16之電極墊（未圖示）與連接墊電性連接，而半導 體s己憶體晶片15、控制器晶片16、外部連接端子19等各要 素電性連接。 此處，複數個連接墊中之連接於半導體記憶體晶片15之 連接墊’以與導線架13側對向之方式，配置於外部連接端 子19並排之方向上。又，複數個連接墊中之連接於控制器 晶片16之連接墊，係配置於控制器晶片i 6之電極墊附近。 其結果’可直接藉由金屬線28將半導體記憶體晶片15之電 極墊與配置於有機基板11之上表面連接墊加以連 接。又，可直接藉由金屬線27將控制器晶片16之電極墊及 配置於有機基板11之上表面lib之連接墊加以連接。 又，複數個連接墊中之電性連接於半導體記憶體晶片15 之連接塾之間距大致為80〜150 μηι左右，電性連接於控制 器晶片1 6之連接墊之間距大致為50~ 120 μιη左右，即，較 之電性連接於半導體記憶體晶片15之連接墊之間距，電性 連接於控制器晶片16之連接墊之間距更小。 圖6係導線架13之平面圖。導線架13係使用較用於有機 基板11之材料更相對低價之通用材料、例如42Alloy(合金） 或銅而構成。導線架13具有記憶體晶片載置部（載置 部）21、基板接著部22、及連結部23。 記憶體晶片載置部21係用以載置半導體記憶體晶片15之 154062.doc 201201327 區域。於該記憶體晶片載置部21之周圍，以自記憶體晶片 載置部2 1延伸之方式，形成有基板接著部22及連結部23。 基板接著部22為接著於有機基板11之上表面ub之區域》 此處’藉由將基板接著部22接著於有機基板11之上表面 lib，可不使基板接著部22與外部連接端子19發生干涉而 接著。又，藉由將基板接著部22之端部（未連接於記憶體 晶片載置部2 1之側之端部）配置於有機基板丨丨内，於半導 體記憶裝置10之最終形狀中，基板接著部22(導線架13)不 會自配置有外部連接端子19之側之侧面露出。其結果，於 將半導體記憶裝置10插入至連接器時，可降低連接器之端 子與導線架13誤接觸之可能性。藉由將基板接著部22接著 於有機基板11之上表面1 lb，記憶體晶片載置部2 1於俯視 時疋位於自有機基板11偏離之位置。又，於有機基板丨1之 厚度較厚，且連接器之端子與導線架13之誤接觸之虞較低 之情形時，記憶體晶片載置部21亦可兼用作為導線架之基 板接著部22與連結部23。 然而，亦存在記憶體晶片載置部21直接與有機基板11接 著之情形（圖3B)。其結果，即便於半導體記憶體晶片15之 晶片面積變大之情形時，亦無需使半導體記憶裝置1〇之大 小增大。特別於如微SD卡（註冊商標）般外形之大小由規格 決定之情形時有效。又，藉由記憶體晶片載置部21直接與 有機基板11接著，有機基板丨丨與導線架13之接著面積變 大，從而可強化有機基板11與導線架13之接著力。又，於 記憶體晶片載置部21與有機基板部22直接接著之情形時， 154062.doc 201201327 亦存在半導體記憶體晶片15與有機基板部22自上方觀察而 重疊之情形。 連結部23將記憶體晶片載置部21間加以連結。雖省略圖 不，但導線架13以複數個記憶體晶片載置部21藉由連結部 23連結之方式構成。如上所述，藉由使複數個記憶體晶片 載置部21連結，可一併製造多個半導體記憶裝置1〇。於圖 6中，將半導體記憶裝置1 〇之外形以二點鍵線表示。連結 部23中之自半導體記憶裝置10之外形突出之剩餘部13&， 最終被切斷並去除。 半導體s己憶體晶片1 5為NAND型快閃記憶體等記憶元 件。半導體記憶體晶片〗5於其丨邊具有複數個電極墊。半 導體記憶體晶片15之電極墊之間距大致為8〇 μπι左右以 上，有機基板11之複數個連接墊中之電性連接於半導體記 憶體晶片1 5之連接墊，配合半導體記憶體晶片J 5而大致形 成為80〜150 μπι。於記憶體晶片載置部21上，積層有複數 個半導體記憶體晶片1 5 »複數個半導體記憶體晶片i 5中之 最下層之半導體記憶體晶片15相對於記憶體晶片載置部2 j 而藉由接著材料25接著。作為接著材料25，例如使用將普 通之聚醢亞胺樹脂、環氧樹脂、丙稀酸樹脂等作為主成分 之熱固性或光固性之晶粒黏著膜（接著劑膜）或者液狀材 料。 於接著於s己憶體晶片載置部21之最下層之半導體記憶體 晶片15上，將另一半導體記憶體晶片15接著成階梯狀，藉 此積層複數個半導體記憶體晶片15。藉由將半導體記憶體 154062.docIn the spread of the use of such a semiconductor memory device, the semiconductor device is placed at a manufacturing cost, and the suppression effect of the semiconductor device is easily limited. [Invention] The present invention provides A semiconductor memory device capable of suppressing the use of an organic substrate and suppressing the manufacturing cost, and a method of manufacturing the same. According to an embodiment, there is provided a semiconductor memory device comprising: an organic substrate provided with an external connection terminal on one side, and singulated into a planar shape substantially the same as a region in which an external connection terminal is provided, and a lead frame And having a mounting region for relatively positioning the organic substrate; and a semiconductor memory wafer followed by the mounting region. According to another embodiment, a method of manufacturing a semiconductor memory device in which an organic substrate on which an external connection terminal is formed is formed into a planar shape substantially the same as a region in which the external connection terminal is formed, and a mounting region is provided One of the lead frames is positioned opposite to the organic substrate, and the semiconductor memory chip is disposed in the mounting region. According to the present invention, the amount of use of the organic substrate can be suppressed to achieve the suppression of the manufacturing cost. [Embodiment] Hereinafter, a semiconductor memory device and a method of manufacturing the same according to the embodiments will be described in detail with reference to the accompanying drawings, and the present invention is not limited by the embodiments. Further, the lead frame in the description does not need to be a conductive material such as 42 alloy or a, and the same purpose can be achieved for a non-conductive material. Fig. 1 is a plan view showing the appearance of a semiconductor memory device according to a first embodiment. Fig. 2 is a bottom plan view showing the appearance of the semiconductor memory device shown in Fig. 2. Figure 3 is a schematic representation of the figure! The internal structure of the semiconductor memory device shown is 154062.doc 201201327. Figure 4 is a cross-sectional view showing a cross-sectional structure taken along line a of the semiconductor memory device shown in Figure 1. The semiconductor memory device 1 is, for example, a micro SD (Secure Digita) digital card (registered trademark). The semiconductor memory device 10 includes an organic substrate 1A, a lead frame 13, a semiconductor memory chip 15, a controller wafer 16, an electronic component 17, and a resin mold portion 18. As shown in Figs. 1 and 2, the semiconductor memory device 覆盖 has its outer periphery exposed to the bottom surface side, and its outer periphery is covered by the resin mold portion 18. The organic substrate 11 is, for example, a wiring net provided inside or on the surface of an insulating resin substrate, and also serves as a component mounting substrate and a terminal forming substrate. As such an organic substrate 11, a printed wiring board using a glass-epoxy resin or a BT resin (bismaleimide-triazine resin) or the like is used. Although the detailed illustration is omitted, the organic substrate is a multilayer structure, and the materials used for the respective layers are different. Figure 5 is a bottom view of the organic substrate. An external connection terminal 19 including a metal layer is provided on the bottom surface (one surface) 1 la of the organic substrate n. The external connection terminal 19 becomes the input terminal of the semiconductor memory device 1G, and the substrate is formed into a substantially planar shape similar to the region s in which the external connection terminal 19 is provided. The upper surface 11b (other surface) of the organic substrate 11 serves as a mounting surface on which the controller wafer 16 and the electronic component 17 are mounted. Therefore, the area of the upper surface of the organic substrate is larger than that of the controller wafer 16 and the electronic component 17 as viewed from the upper surface. The organic substrate U has a multilayer structure and has a wiring layer in which internal wiring is formed. A plurality of connections 154062.doc 201201327 pads (not shown) are formed on the upper surface m of the organic substrate W. The connection pads and the external connection terminals 19 or between the connection pads are electrically connected via internal wiring (including via holes or the like) formed in the wiring layer of the organic substrate. By electrically connecting the semiconductor memory chip 15 and the electrode pads (not shown) of the controller wafer 16 to the connection pads, the semiconductor s memory wafer 15, the controller wafer 16, and the external connection terminals 19 are electrically charged. Sexual connection. Here, the connection pads s connected to the semiconductor memory chip 15 among the plurality of connection pads are disposed in the direction in which the external connection terminals 19 are arranged side by side so as to face the lead frame 13 side. Further, among the plurality of connection pads, the connection pads connected to the controller wafer 16 are disposed near the electrode pads of the controller chip i6. As a result, the electrode pads of the semiconductor memory chip 15 and the connection pads disposed on the upper surface of the organic substrate 11 can be directly connected by the metal wires 28. Further, the electrode pads of the controller wafer 16 and the connection pads disposed on the upper surface lib of the organic substrate 11 can be directly connected by the metal wires 27. Moreover, the distance between the connection pads electrically connected to the semiconductor memory chip 15 in the plurality of connection pads is approximately 80 to 150 μηι, and the distance between the connection pads electrically connected to the controller wafer 16 is approximately 50 to 120 μm. The distance between the connection pads electrically connected to the controller chip 16 is smaller than the distance between the connection pads electrically connected to the semiconductor memory chip 15. Figure 6 is a plan view of the lead frame 13. The lead frame 13 is constructed using a relatively low-cost general-purpose material such as 42 Alloy or copper, which is used for the organic substrate 11. The lead frame 13 has a memory chip mounting portion (mounting portion) 21, a substrate connecting portion 22, and a connecting portion 23. The memory chip mounting portion 21 is for mounting a region of the 154062.doc 201201327 of the semiconductor memory chip 15. A substrate rear portion 22 and a connecting portion 23 are formed around the memory chip mounting portion 21 so as to extend from the memory chip mounting portion 21. The substrate bonding portion 22 is a region following the upper surface ub of the organic substrate 11. Here, by the substrate bonding portion 22 being followed by the upper surface lib of the organic substrate 11, the substrate bonding portion 22 and the external connection terminal 19 can be prevented from interfering. And then. Further, by arranging the end portion of the substrate bonding portion 22 (the end portion not connected to the side of the memory chip mounting portion 21) in the organic substrate, in the final shape of the semiconductor memory device 10, the substrate is next The portion 22 (the lead frame 13) is not exposed from the side surface on the side where the external connection terminal 19 is disposed. As a result, when the semiconductor memory device 10 is inserted into the connector, the possibility that the terminal of the connector is in erroneous contact with the lead frame 13 can be reduced. By adhering the substrate bonding portion 22 to the upper surface 1 lb of the organic substrate 11, the memory chip mounting portion 21 is located at a position deviated from the organic substrate 11 in a plan view. Further, when the thickness of the organic substrate 丨1 is thick and the erroneous contact between the terminal of the connector and the lead frame 13 is low, the memory chip mounting portion 21 can also serve as the substrate subsequent portion 22 of the lead frame. And the connecting portion 23. However, there is also a case where the memory chip mounting portion 21 is directly attached to the organic substrate 11 (Fig. 3B). As a result, even when the area of the wafer of the semiconductor memory chip 15 is increased, it is not necessary to increase the size of the semiconductor memory device 1. It is effective in the case where the size of the shape such as the micro SD card (registered trademark) is determined by the specifications. Further, by directly following the organic wafer 11 with the memory chip mounting portion 21, the area of the organic substrate 丨丨 and the lead frame 13 is increased, and the adhesion between the organic substrate 11 and the lead frame 13 can be enhanced. When the memory chip mounting portion 21 and the organic substrate portion 22 are directly connected to each other, the semiconductor memory chip 15 and the organic substrate portion 22 overlap each other as viewed from above when 154062.doc 201201327. The connecting portion 23 connects the memory chip mounting portions 21 to each other. Although the drawing is omitted, the lead frame 13 is configured such that a plurality of memory chip mounting portions 21 are coupled by a connecting portion 23. As described above, by connecting a plurality of memory chip mounting portions 21, a plurality of semiconductor memory devices 1 can be collectively manufactured. In Fig. 6, the semiconductor memory device 1 is formed by a two-point key line. The remaining portion 13 & of the connecting portion 23 which protrudes from the outside of the semiconductor memory device 10 is finally cut and removed. The semiconductor s memory chip 15 is a memory element such as a NAND type flash memory. The semiconductor memory chip 5 has a plurality of electrode pads on its sides. The distance between the electrode pads of the semiconductor memory chip 15 is approximately 8 〇μπι or more, and the plurality of connection pads of the organic substrate 11 are electrically connected to the connection pads of the semiconductor memory chip 15 to match the semiconductor memory chip J 5 . It is roughly formed to be 80 to 150 μπι. On the memory chip mounting portion 21, a plurality of semiconductor memory chips 15 and a plurality of semiconductor memory chips 15 of the plurality of semiconductor memory chips i 5 are laminated with respect to the memory chip mounting portion 2j. This is followed by the subsequent material 25. As the adhesive material 25, for example, a thermosetting or photocurable die attach film (adhesive film) or a liquid material containing a general polyimine resin, an epoxy resin, an acrylic resin or the like as a main component is used. On the semiconductor memory chip 15 which is the lowermost layer of the suffix wafer mounting portion 21, another semiconductor memory chip 15 is formed in a stepped shape, thereby stacking a plurality of semiconductor memory chips 15. By using semiconductor memory 154062.doc
S 201201327 晶片1 5積層成階梯狀，可使設置於半導體記憶體晶片丨5之 一邊側之電極墊露出。又，各個半導體記憶體晶片15之配 置有電極墊之邊以與有機基板11對向之方式積層。該所露 出之電極墊藉由Au線等金屬線27而與有機基板丨丨之連接墊 電性連接（線結合）^ 控制器晶片16係搭載於有機基板11之上表面丨丨卜。控制 器晶片16自複數個半導體記憶體晶片15中選擇進行資料之 寫入或讀取之半導體記憶體晶片15。控制器晶片16進行向 所選擇之半導體記憶體晶片15寫入資料、或讀取記憶於所 選擇之半導體記憶體晶片1 5中之資料等。於控制器晶片i 6 之上表面，形成有電極墊（未圖示）。又，控制器晶片16之 複數個電極墊係配置於控制器晶片16之周邊。控制器晶片 16具有之電極墊之數量較半導體記憶體晶片15具有之電極 墊之數量更多。又，控制器晶片16具有之電極墊之間距大 致為30〜1〇〇 μιη左右，較有機基板u之複數個連接墊中之 電性連接於控制器晶片1 6之連接墊之間距更窄。此處，控 制器晶片16之電極墊與有機基板u之連接墊藉由金屬線28 而線結合。 電子零件17係搭載於有機基板11之上表面lib。電子零 件17為例如晶片電容、電阻、或電感。此處，藉由將電子 零件Π配置於有機基板"上，可不藉由金屬線加以連接， 而疋經由有機基板之内部配線而與半導體記憶體晶片15、 及控制器晶片16電性連接。其結果，可降低半導體記憶裝 置10之寄生電容、寄生電阻。 I54062.doc 201201327 樹脂模具部18藉由將有機基板丨丨之上表面iib&導線架 13之兩面利用樹脂系材料密封而形成。利用樹脂材料僅將 有機基板11之上表面llb密封，藉此使外部連接端子19露 出於外部。樹脂模具部18構成半導體記憶裝置10之外殼。 樹脂模具部18以完全地覆蓋半導體記憶體晶片15及控制器 晶片16之高度形成。樹脂模具部18藉由如下而形成：利用 模具將安裝有半導體記憶體晶片15等安裝零件之有機基板 11及導線架13覆蓋，將經軟化之樹脂系材料注入至該模具 内。 其次，對半導體記憶裝置10之製造步驟進行說明。圖7 係用以說明半導體記憶裝置10之製造步驟之流程圖。圖8〜 圖13係用以說明半導體記憶裝置丨〇之製造步驟之圖。 首先，將有機基板11單片化成與區域3大致相同之平面 形狀（步驟S1)。有機基板“之單片化係藉由使用切割刀片 (未圖示）之通常之步驟進行’故而省略詳鈿之說明。其 次，於導線架13之基板接著部22塗佈接著劑30(步驟S2， 亦參照圖8)。作為接著劑3 〇，例如使用將普通之聚醢亞胺 樹脂、環氧樹脂、丙烯酸樹脂等作為主成分之熱固性或光 固性之晶粒黏著膜（接著劑膜）或者液狀材料。再者，於記 憶體晶片載置部21與有機基板1丨直接接著之情形時，亦可 於記憶體晶片載置部21之與有機基板11接觸之部分塗佈接 著劑30(參照圖8B)。 其次’使有機基板11之上表面lib接著於塗佈有接著劑 30之基板接著部22(步驟S3，亦參照圖9)。其次，於有機 10- 154062.docS 201201327 The wafers 1 are stacked in a stepped manner, and the electrode pads provided on one side of the semiconductor memory chip cassette 5 can be exposed. Further, each of the semiconductor memory chips 15 is disposed so that the sides of the electrode pads are laminated to face the organic substrate 11. The exposed electrode pad is electrically connected (wire bonded) to the connection pad of the organic substrate by a metal wire 27 such as an Au wire. The controller wafer 16 is mounted on the upper surface of the organic substrate 11. The controller chip 16 selects a semiconductor memory chip 15 for writing or reading data from a plurality of semiconductor memory chips 15. The controller wafer 16 performs writing of data to the selected semiconductor memory chip 15, or reading of data stored in the selected semiconductor memory chip 15 and the like. An electrode pad (not shown) is formed on the upper surface of the controller chip i6. Further, a plurality of electrode pads of the controller wafer 16 are disposed around the controller wafer 16. The controller wafer 16 has a larger number of electrode pads than the semiconductor memory chip 15 has. Moreover, the controller wafer 16 has a distance between the electrode pads of about 30 to 1 μm, which is narrower than a connection between the plurality of connection pads of the organic substrate u and the connection pads electrically connected to the controller wafer 16. Here, the connection pads of the electrode pads of the controller wafer 16 and the organic substrate u are line bonded by the metal wires 28. The electronic component 17 is mounted on the upper surface lib of the organic substrate 11. The electronic component 17 is, for example, a chip capacitor, a resistor, or an inductor. Here, by disposing the electronic component 于 on the organic substrate, the semiconductor memory chip 15 and the controller wafer 16 can be electrically connected to each other via the internal wiring of the organic substrate without being connected by a metal wire. As a result, the parasitic capacitance and parasitic resistance of the semiconductor memory device 10 can be reduced. I54062.doc 201201327 The resin mold portion 18 is formed by sealing both surfaces of the upper surface of the organic substrate iib & lead frame 13 with a resin-based material. Only the upper surface 11b of the organic substrate 11 is sealed with a resin material, whereby the external connection terminal 19 is exposed to the outside. The resin mold portion 18 constitutes an outer casing of the semiconductor memory device 10. The resin mold portion 18 is formed to completely cover the heights of the semiconductor memory chip 15 and the controller wafer 16. The resin mold portion 18 is formed by covering the organic substrate 11 on which the components such as the semiconductor memory wafer 15 are mounted and the lead frame 13 by a mold, and injecting the softened resin material into the mold. Next, the manufacturing steps of the semiconductor memory device 10 will be described. FIG. 7 is a flow chart for explaining the manufacturing steps of the semiconductor memory device 10. 8 to 13 are views for explaining the manufacturing steps of the semiconductor memory device. First, the organic substrate 11 is singulated into a substantially planar shape similar to the region 3 (step S1). The singulation of the organic substrate is performed by a usual procedure using a dicing blade (not shown). Therefore, the detailed description is omitted. Next, the adhesive 30 is applied to the substrate subsequent portion 22 of the lead frame 13 (step S2) Refer to Fig. 8). As the adhesive agent 3, for example, a thermosetting or photocurable die attach film (adhesive film) using a general polyimine resin, an epoxy resin, an acrylic resin or the like as a main component is used. In the case where the memory wafer mounting portion 21 and the organic substrate 1 are directly connected to each other, the adhesive 30 may be applied to the portion of the memory wafer mounting portion 21 that is in contact with the organic substrate 11. (Refer to Fig. 8B) Next, 'the upper surface lib of the organic substrate 11 is followed by the substrate subsequent portion 22 to which the adhesive 30 is applied (step S3, see also Fig. 9). Secondly, in the organic 10-154062.doc
S 201201327 基板11之上表面lib安裝控制器晶片16及電子零件17(步驟 S4，亦參照圖10p其次，使半導體記憶體晶片15經由接 著材料25接著於記憶體晶片載置部21，進而於其上方接著 半導體§己憶體晶片1 5，從而使半導體記憶體晶片丨5積層 (步驟S5，亦參照圖11)。 其次，藉由金屬線27、28將半導體記憶體晶片15之電極 墊與有機基板11之連接墊、及控制器晶片16之電極墊與有 機基板11之連接墊進行線結合（步驟S6，亦參照圖^ 2)。其 次，藉由樹脂系材料將有機基板丨1之上表面1丨b及導線架 13之兩面密封，從而形成樹脂模具部18 ,並切除剩餘部 13a(步驟S7，亦參照圖13)。再者，於圖13中，為了便於說 明，亦表示覆蓋於樹脂模具部18而實際上無法目視確認之 内部之構成（半導體記憶體晶片15等）。藉由上述一連串之 步驟，製造半導體記憶裝置1 〇。 圖14係模式性地表示作為先前例之半導體記憶裝置1〇〇 之内部構成之圖。圖15係表示圖14所示之半導體記憶裝置 100之剖面構造之橫剖面圖。如圖14、圖15所示，於先前 之半導體記憶裝置1〇〇中，將半導體記憶體晶片115積層於 有機基板111上。因此，以包含用以載置半導體記憶體晶 片115之區域之大小形成有機基板ιη。另一方面，於第1 實施形態之半導體記憶裝置10中，將有機基板丨丨單月化成 於俯視時與設置有外部連接端子19之區域S大致相同之平 面形狀，半導體記憶體晶片15配置於導線架13上。因此， 與先前例相比’可大幅抑制有機基板之使用量，從而可實 154062.doc •11 · 201201327 現半導體記憶裝置10之製造成本之抑制。 又，由於將導線架13接著於有機基板n，故而有機基板 U與記憶體晶片載置部21之相對之位置關係得以決定。藉 此，可不發生因半導體記憶體晶片15與有機基板u之位置 偏移引起之、線結合步驟中之施工不良而抑制良率之降 低。又，由於有機基板11與導線架13最終藉由樹脂模具部 18所密封，故而對有機基板"與導線架13之接著不會要求 較咼之可靠性，只要兩者之接著維持至樹脂模具部丨8之形 成步驟為止即可。 控制器晶片16與半導體記憶體晶片15相比，形成之電極 墊之數量易於變多。又，控制器晶片16與半導體記憶體晶 片15相比，自上表面觀察之平面形狀容易形成得較小。因 此’用以將控制器晶片1 6進行線結合之電極墊及連接墊， 與用以將半導體記憶體晶片1 5進行線結合之電極塾及連接 墊相比’更密集地形成。於第1實施形態中，將控制器晶 片16安裝於有機基板11上而並非導線架13上，故而即便於 密集地形成有電極墊及連接墊之條件下，亦可確實地進行 線結合。另一方面’用以半導體記憶體晶片15之線結合之 電極墊及連接墊係其間隔相對較寬。因此，半導體記憶體 晶片15之線結合相對容易，從而即便將半導體記憶體晶片 15安裝於導線架π上亦可進行線結合。 又，由於將控制器晶片16及電子零件17安裝於有機基板 11之上表面lib，故而可使有機基板11之底面lla側、即形 成有外部連接端子19之側大致平坦。藉此，可有利於半導S 201201327 The controller wafer 16 and the electronic component 17 are mounted on the upper surface lib of the substrate 11 (step S4, and also referring to FIG. 10p, the semiconductor memory chip 15 is subsequently attached to the memory chip mounting portion 21 via the bonding material 25, and further The semiconductor CMOS wafer 15 is then overlaid to stack the semiconductor memory wafer (5 (step S5, see also Fig. 11). Next, the electrode pads of the semiconductor memory chip 15 are organically etched by the metal lines 27, 28. The connection pads of the substrate 11 and the electrode pads of the controller wafer 16 are bonded to the connection pads of the organic substrate 11 (step S6, see also FIG. 2). Secondly, the upper surface of the organic substrate 丨1 is made of a resin-based material. 1丨b and both sides of the lead frame 13 are sealed to form the resin mold portion 18, and the remaining portion 13a is cut off (step S7, see also Fig. 13). Further, in Fig. 13, for convenience of explanation, it is also shown to cover the resin. The inside of the mold portion 18 is not visually confirmed (the semiconductor memory chip 15 or the like). The semiconductor memory device 1 is manufactured by the above-described series of steps. Fig. 14 is a schematic representation of FIG. 15 is a cross-sectional view showing a cross-sectional structure of the semiconductor memory device 100 shown in FIG. 14. As shown in FIGS. 14 and 15, the conventional semiconductor memory device is shown in FIG. In the first embodiment, the semiconductor memory wafer 115 is laminated on the organic substrate 111. Therefore, the organic substrate ι is formed to include the size of the region in which the semiconductor memory wafer 115 is placed. In the semiconductor memory device 10, the organic substrate is formed into a planar shape substantially the same as the region S in which the external connection terminals 19 are provided in a plan view, and the semiconductor memory chip 15 is placed on the lead frame 13. Therefore, the conventional memory device 10 is placed on the lead frame 13. Compared with 'the amount of use of the organic substrate can be greatly suppressed, the manufacturing cost of the semiconductor memory device 10 can be suppressed. In addition, since the lead frame 13 is attached to the organic substrate n, the organic substrate U is The positional relationship with respect to the memory chip mounting portion 21 is determined. Thereby, the semiconductor memory chip 15 and the organic substrate u do not occur. The positional deviation causes the construction failure in the wire bonding step to suppress the decrease in the yield. Further, since the organic substrate 11 and the lead frame 13 are finally sealed by the resin mold portion 18, the organic substrate "and the lead frame 13 are Then, reliability is not required, as long as the two are maintained until the formation step of the resin mold portion 8. The number of electrode pads formed by the controller wafer 16 compared with the semiconductor memory wafer 15 is easy. Further, the controller wafer 16 is formed to have a smaller planar shape as viewed from the upper surface than the semiconductor memory chip 15. Therefore, the electrode pads and the connection pads for bonding the controller wafer 16 to the wires are provided. And formed more densely than the electrode pads and the connection pads for bonding the semiconductor memory wafers 15 in line. In the first embodiment, since the controller wafer 16 is mounted on the organic substrate 11 instead of the lead frame 13, the wire bonding can be surely performed even under the condition that the electrode pads and the connection pads are densely formed. On the other hand, the electrode pads and the connection pads for bonding the wires of the semiconductor memory chip 15 are relatively wide. Therefore, the wire bonding of the semiconductor memory chip 15 is relatively easy, so that the wire bonding can be performed even if the semiconductor memory chip 15 is mounted on the lead frame π. Further, since the controller wafer 16 and the electronic component 17 are mounted on the upper surface lib of the organic substrate 11, the side of the bottom surface 11a of the organic substrate 11, that is, the side on which the external connection terminal 19 is formed, can be made substantially flat. Thereby, it can be beneficial to semi-conducting
154062.doc •12- S 201201327 體記憶裝置Η)之小型化。又，藉由減少半導體記憶裝置ι〇 之外周面之凹凸，可有利於實現向半導體記憶裝置ι〇之電 子機器之順利之插入、抽出。 又，外部連接端子19、半導體記憶體晶片15、控制器晶 片16及電子零件17係經由有機基板丨丨之内部配線而連接。 即，半導體記憶體晶片15、控制器晶片16及電子零件口不 經由引線零件而電性連接。藉此，剩餘部13a之切除部分 於樹脂模具部18之外側面露出，但可省略對該部分進行絕 緣處理等之工時，從而可更進一步抑制半導體記憶裝置ι〇 之製造成本。 又，藉由將有機基板11之平面形狀小型化，可抑制因電 子零件17之安裝步驟等中對有機基板u施加之熱引起之有 機基板11之變形。如上所述，存在有機基板丨丨為多層構 造，且對應各層使用之材料不同之情形。因對應各層材料 不同，故對應各層線膨服係數亦不同，因此易於發生因熱 歷程引起之變形。此處，藉由將有機基板u之平面形狀小 型化，佔據於半導體記憶裝置10整體之有機基板丨丨之比例 少’從而可使半導體記憶裝置1〇整體中之變形不易發 生。 再者，記憶體晶片載置部21與有機基板11之相對之位置 關係之決定並不限定於藉由接著導線架丨3進行之情形。例 如’亦可將有機基板11與導線架13分別固定於用以形成樹 脂模具部18之模具。藉由將有機基板^與導線架13固定於 模具’而決定彼此之相對之位置關係。 154062.doc -13- 201201327 再者，於第1實施形態中，列舉在記憶體晶片載置部21 上積層複數個半導體記憶體晶片1 5之例進行了說明，但並 不限定於此，亦可僅使1塊半導體記憶體晶片15接著於記 憶體晶片載置部21上而構成半導體記憶裝置1〇。 又，於第1實施形態中，列舉導線架13中之連結部23向 較樹脂模具部1 8更向外侧突出之例進行了說明，但並不限 定於此，亦能以基板接著部22向樹脂模具部18之外側突出 之方式構成。例如’亦能以基板接著部22向夾持有機基板 11之記憶體晶片載置部21之相反側突出而與鄰接之記憶體 晶片載置部連接之方式構成。 又，於利用使用有非導電性之材料（例如，聚萘二甲酸 二乙醋或聚對苯二曱酸乙二酯）之導線架13之情形時，即 便向導線架13之樹脂模具部18之外側突出之部分與插入半 導體s己憶裝置10之插口誤接觸，亦可破實地防止與半導體 。己隐體晶片15之短路。其原因在於，由於導線架I]為非導 電性’故而配置於基板接著部22上之半導體記憶體晶片15 與插口可電性分離。 又’半導體記憶裝置10之製造步驟並不限定於圖7之流 程圖所示之情形。例如，亦可於將有機基板u接著於導線 架1 3之前，將控制器晶片16及電子零件安裝於有機基板 11。又，亦可於將有機基板u單片化之前，將控制器晶片 16與電子零件安裝於有機基板η。 又，於第1實施形態中，以將微SD卡作為半導體記憶裝 置1〇為例進行了說明，但並不限定於此，可於包含半導體 I54062.doc -14· 201201327 記憶體晶片而構成之各種記憶裝置中應用本實施形態。 圖16係模式性地表示第2實施形態之半導體記憶裝置之 内部構成之平面圖。圖17係表示沿圖16所示之半;體記憶 裝置之B-B線之剖面構造的橫剖面圖。再者，對與上述^ 施形態相同之構成賦予相同之符號並省略詳細之說明。 又，第2實施形態之半導體記憶裝置15〇之外觀與上°述第i 實施形態大致相同’故而亦省略外觀圖。，圖“係與圖 3相同地省略樹脂模具部18而進行圖示。 半導體記憶裝置150包含有機基板u、非導電性支持基 板153、半導體記憶體晶片15、控制器晶片丨6、電子零件 17、及樹脂模具部18而構成。 非導電性支持基板153具有與第丨實施形態之半導體記憶 裝置10之外形大致相同之形狀，但於配置有有機基板此 部分具有開口 155。有機基板丨丨於開口 155之至少i邊之 邊，經由接著劑131而與非導電性支持基板153連接。又， 於第2面153b，於有機基板丨丨之上表面Ub，自開口 155露 出控制器晶片16與電子零件17，半導體記憶體晶片15之電 極墊與有機基板11之連接墊、及控制器晶片16之電極墊與 有機基板11之連接墊係藉由金屬線27、28而連接。又，於 第1面153a中，有機基板11之外部連接端子19自樹脂模具 部18露出。 以下，一面說明半導體記憶裝置15〇之製造步驟說明， 一面對上述不同點進行說明。圖18係用以說明半導體記憶 裝置150之製造步驟之流程圖。圖丨9係自第i面丨53a側觀察 154062.doc -15- 201201327 非導電性支持基板153之圖。圖20〜圖24係用以說明半導體 記憶裝置15〇之製造步驟之圖。 非導電性支持基板153係使用非導電性之材料、例如聚 萘二甲酸二乙酯或聚對苯二甲酸乙二酯等樹脂材料之板構 件。於圖19中，表示僅形成有1個成為半導體記憶裝置ι5〇 之最終製品形狀之製品區域158的狀態之非導電性支持基 板153 ’但亦可使用形成有複數個製品區域158之1塊較大 之非導電性支持基板153。 於非導電性支持基板153之第1面153a側，設置有所要接 著有機基板11之接著區域154。首先，於該接著區域154之 一部分形成開口 155(步驟S11)。 然後，於形成有開口 155之接著區域154接著有機基板 11(步驟S12)。於圖20中，表示自第2面153b觀察非導電性 支持基板153之狀態。如圖20或圖21所示，由於於接著區 域154形成有開口 155，因此於將有機基板11之上表面ilb 側接著於接著區域154後，有機基板11之上表面lib之一部 分亦自開口 155露出。 其次，於自開口 155所露出之有機基板11之上表面Ub安 裝控制器晶片16及電子零件17(步驟S13，亦參照圖22)。 於非導電性支持基板153之第2面153b側，設置有在不與開 口 155重疊之位置積層半導體記憶體晶片15之記憶體晶片 載置部156。於該記憶體晶片載置部156積層半導體記憶體 晶片15(步驟S14，亦參照圖23)。 其次，藉由金屬線27、28將半導體記憶體晶片15之電極 154062.doc154062.doc •12- S 201201327 Body memory device Η) miniaturization. Further, by reducing the unevenness on the outer peripheral surface of the semiconductor memory device, it is possible to facilitate the smooth insertion and extraction of the electronic device to the semiconductor memory device. Further, the external connection terminal 19, the semiconductor memory chip 15, the controller wafer 16, and the electronic component 17 are connected via the internal wiring of the organic substrate. That is, the semiconductor memory chip 15, the controller wafer 16, and the electronic component port are electrically connected without being connected via a lead component. Thereby, the cut portion of the remaining portion 13a is exposed on the outer surface of the resin mold portion 18. However, the number of man-hours for performing the insulating treatment on the portion can be omitted, and the manufacturing cost of the semiconductor memory device can be further suppressed. Further, by miniaturizing the planar shape of the organic substrate 11, deformation of the organic substrate 11 due to heat applied to the organic substrate u in the mounting step of the electronic component 17 or the like can be suppressed. As described above, there is a case where the organic substrate is in a multi-layered structure and the materials used for the respective layers are different. Since the material of each layer is different, the coefficient of expansion corresponding to each layer is also different, so deformation due to thermal history is apt to occur. Here, by miniaturizing the planar shape of the organic substrate u, the proportion of the organic substrate 占据 which is occupied by the entire semiconductor memory device 10 is small, so that deformation of the entire semiconductor memory device 1 can be prevented from occurring. Further, the determination of the positional relationship between the memory chip mounting portion 21 and the organic substrate 11 is not limited to the case where the lead frame 3 is subsequently used. For example, the organic substrate 11 and the lead frame 13 may be respectively fixed to a mold for forming the resin mold portion 18. The relative positional relationship of each other is determined by fixing the organic substrate and the lead frame 13 to the mold '. 154062.doc -13-201201327 In the first embodiment, an example in which a plurality of semiconductor memory chips 15 are stacked on the memory chip mounting portion 21 has been described. However, the present invention is not limited thereto. Only one semiconductor memory chip 15 can be connected to the memory chip mounting portion 21 to constitute the semiconductor memory device 1 . In the first embodiment, the example in which the connecting portion 23 of the lead frame 13 protrudes outward from the resin mold portion 18 has been described. However, the present invention is not limited thereto, and the substrate rear portion 22 may be used. The resin mold portion 18 is configured to protrude from the outside. For example, the substrate substrate 22 can be formed so as to protrude from the opposite side of the memory chip mounting portion 21 sandwiching the organic substrate 11 and to be connected to the adjacent memory chip mounting portion. Further, in the case of using the lead frame 13 using a non-conductive material (for example, polyethylene naphthalate or polyethylene terephthalate), even the resin mold portion 18 of the wire guide 13 The portion protruding outside is mistakenly contacted with the socket inserted into the semiconductor device 10, and the semiconductor can be prevented from being broken. The short circuit of the hidden wafer 15 has been completed. This is because the lead frame I] is non-conductive, so that the semiconductor memory chip 15 disposed on the substrate connecting portion 22 can be electrically separated from the socket. Further, the manufacturing steps of the semiconductor memory device 10 are not limited to those shown in the flowchart of Fig. 7. For example, the controller wafer 16 and the electronic component may be mounted on the organic substrate 11 before the organic substrate u is attached to the lead frame 13. Further, the controller wafer 16 and the electronic component may be mounted on the organic substrate η before the organic substrate u is singulated. Further, in the first embodiment, the microSD card has been described as an example of the semiconductor memory device 1A. However, the present invention is not limited thereto, and may be formed of a memory chip including a semiconductor I54062.doc -14·201201327. This embodiment is applied to various memory devices. Fig. 16 is a plan view schematically showing the internal structure of the semiconductor memory device of the second embodiment. Figure 17 is a cross-sectional view showing the cross-sectional structure taken along the line B-B of the bulk memory device taken along the half shown in Figure 16; The same components as those in the above-described embodiments are denoted by the same reference numerals, and the detailed description thereof will be omitted. Further, the appearance of the semiconductor memory device 15 of the second embodiment is substantially the same as that of the first embodiment described above. Therefore, the external view is also omitted. In the same manner as in Fig. 3, the resin mold portion 18 is omitted. The semiconductor memory device 150 includes an organic substrate u, a non-conductive support substrate 153, a semiconductor memory chip 15, a controller wafer cassette 6, and an electronic component 17. The non-conductive support substrate 153 has substantially the same shape as the semiconductor memory device 10 of the second embodiment, but has an opening 155 in the portion where the organic substrate is disposed. The side of at least the i side of the opening 155 is connected to the non-conductive support substrate 153 via the adhesive 131. Further, on the second surface 153b, the controller wafer 16 is exposed from the opening 155 on the upper surface Ub of the organic substrate The electronic component 17, the connection pad of the electrode pad of the semiconductor memory chip 15 and the organic substrate 11, and the connection pad of the electrode pad of the controller wafer 16 and the organic substrate 11 are connected by the metal wires 27 and 28. In the one surface 153a, the external connection terminal 19 of the organic substrate 11 is exposed from the resin mold portion 18. Hereinafter, the description of the manufacturing steps of the semiconductor memory device 15 will be described. Fig. 18 is a flow chart for explaining the manufacturing steps of the semiconductor memory device 150. Fig. 9 is a view of the non-conductive support substrate 153 as viewed from the side of the i-th face 53a 154062.doc -15-201201327 20 to 24 are diagrams for explaining the manufacturing steps of the semiconductor memory device 15. The non-conductive support substrate 153 is made of a non-conductive material such as polyethylene naphthalate or polyethylene terephthalate. A plate member of a resin material such as a diester. Fig. 19 shows a non-conductive support substrate 153' in which only one product region 158 which is a final product shape of the semiconductor memory device 形成5 is formed. A large non-conductive support substrate 153 of a plurality of product regions 158. On the first surface 153a side of the non-conductive support substrate 153, a subsequent region 154 to be followed by the organic substrate 11 is provided. First, in the subsequent region An opening 155 is formed in one of the portions 154 (step S11). Then, the organic substrate 11 is adhered to the succeeding region 154 in which the opening 155 is formed (step S12). In Fig. 20, the non-conductive property is observed from the second surface 153b. The state of the substrate 153 is supported. As shown in FIG. 20 or FIG. 21, since the opening 155 is formed in the succeeding region 154, after the upper surface ilb side of the organic substrate 11 is followed by the succeeding region 154, the upper surface lib of the organic substrate 11 is formed. A part of the substrate 155 is exposed from the opening 155. Next, the controller wafer 16 and the electronic component 17 are mounted on the upper surface Ub of the organic substrate 11 exposed from the opening 155 (step S13, see also Fig. 22). The non-conductive support substrate 153 On the second surface 153b side, a memory chip mounting portion 156 in which the semiconductor memory chip 15 is laminated without overlapping the opening 155 is provided. The semiconductor memory chip 15 is laminated on the memory chip mounting portion 156 (step S14, see also Fig. 23). Next, the electrode of the semiconductor memory chip 15 is 154062.doc by the metal lines 27, 28.
S 201201327 墊與有機基板11之連接墊、及控制器晶片16之電極墊與有 機基板11之連接墊進行線結合（步驟S15，亦參照圖24)。藉 此，有機基板11之配線層與半導體記憶體晶片15電性連 接。 其次’藉由樹脂系材料將非導電性支持基板153之兩面 密封’從而形成樹脂模具部18，並切除自製品區域158突 出之部分（步驟S16)。藉此，製造圖16或圖17所示之半導 體記憶裝置150。再者，將有機基板11單片化成與區域 S(亦參照圖5)大致相同之形狀之步驟等係與第丨實施形態 相同地進行。 如以上說明，於第2實施形態中，由於將有機基板1 i單 片化成與區域S大致相同之平面形狀，因而可大幅抑制有 機基板之使用量，從而可實現半導體記憶裝置15〇之製造 成本之抑制。 又’由於藉由接著劑131使有機基板η接著於非導電性 支持基板153，故而決定有機基板丨丨與記憶體晶片載置部 15 6之相對之位置關係。藉此，可減少因半導體記憶體晶 片15與有機基板11之位置偏移引起之線結合步驟中之施工 不良。其結果’可抑制良率之降低。再者，由於有機基板 Π之整個周圍係經由接著劑13 1而與非導電性支持基板153 接著，故而可有效地防止半導體記憶體晶片15與有機基板 11之位置偏移β又，由於有機基板11與·非導電性支持基板 153最終藉由樹脂模具部18予以密封，故而對有機基板u 與非導電性支持基板153之接著不會要求較高之可靠性。 154062.doc 17 201201327 至少’有機基板11與非導電性支持基板153兩者之接著只 要維持至樹脂模具部18之形成步驟為止即可。 又，由於將控制器晶片16及電子零件17安裝於有機基板 11之上表面lib，故而可使有機基板η之底面丨^側、即形 成有外部連接端子19之側大致平坦。藉此，可有助於半導 體記憶裝置15 0之小型化。又，藉由減少半導體記憶裝置 15〇之外周面之凹凸’可有助於實現向半導體記憶裝置15〇 之電子機器之順利之插入、抽出。又，上表面1 1 b位於較 第2面153b更靠第1面153a側。因此，可說控制器晶片16及 電子零件17之底面位於較半導體記憶體晶片15之底面更低 之位置（第1面153a側）。其結果，控制器晶片丨6及電子零件 17可使用其高度相對較高者。 又’藉由將有機基板11之平面形狀小型化，可抑制因電 子零件17之安裝步驟等中對有機基板丨丨施加之熱引起之有 機基板11之變形。如上所述，有機基板U為多層構造，會 有各層所使用之材料不同之情形。因各層之材料不同，故 各層之線膨脹係數亦不同，因此容易發生因熱歷程引起之 變形。此處，藉由將有機基板11之平面形狀小型化，佔據 半導體記憶裝置150整體之有機基板丨丨之比例變少，從而 可使半導體記憶裝置150整體之變形不易發生。 又’非導電性支持基板153由非導電性之材料構成。因 此’即便於半導體記憶裝置15〇之外周面露出之非導電性 支持基板153、與供半導體記憶裝置15〇插入之插口誤接 觸，亦可確實地防止與半導體記憶體晶片15之短路。其原 154062.doc • 18 - 201201327 因在於’由於非導電性支持基板153為非導電性，故而可 將積層於記憶體晶片載置部156之半導體記憶體晶片叫 插口電性分離。 ^ 再者，於第2實施形態中，列舉在記憶體晶片冑置部ΐ56 上積層複數個半導體記憶體晶片15之例進行了說明，但並 不限定於此，亦可僅使丨塊半導體記憶體晶片15接著於記 憶體晶片載置部156上而構成半導體記憶裝置15〇。 又，半導體記憶裝置15〇之製造步驟並不限定於圖18之 流程圖所示之情形。例如，亦可於將有機基板丨丨接著於非 導電性支持基板153之前，將控制器晶片16及電子零件17 安裝於有機基板11。又，亦可於將有機基板丨丨單片化之 前，將控制器晶片16及電子零件17安裝於有機基板u。 圖25係表示第2實施形態之變形例1之半導體記憶裝置 150所具備之非導電性支持基板153。於本變形例！中，除 接著區域154外，於記憶體晶片載置部156亦形成有開口 159 ° 圖26係具備圖25所示之非導電性支持基板i 53之半導體 s己憶裝置150之剖面圖，且係相當於表示沿圖16之8_8線之 剖面構造之橫剖面圖者β如圖26所示’開口 159較半導體 記憶體晶片15小一圈，半導體記憶體晶片15之周圍經由接 著材料25而與非導電性支持基板153連接。其結果，半導 體記憶體晶片15之背面（與非導電性支持基板1 53對向之面） 中’其一部分藉由開口 159露出。藉由於記憶體晶片載置 部156形成開口 159 ’覆蓋非導電性支持基板153之第1面 154062.doc •19· 201201327 153a之樹脂模具部18不僅與非導電性支持基板153接觸， 亦與半導體記憶體晶片15之背面接觸。 例如，於構成樹脂模具部18之樹脂材料與半導體記憶體 晶片15之密著力較構成樹脂模具部丨8之樹脂材料與非導電 性支持基板153之密著力更高之情形時，如本變形例丨般構 成而使樹脂模具部18與半導體記憶體晶片15接觸，藉此可 提高樹脂模具部1 8之密著力。藉此，樹脂模具部〗8難以自 非導電性支持基板153浮起或剝落。 向記憶體晶片載置部156之開口 159之形成亦可與例如步 驟S11所示之開口 155之形成同時進行。其結果，可將步驟 簡化。 圖27係表示第2實施形態之變形例2之半導體記憶裝置 150包含之非導電性支持基板153的平面圖。於本變形例2 中，於除接著區域154及記憶體晶片载置部156外之區域， 以跨越製品區域158之外緣之方式形成有開口 16〇。又，開 口 160沿製品區域158之外緣形成有複數個。又，於本變形 例2中’製品區域1 58與其以外之區域以一部分而連結。 圖28係包含圖27所示之非導電性支持基板ι53之半導體 s己憶裝置150之剖面圖，且係相當於表示沿圖丨6之B B線之 剖面構造之橫剖面圖。於本變形例2中，如圖28所示，以 不與開口 1 5 5之一部分（開口 1 5 5與非導電性支持基板丨5 3邊 界之一部分）重疊之方式，藉由接著劑131將有機基板11接 著於非導電性支持基板153。更具體而言，於製品區域158 之外緣部分（圖27之有機基板11之與記憶體晶片載置部丨56 154062.docS 201201327 The connection pad of the pad and the organic substrate 11 and the electrode pads of the controller wafer 16 are bonded to the connection pads of the organic substrate 11 (step S15, see also Fig. 24). Thereby, the wiring layer of the organic substrate 11 is electrically connected to the semiconductor memory chip 15. Then, the both sides of the non-conductive support substrate 153 are sealed by a resin material to form the resin mold portion 18, and the portion protruding from the product region 158 is cut out (step S16). Thereby, the semiconductor memory device 150 shown in Fig. 16 or Fig. 17 is manufactured. Further, the step of singulating the organic substrate 11 into a shape substantially the same as that of the region S (see also Fig. 5) is carried out in the same manner as in the third embodiment. As described above, in the second embodiment, since the organic substrate 1 i is formed into a substantially planar shape similar to the region S, the amount of use of the organic substrate can be greatly suppressed, and the manufacturing cost of the semiconductor memory device 15 can be realized. Suppression. Further, since the organic substrate η is followed by the non-conductive support substrate 153 by the adhesive 131, the relative positional relationship between the organic substrate 丨丨 and the memory chip mounting portion 156 is determined. Thereby, the construction failure in the wire bonding step due to the positional deviation of the semiconductor memory chip 15 and the organic substrate 11 can be reduced. As a result, the decrease in yield can be suppressed. Further, since the entire periphery of the organic substrate 接着 is followed by the non-conductive support substrate 153 via the adhesive 13 1 , the positional shift of the semiconductor memory wafer 15 and the organic substrate 11 can be effectively prevented. 11 and the non-conductive support substrate 153 are finally sealed by the resin mold portion 18, so that high reliability is not required for the organic substrate u and the non-conductive support substrate 153. 154062.doc 17 201201327 At least both the organic substrate 11 and the non-conductive support substrate 153 may be maintained until the formation step of the resin mold portion 18. Further, since the controller wafer 16 and the electronic component 17 are mounted on the upper surface lib of the organic substrate 11, the side of the bottom surface of the organic substrate η, that is, the side on which the external connection terminal 19 is formed is substantially flat. Thereby, the miniaturization of the semiconductor memory device 150 can be facilitated. Further, by reducing the unevenness on the outer peripheral surface of the semiconductor memory device 15 可, it is possible to facilitate the smooth insertion and extraction of the electronic device to the semiconductor memory device 15 . Further, the upper surface 1 1 b is located closer to the first surface 153a than the second surface 153b. Therefore, it can be said that the bottom surfaces of the controller wafer 16 and the electronic component 17 are located lower than the bottom surface of the semiconductor memory chip 15 (on the side of the first surface 153a). As a result, the controller wafer cassette 6 and the electronic component 17 can use a relatively high height. Further, by miniaturizing the planar shape of the organic substrate 11, it is possible to suppress deformation of the organic substrate 11 due to heat applied to the organic substrate by the mounting step of the electronic component 17. As described above, the organic substrate U has a multilayer structure, and the materials used for the respective layers may be different. Since the material of each layer is different, the linear expansion coefficients of the layers are also different, so deformation due to thermal history is liable to occur. Here, by miniaturizing the planar shape of the organic substrate 11, the proportion of the organic substrate 占据 which occupies the entire semiconductor memory device 150 is reduced, and deformation of the entire semiconductor memory device 150 is less likely to occur. Further, the non-conductive support substrate 153 is made of a non-conductive material. Therefore, even if the non-conductive support substrate 153 exposed on the peripheral surface of the semiconductor memory device 15 is erroneously contacted with the socket into which the semiconductor memory device 15 is inserted, the short circuit with the semiconductor memory chip 15 can be reliably prevented. The original 154062.doc • 18 - 201201327 is because the non-conductive support substrate 153 is electrically non-conductive, so that the semiconductor memory chip laminated on the memory chip mounting portion 156 can be electrically separated. Further, in the second embodiment, an example in which a plurality of semiconductor memory chips 15 are stacked on the memory chip mounting unit ΐ56 has been described. However, the present invention is not limited thereto, and only the semiconductor memory may be memorized. The bulk wafer 15 is then placed on the memory chip mounting portion 156 to constitute a semiconductor memory device 15A. Further, the manufacturing steps of the semiconductor memory device 15 are not limited to those shown in the flowchart of Fig. 18. For example, the controller wafer 16 and the electronic component 17 may be mounted on the organic substrate 11 before the organic substrate is subsequently attached to the non-conductive support substrate 153. Further, the controller wafer 16 and the electronic component 17 may be mounted on the organic substrate u before the organic substrate is singulated. Fig. 25 is a view showing a non-conductive support substrate 153 included in the semiconductor memory device 150 according to the first modification of the second embodiment. In this variant! In addition to the region 154, an opening 159 is also formed in the memory chip mounting portion 156. FIG. 26 is a cross-sectional view of the semiconductor splicing device 150 including the non-conductive supporting substrate i53 shown in FIG. Corresponding to the cross-sectional view showing the cross-sectional structure along the line 8-8 of Fig. 16, the opening 159 is smaller than the semiconductor memory chip 15 as shown in Fig. 26, and the periphery of the semiconductor memory chip 15 is via the bonding material 25. The non-conductive support substrate 153 is connected. As a result, a part of the back surface of the semiconductor memory wafer 15 (the surface facing the non-conductive support substrate 153) is exposed by the opening 159. The resin mold portion 18 that covers the first surface 154062.doc of the non-conductive support substrate 153 by the opening 159' of the memory wafer mounting portion 156 is not only in contact with the non-conductive support substrate 153 but also with the semiconductor. The back side of the memory chip 15 is in contact. For example, when the adhesion between the resin material constituting the resin mold portion 18 and the semiconductor memory wafer 15 is higher than the adhesion between the resin material constituting the resin mold portion 8 and the non-conductive support substrate 153, the present modification is as described above. The resin mold portion 18 is brought into contact with the semiconductor memory chip 15 in a manner similar to the configuration, whereby the adhesion of the resin mold portion 18 can be improved. Thereby, it is difficult for the resin mold portion 8 to float or peel off from the non-conductive support substrate 153. The formation of the opening 159 to the memory chip mounting portion 156 can also be performed simultaneously with the formation of the opening 155 as shown, for example, in step S11. As a result, the steps can be simplified. Fig. 27 is a plan view showing the non-conductive support substrate 153 included in the semiconductor memory device 150 according to the second modification of the second embodiment. In the second modification, the opening 16 is formed so as to extend beyond the outer edge of the product region 158 in the region other than the region 154 and the memory chip mounting portion 156. Further, the opening 160 is formed in plural along the outer edge of the product region 158. Further, in the second modification, the "product region 158" and the other regions are connected to each other in a part. Fig. 28 is a cross-sectional view showing a semiconductor device 150 including the non-conductive support substrate ι53 shown in Fig. 27, and is a cross-sectional view showing a cross-sectional structure taken along line B B of Fig. 6. In the second modification, as shown in FIG. 28, the adhesive 131 is not overlapped with a portion of the opening 155 (one portion of the boundary between the opening 155 and the non-conductive supporting substrate 丨5 3). The organic substrate 11 is next to the non-conductive support substrate 153. More specifically, the outer edge portion of the product region 158 (the organic substrate 11 of FIG. 27 and the memory chip mounting portion 丨56 154062.doc)
S •20· 201201327 為相反側之邊），以不與開口 155與非導電性支持基板153 之邊界重疊之方式’將有機基板11接著於非導電性支持基 板 153。 藉由如上所述般構成，覆蓋非導電性支持基板丨53之兩 面153a、153b之樹脂模具部18間通過開口 155而成為一 體。因此’樹脂模具部18難以自非導電性支持基板丨53浮 起或剝落。 又，通過開口 160部分而覆蓋兩面153a、1531?之樹脂模 具部1 8間成為一體，從而樹脂模具部1 8難以自非導電性支 持基板153浮起或剝落。再者，若形成有開口 155或開口 160中任—方’則具有樹脂模具部18難以自非導電性支持 基板153浮起或剝落之效果。 圖29係第2實施形態之變形例3之半導體記憶裝置15〇包 3之非導電性支持基板153的平面圖。於本變形例3中，於 除接著區域154及記憶體晶片載置部156外之區域内形成有 開口 161。更具體而言，以包圍記憶體晶片載置部156之方 式形成有複數個開口 161。 圖30係包含圖29所示之非導電性支持基板153之半導體 5己憶裝置150之剖面圖，且係相當於表示沿圖162B b線之 剖面構造之橫剖面圖者。與上述變形例2相同地，覆蓋非 導電性支持基板153之兩面153a、153b之樹脂模具部18間 通過開口 161成為一體，故而樹脂模具部18難以自非導電 性支持基板153浮起或剝落。再者，若開口 161形成於包圍 記憶體晶片載置部156之邊之任一邊，則具有樹脂模具部 154062.doc 21 201201327 1 8難以自非導電性支持基板！ 53浮起或剝落之效果。又， 並非形成1個較大之開口 161，而是形成複數個相對較小之 開口 161，藉此可增強非導電性支持基板153之強度，從而 於進行線結合時，可減少金屬線27之連接不良。 圖3 1係表示第2實施形態之變形例4之半導體記憶裝置 150包含之非導電性支持基板153的平面圖。於本變形例4 中，於記憶體晶片載置部156形成有開口 159，以包圍記憶 體晶片載置部156之周圍之方式形成有開口 161。 圖32係包含圖31所示之非導電性支持基板153之半導體 §己憶裝置150之剖面圖，且係相當於表示沿圖丨6之B_B線之 剖面構造的橫剖面圖者。如圖32所示，通過開口 159而樹 脂模具部18與半導體記憶體晶片15接觸，通過開口 161而 覆蓋非導電性支持基板153之兩面153、153b之樹脂模具部 18間成為一體，因而樹脂模具部18難以自非導電性支持基 板153浮起或剝落。 本變形例4係組合變形例1與變形例3者，且具有兩方之 變形例之效果。 再者，上述實施形態係例示，發明之範圍並不限定於 此。 進一步之效果或變形例可由本領域技術人員容易地導 出。藉此，本發明之更廣泛之態樣並不限定於如上所述般 表不且記述之特定之詳細及代表性之實施形態。因此，可 不脫離藉由隨附之申請專利範圍及其均等物定義之總括性 之發明之概念性精神或範圍而進行各種變更。 154062.docS 20: 201201327 is the opposite side, and the organic substrate 11 is attached to the non-conductive support substrate 153 so as not to overlap the boundary between the opening 155 and the non-conductive support substrate 153. With the above configuration, the resin mold portions 18 covering the both surfaces 153a and 153b of the non-conductive support substrate 丨53 are integrally formed by the openings 155. Therefore, the resin mold portion 18 is less likely to float or peel off from the non-conductive support substrate 丨53. Further, the resin mold portion 18 which covers the both surfaces 153a and 1531 through the opening 160 is integrated, and the resin mold portion 18 is less likely to float or peel off from the non-conductive support substrate 153. Further, when the opening 155 or any one of the openings 160 is formed, the resin mold portion 18 is less likely to float or peel off from the non-conductive support substrate 153. Fig. 29 is a plan view showing the non-conductive support substrate 153 of the semiconductor memory device 15 of the third modification of the second embodiment. In the third modification, the opening 161 is formed in a region other than the region 154 and the memory chip mounting portion 156. More specifically, a plurality of openings 161 are formed in such a manner as to surround the memory chip mounting portion 156. Fig. 30 is a cross-sectional view showing a semiconductor device 5 including the non-conductive support substrate 153 shown in Fig. 29, and corresponds to a cross-sectional view showing a cross-sectional structure taken along line 162B of Fig. 162. In the same manner as in the above-described second modification, the resin mold portions 18 covering the both surfaces 153a and 153b of the non-conductive support substrate 153 are integrated by the openings 161. Therefore, the resin mold portion 18 is less likely to float or peel off from the non-conductive support substrate 153. Further, when the opening 161 is formed on either side of the side surrounding the memory chip mounting portion 156, the resin mold portion 154062.doc 21 201201327 18 is difficult to be supported from the non-conductive support substrate! 53 The effect of floating or peeling off. Moreover, instead of forming one large opening 161, a plurality of relatively small openings 161 are formed, whereby the strength of the non-conductive support substrate 153 can be enhanced, thereby reducing the metal wire 27 when performing wire bonding. Poor connection. Fig. 3 is a plan view showing a non-conductive support substrate 153 included in the semiconductor memory device 150 according to the fourth modification of the second embodiment. In the fourth modification, the memory chip mounting portion 156 is formed with an opening 159, and an opening 161 is formed to surround the periphery of the memory chip mounting portion 156. Fig. 32 is a cross-sectional view showing a semiconductor device 150 including the non-conductive support substrate 153 shown in Fig. 31, and corresponds to a cross-sectional view showing a cross-sectional structure taken along line B_B of Fig. 6. As shown in FIG. 32, the resin mold portion 18 is in contact with the semiconductor memory chip 15 through the opening 159, and the resin mold portion 18 covering the both surfaces 153 and 153b of the non-conductive support substrate 153 through the opening 161 is integrated, and thus the resin mold is formed. The portion 18 is difficult to float or peel off from the non-conductive support substrate 153. In the fourth modification, the first modification and the third modification are combined, and the effects of the two modifications are obtained. Furthermore, the above embodiments are illustrative, and the scope of the invention is not limited thereto. Further effects or modifications can be easily derived by those skilled in the art. Therefore, the broader aspects of the invention are not limited to the specific details and representative embodiments described above. Therefore, various modifications may be made without departing from the spirit and scope of the inventions of the invention. 154062.doc
S •22· 201201327 【圖式簡單說明】 圖1係表示第1實施形態之半導體記憶裝置之外觀之平面 圖； 圖2係表示圖1所示之半導體記憶裝置之外觀之仰視圖； 圖3(A)、（B)係模式性地表示圖示之半導體記憶裝置 之内部構成之圖； 圖4係表示沿圖i所示之半導體記憶裝置之α·α線之剖面 構造之橫剖面圖； 圖5係有機基板之仰視圖； 圖6係導線架之平面圖； 圖7係用以說明半導體記憶裝置之製造步驟之流程圖； 圖8(A)、（Β)係用以說明半導體記憶裝置之製造步驟之 ISI · 圖， 圖9係用以說明半導體記憶裝置之製造步驟之圖； 圖10係用以說明半導體記憶裝置之製造步驟之圖； 圖11係用以說明半導體記憶裝置之製造步驟之圖； 圖12係用以說明半導體記憶裝置之製造步驟之圖； 圖13係用以說明半導體記憶裝置之製造步驟之圖； 圖14係模式性地表示作為先前例之半導體記憶裝置之内 部構成的圖； 圖15係表示圖14所示之半導體記憶裝置之剖面構造之橫 剖面圖； 圖16係模式性地表示第2實施形態之半導體記憶裝置之 内部構成之平面圖； 154062.doc -23· 201201327 圖17係表示沿圖丨6所示之半導體記憶裝置之B-B線之剖 面構造的橫剖面圖； 圖1 8係用以說明半導體記憶裝置之製造步驟之流程圖； 圖19係自第1面側觀察非導電性支持基板之圖， 圖20係用以說明半導體記憶裝置之製造步驟之圖； 圖2 1係用以說明半導體記憶裝置之製造步驟之圖，且係 沿圖20所示之C-C線之箭視剖面圖； 圖22係用以說明半導體記憶裝置之製造步驟之圖； 圖23係用以說明半導體記憶裝置之製造步驟之圖； 圖24係用以說明半導體記憶裝置之製造步驟之圖； 圖25係表示第2實施形態之變形例1之半導體記憶裝置包 含之非導電性支持基板的平面圖； 圖26係包含圖25所示之非導電性支持基板之半導體記憶 裝置之剖面圖； 圖27係表示第2實施形態之變形例2之半導體記憶裝置包 含之非導電性支持基板的平面圖； 圖28係包含圖27所示之非導電性支持基板之半導體記憶 裝置之剖面圖； 圖2 9係表示第2實施形態之變形例3之半導體記憶裝置包 含之非導電性支持基板之平面圖； 圖30係包含圖29所示之非導電性支持基板之半導體記憶 裝置之剖面圖； 圖3 1係表示第2貫施形態之變形例4之半導體記憶裝置包 含之非導電性支持基板的平面圖；及BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing the appearance of a semiconductor memory device according to a first embodiment; Fig. 2 is a bottom view showing the appearance of the semiconductor memory device shown in Fig. 1; Fig. 3 (A) And (B) schematically show the internal structure of the semiconductor memory device shown in the drawing; FIG. 4 is a cross-sectional view showing the cross-sectional structure of the α·α line of the semiconductor memory device shown in FIG. Figure 6 is a plan view showing the manufacturing steps of the semiconductor memory device; Figure 8 (A), (Β) is used to explain the manufacturing steps of the semiconductor memory device. FIG. 9 is a view for explaining a manufacturing step of a semiconductor memory device; FIG. 10 is a view for explaining a manufacturing step of the semiconductor memory device; and FIG. 11 is a view for explaining a manufacturing step of the semiconductor memory device; 12 is a view for explaining a manufacturing step of a semiconductor memory device; FIG. 13 is a view for explaining a manufacturing step of the semiconductor memory device; and FIG. 14 is a view schematically showing a semiconductor memory device as a prior example; FIG. 15 is a cross-sectional view showing a cross-sectional structure of the semiconductor memory device shown in FIG. 14. FIG. 16 is a plan view schematically showing an internal configuration of the semiconductor memory device according to the second embodiment; 154062.doc -23·201201327 FIG. 17 is a cross-sectional view showing a cross-sectional structure taken along line BB of the semiconductor memory device shown in FIG. 6. FIG. 18 is a flow chart for explaining a manufacturing procedure of the semiconductor memory device; FIG. 20 is a view for explaining a manufacturing step of the semiconductor memory device; FIG. 2 is a view for explaining a manufacturing step of the semiconductor memory device, and is a view along the line of FIG. Figure 22 is a diagram for explaining the manufacturing steps of the semiconductor memory device; Figure 23 is a diagram for explaining the manufacturing steps of the semiconductor memory device; Figure 24 is a diagram for explaining the semiconductor memory device; FIG. 25 is a plan view showing a non-conductive support substrate included in the semiconductor memory device according to the first modification of the second embodiment; FIG. 26 is a view showing the non-conductive substrate shown in FIG. FIG. 27 is a plan view showing a non-conductive support substrate included in the semiconductor memory device according to the second modification of the second embodiment; FIG. 28 is a view showing the non-conductive property shown in FIG. FIG. 2 is a plan view showing a non-conductive support substrate included in the semiconductor memory device according to the third modification of the second embodiment; FIG. 30 is a view showing the non-conductive support shown in FIG. FIG. 3 is a plan view showing a non-conductive support substrate included in a semiconductor memory device according to a fourth modification of the second embodiment; and
154062.doc -24· S 201201327 圖32係包3 g 3 1所TF之非導電性支持基板之半導體記憶 裝置之刮面圖。 【主要元件符號說明】 10 ' 100 ' 150 半導體記憶裝置 11 、 111 有機基板 11a 有機基板11之底面 lib 有機基板11之上表面 13 導線架 13a 剩餘部 15 、 115 半導體記憶體晶片 16 控制器晶片 17 電子零件 18 樹脂模具部 19 外部連接端子 21 、 156 記憶體晶片載置部 22 基板接著部 23 連結部 25 接著材料 27 ' 28 金屬線 30 、 131 接著劑 153 非導電性支持基板 153a 第1面 153b 第2面 154 接著區域 154062.doc •25· 201201327 155 、159、 160、 161 開 口 158 製 品區 A-A 、B-B、 C-C 線 S 區 域 SI、 S2 ' S3 、S4 、S5、 步 驟 S6 、 S7 、 Sll 、 S12 、 S13 、 S14 、 S15 、 S16 154062.doc 26154062.doc -24· S 201201327 Figure 32 is a plan view of a semiconductor memory device of a non-conductive support substrate of 3 g 3 1 TF. [Main component symbol description] 10 '100' 150 semiconductor memory device 11, 111 organic substrate 11a bottom surface of organic substrate 11 lib upper surface 13 of organic substrate 11 lead frame 13a remaining portion 15, 115 semiconductor memory chip 16 controller wafer 17 Electronic component 18 Resin mold portion 19 External connection terminal 21, 156 Memory chip mounting portion 22 Substrate adhesion portion 23 Connection portion 25 Next material 27' 28 Metal wire 30, 131 Next agent 153 Non-conductive support substrate 153a First surface 153b Second face 154 Next area 154062.doc •25· 201201327 155, 159, 160, 161 Opening 158 Product area AA, BB, CC line S Area SI, S2 'S3, S4, S5, step S6, S7, S11, S12 , S13, S14, S15, S16 154062.doc 26
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI621232B (en) * | 2016-03-15 | 2018-04-11 | Toshiba Memory Corp | Semiconductor device |
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