201201256 六、發明說明： 【發明所屬之技術領域】 置的製程，特別是關於形成積體 本發明係關於形成積體電路裝 電路裝置中閘極的製程。 【先前技術】 為巾，現今_勢是_不_增加裝置的密度。 度，持續不斷地努力在半導體晶圓上縮小這也裝置 米層級。為了達成如此高的裝置封裝密度；須使 小的特徵尺寸。如此包括互連線猶寬和間距以及例如 疋不同特徵的邊緣及角落的表面幾何輪廓。 產生具有微小間距於相鄰的特徵 來達成。，言，微影 其包括用來製造積體電路的技術，在其中將 感物f(此處稱為光阻)且將較之塗佈表面 暴路於切(例如光學光、x光或是電子束)之下，1 但此i像被^佈甘/、適接收—欲轉換圖案的投影成像。一 又衫，八會無法抹除地形成在塗佈物質上。經由光罩 ===致此成像區域可以或多或少的溶解於二特= 在齡抛中較㈣可溶_域的移除 在土布中遠下較難溶解之高分子的圖案成像。 同的此是所欲職的正像或負像。多年來有著兩種不 =二:ΐ來:正光阻及負光阻。使用正光阻，暴露於光 光、=二口 射·，*使用負光阻’収沒有暴露於 刀日在，揚時被除去。歷史上，負光阻無法在線寬及 201201256 要小於3微米的需求下使用。因此 代負光阻被使用在超大型積體電路(vLSI)裝置的製程中。先取 響使突用起正的固Γ問題可以對積體電路產生致命的影 機制可以在多需=欲見的凹入輪靡。許多已知 層材料具有較快::刻=的較一上 ΐί層特徵中產生凹入輪廓的機制是氧化效應。另 二疊之側壁除了基底以外 廓》此外尚有其他的」此機快很多’導致一凹入的侧壁輪 其已熟知會對單層特應、,及_效應’ 導rr速率差異“者 般而δ，較Α的摻雜濃度階級，則其_速率較快。例 二:=:==rr 產生 導===== 如此的問題造成唯持夕個彼此分開的導電結構發生短路。™ 奈二界尺寸變得十分困難，一5 201201256 【發明内容】 本發明揭露半導體農置及其製造方法。根據 施例’一種製造—半導體裝置財法，包含形成複數層 的閘極結構，㈣該閘極結構，以及在極 μ 二 蚀刻之前進行氬/氧處理，以形成—瓶狀閘極結。構。、最ά又 一在某些實施例中，該閘極結構是多晶石夕。在如此 例中， 紅/乳處理包括氧氣的流量在0到200 SCCM範圍201201256 VI. Description of the Invention: [Technical Field] The present invention relates to a process for forming a gate in an integrated circuit package circuit device. [Prior Art] For the towel, the current situation is _ no _ increase the density of the device. Degree, continuous efforts to shrink the semiconductor level on the semiconductor wafer. In order to achieve such a high package density, small feature sizes are required. This includes the interconnect width and spacing as well as the surface geometry of the edges and corners of different features such as 疋. This is achieved by creating features with tiny spacings adjacent to each other. , whispering, including the technique used to make the integrated circuit, in which the sense f (herein referred to as photoresist) will be traversed by the coated surface (eg optical light, x-ray or Under the electron beam), 1 but this i image is imaged by the ^Bugan/, suitable for receiving-to-convert pattern. Once again, the eight will be formed on the coated material without being erased. Through the mask ===, the imaged area can be more or less dissolved in the second special = in the age of throwing (4) soluble _ domain removal pattern imaging of the polymer that is more difficult to dissolve in the soil cloth. The same is the right or negative image of the job. There have been two kinds of failures over the years = two: ΐ: positive and negative photoresist. Using a positive photoresist, exposure to light, = two-shot, * using a negative photoresist, the exposure is not exposed to the knife, and the time is removed. Historically, negative photoresists have not been able to be used in line widths and 201201256 to be less than 3 microns. Therefore, the negative photoresist is used in the process of a very large integrated circuit (vLSI) device. The first problem is that the solid-state problem that can be used to make a sudden impact can have a fatal shadow mechanism on the integrated circuit. Many known layer materials have a faster::The mechanism of the concave profile in the upper layer of the layer is an oxidation effect. The other two sides of the stack are in addition to the base profile. There are other "this machine is much faster" which results in a recessed sidewall wheel which is well known for single layer specificity, and _effect 'derivative rr rate difference' Generally, δ, the helium doping concentration class, its _ rate is faster. Example 2: =:==rr Produces the derivative ===== This problem causes a short circuit of the conductive structures separated from each other. The size of the TM nanosphere becomes very difficult, a 5 201201256 [Explanation] The invention discloses a semiconductor farm and a manufacturing method thereof. According to the embodiment, a manufacturing-semiconductor device method includes a gate structure for forming a plurality of layers, (4) The gate structure, and argon/oxygen treatment prior to the pole etch, to form a bottle-like gate junction. Finally, in some embodiments, the gate structure is polycrystalline In this case, the red/milk treatment includes oxygen flow in the range of 0 to 200 SCCM.
流量在0到1000 SCCM範圍之間。 a ’ ’ 在某些實施财’該氬/減理包減加_分 到 ;〇〇〇瓦特棚之·能#可賴在丨。到_瓦特 1圍之 間0 在某些實施例中，該閘極結構是石夕化鶴、第一多晶石夕層歲第二 之多層結構。在如此的實施财，該氬/氧處理係在第二 :日料度__)之前進行。替代地，該氬/氧處理係在第 ^的夕晶補度侧(0E1)之前進行。而在另一替代實施例中， 忒虱/虱處理係在矽化鎢過度蝕刻之前進行。 施例中’該閘極結構是金屬閉極。在如此的實施例 =氬/氧處理包純氣的流量在G到⑽細之間，及 在〇到麵SCCM範圍之間。此外，在某些實施例中， =處理包括施加_奸能量在1G到議聽範圍之間 及偏屋能量可運用在1G到期瓦特範圍之間。 旦錢/氧處理也可以非同步地在一餘刻機中進行，且包括氬的流 =運?在0到1000 SCCM範圖之間’氧的流量可運用在0到200 Μ範圍之間，及源極解離分子能量可運用⑺到ι〇〇〇瓦特範 圍之間’偏愿能量可運用丨G到300瓦特範圍之間。 201201256 =發明之另-目的為提供—種半導體裝置之閘極結構 ϊί爲包含—介電層於—半導體基板之上’―第—多晶石夕層二 ”，曰曰之上’以及-第二多晶㈣於該第—多晶梦層之上：心 -户晶梦層與該第二多轉層為具有瓶狀之多層腿結構。" 在某些實施财，職狀結構可以藉由在該閘極 前f于氬/氧處理而形成。在某些實施例中，該閘極 、，，口構疋夕日日石夕。在如此的實施例中，該氯/氧處理包括 s_圍之間，及氬的流量在G到聰‘ 外’在如此的實施例中，該氬/氧處理包括施加解離分子能 d^1000瓦特範圍之間及偏壓能量可運用在10到300瓦 特摩II圍之間。 在某些實施例中，該閘極結構是石夕化鎮、第一多晶石夕層血第二 多晶石夕層^縣構4如此的實施财，錢/氧處理係在第二 -人，夕日日石夕過度敍刻(〇E2)之前進行。替代地，該氬/氧處理係在第 -:广的多晶料度_(〇叫之前進行。❿在另—替代實施例中， 該氬/氧處理係在矽化鎢過度蝕刻之前進行。 在某&些實施例中，該閘極結構是金屬開極。在如此的實施例 中，泫虱/氧處理包括氧氣的流量在〇到2〇〇 SCCM範圍之間，及 氬，流量在G到1咖SCCM範圍之間。此外，在某些實施例中， 錢/氧處理包減加解離奸能量在1()到丨_瓦雜圍之間 及偏壓能量可運用在1〇到300瓦特範圍之間。 本發明之又一目的為提供一種半導體裝置，其包含一第一 多晶石夕結構以及-第二多Μ結構，其中該第—多晶雜構與 该第二多晶梦結構至少—者包括—瓶狀輪磨，其包含自一晶圓 側的帛寬度、-第二寬度於該第—寬度之上，該第二寬度 201201256 大於該第一寬度，一第三寬度於該第二寬度之上，該第二 小於該第二寬度。 又 在某些實施例中 多晶石夕結構之介面。 該第二寬度係位於第一多晶石夕結構與該第二 在某些實施例中，該第二寬度係位於該第一多晶矽結構中。 在某些實施例中，該第二寬度係位於該第二多晶矽結構中。The flow rate is between 0 and 1000 SCCM. a ’ ’ In some implementations, the argon/reduction package is reduced by _ points; 〇〇〇瓦特棚之之# can be relied upon. Between watts and watts 1 In some embodiments, the gate structure is a multi-layered structure of Shi Xihua, the first polycrystalline stone layer and the second. In such an implementation, the argon/oxygen treatment is carried out before the second: day __). Alternatively, the argon/oxygen treatment is carried out before the etched side (0E1). In yet another alternative embodiment, the ruthenium/iridium treatment is performed prior to over-etching of the tungsten telluride. In the embodiment, the gate structure is a metal closed pole. In such an embodiment = argon / oxygen treatment package pure gas flow rate between G to (10) fine, and between the 〇 to the surface SCCM range. Moreover, in some embodiments, the = processing includes applying smuggling energy between 1G and the listening range and the partial house energy can be applied between the 1G expiring watts. Once the money/oxygen treatment can also be carried out asynchronously in a remnant, and including the flow of argon = transport? The flow of oxygen between 0 and 1000 SCCM can be used between 0 and 200 ,, And the source dissociation molecular energy can be used between (7) and ι〇〇〇瓦特's bias energy can be applied between 丨G and 300 watts. 201201256=Inventive--The purpose is to provide a gate structure of a semiconductor device, including a dielectric layer on a semiconductor substrate, a 'polycrystalline slab layer II', a top and a The second polycrystal (4) is above the first polycrystalline dream layer: the heart-occupational dream layer and the second multi-layered layer have a multi-layer leg structure with a bottle shape. " In some implementations, the job structure can be borrowed Formed by argon/oxygen treatment prior to the gate. In some embodiments, the gate, the, and the mouth are in the form of a day. In such an embodiment, the chlorine/oxygen treatment comprises s Between the circumferences, and the flow rate of argon in the G to Cong 'outside' In such an embodiment, the argon/oxygen treatment includes applying dissociation molecules between d^1000 watts and biasing energy of 10 to 300 In some embodiments, the gate structure is Shi Xihua Town, the first polycrystalline stone, the second polycrystalline stone, the Xi layer, the county structure 4, such implementation, money / The oxygen treatment is carried out before the second-person, annihilation of the day (〇E2). Alternatively, the argon/oxygen treatment is in the first:: wide polycrystalline material The argon/oxygen treatment is performed prior to over-etching of the tungsten telluride. In some & embodiments, the gate structure is a metal open. In an embodiment, the helium/oxygen treatment comprises a flow of oxygen between 〇2 〇〇SCCM and argon with a flow between G and 1 café SCCM. Further, in some embodiments, money/ The oxygen treatment package reduces the dissociation energy between 1 () and 丨 _ _ _ _ _ and the bias energy can be used between 1 〇 and 300 watts. A further object of the present invention is to provide a semiconductor device including a first polycrystalline liturgical structure and a second multi-twisted structure, wherein the first polycrystalline heterostructure and the second polycrystalline dream structure comprise, at least, a bottle-shaped wheel grinding, which is included from a wafer side帛 width, - the second width is above the first width, the second width 201201256 is greater than the first width, a third width is above the second width, and the second is smaller than the second width. The interface of the polycrystalline stone structure in some embodiments. The second width is located in the first polycrystal Xi structure and the second In certain embodiments, the width of the second line at the first polysilicon structure. In certain embodiments, the width of the second line located in the second polysilicon structure.
在某些實施例中，該第一多晶矽結構與該第二多晶矽結 是使用-包括氬/氧處理的製程製造，其中該氬/氧 = 離子轟擊和氧分子氧化。 匕枯風 本發明之目的，特徵，和實施例，會在下列實施方 節中搭配圖式被描述。 、』早 【實施方式】 根據本發明所揭露的技術，一包含字元線或類似結構 ，置可以根據-種可以改善製程可靠性的製程被製造 是，此處所揭露的半導體製造紐可喻傳統的半導 但 °根據某些實關，此處所揭露的ΐΐί製 包括於侧之後實施—非同步的氬/氧處理，舉例而^ 曰曰石f間極侧之後’所實施的非同步的氬/氧處理可以有“二 J障擴散氧化結構的高度’將阻障擴散氧:鬥二 處。 、3… t i物’ 且降低後4氧化製】上的難 201201256 第1A圖顯示根據傳統製程用來製造一電 一電晶體於~旦H1 士：In certain embodiments, the first polysilicon structure and the second polysilicon junction are fabricated using a process including argon/oxygen treatment wherein the argon/oxygen = ion bombardment and oxygen molecular oxidation. The purpose, features, and embodiments of the present invention are described in the following embodiments in conjunction with the drawings. [Embodiment] According to the technology disclosed in the present invention, a word line or the like is included, and the process can be manufactured according to a process which can improve the process reliability. The semiconductor manufacturing disclosed herein is a conventional Semi-conducting but according to some implementations, the ΐΐ 制 system disclosed herein is implemented after the side - non-synchronous argon / oxygen treatment, for example, ^ 曰曰 f f inter-electrode side after the implementation of the non-synchronized argon /Oxygen treatment can have "two J barrier diffusion oxidation structure height" will block the diffusion of oxygen: bucket two., 3... ti thing 'and lower 4 oxidation system' on the difficulty 201201256 Figure 1A shows according to the traditional process To make a battery, a transistor, and a H1:
瓜肷的嘴八举皁層112、一底4 阻層116。在一實施例中，第-多晶矽層106是作為字元線。 底部抗反射層(BARC)114及一圖案化光 第一多晶矽層104是作為位元線而第二 此薄膜堆4結構100可以由不同的製程形成，舉例而古包括已 知的沈積製程，作為積體電路製程的—部分。舉例而言此薄膜堆 疊結構可以是製造-記顏元件，例如是動態隨機存取記憶 體(DRAM)元件或是快閃記憶元件，製程的一部分。在某些實施例 中，可以於氧化矽·氮化矽-氧化矽(〇N〇)層1〇2和基板之;包括額 外的層次，係根據此元件的製程所需。 此圖案化光阻層116可以被圖案化以形成一對字元線。第 1A-1D圖顯示形成此字元線的中間步驟結果。必須強調的是，第 1A-1D圖顯示的字元線結構可以製造成電晶體結構中包括多晶矽 或碎化鶴(WSix)或嫣閘極。 第1B圖顯示一堆疊結構12〇之示意圖，其係在結構1〇〇進行 I虫刻製程以移除多晶石夕硬式幕罩層112 —部分之後的結構。此钱 刻製程包括一個或多個濕式或乾式蝕刻製程，包括一多晶矽硬式 幕罩蝕刻製程。此蝕刻製程包括移除多晶矽硬式幕罩層U2、底部 抗反射層(BARC)114及一部分的四乙氧基矽烷(TE〇s)11()層在結 201201256 構100中未被光阻層U6覆蓋的 f00中被光阻層116所覆蓋的層〗〗〇、m和114:區域此= 製程除去光阻層116和底部抗反射層(BARQ114。〃 第1C圖顯示一堆疊結構13〇 ^ 罐程以移除四乙氧基卿E0S)硬:幕罩: =此靖程包括一個或多個濕式蝕刻▲ 乳基魏(TEQS)硬式幕罩_製程。此^J四乙The melon mouth has eight soap layers 112 and one bottom 4 resist layer 116. In an embodiment, the poly-polysilicon layer 106 is used as a word line. The bottom anti-reflective layer (BARC) 114 and the patterned first polysilicon layer 104 are used as bit lines and the second film stack 4 structure 100 can be formed by different processes, for example, including known deposition processes. As part of the integrated circuit process. For example, the film stack structure can be a fabrication-recording component, such as a dynamic random access memory (DRAM) component or a flash memory component, part of a process. In some embodiments, the ruthenium oxide tantalum nitride-ruthenium oxide (〇N〇) layer 1 〇 2 and the substrate may be included; additional layers are included, depending on the process of the component. This patterned photoresist layer 116 can be patterned to form a pair of word lines. Figures 1A-1D show the results of the intermediate steps that form this character line. It must be emphasized that the word line structure shown in Figures 1A-1D can be fabricated to include polycrystalline germanium or shattered cranes (WSix) or germanium gates in the crystal structure. Fig. 1B shows a schematic view of a stacked structure 12A which is structured after the structure is removed to remove the portion of the polycrystalline hard mask layer 112. The process includes one or more wet or dry etch processes, including a polysilicon hard mask etch process. The etching process includes removing the polysilicon hard mask layer U2, the bottom anti-reflective layer (BARC) 114, and a portion of the tetraethoxy decane (TE〇s) 11 () layer in the junction 201201256 structure 100 without the photoresist layer U6 The layer covered by the photoresist layer 116 in the covered f00 is 〇, m, and 114: region. This process removes the photoresist layer 116 and the bottom anti-reflection layer (BARQ 114. 〃 1C shows a stacked structure 13 〇 ^ can To remove the tetraethoxyqing E0S) hard: mask: = This process includes one or more wet etching ▲ milk based Wei (TEQS) hard mask _ process. This ^J four B
卿)110及-部分的简J 此__询份多晶石夕“幕m和1〇8部分’ 第1D圖顯示一堆疊結構14〇之示意圖，其係在 飯刻製程以移除多晶石夕層刚和1〇6 一部分之後的仃 製程包括-個或多個濕式蚀刻製程，包括^刻 、、，。構13〇中未被多晶㈣式幕罩㈣2覆 = =和108 此侧製程則會消耗完剩餘的多晶石夕硬式幕 及一部分的四乙氧基矽烷(TE〇s)硬式幕罩層11〇。 θ =⑽生成結構14〇_刻製程也導致形成一個或 H结構之間。在某些情況下’氧化結構具有—非理 予 f於字元線結構之間。當半導難置巾的臨界尺寸變的 :著=“奈米和45奈米技術節點時’此橋接效應會變得； 201201256 彡閱第2A〜2B ® ’為根據本發明之—實施例製程以形 二处夕一閘極結構的剖面示意圖。第2A圖顯示—個與第lc ηη ϋ 13G完全相同或是大致相同的結構2GG。@此，對於結構 、田述’包括製造結構13〇的步驟可以適驗結構2〇〇。 圖中的結構220可以使用上述内含同步氧/氬處理步驟於 1/1 *自、。構200中製造。此内含同步氧/氬處理可以在此製程 =時間點進行，舉例而言’可以根據以下不同製程實施例 2品求’於最終過祕刻完成之前進行，以形成一中間寬兩邊 閘極結構。此同位氧/氬處理可以生成—具有—高分子氧 S、中間結構(未示）。並且與傳統的閘極结構結構相較，本發明 之結構具有較小或較薄的阻障擴散氧化層。 在-實施例中’結構220可以藉由包括一石夕化鶴(WSix)主敍刻 、接著進行一魏鎮(WSix)過度触刻(〇e)、之後再使用同步 氧/氬處理接著除去多晶石夕閘極表面的氧化石夕、再進行一多晶石夕 ，，刻(ME)、接著進行第—次的多晶料度細(〇E)、最後是第 二次的多晶矽過度蝕刻(0E)之製程自結構2〇〇中製造。 此氧/氬處理可以是利用單一步驟進行，其包括氬離子縣結 構H0及曝露結構Μ〇於氧氣中。於此氧/氬處理中，氧氣提供^ 助多晶矽殘留與蝕刻後的聚合物的氧化移除過程。 八 β在閘極是多晶矽的實施例中，所進行的同步氧/氬處理，最好 疋在第二次的多晶矽過度蝕刻(〇£)之前進行，其氬的流量可運用 在〇到1〇〇〇標準立方公尺/每分鐘(SCCM)範圍之間，氧的流量可 =在0到200 SCCM範圍之間。此外，此製程之源極解離分子 旎罝可運用在10到1000瓦特範圍之間，此製程之偏壓能量可運 用在10到300瓦特範圍之間。在替代實施例中，同步氧/氯處理， 201201256 也可以在第-次的多晶石夕過度餘刻(0E)之前或是進行 (WSix)過度#刻(〇£)之前進行。 在閘極是金屬閘極(例如鶴)的實施例中，所進行的同 理，其氬的流量可運用在〇到1000 SCCM範圍之間， 運用在0到200 SCCM範圍之間。此外，此製程之源極解離L分子 能量可運用1〇到1000瓦特範圍之間，此製程 10到300瓦特範圍之間。 >=*里j連用 替代實施例中’結構220可以藉由包括—魏鶴(W㈣ 主飯刻(ME)、接著進行一石夕化鶴(概伽度餘刻(〇e)、再進行一 多晶石夕主㈣_)之後、接著破真錢行氧/氬處⑬、接著進行一 、最後是—第二多晶料賴刻_之 製私自、、、。構200中製造。在此實施例中，氧/氬處理可以是利用氧 二在氧化谢進行的氧/氬處理，其氬 SCCM範圍之間，氧的流量可運用在0 7 27H ΐΓ乾圍之間。此外，此製程之源極解離分子能量最好 ^ = G瓦特範圍之間，此㈣ 1之偏魏量可運用在 2MHz 10到2〇〇〇瓦特範圍之間。 以;可以是_上述方法關步或非同步方式進行， 乃於‘ 2子凡線橋接失效而不會嚴重地影響閘極的臨界尺寸 及輪廓。此氧/氬處理也可崎低阻賴散氧化層的高度。 之閘極結構220 &括一組瓶狀字元線結構222和224。 第一 I ΐϊ構222 * 224具有至少某種瓶狀輪廓，其包括第一、 = W1、W2和W3。此第-及第三寬度W1和W3 = 或是大致_的寬度。然而，第二M W是 和M4兩’且大於第三寬度W3。因此’字元線結構222 ':匕括’自一晶圓側(在第2Β圖所示晶圓係在ΟΝΟ層 11 201201256 102 =下）、-第_寬度、―第二寬度高於第—寬度，此第二寬度 ^於第—寬J ’―第三寬度高於第二寬度，此第三寬度小於第二 寬度。更特定的是，每一個字元線結構222和224可以包括第一 晶了層1〇4和1〇6’其中第一多晶矽層ι〇4自晶圓側向上 k =第一夕晶石夕層1〇6自晶圓側向上變窄。舉例而言，在此例 二貫H中’第一多晶石夕層刚自第一寬度wi變寬為第二寬度 二2 ’而第二夕晶石夕層1〇6自第二寬度號變窄為第三寬度奶。 關極結構中具有第二寬度W2最寬的部分並不—定是在 f-夕晶判HM與第二多晶碎層廳介面之處，也可以向上或 向下移動而在第-多晶石夕層1〇4中或是第二多晶梦層中。 列的 線結構222和224可以有效地增加此多晶石夕閘極姓 _界尺相不需要_產生衫_產物㈣程及不會需要 、土^穩定的製程或設備。因為瓶狀字元線結構222和224的¥ = 的使用’可以如上述般降低阻障擴 如此改善了製程較已知技術更佳，特別是與牽 已知界尺寸的製程相較。舉例而言’某些如此的 而，如^製程將ΐΓ生引更入f產雜生的聚合物的分子於侧製程中；然 性不$㈣塑】纟越賴副聽及糾製程或設備的穩定 式幕罩：；:涉到沈積一層襯塾層於硬 ^斤^之製程有效地放大此多轉閘極侧的臨界尺寸而不會 生更夕的副產物及不會嚴重地增加製程的成本。 ^然本發明係已參照實施例來加以描述，然本發明創作並 =艮於其詳細描述内容。替換方式及修改樣式係已於先前扩 且其他替換方式及修改樣式將為熟習此項技蔽： 人士所思及。制是，所有具有實f上相同於本發明之 201201256 合而達成與本發明實質上相同結果者，皆不脫離本發明之精神 範疇。因此，所有此等同的替換方式及修改樣式係意欲落在本 發明於隨附申請專利範圍及其均等物所界定的範疇之中。 【圖式簡單說明】 本發明係由申請專利範圍所界定。這些和其它目的，特 徵’和實施例，會在下列實施方式的章節中搭配圖式被描 述，其中：卿)110 and - Part of Jane J This is a schematic diagram of a stacking structure 14 第The tantalum process after the shoal layer and the 〇6 part includes one or more wet etching processes, including ^, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The side process consumes the remaining polycrystalline hard curtain and a portion of the tetraethoxy decane (TE〇s) hard mask layer 11 〇 θ = (10) generates a structure 14 〇 etch process also leads to the formation of a H or Between the structures. In some cases, the 'oxidation structure has - the difference between the f and the word line structure. When the critical dimension of the semi-conductive towel is changed: "=" and "45 nm technology node" This bridging effect will become; 201201256 Ref. 2A~2B ® ' is a schematic cross-sectional view of a second gate structure according to the embodiment of the present invention. Fig. 2A shows a structure 2GG which is identical or substantially identical to the lc ηη ϋ 13G. @这, For the structure, the description of the field, including the steps of manufacturing the structure, can be adapted to the structure 2〇〇. The structure 220 in the Figure can be used in the above described simultaneous oxygen/argon treatment step at 1/1*. Made in structure 200. The simultaneous oxygen/argon treatment may be performed at this process=time point, for example, 'can be made according to the following different process examples 2' before the final smear is completed to form a middle width two-sided gate structure . This isotopic oxygen/argon treatment can produce - with - a polymeric oxygen S, an intermediate structure (not shown). And the structure of the present invention has a smaller or thinner barrier diffusion oxide layer than conventional gate structures. In the embodiment, the structure 220 can be removed by including a WSix main stencil, followed by a WSix over-touch (〇e), followed by simultaneous oxygen/argon treatment followed by removal. The oxidized stone on the surface of the spar sluice gate, and then a polycrystalline stone, the engraved (ME), followed by the first polycrystalline fineness (〇E), and finally the second polycrystalline bismuth overetching The process of (0E) is manufactured from Structure 2〇〇. This oxygen/argon treatment can be carried out in a single step comprising an argon ion county structure H0 and an exposed structure in oxygen. In this oxygen/argon treatment, oxygen provides a polycrystalline ruthenium residue and an oxidative removal process of the etched polymer. In the embodiment where the gate is a polysilicon, the simultaneous oxygen/argon treatment is preferably performed before the second polysilicon overetch (〇), and the flow rate of the argon can be applied to 1〇. Between the standard cubic meters per minute (SCCM) range, the oxygen flow rate can be between 0 and 200 SCCM. In addition, the source dissociation molecular enthalpy of this process can be used between 10 and 1000 watts, and the bias energy of this process can be used between 10 and 300 watts. In an alternate embodiment, the simultaneous oxygen/chlorine treatment, 201201256, may also be performed prior to the first polylithic excess (0E) or prior to (WSix) excessive #〇 (〇£). In the embodiment where the gate is a metal gate (e.g., a crane), the argon flow rate can be applied between 〇 to 1000 SCCM and between 0 and 200 SCCM. In addition, the source of this process can dissociate L molecules from 1 〇 to 1000 watts, which is between 10 and 300 watts. >=* In the alternative embodiment, the structure 220 can be carried out by including - Wei He (W (four) main meal (ME), followed by a stone Xihua crane (absolute gamma remnant (〇e), another one After the polycrystalline stone (4) _), then the real money is emptied into the oxygen/argon 13 , and then the first and the second is - the second polycrystalline material is etched into the private, and is manufactured in the structure 200. In the example, the oxygen/argon treatment may be an oxygen/argon treatment using oxygen dioxide in the oxidation, and between the argon SCCM ranges, the oxygen flow rate may be used between 0 7 27H and the dry circumference. In addition, the source of the process The polar dissociation molecular energy is best between ^ = G watt range, and the (4) 1 bias can be used between 2MHz and 10 to 2 watts. It can be _ the above method is closed or asynchronous However, the failure of the bridge is not severely affected by the critical dimension and profile of the gate. This oxygen/argon treatment can also lower the height of the oxide layer. The gate structure 220 & A set of bottle-shaped character line structures 222 and 224. The first I-frame structure 222*224 has at least some bottle-like profile including the first, =W1 , W2 and W3. The first and third widths W1 and W3 = or a width of substantially _. However, the second MW is two and M4' and larger than the third width W3. Therefore, the word line structure 222 ': Included from the side of a wafer (the wafer shown in Figure 2 is below the layer 11 201201256 102 =), the _width, the second width is higher than the first width, and the second width is the first The width J'-the third width is higher than the second width, and the third width is smaller than the second width. More specifically, each of the word line structures 222 and 224 may include the first crystal layers 1〇4 and 1〇6. 'Where the first polysilicon layer ι〇4 is from the wafer side up k = the first crystallization layer 1 〇 6 is narrowed from the wafer side upward. For example, in this example, the second H is 'first The polycrystalline stone layer has just widened from the first width wi to the second width two 2' and the second cherished stone layer 1〇6 has been narrowed from the second width number to the third width milk. The widest part of the width W2 is not fixed at the interface between the HM and the second polycrystalline layer, and can also be moved up or down while in the first-polycrystalline layer 1〇4 Medium or second polycrystalline dream The line structure 222 and 224 of the column can effectively increase the polycrystalline stone sluice gate _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The use of ¥ = of word line structures 222 and 224 can reduce the barrier spread as described above. This improves the process better than known techniques, especially compared to processes that involve known dimensions. For example, 'some Something like this, such as the process, will introduce the molecules of the polymer into the side process in the side process; the value is not (4) plastic] 纟 赖 副 副 副 纠 纠 纠 纠 纠 纠 纠:;: involved in the deposition of a layer of lining layer in the hard ^ ^ ^ ^ process to effectively enlarge the critical dimension of the multi-turn gate side without the occurrence of more by-products and will not seriously increase the cost of the process. The present invention has been described with reference to the embodiments, but the present invention is written and described in detail. Alternatives and modifications to the styles have been previously expanded and other alternatives and modifications will be familiar to this technique: People think. It is to be understood that all of the same as the present invention, which is substantially the same as the present invention, which is substantially the same as the present invention, does not depart from the spirit of the invention. Therefore, all such equivalents and modifications are intended to be included within the scope of the invention as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the accompanying drawings in the following sections of the embodiments, in which:
第1A〜1D圖顯示根據習知技術用來製造 製程别面示意圖0 一半導體裝置之 導體裝 第2A〜2B圖顯示根據本發明一實施例用來製造一半 置之製程方法剖面示意圖。 【主要元件符號說明】 100 :薄膜堆疊結構 102 :氧化矽-氮化矽_氧化矽(ΟΝΟ)層1A to 1D are views showing a process for manufacturing a process according to a conventional technique. A conductor package of a semiconductor device. Figs. 2A to 2B are schematic cross-sectional views showing a process for fabricating a half of a process according to an embodiment of the present invention. [Explanation of main component symbols] 100 : Thin film stack structure 102 : yttrium oxide-tantalum nitride 矽 矽 (矽) layer
104 :第一多晶矽層 106 .苐·一多晶碎層 108 :矽化鎢(WSix)層 110 :四乙氧基矽烷(TEOS)硬式幕罩層 112 :多晶矽硬式幕罩層 114 :底部抗反射層(BARC) 116 :光阻層 222、224 :字元線結構 13104: first polysilicon layer 106. 苐·a polycrystalline layer 108: tungsten germanium (WSix) layer 110: tetraethoxy decane (TEOS) hard mask layer 112: polycrystalline hard mask layer 114: bottom resistance Reflective layer (BARC) 116: photoresist layer 222, 224: word line structure 13