201145841 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種產生時脈資料回復訊號相位鎖住指標的電 路及其方法，尤指一種根據對一頻道的資料執行超取樣後，所產生 的複數個交流項，以產生時脈資料回復訊號相位鎖住指標的電路及 其方法。 【先前技術】 在先前技術中，可利用鎖相迴路鎖住指標(phasel〇ckk)〇pl〇ck indicator)，產生以鎖相迴路為基礎的時脈資料回復器的鎖住指標； 可傳送已知的位元型態並檢查回傳位元的錯誤率以產生時脈資料回 復讯號相位鎖住指標；可利用已知的參考時脈，在比較參考時脈和 時脈資料回復器的時脈’以產生雜資料回復訊助位鎖住指標。 如果時脈資料回復ϋ並相鎖相迴路為基礎，則無法利用鎖相 迴路鎖住指標以產生Β械資料回復訊號她鎖住指標^而對於非鎖 相迴路為基_時脈資料回復H，係侧傳送已知的位元型態或已 知的參考時脈，以產生時脈資料回復訊號相位鎖住指標。因此，先 前技術對於非鎖相迴路為基礎的時脈資料回復器，必須額外利用已 知的位元型態或已知的參考時脈，才能從頻道所傳送的資料令產生 時脈資料_訊號她鎖健標。所以，上述產生雜資料回復訊 號相位鎖住指標的方法，對於使用者而言，都不是較佳的選擇。 201145841 【發明内容】 本發明的一實施例提供一種產生時脈資料回復訊號相位鎖住指 標的電路。該電路包含—超取樣邏輯單元、—交流估計單元及一邏 輯處理器。該超取樣邏輯單元係用以根據一超取樣(〇versampHng) 時脈’對來自一頻道的資料執行一超取樣動作，以產生複數個交流 項(AC term)，以及根據一輸出時脈，從該複數個交流項中輸出和該 鲁輸出時脈相關的複數個交流項；該交流估計單元係柄接於該超取樣 邏輯單兀’用以對於一第一預定時間内由該超取樣邏輯單元輸入的 、复數個父",!_項執行一離散餘弦轉換（此⑽把加仍免加， DCT)以產生—第—數值，及執行-離散正弦轉換（diseretesine =form,DST) ’以產生—第二數值；及該邏輯處理器係祕於該 又二估5十單凡’用以比較一第二預定時間内該第-數值的數目與該 第數值的數目，並據以產生一時脈資料回復訊號相位鎖住指標。 t »本么明的另—實施例提供—種產生時脈資料回復訊號相位鎖住 =的方法。該方法包含根據—超取樣時脈，對來自—頻道的資料 ^丁，取樣動作，以產生複數個交流項；根據—輸出時脈，從該 ^個交流項中輸出和該輸出時脈相關的複數個交流項至一交流估 、、^疋，對於—第—預㈣間内輸人至該交流估計單元的複數個交 執仃—離散餘弦轉換’以產生—第—數值，及執行一離散正 的盤、卩產生—第二數值；及比較—第二預定時間誠第一數值 、目與該第二數值的數目，並據以產生4脈資料回復訊號相位 201145841 鎖住指標。 本發明所提供的一種產生時脈資料回復訊號相位鎖住指標的電 路及其方法，係利用一交流估計單元對於一第一預定時間内由一超 取樣邏輯單元輸入的複數個交流項，執行一離散餘弦轉換，以產生 一第一數值，及執行一離散正弦轉換，以產生一第二數值；再利用 一邏輯處理器比較一第二預定時間内該第一數值的數目與該第二數 值的數目，並據以產生一時脈資料回復訊號相位鎖住指標。如此， 本發明便不需利用一鎖相迴路鎖住指標、已知的位元型態及/或已知 的參考時脈以產生該時脈資料回復訊號相位鎖住指標。 【實施方式】 凊參照第1圖’第1圖係為本發明的—實施例說明產生時脈資 料回復訊號相位鎖住指標的電路刚的示意圖。電路励包含一超 取樣邏輯單元1(32、一交流估計單元104及-邏輯處理器106。超取 樣邏輯單元1G2伽以根據-超取樣(Qvei> 時脈c〇v ，對來 自-頻道的倾執行—超取樣動作，以產生複數個交流項(AC term) ’以及根據一輸㈣脈c〇，從複數個交流項中輸出和輸出時 脈Co相關的複數個交流項。另夕卜超取樣時脈㈤的頻率必須大 於貝料的鮮的二倍。在本實施射，超取斜脈c〇v係為 10GHz， 資料的頻率㈣2.5GHZ，但本發賴不受限於超取樣雜c〇v係為 10GHz’資料的頻率係為2.5GHZ。 201145841 請參照第2A圖和第2B圖，第2A圖和第2B圖係說明超取樣 邏輯單元102所輸出的交流項的示意圖。因為超取樣時脈c〇v為 10GHz以及資料的頻率為2.5GHz’所以超取樣邏輯單元1〇2所輸出 的交流項必須是4位元項(1 〇GHz/2.5GHz = 4)。當4位元項不全為 “0”或不全為“Γ時，則超取樣邏輯單元1〇2記錄此4位元項為 一交流項。如第2A圖所示，4位元項料“0111”，則超取樣邏輯 單元102記錄4位元項“0111”為一交流項。同理，當4位元項全 為“0”或全為“Γ日寺，則超取樣邏輯單元1〇2記錄此4位元項為 :直流項。如第2B圖所示，4位元項係為“ιηι”，則超取樣邏輯 單TC202記錄4位元項“lm，，為一直流項。 。月…第3 ® ’第3圖係說明超取樣邏輯單元1〇2_輸出時 =〇 ’輸出和輸㈣脈相_交流項的示意圖。超取樣邏輯單元 不斷地利用超取樣(oversampling)時脈cov，對來自一頻道的資201145841 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit and method for generating a phase lock signal of a clock signal reply signal, and more particularly to a method for performing oversampling based on data of a channel A plurality of generated alternating current items are used to generate a clock signal to reply to the signal phase locking indicator circuit and method thereof. [Prior Art] In the prior art, a phase-locked loop lock indicator (phasel〇ckk) 〇pl〇ck indicator) can be used to generate a lock indicator of a clock data recoverer based on a phase-locked loop; Know the bit pattern and check the error rate of the return bit to generate the clock data reply signal phase lock indicator; use the known reference clock to compare the reference clock and clock data recoverer Pulse 'to generate miscellaneous data to help the information to lock the indicator. If the clock data is restored and the phase-locked loop is based, it is impossible to lock the indicator with the phase-locked loop to generate the mechanical data reply signal. She locks the index ^ and for the non-phase-locked loop, the base_clock data returns H, The system side transmits a known bit pattern or a known reference clock to generate a clock data recovery signal phase lock indicator. Therefore, the prior art for the non-phase-locked loop-based clock data restorer must additionally use the known bit type or the known reference clock to generate the clock data_signal from the data transmitted by the channel. She locks the mark. Therefore, the above method of generating a data recovery signal phase lock indicator is not a preferred choice for the user. 201145841 SUMMARY OF THE INVENTION An embodiment of the present invention provides a circuit for generating a clock signal recovery signal phase lock indicator. The circuit includes an oversampling logic unit, an alternating current estimating unit, and a logic processor. The oversampling logic unit is configured to perform an oversampling operation on data from a channel according to an oversampling (〇versampHng) clock to generate a plurality of AC terms, and according to an output clock, And outputting, in the plurality of communication items, a plurality of alternating items related to the Lu output clock; the AC estimating unit is coupled to the oversampling logic unit 用以 for being used by the oversampling logic unit for a first predetermined time The input, plural parent ", !_ items perform a discrete cosine transform (this (10) adds plus, DCT) to produce - the first value, and the execution - discrete sine transform (diseretesine = form, DST) ' Generating a second value; and the logic processor is secretively determining the number of the first value and the number of the first value for comparing a second predetermined time, and generating a moment Pulse data reply signal phase lock indicator. t » The other embodiment of the present invention provides a method for generating a clock signal response signal phase lock =. The method comprises: according to the super-sampling clock, the data from the channel, the sampling action, to generate a plurality of alternating items; according to the output clock, the output from the communication items is related to the output clock a plurality of exchange items to an exchange estimate, ^疋, for a plurality of exchanges between the first and the first (four) inputs to the exchange estimation unit - discrete cosine transforms to generate - the first value, and perform a discrete Positive disc, 卩 generates - second value; and comparison - the second predetermined time is the first value, the number of the second value, and accordingly generates a 4-pulse data reply signal phase 201145841 lock indicator. The invention provides a circuit for generating a clock signal reply signal phase lock index and a method thereof, which are performed by an AC estimation unit for a plurality of AC items input by an oversampling logic unit in a first predetermined time period. Discrete cosine transform to generate a first value, and perform a discrete sine transform to generate a second value; and use a logic processor to compare the number of the first value with the second value for a second predetermined time The number, and accordingly, generates a clock data response signal phase lock indicator. Thus, the present invention does not require the use of a phase locked loop to lock the indicator, the known bit pattern and/or the known reference clock to generate the clock data recovery signal phase lock indicator. [Embodiment] Referring to Fig. 1 'Fig. 1 is a schematic diagram showing a circuit for generating a clock signal reply signal phase lock index according to an embodiment of the present invention. The circuit excitation includes an oversampling logic unit 1 (32, an AC estimation unit 104 and a logic processor 106. The oversampling logic unit 1G2 is gamified according to - oversampling (Qvei> clock c〇v, for the channel from the channel) Execution-supersampling action to generate a plurality of AC terms 'and a plurality of AC terms related to the output and output of the clock Co from a plurality of AC terms according to a transmission (four) pulse c〇. The frequency of the clock (five) must be twice as large as the freshness of the beech. In this implementation, the super-pulse c〇v is 10 GHz, and the frequency of the data is (4) 2.5 GHz, but the reliance is not limited to oversampling. The frequency system of the 〇v system is 10 GHz' data is 2.5 GHz. 201145841 Please refer to FIG. 2A and FIG. 2B, and FIG. 2A and FIG. 2B are diagrams illustrating the AC term output by the oversampling logic unit 102. The clock c〇v is 10 GHz and the data frequency is 2.5 GHz' so the AC term output by the oversampling logic unit 1 〇 2 must be a 4-bit term (1 〇 GHz / 2.5 GHz = 4). When the 4-bit term If not all "0" or not all Γ, then the oversampling logic unit 1 〇 2 records this 4 bit As shown in Fig. 2A, the 4-bit item "0111", the oversampling logic unit 102 records the 4-bit item "0111" as an exchange term. Similarly, when the 4-bit item is all “0” or all “Γ日寺, the oversampling logic unit 1〇2 records this 4-bit item as: DC item. As shown in Figure 2B, the 4-bit item is “ιηι”, then the oversampling The logic single TC202 records the 4-bit term "lm, which is a constant stream term. Month... 3rd '3rd figure shows the oversampling logic unit 1〇2_output = 〇' output and output (four) pulse phase _AC Schematic of the item. The oversampling logic unit continually uses the oversampling clock cov to fund the channel.
數個交流項至交流料單元104。 種C。，輸出和輸出時脈c。相關的複 104 〇Several exchange items are passed to the alternating material unit 104. Kind C. , output and output clock c. Related complex 104 〇
早凡102 ’包含一離散 。離散餘弦轉換器1042 201145841 係用以對& t-預定時間T1内由超取樣邏輯單元ι〇2輸入的複 數個交流項，執行一離散餘弦轉換（discrete cosine transform，DCT)， 以產生-第-數值VI(如〇或…及離散正弦轉換器讓係用以對 於預定時間τ内由超取樣邏輯單元1〇2輸入的複數個交流項，執行 -離散正弦轉換（di_tesinetmsf_，DsT)，以產生—第二數值 V2(如1或〇)。邏輯處理器1〇6係輕接於交流估計單元辦，用以根 據-第二預定時間T2内的第一數值V1的數目與第二數值％的數 目，並據以產生一時脈資料回復訊號相位鎖住指標CDRPLI。當第 二預定時間T2 _第—數值V1的數目係小於第二數值％的數目 時’邏輯處理器106產生一時脈資料回復訊號相位鎖住指標 CDRPLI。 «月多’、、、第4圖’第4圖係為本發明的另一實施例說明等化訊號 的方法的流程圖。第4圖之方法係利用第1圖的產生時脈資料回復 讯號相位鎖住指標的電路1〇〇說明，詳細步驟如下： 步驟400 : 步驟402 : 步驟404 : 步驟406 : 根據超取樣時脈Cov，對來自一頻道的資料執行超取 動作，以產生複數個交流項； 根據輸出時脈〇>，從複數個交流射輸出和輸出時 〇〇相_複數個交流項至交流估計單元1〇4 . ::於第-預定時間丁丨内輸入至交流估計單元1〇4的 數個交流項’執行離散餘弦轉換，以產生第—數值^ 201145841 及執行離散正弦轉換，以產生第二數值V2 ; 步驟408 :比較第二預定時間T2内第一數值VI的數目是否小於 第一數值V2的數目，如果是，進行步驟41〇;如果否， 跳回步驟402 ; 步驟410 :輸出時脈資料回復訊號相位鎖住指標CDRpLI，跳回步 驟 402。 在步驟402 t，超取樣邏輯單元搬根據超取樣時脈—，對 來自一頻道的倾執行超取樣動作，以產生複數個交流項。超取樣 時脈C〇V的頻率必須大於資料的頻率的二倍。在第4圖的實施例 中，超取樣時脈Cov係為1〇GHz，資料的頻率係為2 5GHz，但本 發明並不受限於超取樣時脈Cqv係為1QGHz，倾的頻率係為 2.5GHZ。在步驟404中，超取樣邏輯單元202可根據輸出時脈α 的正緣或負緣’輸出和輸出雜叫目_複數做流項至交汽估 計單元。在步驟中，當第二預定時間T2内第一數值則 數目係小於第二數值％的數目時，邏輯處理器礙輸出時脈資料 回復訊號相位鎖住指標CDRPLI。 綜上所述，本發明所提供的產生時脈資料回復訊號相位鎖住指 標的電路及其方法’係·交流估計單元對於第—預料間内由超 取樣邏輯W輸人的複數個交流項，執行離散餘弦轉換，以產生第 -數值，及執行離散正弦轉換，以產生第二數值；再细邏輯處理 益比較第-預定時咖第-數值的數目與第二數_數目，並據以 201145841 產生時脈資料回復訊號相位鎖住指標。如此，本發明便不需利用鎖 相迴路鎖住指標、已知的位元型態及/或已知的參考時脈以產生時脈 資料回復訊號相位鎖住指標。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖係為本發明的一實施例說明產生時脈資料回復訊號相位鎖住 指標的電路的示意圖。 第2A圖和第2B圖係說明超取樣邏輯單元所輸出的交流項的示意 圖。 第3圖係說明超取樣邏輯單元根據輸出時脈，輸出和輸出時脈相關 的交流項的示意圖。 第4圖係為本翻的另—實關說明等化訊躺方法的流程圖。As early as 102 ’ contains a discrete. Discrete cosine converter 1042 201145841 is used to perform a discrete cosine transform (DCT) on a plurality of AC terms input by the oversampling logic unit ι2 in the predetermined time T1 to generate - - a value VI (such as 〇 or ... and a discrete sine converter) for performing a discrete sinusoidal transformation (di_tesinetmsf_, DsT) for a plurality of alternating terms input by the oversampling logic unit 1 〇 2 within a predetermined time τ to generate a second value V2 (such as 1 or 〇). The logical processor 1 轻 6 is lightly connected to the AC estimation unit for using the number of the first value V1 and the second value % in the second predetermined time T2 The number, and accordingly, generates a clock data reply signal phase lock indicator CDRPLI. When the number of second predetermined time T2_the first value V1 is less than the number of the second value %, the logical processor 106 generates a clock data reply signal. The phase lock indicator CDRPLI. «月多', 4, 4' is a flowchart illustrating a method of equalizing a signal according to another embodiment of the present invention. The method of Fig. 4 utilizes the method of Fig. 1. Generating time The circuit of the response signal phase lock indicator is described in detail. The detailed steps are as follows: Step 400: Step 402: Step 404: Step 406: Perform a super-fetch operation on the data from a channel according to the oversampling clock Cov Generate a plurality of AC terms; according to the output clock 〇>, from a plurality of AC shot outputs and outputs 〇〇 phase _ plural exchange items to the AC estimation unit 1〇4. :: Input in the first-predetermined time The plurality of alternating terms to the AC estimating unit 1-4 perform a discrete cosine transform to generate a first value ^ 201145841 and perform a discrete sine transform to generate a second value V2; Step 408: compare the first predetermined time T2 Whether the number of values VI is less than the number of the first value V2, if yes, proceed to step 41; if not, jump back to step 402; step 410: output the clock data reply signal phase lock indicator CDRpLI, and jump back to step 402. Step 402 t, the oversampling logic unit performs an oversampling operation on the tilt from the channel according to the oversampling clock—to generate a plurality of alternating items. The frequency of the oversampled clock C〇V must be large. The frequency of the data is twice. In the embodiment of Fig. 4, the oversampling clock Cov is 1 〇 GHz, and the frequency of the data is 25 GHz, but the present invention is not limited to the oversampling clock Cqv system. At 1Q GHz, the frequency of the tilt is 2.5 GHz. In step 404, the oversampling logic unit 202 can output and output the hash _ complex number to the traffic estimation unit according to the positive or negative edge of the output clock α. In the step, when the number of the first value in the second predetermined time T2 is less than the number of the second value %, the logic processor blocks the output clock signal to recover the signal phase lock indicator CDRPLI. In summary, the circuit and method for generating a clock phase response index of a clock data provided by the present invention are a plurality of communication items that are input by the super-sampling logic W in the first-expected interval. Performing a discrete cosine transform to generate a first-value, and performing a discrete sinusoidal transformation to generate a second value; the finer logical processing compares the number of the first-predetermined time-number with the second number_number, and according to 201145841 Generate clock data reply signal phase lock indicator. Thus, the present invention eliminates the need for a phase locked loop to lock the indicator, known bit patterns, and/or known reference clocks to generate a clock data recovery signal phase lock indicator. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a circuit for generating a clock phase response signal phase lock indicator according to an embodiment of the present invention. Figures 2A and 2B are schematic diagrams showing the AC terms output by the oversampling logic unit. Figure 3 is a diagram illustrating the super-sampling logic unit based on the output clock, the output and output clock related AC terms. The fourth figure is a flow chart of the method of the chemistry lying in the other.
【主要元件符號說明】 100 102 104 106 1042 電路 超取樣邏輯單元 交流估計單元 邏輯處理器 離散餘弦轉換器 離散正弦轉換器 10 1044 201145841 VI 第一數值 V2 第二數值 CDRPLI 時脈資料回復訊號相位鎖住指標 400-410 步驟[Main component symbol description] 100 102 104 106 1042 Circuit oversampling logic unit AC estimation unit Logical processor discrete cosine converter discrete sine converter 10 1044 201145841 VI First value V2 Second value CDRPLI Clock data reply signal phase lock Indicator 400-410 steps