201144998 六、發明說明： 【發明所屬之技術頜域】 [0001] 本發明係關於一種電腦系統。 【先前技術】 [0002] 電腦系統的主機板上會設置一電池，該電池用於在主機 板未接外部電源時給主機板上的一CMOS晶片進行供電’ 〇201144998 VI. Description of the Invention: [Technical Jaw Domain of the Invention] [0001] The present invention relates to a computer system. [Prior Art] [0002] A battery is provided on the motherboard of a computer system for supplying power to a CMOS chip on the motherboard when the motherboard is not connected to an external power supply.
以保證該CMOS晶片内存儲的資訊不會丟失。該CMOS晶片 内存儲有用戶對BI〇S的一些設定，當用戶透過BIOS設置 程式對CMOS晶片進行設置時，設置值並沒有回存到CMOS 晶片中，而是放到南橋晶片（ICH)的靜態記憶體中，該 . ..丨. ... ：... . ：· 靜態記憶體時翁需要電源供應以維持内部存儲的資訊， 一旦沒有電源供應這些資訊就會丟失，想要恢復出廠時 的BIOS設定，通常的做法是透過跳帽的方式來使該靜態 記憶體上的重定引腳變為低電平，如此#可清除CMOS設 置，但這種方法需要用戶打開機箱進行操作，不是很方 便。 【發明内容】 '八1 .:.一 [0003] 鑒於上述内容，有必要提供一種可•便對C0MS晶片進行 清除操作的電腦系統。 [0004] —種電腦系統，包括一機箱及一設於機箱内的主機板， 該主機板上設有一用於清除CMOS設置的重定引腳，該機 箱外側設有兩開關，該重定引腳依次透過該兩開關後接 地。 [0005] 相較習知技術，該電腦系統在該機箱外側設有該兩開關 ’且將用於清除CMOS設置的重定引腳依次透過該兩開關 7 表單編號A0101 第3頁/共10頁 201144998 後接地，當需要進行CMOS清除操作時，只需同時按下該 兩開關即可方便進行C0MS清除的操作，無需打開機箱， 十分方便。又因為設置了兩開關’故可有欵防止誤操作 〇 【實施方式】 [〇〇〇6]請共同參考圖1及圖2，本發明電腦系統100的較佳實施方 式包括一機箱10及一設於該機箱1〇内部的主機板2〇。 [0007] 該機箱10外側設有兩開關K1及K2，該兩開關{(1及1(2可以 設於人手易操作的地方’如機箱1〇的前面板12上。該機 箱1 0還設有其他元件，如電源開關、重定開關、光碟機 安裝區等，由於這些元件為習知技術，故此處不具體摇 述。 [0008] 該主機板20包括一電池BAT、兩二極體D1及D2、一南橋 晶片22、兩電阻R1及R2、兩電容C1及C2、一3. 3V備用電 源輸入端P3V3_ST_BY。該主機板:2:0._還包括其他元件，如 北橋晶片、中央處理器等，由於這些元件為習知技術， 故此處不具體描述。 [0009] 該南橋晶片22包括一内部靜態記憶體222，用於存儲 CMOS設置值，該内部靜態記憶體22包括一電壓引腳 VCCRTC及一重定引腳RTCRST。該電壓引腳VCCRTC需時 刻保持高電平，以保證存儲在其内的CMOS設置值不會丟 失。當該重定引腳RTCRST變為低電平時，該内部靜態記 憶體222内部存儲的内容即被清除，從而達到清除CMOS設 置的目的。 099118307 表單編號A0101 第4頁/共1〇頁 0992032439-0 201144998 [0010] ο [0011] ο [0012] 其中，该二極體D1的陽極連接至-3.3V傷用電源輸入端 P3V3一STBY，该二極體…的陽極透過該電阻Ri連接至該 電池BAT的正極’該電池BAT的負極接地。該兩二極體D1 及D2的陰極連接至料橋晶片22的㈣靜態記憶體22的 電壓引腳VCCRTC ’該兩二極體D1及D2的陰極還透過電容 C1接地’該内部靜態記憶體22的電壓引腳VCCRTC透過電 阻R2連接至該内部靜態記憶體22的重定引腳RTCRST，該 内部靜態記憶體22的重定引腳rTCRSt透過電容C2接地。 該内部靜態記憶體22的重定引腳RTCRST還依次透過該兩 開關K1、開關K2及一電阻!^3接地。本實施方式中，該兩 開關K1及K2為常開開關，即按下開關後開關閉合，鬆開 開關後開關自動打開。 當該主機板20連接外部電源時，該3.3V備用電源輸入端 P3V3一STBY始終輸出高電平電壓，故此時該靜態記憶體 22的電壓引腳VCCRTC及重定引腳RTCRST均接收高電平。 而當該主機板20未速接外部電源時，該電池BAT將提供高 電平電壓，故此時該靜態記憶體22的電壓引腳VCCRTC及 重定引腳RTCRST均接收高電平。即無論該主機板20是否 連接外部電源，該靜態記憶體22的電壓引腳VCCRTC及重 定引腳RTCRST均接收高電平，系統處於正常工作狀態’ 設定的CMOS設置不會清除》 當用戶需要清除CMOS設置時，只需同時按下該兩開關K1 、K2，此時該靜態記憶體22的重定引腳RTCRST將被拉低 ，該内部靜態記憶體222内部存儲的内容即被清除，從而 達到清除CMOS設置的目的，由於該兩開關以及1^2是設置 099118307 表單編號A0101 第5頁/共1〇頁 0992032439-0 201144998 在機箱10外侧的，故清除CMOS時無需打開機箱10進行操 作，十分方便。另外，本發明之所以設置兩開關K1及K2 ，是產生防止誤操作的作用，因為兩開關K1及K2必須同 時按下才能實現清除CMOS設置，故不會出現人為不小心 觸碰其中一個開關而清除CMOS設置的現象。其他實施方 式中，如果該用於清除CMOS設置的重定引腳RTCRST是設 置於其他晶片（可能為中央處理器）上時，只需將該兩 開關K1及K2的一端連接至該重定引腳RTCRST，另一端接 地即可。 [0013] 綜上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0014] 圖1係本發明電腦系統較佳實施方式的電路圖。 [0015] 圖2係本發明電腦系統較佳實施方式中機箱的示意圖。 【主要元件符號說明】 [0016] 電腦系統：1 0 0 [0017] 機箱：10 [0018] 前面板：1 2 [0019] 主機板：20 [0020] 開關：K1、K2 [0021] 電池：ΒΑΤ 099118307 表單編號Α0101 第6頁/共10頁 0992032439-0 201144998 [0022] 二極體：D1、D2 [0023] 南橋晶片：22 [0024] 電阻·· Rl、R2、R3 [0025] 電容：Cl、C2To ensure that the information stored in the CMOS chip is not lost. The CMOS chip stores some settings of the user's BI〇S. When the user sets the CMOS chip through the BIOS setup program, the set value is not restored to the CMOS chip, but is placed on the static of the south bridge chip (ICH). In memory, the . . . 丨. ... :... . :· Static memory when Weng needs power supply to maintain the internal storage information, once there is no power supply, this information will be lost, want to restore the factory BIOS setting, the usual way is to jump the cap to make the reset pin on the static memory low, so #clear CMOS settings, but this method requires the user to open the chassis for operation, not very Convenience. SUMMARY OF THE INVENTION [8]: 1. [0003] In view of the above, it is necessary to provide a computer system that can perform a cleaning operation on a C0MS wafer. [0004] A computer system includes a chassis and a motherboard disposed in the chassis, the motherboard is provided with a reset pin for clearing the CMOS setting, and two switches are disposed outside the chassis, and the reset pins are sequentially Ground through the two switches. [0005] Compared with the prior art, the computer system is provided with the two switches on the outside of the chassis and the re-spinning pins for clearing the CMOS settings are sequentially transmitted through the two switches. 7 Form No. A0101 Page 3 of 10 201144998 After grounding, when CMOS clear operation is required, it is convenient to perform C0MS clear operation by pressing the two switches at the same time, which is very convenient. Moreover, since the two switches are provided, it is possible to prevent misoperations. [Embodiment] [〇〇〇6] Please refer to FIG. 1 and FIG. 2 together. The preferred embodiment of the computer system 100 of the present invention includes a chassis 10 and a device. The motherboard 2 inside the chassis 1〇. [0007] The outside of the chassis 10 is provided with two switches K1 and K2, and the two switches {(1 and 1 (2 can be set in a hand-operable place) such as the front panel 12 of the chassis 1 . The chassis 10 is also provided. There are other components, such as a power switch, a reset switch, a CD-ROM installation area, etc., since these components are conventional technologies, they are not specifically described herein. [0008] The motherboard 20 includes a battery BAT, two diodes D1, and D2, a south bridge chip 22, two resistors R1 and R2, two capacitors C1 and C2, a 3. 3V standby power input terminal P3V3_ST_BY. The motherboard: 2:0._ also includes other components, such as a north bridge chip, a central processor Etc., since these components are conventional technologies, they are not specifically described herein. [0009] The south bridge wafer 22 includes an internal static memory 222 for storing CMOS settings, and the internal static memory 22 includes a voltage pin VCCRTC. And a reset pin RTCRST. The voltage pin VCCRTC needs to be kept high at all times to ensure that the CMOS setting value stored therein is not lost. When the re-set pin RTCRST goes low, the internal static memory 222 internally stored content is cleared, Thus, the purpose of clearing the CMOS setting is achieved. 099118307 Form No. A0101 Page 4 / Total 1 page 0992032439-0 201144998 [0010] ο [0012] wherein the anode of the diode D1 is connected to -3.3V With the power input terminal P3V3_STBY, the anode of the diode is connected to the positive pole of the battery BAT through the resistor Ri. The cathode of the battery BAT is grounded. The cathodes of the two diodes D1 and D2 are connected to the bridge wafer 22 (4) The voltage pin VCCRTC of the static memory 22 'The cathodes of the two diodes D1 and D2 are also grounded through the capacitor C1'. The voltage pin VCCRTC of the internal static memory 22 is connected to the internal static memory 22 through the resistor R2. The re-set pin RTCRST, the re-set pin rTCRSt of the internal static memory 22 is grounded through the capacitor C2. The re-set pin RTCRST of the internal static memory 22 is also grounded through the two switches K1, K2 and a resistor! In the embodiment, the two switches K1 and K2 are normally open switches, that is, the switch is closed after the switch is pressed, and the switch is automatically opened after the switch is released. When the motherboard 20 is connected to an external power source, the 3.3V standby power input terminal P3V3 one STBY always outputs a high level voltage, so the voltage pin VCCRTC and the re-set pin RTCRST of the static memory 22 both receive a high level. When the motherboard 20 is not connected to an external power source, the battery BAT will provide a high level. The level voltage, so the voltage pin VCCRTC and the re-set pin RTCRST of the static memory 22 receive a high level at this time. That is, regardless of whether the motherboard 20 is connected to an external power source, the voltage pin VCCRTC and the re-set pin RTCRST of the static memory 22 receive a high level, and the system is in a normal working state 'The set CMOS setting is not cleared>> When the user needs to clear In the CMOS setting, only the two switches K1 and K2 are pressed at the same time. At this time, the reset pin RTCRST of the static memory 22 is pulled low, and the content stored in the internal static memory 222 is cleared, thereby clearing. The purpose of the CMOS setting is because the two switches and 1^2 are set to 099118307 Form No. A0101 Page 5 / Total 1 page 0992032439-0 201144998 On the outside of the chassis 10, it is very convenient to open the chassis 10 without clearing the CMOS. . In addition, the reason why the two switches K1 and K2 are provided in the present invention is to prevent the erroneous operation, because the two switches K1 and K2 must be pressed simultaneously to clear the CMOS setting, so that no one accidentally touches one of the switches to clear it. The phenomenon of CMOS settings. In other embodiments, if the reset pin RTCRST for clearing the CMOS setting is set on another chip (possibly a central processing unit), only one end of the two switches K1 and K2 is connected to the re-set pin RTCRST. The other end can be grounded. [0013] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIG. 1 is a circuit diagram of a preferred embodiment of a computer system of the present invention. 2 is a schematic diagram of a chassis in a preferred embodiment of the computer system of the present invention. [Main component symbol description] [0016] Computer system: 1 0 0 [0017] Chassis: 10 [0018] Front panel: 1 2 [0019] Motherboard: 20 [0020] Switch: K1, K2 [0021] Battery: ΒΑΤ 099118307 Form No. 1010101 Page 6 / Total 10 Page 0992032439-0 201144998 [0022] Diode: D1, D2 [0023] South Bridge Wafer: 22 [0024] Resistor · · Rl, R2, R3 [0025] Capacitance: Cl, C2
[0026] 備用電源輸入端：P3V3_STBY[0026] Backup power input: P3V3_STBY
[0027] 靜態記憶體：222 〇 〇 099118307 表單編號A0101 第7頁/共10頁 0992032439-0[0027] Static Memory: 222 〇 〇 099118307 Form Number A0101 Page 7 of 10 0992032439-0