«81828 五、新型說明： 【新型所屬之技術領域】 本創作係有關於電腦裝置，尤指一種系統設定儲存器 之外控式重置電路。 【先前技術】 電腦設備的系統設定參數係紀錄電腦設備操作所需的 資訊，例如中央處理器的外频、主機板存儲器的參數、系 =時間、顯示器的解析度及電源管理等，通常該等系統設 疋參數係儲存於其主機板的系統設定存儲器内。請參閱第 四圖，爲使該等系統設定參數不致因系統關機而不復存 在，—般作法是將該一系統設定存儲器（53〇)連接至一存儲 器供電電路（550)，而該存儲器供電電路（55〇)同時連接電源 供應器的直流電源V3或使用電池BAT，於電源供應器停 止供電時，仍由電池BAT續繼供電，確保設定參數不遺失。 =為可重設該系統設定存儲器（53〇)的設定參數，該系統設 :存㈣（530)與存儲ϋ供電電路（55())之間再連接有一跳線 器JCMOS，其第一支接腳係連接至該一存儲器供電電路 (55〇)的輪出端，而第二支接腳則連接至該系統設定存儲器 ⑽)電源端，第三支接腳則連接至一低電位；一般正常使 =時將m第二支接腳短接，令存儲器供電電路（別) ’續供應電源予該系統設定存儲器（53〇)，反之欲重設系統 設定存儲器（530)的設定參數，則反將第：支接腳短接至第 j接m统設定存儲器⑽)連接至低電位而清 儲存設定參數。 3 由於跳線器JCMOS同樣 仕主機板上，一旦用戶需 重新載入預設值，或因中央虛 器的超頻動作使電腦無法 重新啟動時，此時需要清除儲 A ^ 储存在存儲器（530)的系統設定 參數。因此必須打開電腦機殼 x找到跳線器JCMOS，再將 第二及第三接聊短接’始可自， .^ 存儲器（53〇)中清除系統設定 參數。因此對於使用者來說步驟 37踢相备繁複不方便需有更簡 易的方式以清除系統設定參數。 【新型内容】 有鑑於此，本創作主|日Μα , +怎』忭王要目的係提供一種系統設定儲存 器之外控式重置電路，讓俅用去丨成… 便用者利用機殼上的重置按鍵即 能快速清除系統設定參數，而無 向>貝經由打開電腦機箱及進 行跳線的繁瑣程序。 欲·達上述目的所使用的 的主要技術手段係令該系統設定 儲存器之外控式重置電路包括— _ 电降匕栝重置按鍵、一訊號延遲單 元及一清除控制電路；其中： 該重置按鍵係供設置在電腦機殼外； 該δίΐ波延遲單元係連接至气_番_ t υ1尔逆接主这重置按鍵，延遲該重置按 鍵傳來的一重置訊號； η該，除控料元係連接至該m號延遲單&，透過該訊 遲單兀連接至該重置按鍵，以取得該延遲的重置訊號， 當收到該延遲的重置訊號後’於輸出端輸出-清除訊號， ^中該輸出端係供與—系統設定存儲器的__電源供應接腳 連接，該系統設定存儲器係儲存有系統設定參數。 儲t本倉作利用原機殼的重置按鍵供使用者清除系統設定 子°° °又定參數，讓使用者不必拆開機殼即可清除其設 基於不干擾重置按鍵原有的作業系統重置功能，故 觸發兮ί訊號延遲單元在重置按鍵按下—段時間後，才會 ::該::除控制單元，由該清除控制單元對系統設定儲存 % ^ ^ ’令其原本的重置功能仍可以短暫按觸的方式 不受影響，達到一鍵兩用的優點。由此可知，本創 2供使用者免開機箱清除系統設定參數的使用方式，有 效鈿紐傳統清除系統設定參數的時間，具有便捷的效益。 【實施方式】«81828 V. New description: [New technical field] This creation is about computer devices, especially a system-controlled memory external control reset circuit. [Prior Art] The system setting parameters of a computer device are information required to record the operation of a computer device, such as the FSB of the central processing unit, the parameters of the motherboard memory, the system=time, the resolution of the display, and the power management. The system settings parameters are stored in the system settings memory of their motherboard. Referring to the fourth figure, in order to prevent the system setting parameters from being lost due to system shutdown, it is common practice to connect the system setting memory (53〇) to a memory power supply circuit (550), and the memory power supply The circuit (55〇) is connected to the DC power supply V3 of the power supply at the same time or uses the battery BAT. When the power supply stops supplying power, the battery BAT is continuously supplied with power to ensure that the setting parameters are not lost. = The setting parameter of the system setting memory (53〇) can be reset. The system is set to: (4) (530) and the storage power supply circuit (55 ()) is connected with a jumper JCMOS, the first branch The pin is connected to the round output end of the memory power supply circuit (55〇), and the second pin is connected to the power supply end of the system setting memory (10), and the third pin is connected to a low potential; Normally, the second branch pin of m is shorted, so that the memory power supply circuit (other) 'continues to supply power to the system setting memory (53〇), and vice versa, if the setting parameter of the system setting memory (530) is to be reset, Reverse the first: the pin is shorted to the jth connection setting memory (10)) and connected to the low potential to clear the setting parameters. 3 Because the jumper JCMOS is also on the motherboard, once the user needs to reload the preset value, or the computer cannot be restarted due to the overclocking action of the central virtual device, it is necessary to clear the storage A ^ and store it in the memory (530). System setting parameters. Therefore, you must open the computer case x to find the jumper JCMOS, then short the second and third chats, and clear the system setting parameters from the memory (53〇). Therefore, it is more convenient for the user to play the step 37 in a complicated manner to clear the system setting parameters. [New content] In view of this, the author of the creation of the main Μ , , , , , , , 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要The reset button on the top can quickly clear the system setting parameters, while the undirected > is a cumbersome procedure for opening the computer case and performing jumpers. The main technical means used to achieve the above purpose is to enable the system to set a memory external reset circuit including - _ electric drop reset button, a signal delay unit and a clear control circuit; wherein: The reset button is provided outside the computer casing; the δίΐ wave delay unit is connected to the gas reset button, and the reset button is delayed, and a reset signal is sent from the reset button; The control unit is connected to the m delay list & and is connected to the reset button through the delay unit to obtain the delayed reset signal, and after receiving the delayed reset signal, the output is output. The terminal output-clear signal, where the output terminal is connected to the __ power supply pin of the system setting memory, the system setting memory stores system setting parameters. The storage compartment uses the reset button of the original casing for the user to clear the system setting ° ° ° and set the parameters, so that the user can clear the original operation without disturbing the reset button without disassembling the boot casing. The system reset function, so the trigger 兮 讯 signal delay unit will be reset after the reset button is pressed for a while:: This:: In addition to the control unit, the clear control unit saves the system to save % ^ ^ ' The reset function can still be unaffected by the short-touch method, achieving the advantage of one-button dual use. It can be seen that the user 2 is free from the use of the setting parameters of the chassis clearing system, and has the advantage of setting the parameters of the traditional cleaning system. [Embodiment]
月 > 閱第圖及第二圖，本創作系統設定儲存器（丨3〇) 之外控式重置電路的卜較佳實施例，其包括—重置按鍵 RST(u〇)、一訊號延遲單元（120)以及一清除控制電路 (140)。 上述重置按鍵RST(1 1〇)係供設置在電腦機殼外，用來 執仃？ t k重置程序及清除該系、统設定存儲器的系統設定 參數》 上述訊號延遲單元（120)係連接至該重置按鍵（11〇)， I遲肩重置按鍵（11〇)傳來的一重置訊號。該訊號延遲單 •元（120)包括—第—電?且R1、—第―電子開關w 一第二 ^電阻R2以及一電容C ;該第一電阻R1的一端係與一第一 正電壓VI連接，該第一電子開關S1的控制端係與該重置 按鍵（110)相連，並與該第―電阻^的另 端係接地；該第二電阻R2的一端係與該第一電子開關S1 的另一端相連，其另一端係與一第二正電壓V2相連，而 該第一電子開關S1的另一端則連接至接地端；又該電容c 係並：於第-電子開關S1的二端。當該重置㈣（110)未 按下％，該第一電子開關s丨之控制端係透過第一電阻R1 5 M381828 連接至該第一正電壓V1’而進入導通接地；若當該重置按 鍵⑴〇)按下時，該第一電子開關S1之控制端接至接地端 而不再導通，此時該第二正„ V2經第二電阻R2對該電 容C充電。此外，電容C充滿電必須令重置開關⑴〇)保 持按下一段時間。 上述清除控制電路（140)係連接至該訊號延遲單元 • (120)，並供系統設定儲存器（130)的電源端連接，於本實施 例中，該清除控制電路（140)係為一第二電子開關S2，其 • 中該第二電子開關S2的控制端係與該該訊號延遲單元（120) 的電容C連接，其一端係接地，m另一端係與該系統設定 存儲器(130)之該電源供應接腳相連。因此，當該重置按鍵 (110)被按下一段時間後，該訊號延遲單元（12〇)的電容c 提供尚電位電壓至且第二電子開關的控制端，令該第二 電子開關導通接地，此時該系統設定存儲器（130)的電源端 即一同接地，而達到清除設定參數的效果；因此，若電容 C提供電壓不足以令該第二電子開關S2導通，則將無法清 Φ 除系統設定存儲器（1 30)。 - 由上述可知，當該重置按鍵RST(llO)按下的瞬間並不 足以觸發清除控制電路（140)對系統設定存儲器（130)進行清 除動作，而必須延遲一段時間才能清除系統設定存儲器（130) 的設定參數。因此，本創作直接使用機殼上的重置按鍵 (110) ’若使用者只按壓重置按鍵（11〇)而不持續按壓一段時 間’則僅會重新啟動電腦作業系統；如使用者欲清除機殼 内的系統設定存儲器（130)，則只要按壓重置按鍵（11〇)，令 訊號延遲單元（120)的電容C充電達到足以觸發清除控制電 6 MJ81828 路（14〇)即可。是故，本創作直接利用重置按鍵（110)作為清 除按鍵用，仍能保留原重置按鍵的功能。 上述第一電子開關s 1及該第二電子開關S2可為一電 b曰體或更具體而言，一MOSFET ;該系統設定存儲器（13〇) 可為 CMOS RAM。 °月參閱第二圖，該系統設定儲存器之外控式重置電路 更包括一存儲器供電電路（丨5〇)。 該存儲器供電電路（150)包含有一電源輸入端V3' — • 鈕扣電池BAT及一跳線器JCM0S。該電源輸入端V3係一 外部電源，經由一第一二極體D1及一第三電阻R3連接至 該跳線器JCM0S的第一接腳；該紅扣電池bat係經由一 第 極體D2及該第三電阻R3連接至該跳線器jcm〇S 的第一接腳；該跳線器JCM0S的第二接腳係連接至該系 統設定存儲器（130)之該電源供應接腳，該跳線器JCM〇s 的第三接腳係接至低電位；正常使用時，將第一及第二接 腳短接，令存儲器供電電路（15〇)持續供應電源予該系統設 參定存儲器（130)，反之欲重設系統設定存儲器（130)的設定參 數’則反將第二接腳短接至第三接腳，令系統設定存儲器 (130)連接至低電位而清除原儲存設定參數。 重置按鍵（110)的原本功能係供使用者按處以啟動電腦 系統的重置，藉由按觸重置按鍵（π〇)的時間長於一預期時 間時方啟動清除系統設定參數，使單一按鍵可操控二不同 功能》同時’經由按觸重置按鍵（11〇)清除系統設定參數的 方式亦可免除必須打開機箱，找到對應的跳線以清空系統 設定參數的傳統清除系統設定參數步驟，達到一鍵雙用及 7 咖丄828 便捷操作的效益。 【圖式簡單說明】 電拉笛— 儿认义邱仔态之外控式重置 电路第一貫施例的一功能方塊圖； 第一圖係根據本創作一系铋今宗性产„。 電路a Α 糸統°又疋儲存器之外控式重置 电路第二貫施例的一電路圖； 第三圖係根據本創作該系缔a宗 雷故认4妨 糸統δ又疋儲存器之外控式重置Month> Referring to the figure and the second figure, the author system sets a memory (丨3〇) external control reset circuit, which includes a reset button RST (u〇), a signal A delay unit (120) and a clear control circuit (140). The above reset button RST (1 1〇) is provided outside the computer case for holding? Tk reset program and clear system setting parameters of the system setting memory. The above signal delay unit (120) is connected to the reset button (11〇), and the one of the delayed shoulder reset button (11〇) Reset the signal. The signal delay unit (120) includes - a first power and a R1, a first electronic switch w a second resistor R2 and a capacitor C; one end of the first resistor R1 is coupled to a first positive voltage VI Connected, the control end of the first electronic switch S1 is connected to the reset button (110), and is grounded to the other end of the first resistor; the end of the second resistor R2 is coupled to the first electronic switch S1. The other end is connected, the other end of which is connected to a second positive voltage V2, and the other end of the first electronic switch S1 is connected to the ground end; and the capacitor c is coupled to the two ends of the first electronic switch S1. . When the reset (four) (110) is not pressed by %, the control end of the first electronic switch s is connected to the first positive voltage V1' through the first resistor R1 5 M381828 to enter the conduction ground; if the reset When the button (1) 〇) is pressed, the control end of the first electronic switch S1 is connected to the ground terminal and is no longer turned on. At this time, the second positive V 2 charges the capacitor C via the second resistor R2. In addition, the capacitor C is full. The electric power must keep the reset switch (1) 〇) pressed for a period of time. The above clear control circuit (140) is connected to the signal delay unit (120) and is connected to the power supply end of the system setting memory (130). In an embodiment, the clear control circuit (140) is a second electronic switch S2, wherein the control end of the second electronic switch S2 is connected to the capacitor C of the signal delay unit (120), and one end thereof is connected Grounding, the other end of the m is connected to the power supply pin of the system setting memory (130). Therefore, when the reset button (110) is pressed for a period of time, the capacitance of the signal delay unit (12〇) c Providing a potential voltage to the control end of the second electronic switch, The second electronic switch is grounded. At this time, the power supply end of the system setting memory (130) is grounded together, and the effect of clearing the setting parameter is achieved; therefore, if the voltage supplied by the capacitor C is insufficient to make the second electronic switch S2 be turned on, It will be impossible to clear Φ except the system setting memory (1 30). - As can be seen from the above, when the reset button RST (110) is pressed, it is not enough to trigger the clear control circuit (140) to perform the system setting memory (130). Clear the action, and it must be delayed for a while to clear the setting parameters of the system setting memory (130). Therefore, this creation directly uses the reset button (110) on the case 'If the user only presses the reset button (11〇) If you do not press for a while, you will only restart the computer operating system; if the user wants to clear the system setting memory (130) in the case, just press the reset button (11〇) to make the signal delay unit (120) Capacitor C can be charged enough to trigger the clear control circuit 6 MJ81828 (14〇). Therefore, this creation directly uses the reset button (110) as the clear button, still can guarantee The function of the reset button is left. The first electronic switch s 1 and the second electronic switch S2 may be an electric b body or, more specifically, a MOSFET; the system setting memory (13〇) may be a CMOS RAM Referring to the second figure, the system setting memory external reset circuit further includes a memory power supply circuit (丨5〇). The memory power supply circuit (150) includes a power input terminal V3' — • button battery BAT and a jumper JCM0S. The power input terminal V3 is an external power source, and is connected to the first pin of the jumper JCM0S via a first diode D1 and a third resistor R3; the red buckle battery bat Connected to the first pin of the jumper jcm〇S via a first pole body D2 and the third resistor R3; the second pin of the jumper JCM0S is connected to the system setting memory (130) The power supply pin, the third pin of the jumper JCM〇s is connected to a low potential; in normal use, the first and second pins are shorted, so that the memory supply circuit (15〇) continues to supply power to the power supply circuit. The system is configured with a reference memory (130), and vice versa. 130) parameter set 'is the inverse of the second pin is shorted to the third pin, so that the system setting memory (130) connected to a low potential cleared as stored set parameters. The original function of the reset button (110) is for the user to press the button to start the reset of the computer system, and when the reset button (π〇) is pressed for longer than an expected time, the system setting parameter is cleared to make a single button. It can control two different functions. At the same time, the method of clearing the system setting parameters by pressing the reset button (11〇) can also eliminate the steps of the traditional clearing system setting parameters that must be opened to find the corresponding jumper to clear the system setting parameters. One-button dual-use and 7-cafe 828 for easy operation. [Simple diagram of the figure] Electric flute - a functional block diagram of the first embodiment of the control reset circuit of Qiu Zi State; the first picture is based on the creation of this series. Circuit a Α 糸 ° 疋 疋 疋 疋 疋 疋 控 控 控 控 控 控 控 控 控 控 控 控 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 第三 第三 第三 ; 第三 第三 第三 第三 根据Control reset
電路的該第一實施例的一電路圖； 【主要元件符號說明】 第四圖係習知系統設定儲存器清除電路的一電路圖。 1 ΐ -rr 从々々 5為 oO 1 (110)重置按鍵 （120)訊號延遲單元 (13〇)系統設定存儲器 (14〇)清除控制電路 (150)存儲器供電電路 (530)系統設定存儲器 (550)存儲器供電電路 8A circuit diagram of the first embodiment of the circuit; [Major component symbol description] The fourth diagram is a circuit diagram of a conventional system setting memory clearing circuit. 1 ΐ -rr From 々々5 to oO 1 (110) Reset button (120) Signal delay unit (13〇) System setting memory (14〇) Clear control circuit (150) Memory supply circuit (530) System setting memory ( 550) Memory Power Supply Circuit 8