TW201143090A - Double diffused drain metal-oxide-semiconductor devices with floating poly thereon and methods of manufacturing the same - Google Patents

Abstract

A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate, a patterned second conductive layer on the patterned second dielectric layer; and the patterned second conductive layer including a second conductive portion on the second dielectric portion.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a metal oxide semiconductor device, and more particularly to a double diffused gate metal oxide semiconductor device having floating poly germanium and Production method. [Prior Art] When used as a component of a power integrated circuit, a metal-oxide-semiconductor (MOS) device must be capable of maintaining a high operating voltage. In order to achieve this, the gate and the drain of the conventional MOS device must be separated by a sufficient distance, but the size of the MOS device cannot be further reduced. This issue will be described below. 1A and 1B are schematic cross-sectional views showing a conventional metal oxide semiconductor device. Referring to FIG. 1A, the MOS device 1-1 may include a P-type substrate 10, a plurality of first isolation structures 13 on the substrate 1〇, an n-type well region 11 and a p-type in the substrate 1〇. Well area 丨2, high-voltage “p” minus, HVPM zone 17-1 located in N-type well zone 11, a pair of p+-type zone ΐ8_ι, high pressure located in p-type well zone p A high-voltage "n" minus (HVNM) region 17-2, and a pair of N+ type regions 18-2. One of the p+ type regions 18-1 is located in the high pressure P-type region' and the other P+ type region 18-1 is located in the N type well region 11. One of the N+ type zones 18-2 is located in the high pressure N-type zone 17-2, and the other N+ type zone 18_2 is located in the p-type well zone 12. Further, the metal oxide semiconductor device 1-1 includes a patterned dielectric layer on the substrate u and a patterned conductive layer on the patterned dielectric layer. The patterned dielectric layer 201143090 ' 1 i includes a first portion 14-1 and a second portion 14-2, and the patterned conductive layer includes a first portion 15-1 and a second portion 15-2. A plurality of second isolation structures μ may be formed along the sidewalls of the patterned dielectric layer and the patterned conductive layer. The metal oxide semiconductor device 1-1 can function as a power management integrated circuit (PMIC) and operates at a relatively high voltage of, for example, 12 volts. In some applications, the distance WG between the poles of the interpolar plate can be L2 micron (μιη) or higher to push such a high voltage. The gate here may, for example, be the first portion of the patterned conductive layer: portion 15-turn, and the drain may be, for example, the pattern 18-1 located in the high voltage ρ_type region 17_丨. Further, when the operating voltage is higher, the distance W0 is larger. In the case of +, for example, when the metal oxide is semi-conductive, the distance is W. Can be increased to ~. When the metal oxide; the conductor « is operated at a higher voltage, for example, the face = w 〇 can be increased to 80 μm. For the distance, please refer to the metal oxide semiconductor device (Fig. 7), which can be similar to the metal oxide semiconductor device μ described in Fig. 1. Two: The difference is that the metal oxide semiconductor | £1_2 includes, area 17- 1 and called - and the high voltage Ν type area 17_2 and the middle of the oxide semiconductor nightmare] 2 sets of PCT & metal η Β § device _ eight metal bismuth semiconductor device Μ罝 have the same question 4, its size It is impossible to further reduce the size of the gate. It is important to increase the distance between the gates and the gates of the gates. It is important to maintain a high operating voltage. [Invention] The embodiment of the present invention provides a metal oxide semiconductor device 201143090

TW5638FA η, the inclusion-diffusion region is located at - the substrate, the second electrical layer: the first conductive layer, the patterned second dielectric layer, and the patterned m-th diffusion region comprise a second dopant type One part and the second part of the first type. The patterned first dielectric layer includes =: expansion, the first dielectric portion on the first portion of the region, and the second dielectric portion of the first conductive layer including the bit τ: " the first on the electrical portion a conductive portion, and a second dielectric portion t: a conductive portion. The patterned second dielectric layer includes a third dielectric portion, and an electrical portion. The third dielectric portion is extended on the first conductive portion: and: the sidewall of the first conductive portion extends to the substrate. The two conductive portions extend over the second conductive portion to the substrate. The patterned second conductive layer is located on the patterned second dielectric layer. The patterned second conductive layer includes a third conductive portion, and the fourth conductive portion and the second conductive portion are located on the third dielectric portion, and the fourth conductive portion It is located on the fourth dielectric part. The (4) oxide semiconductor device provided by the present invention may include a diffusion region located in a substrate, and the f-scatter region includes a - second holding type -::! = one of the second part of the type. The patterned first-dielectric layer includes a first-dielectric portion on a first portion of the diffusion region. Patterning the first conductive layer = - on the dielectric layer ' and patterning the first conductive layer comprises placing the first electrical portion on the first conductive portion == . The side wall of the first conductive portion of the mouth extends to the substrate. Patterning 201143090

The I IW5638PA second conductive layer is on the second dielectric layer and includes a second conductive portion on the second dielectric portion. A metal oxide semiconductor device provided by an embodiment of the present invention may include a diffusion region in a substrate, a patterned first dielectric layer, a patterned first conductive layer, and a patterned second conductive layer. The diffusion region includes a first portion having a second dopant type and a second portion having a first dopant type. The patterned first dielectric layer includes a first dielectric portion on a first portion of the diffusion region. The patterned first conductive layer is on the patterned first dielectric layer φ and includes a second dielectric portion and a third dielectric portion. The second dielectric portion extends over the first conductive portion and extends along the first side wall of the first conductive portion to the substrate. The third dielectric portion extends over the first conductive portion and extends along the second sidewall of the first conductive portion to the substrate. The second and third dielectric portions are separated from each other on the first conductive portion. The patterned second conductive layer is patterned on the second dielectric layer and includes a second conductive portion and a third conductive portion. The second conductive portion is on the second dielectric portion and the third conductive portion is on the third dielectric portion. Other features and advantages of the invention will be set forth in the description which follows. The features and advantages of the present invention are apparent from the elements and combinations thereof pointed out. The above general description and the following detailed description are intended to be illustrative of the invention and are not intended to limit the scope of the invention. In order to make the above description of the present invention more comprehensible, the following description of the preferred embodiments and the accompanying drawings will be described in detail as follows: 201143090 i [Embodiment] The following is a detailed description with reference to the accompanying drawings. invention. When the circumstances permit, the same reference numbers are used to identify the same or similar parts in the drawings. It is important to note that the 'pattern is the form of closure rather than the exact size. 2D through 2D are cross-sectional views showing a method of fabricating a double diffused drain (DDD) metal oxide semiconductor device in accordance with an embodiment of the present invention. Referring to Figure 2A, a substrate 20 is provided. A plurality of isolation structures 23 may be formed on the substrate 2A. In one embodiment, the isolation structure 23 may comprise a cerium oxide, such as cerium oxide, but is not limited thereto. In addition, the isolation structure 23 may include a field oxide layer (FOX) structure, and the field oxide layer structure may be formed on the substrate 20 by an oxidation process. Alternatively, the isolation structure 23 may include a shallow trench isolation (STI) structure, and the shallow trench isolation structure may be formed by performing a lithography process and an engraving process prior to the oxidation process. Then, the first dopant can be implanted in the substrate 2, and the first dopant is, for example, a dopant of about (4) dopant (in the embodiment, the substrate 20 is doped before the second doping) The foreign matter, for example, the first dopant of the p-type dopant can be diffused to the desired depth, and the first part of the diffusion region is formed as the substrate 2〇+ type well region 21. Ground, a second dopant having a concentration of 'cute in cm' can be implanted in the substrate. The implanted dopant-diffusion can diffuse to form a second portion of the diffusion region, that is, p in the substrate 20. The well region 22. The rear germanium dielectric layer (not shown) can be formed on the substrate 2G by deposition. After that, the first conductive layer (not shown in the figure can be used by another Oxidation process (〇χί_(10) mouth coffee (10)) formed in the first media ^ 201143090

• ^ TW5638PA

On the floor. Next, the patterned first conductive layer 25 can be formed by an etching process, and then the patterned first dielectric layer 24 is formed using the patterned first conductive layer 25 as a mask. In one embodiment of the invention, the patterned first dielectric layer 24 may comprise a stone oxide, such as a dioxide dioxide. Further, the patterned first conductive layer 25 may include a stacked structure, and the tungsten telluride is stacked on the poly-silicon layer. The patterned first conductive layer 25 can include a first portion 25-1 on the N-well region 21 and a second portion 25-2 on the P-well region 22. The patterned first dielectric layer 24 can include a first portion 24-1 on the N-type well region 21 and a second portion 24-2 on the P-type well region 22. Referring to FIG. 2B, the second dielectric layer 34 can be formed on the patterned first conductive layer 25 and the substrate 20 by a deposition process. In an embodiment, the second dielectric layer 34 may include a high temperature oxide (HT0). In another embodiment, the second dielectric layer 34 may comprise a stone oxide or tantalum nitride. Next, the second conductive layer 35 can be formed on the second dielectric layer 34 by a deposition process. The second conductive layer 35 may include a plurality of twins. • Referring to Figure 2C, the second conductive layer 35 can be etched to form the patterned second conductive layer 350. The second conductive layer 350 may include a first portion 35-1 and a second portion 35-2. Next, the second dielectric layer 34 can be etched using the patterned second conductive layer 350 as a mask to form a patterned second dielectric layer 340. The patterned second dielectric layer 340 includes a first portion 34-1 and a second portion 34-2. The first portion 34-1 of the patterned second dielectric layer 340 may extend over the first portion 25-1 of the patterned first conductive layer 25, covering a portion of the upper surface 251 of the first portion 25-1, and along The sidewall 251R of the first portion 25-1 of the pattern 牝 first conductive layer 25 extends onto the substrate 20. In addition, a first portion 35-1 of the second conductive layer 350 may be deposited on the first portion 34-1 of the patterned second dielectric layer 340. Similarly, the second portion 34-2 of the patterned second dielectric layer 340 can extend over the second portion 25-2 of the patterned first conductive layer 25, covering the upper surface 252T of the second portion 25-2, and A sidewall 252R of the second portion 25-2 of the patterned first conductive layer 25 extends along the substrate 20. Additionally, the second portion 35-2 of the patterned second conductive layer 350 can be located on the second portion 34-2 of the patterned second conductive layer 340. Referring to Figure 2D, for example, the isolation structure of the spacers 26 can be formed by a deposition process. In particular, some of the spacers 26 may be formed toward the substrate 20 and along the sidewalls 351R and 352R of the first portion 35-1 and the second portion 35-2, respectively, and the other spacers 26 may face the substrate 20 and The sidewalls 251L and 252L of the first portion 25-1 and the second portion 25-2 are formed, respectively. For example, the second isolation structure 26 can include tetraethyl orthosilicate (TEOS). Thereafter, the first dopant having a concentration of about 1 〇 12 to 1013 cm·3 can be implanted in a portion of the N-type well 21 by an implantation process to form a first high-pressure-P-type region. Planting area 27-1. In one embodiment, the first implant region 27-1 has a depth of 0.4 to 0.6 μm, and can be patterned with the first portion 34-1 of the second dielectric layer 340 and the patterned second conductive layer 350. The first part 35-1 overlaps. Similarly, the first dopant having a concentration of about 1〇12 to 1〇13 cnT3 can be implanted in a portion of the P-type region 22 by the implantation process to form the second implant region 27-2. . The second planting zone 27-2 can be used as a high pressure N-type zone. In one embodiment, the second implant zone 27-2 may have a depth of between about 0.4 and 0.6 μm, 201143090

The TW5638PA and the second portion 34-2 of the second dielectric layer 340 and the second portion 35-2 of the patterned first conductive layer 350 overlap. Then 'can be formed by the implantation process—called the third planting area, and the middle third planting area 28-丨 is located in the first planting area 274, and the other second planting d 28 The -1 system is located in the N-type crucible 21. In one embodiment, the concentration of the two second implanted regions 28-1 is between about 1〇15 and 1〇16 cm_3.

And its depth is about 〇.2叩. Similarly, two fourth planting zones-2 can be formed, wherein one fourth planting zone 28_2 is formed in the second planting zone 27_2, and the other fourth planting zone 28-2 is formed in the P-type. In the well 22. The concentration of the two fourth planting zones 28-2 is approximately between 1〇i5 and 1〇丨6. Melon _3, and its depth is about 0.2 μηη. And then 'the first dopant having a first concentration of about A 1013 cm·3 can be doped in the first portion 35_1 and the second portion 35·2 of the patterned second conductive layer 35〇' (10) into a non- The metal structure semiconductor device 2-1 is double-spread by a symmetrical structure. <Fig. 3 is a schematic cross-sectional view showing a double-diffused electrodeless metal oxide semiconductor device 3-1 according to an embodiment of the present invention. Referring to the second embodiment, the metal oxide semiconductor device 3-1 can be similar to the metal oxide semiconductor device 2_丨 described with reference to FIG. 2D, but the first portion 45-1 and the first portion of the second conductive layer 35 are patterned. The two portions 45-2 can replace the first portion 35] and the second portion of the patterned second conductive layer 350, respectively. Specifically, a first dopant having a second concentration of about 1G14em_3 may be doped in the first portion and the second portion 45-2 of the patterned second conductive layer 35 by an implantation process, And the second concentration is greater than the first concentration. The patterned second conductive layer 35 of the metal oxide semiconductor device 3-1 has a doping [201143090 1 W3035t" A * i , object. Therefore, the metal oxide semiconductor device 3-1 may be more suitable for low resistance applications than the metal oxide semiconductor device 2-1. Fig. 3B is a cross-sectional view showing a double diffused drain metal oxide semiconductor device 3-2 according to another embodiment of the present invention. Referring to FIG. 3B, the MOS device 3-2 can be similar to the MOS device 2-1 described with reference to FIG. 2D, but the second dielectric layer 440 and the patterned second conductive layer 450 are patterned. The patterned second dielectric layer 340 and the patterned second conductive layer 350 may be replaced, respectively. Specifically, after etching the second conductive layer 35 as shown in FIG. 2B, the patterned second conductive layer 450 φ includes the third portion 35-3 on the isolation structure 23, and includes the first portion 35-1 And the second part 35-2. In addition, after etching the second dielectric layer 34 as shown in FIG. 2B, the patterned second dielectric layer 440 includes a third portion 34-3 on the isolation structure 23, and includes a first portion 34-1 and a portion The second part is 34-2. The metal oxide semiconductor device 3-2 has third portions 34-3 and 35-3. Therefore, the metal oxide semiconductor device 3-2 may be more suitable for high resistance applications than the metal oxide semiconductor device 2-1. 4A and 4B are schematic cross-sectional views showing a method of fabricating a double-diffused metal oxide semiconductor device in accordance with another embodiment of the present invention. After forming the second dielectric layer 34 and the second conductive layer 35 as shown in FIG. 2B, referring to FIG. 4A, the patterned second conductive layer 550 can be etched by etching the second conductive layer 35 in the etching process. form. The patterned second conductive layer 550 can include a first portion 35-1R and a first portion 35-1L on the N-well 21, and a second portion 35-2R and a second portion 35-2L on the P-well 22. Next, the patterned second dielectric layer 540 can be patterned by using the second 12 201143090

The TW5638PA conductive layer 550 is a mask formed by etching a second dielectric layer 34 in an etching process. The patterned second dielectric layer 540 can include a first portion 34-1R and a first portion 34-1L on the N-well 21, and a second portion 34-2R and a second portion 34-2L on the P-well 22. . The first portion 34-1R of the patterned second dielectric layer 540 may extend over the first portion 25-1 of the first conductive layer 25, covering a portion of the upper surface 251T of the first portion 25-1, and patterning along The sidewall 251R of the first portion 25-1 of the first conductive layer 25 extends to the substrate 20. Additionally, the first portion φ 35-1R of the patterned second conductive layer 550 can be located on the first portion 34-1R of the patterned second dielectric layer 540. Similarly, the first portion 34-1L of the patterned second dielectric layer 540 may extend over the first portion 25-1 of the patterned conductive layer 25, covering another portion of the upper surface 251T of the first portion 25-1, and along The first portion 25-1 of the patterned first conductive layer 25 extends to the substrate 20. The first portions 35-1R and 35-1L may be separated from each other on the upper surface 251T. Additionally, the first portion 35-1L of the patterned second conductive layer 550 can be located on the first portion 34-1L of the patterned second dielectric layer 540. • Similarly, the second portion 34-2R of the patterned second dielectric layer 540 can extend over the second portion 25-2 of the patterned first conductive layer 25, covering the upper surface 252T of the second portion 25-2. A portion extends along the sidewall 252R of the second portion 25-2 of the patterned first conductive layer 25 to the substrate 20. Additionally, the second portion 35-2R of the patterned second conductive layer 550 can be located on the second portion 34-2R of the patterned second dielectric layer 540. Similarly, the second portion 34-2L of the patterned second dielectric layer 540 can extend over the second portion 25-2 of the patterned first conductive layer 25, covering the upper surface 252T of the second portion 25-2. A portion extends along the sidewall 252L of the second portion 25-2 of the conductive layer 25 along the patterned s 13 201143090 i 1 * to the substrate 20. The second portions 35-1R and 35-1L may be separated from each other on the upper surface 252T. Additionally, the second portion 35-2L of the patterned second conductive layer 550 can be located on the second portion 34-2L of the patterned second dielectric layer 540. Referring to FIG. 4B, the spacers 46 may be formed along the sidewalls of the patterned first conductive layer 550 and the patterned second dielectric layer 540. Next, a pair of first implanting regions 27-1 and 29-1 may be formed in the N-type well 21. The first planting zone 27-1 may overlap the first sections 34-1R and 35-1R. The first planting zone 29-1 separated from the first planting zone 27-1 may overlap the first sections 34-1L and 35-1L. Similarly, a pair of second implant regions 27-2 and 29-2 can be formed in the P-well 22. The second implanting zone 27-2 can overlap the second sections 34-2L and 35-2L. The second planting zone 29-2 separated from the second planting zone 27-2 may overlap with the other second sections 34-2L and 35-2L. A pair of third implanting regions 28-1 may be formed in the first implanting regions 27-1 and 29-1, respectively. Similarly, a pair of fourth implanting regions 28-2 may be formed in the second implanting regions 27-2 and 29-2, respectively. Next, a second dopant may be doped to the first portions 35-1R and 35-1L and the second portions 35-2R and 35-2L of the patterned second conductive layer 550. The first dopant has a first concentration of about 1013 cm·3 such that the double-diffused metal oxide semiconductor device 4-1 has a symmetrical structure. Fig. 5A is a cross-sectional view showing a double diffused drain metal oxide semiconductor device 5-1 according to still another embodiment of the present invention. Referring to FIG. 5A, the metal oxide semiconductor device 5-1 can be similar to the metal oxide semiconductor device described in FIG. 4B - but the patterned second conductive layer 550 201143090 · TW5638P is incorporated into the first portion 55-1R. And 55-1L and second portions 55-2R and 55-2L may respectively replace the first portions 35-1R and 35-1L and the second portions 35-2R and 35-2L of the patterned second conductive layer 550. Specifically, the first dopant having a second concentration of about 1014 cm_3 may be doped to the first portions 55-1R and 55-1L and the second portion of the patterned second conductive layer 550 by an implantation process. Parts 55-2R and 55-2L. The first portions 55-1R and 55-1L of the patterned second conductive layer 550 of the MOS device 5-1 and the second portions 55-2R and 55-2L have dopants. Therefore, the metal oxide semiconductor device 5-1 may be more suitable for low resistance applications than the metal oxide semiconductor device 4-1. FIG. 5B is a cross-sectional view showing a double-diffused-drain metal oxide semiconductor device 5-2 according to an embodiment of the present invention. Referring to FIG. 5B, the metal oxide semiconductor device 5-2 can be similar to the reference to FIG. The metal oxide semiconductor device 4-1, but the patterned second dielectric layer 640 and the patterned second conductive layer 650 may, for example, replace the patterned second dielectric layer 540 and the patterned second conductive layer 550, respectively. . Specifically, after etching the second conductive layer 35 as shown in FIG. 2B, the patterned second conductive layer 650 includes the third portion 35-3 on the isolation structure 23, and includes the first portion 35-1R. And 35-1L and the second parts 35-2R and 35-2L. Furthermore, after etching the second dielectric layer 34 as shown in FIG. 2B, the patterned second dielectric layer 640 includes a third portion 34-3 on the isolation structure 23, and includes a first portion 34-1R and 34-1L and second portions 34-2R and 34-2L. The metal oxide semiconductor device 5-2 has third portions 34-3 and 35-3. Therefore, the metal oxide semiconductor device 5-2 is more suitable for high resistance applications than the metal oxide semiconductor device 4-1. [ 15 201143090 TW5638PA . ' As described above, the concentration of the dopant in the high-pressure P-type region 27-1 and the high-pressure N-region 27-2 may be about 1012 to 1013 cnT3. When the concentration is at this level, the double-diffused-electrode-metal oxide semiconductor device having the structure according to the present invention may have a breakdown voltage greater than that of the double-diffused-electrode-metal oxide semiconductor device having the structure of the present invention, and the drain is There may be no significant change in the drain-to-source on-state resistance ( RdsON ). When the concentration level is increased, for example, increasing to more than 1〇12 to 1013 cm·3, the breakdown voltage may decrease, and the drain-to-source on-resistance may also decrease. A double-diffused-drain metal oxide semiconductor device having a low-drain-to-source on-resistance allows the power management integrated circuit to have a large power. According to this, the double-diffused-electrode metal oxide semiconductor device according to the present invention can be used in a high-voltage environment by increasing the concentration of the gate to the drain. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is defined by the scope of the appended claims, and the method and/or procedures of the present invention may be disclosed in a particular order. However, the methods or sequences of the present invention are not limited to this particular order. It will be appreciated by those of ordinary skill in the art that the steps of the method or procedure may have other sequences. Therefore, the specific order of steps described above is not intended to limit the scope of the invention. Furthermore, the scope of the patent application, which is related to the method and/or procedure of the present invention, should not be limited to the order of the steps described. Technical party to which the present invention pertains 201143090

‘ The general knowledge of the 1W5638PA domain may be different, but the spirit and scope of the present invention will not be removed. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are schematic cross-sectional views showing a conventional metal oxide semiconductor device; FIGS. 2A to 2D are diagrams showing a double diffused drain metal oxide according to an embodiment of the present invention. FIG. 3A is a schematic cross-sectional view showing a double-diffused drain metal oxide semiconductor device according to an embodiment of the present invention; FIG. 3B is a cross-sectional view showing another embodiment of the present invention; FIG. 4A and FIG. 4B are schematic cross-sectional views showing a method of fabricating a double-diffused metal oxide semiconductor device according to another embodiment of the present invention; FIG. 5A is a diagram A schematic cross-sectional view of a double-diffused-drain metal-oxide-semiconductor device according to still another embodiment of the present invention; and FIG. 5B is a cross-sectional view showing a double-diffused-drain metal-oxide-semiconductor device according to still another embodiment of the present invention. . [Explanation of main component symbols] 1-1, 1-2, 2-1, 3-1, 3-2, 5-1, 5-2: Metal oxide semiconductor device 10, 20: Substrate 11: N-type well region 12: P-type well area 13, 16, 23: isolation structure - 17 201143090 TW5638FA * ' 14-1 : The first part of the patterned dielectric layer 14 - 2: the second part of the patterned dielectric layer 15- 1 : The first portion of the patterned conductive layer 15-2: the second portion of the patterned conductive layer 17-1, 19-1: high voltage P-type region 17-2, 19-2: high voltage N-type region 18- 1. P+ type zone 18-2 · N+ type zone 24: patterned first dielectric layer 24-1: first part of N-type well zone 24-2: second part of P-type well zone 25: patterned first Conductive layer 25-1: first portion 25-2 of the first conductive layer: second portion 26, 46 of the first conductive layer: spacers 27-1, 29-1: first implant region 27-2 29-2: Second planting area 28-1: Third planting area 28-2: Fourth planting area 34: Second dielectric layer 34-1, 34-1L, 34-1R: Patterned second The first portion 34-2, 34-2R, 34-2L of the dielectric layer: the second portion 34-3 of the patterned second dielectric layer: the third portion 35 of the patterned second dielectric layer: second Conductive layer 35-1, 45- 1, 35_1L, 35-1R, 55-1L, 55-1R: Patterning 201143090

• TW5638PA first portion of the second conductive layer 35-2, 45-2, 35-2L, 35-2R, 55-2L, 55-2R: patterned second portion of the second conductive layer 35-3: patterning Third portion 251R, 251L, 252R, 252L, 351R, 352R of the second conductive layer: sidewalls 251T, 252T: upper surface 340, 440, 540, 640: patterned second dielectric layer 350, 450, 550, 650 : Patterning the second conductive layer

19

Claims (1)

201143090 1 W^03»PA * 5 , VII. Patent application scope: 1. A metal oxide semiconductor device comprising: a diffusion region in a substrate, comprising a first part having a second dopant type And a second portion having a first dopant type; a patterned first dielectric layer comprising a first dielectric portion and a second dielectric portion, the first dielectric portion being located in the diffusion a first portion of the region, the second dielectric portion being located on the second portion of the diffusion region; a patterned first conductive layer on the patterned first dielectric layer, the pattern The first conductive layer includes a first conductive portion and a second conductive Φ portion, the first conductive portion is located on the first dielectric portion, and the second conductive portion is located on the second dielectric portion; a patterned second dielectric layer includes a third dielectric portion and a fourth dielectric portion, the third dielectric portion extending over the first conductive portion and along one of the first conductive portions a sidewall extending to the substrate, the fourth dielectric portion being attached to the second conductive portion Extending upwardly and extending along a sidewall of the second conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, Φ the patterned second conductive layer comprises a first a third conductive portion and a fourth conductive portion, the third conductive portion is located on the third dielectric portion, and the fourth conductive portion is located on the fourth dielectric portion. 2. The device of claim 1, further comprising a first implant region, the second dopant type, located in the first portion of the diffusion region, the first implant region And overlapping the third dielectric portion and the third conductive portion. 3. The apparatus of claim 1, further comprising a 20201143090 • TW5638PA: cloth doping type, the second part of the diffusion zone is a second-planting zone and the a fourth dielectric portion and the fourth conductive portion 4. The device according to the scope of claim 2, =, a plurality of isolation structures, wherein the patterned: dielectric layer is located on the _ structures The plurality of patterned second conductive layers includes the fifth dielectric layer and the fifth conductive portion. The apparatus of the first aspect of the invention, wherein the pattern guiding layer comprises a plurality of first dopants, and the first one is a first A dopant type and having a first concentration. The method of claim 5, wherein the pattern of the first conductive layer comprises a plurality of first dopings of the first dopant type and having the first concentration. °海苐一/辰度系 greater than - you Ir as described in the scope of claim 2, the device further includes - the first planting zone is located in the first part of the diffusion zone, wherein the third planting zone A series is disposed in the first planting area. 8. The device of claim 1, wherein the first two== the first conductive portion of the first conductive portion—the second surface; the fifth plurality includes a fifth dielectric portion, the portion The second surface of the upper surface of the upper portion of the conductive portion is separated from each other by the third dielectric portion and the fifth dielectric portion. The device according to claim 8 further includes the first七* 21 201143090 1 W^bJSPA dopant type - the third planting zone, the third planting zone is located in the first part of the diffusion zone, and the third planting zone and the fifth mediation The electricity partially overlaps. 10. A metal oxide semiconductor device comprising: a germanium-diffusion region in a substrate - comprising a first portion of the second dopant type and a second portion having a first dopant type a patterned first dielectric layer including a first dielectric portion on the first portion of the diffusion region; a patterned first conductive layer on the patterned first dielectric layer, The patterned first conductive layer includes a first conductive portion on the first dielectric portion; a patterned second dielectric layer includes a second dielectric portion, the second dielectric portion is attached to the first a first portion of one of the upper surfaces of the conductive portion extends 'and extends along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer is disposed on the patterned second dielectric layer The patterned second conductive layer includes a second conductive portion on the second dielectric portion. The device of claim 10, further comprising a first implanting region as the second dopant type, located in the first portion of the diffusion region, the first implant region And overlapping the second dielectric portion and the second conductive portion. 12. The device of claim 1, wherein the patterned second dielectric layer comprises a third dielectric portion and the third dielectric portion is attached to the first conductive portion The second dielectric portion and the third dielectric portion of the second portion of the surface are separated from each other on the upper surface by 22 201143090. * TW5638PA includes a device according to item 12 of the stomach patent (4), wherein In addition, the first cloth (four) is the second dopant type, located at 14th. And the second planting zone and the third dielectric component are as heavy as the device described in claim 10, and include a plurality of isolation structures on the substrate, 5 comprising a plurality of dielectric devices on the isolation structure. 5. The device according to claim 10, wherein the second conductive layer comprises a plurality of first dopants, and the first: two The system is of the first dopant type and has a first concentrate. The first conductive layer includes a plurality of first dopants, and the first plurality of first dopant types have a first eve ', at the first - concentration. The second concentration is greater than the apparatus described in claim 1, wherein the first dielectric layer comprises the second portion of the second portion of the diffusion region. The dielectric portion 'the patterned first conductive layer includes a third conductive portion on the third dielectric layer' and the patterned second dielectric layer includes a fourth dielectric portion 'the fourth dielectric portion Extending to the first portion of the upper surface of the third conductive portion and extending along the third conductive sidewall to the substrate. 18. The device of claim 17, wherein the patterned second conductive layer comprises a fourth conductive portion on the fourth dielectric portion, the metal oxide semiconductor device further comprising - a second The implanting region is the first dopant type and is located in the second portion of the diffusion region, and has a 23 201143090 TW5638PA § hai first planting zone overlapping the fourth dielectric portion. a metal oxide semiconductor device comprising: - a diffusion region in the substrate, comprising a second portion having a second dopant type and a second portion having a first dopant type; - patterning The first dielectric layer 'includes one of the first dielectric portions on the diffusion region; ^ the second-patterned first-conductive layer' is located at the patterned first patterned first conductive layer, including the first 3 on the dielectric portion, - conductive portion; 1 - the first - patterned second dielectric layer 'including a second dielectric portion and three: electrical portion 'the second dielectric portion is attached to the first a conductive portion extending over the first conductive portion of the first conductive portion extending to the substrate, the second "electrical portion" extending over the first conductive portion and extending along the first conductive second sidewall to the substrate The second dielectric portion and the first electrical portion are separated from each other on the first conductive portion; and a patterned second conductive layer is disposed on the patterned second dielectric sound, the patterned second The conductive layer includes a second conductive portion on the second dielectric portion, and is located a third conductive portion on the third dielectric portion. The device of claim 19, further comprising a f implant region as the second dopant type, located in the diffusion region In the third part, the first planting zone overlaps with the second dielectric component. 21. The device of claim 19, further comprising a vertical-planting zone for the second The dopant pattern is located in the first trowel of the diffusion region, and the second implant region overlaps the third dielectric portion. 24 201143090 • · TW5638PX. 22. As described in claim 19 The device further includes a plurality of isolation structures on the substrate, wherein the patterned second dielectric layer comprises a plurality of fourth dielectric portions on the isolation structures, and the patterned second conductive layer comprises A plurality of fourth conductive portions on the fourth dielectric portion. The device of claim 19, wherein the patterned second conductive layer comprises a plurality of first dopants, the a dopant is the first dopant type and has a first concentration The device of claim 23, wherein the patterned second conductive layer comprises a plurality of first dopants, the first dopants being the first dopant type and having The second concentration is greater than the first concentration. The device of claim 23, wherein the patterned first dielectric layer comprises the second portion of the diffusion region a fourth dielectric portion, the patterned first conductive layer includes a fourth conductive portion on the fourth dielectric portion, and the patterned second dielectric layer includes a fifth dielectric portion and a sixth dielectric portion extending over the fourth conductive portion and extending along the first sidewall of the fourth conductive portion to the substrate, and the sixth dielectric portion is tied to The fourth conductive portion extends and extends along the second sidewall of the fourth conductive portion to the substrate, and the fifth portion and the sixth portion are separated from each other on the fourth conductive portion. 25