201142809 六、發明說明： 【發明所屬之技術領域】 本發明係關於顯示裝置，尤其關於用於在圖形顯示裝置内 儲存及存取像素資料之系統及方法。 【先前技術】 行動裝置例如手機，通常使用液晶顯示（LCD )面板以顯 示影音或是靜態的圖像。LCD面板通常可耦合至顯示驅動器， 其可使用同步訊號從處理器接收影像資料，並執行LCD面板 的驅動控制。 在某些系統中，顯示控制器亦可用於接管主處理器所供應 的影像及同步訊號。顯示控制器亦可具有一個記憶體，用於儲 存即將被顯示的圖形之像素資料。為了有效降低功抵，顯示控 制器所安裝的記憶體通常為靜態隨機存取記憶體（SRAM)，其 它類型的記憶體例如動態隨機存取記憶體（DRAM)消粍 能。雖然SRAM的存取速度比和處理器連接之匯流排 便度慢，對於小尺寸的⑽面板而言，使用 高顯」 ’由於行動襄置逐漸地採用較大尺寸且具有較 資料、_度的顯示面板’儲存於顯示控制器之奸體的傻夺 度將嚴重地阻礙更高解析度丄：SRAM有限的存取速 種系统及方法’其可用更有效率的方 201142809 【發明内容】 财ΛΑ ί發明係揭露用於在圖形顯示裝置内儲存及存取像素資 置内儲S 口料在某一實施例中’係揭露一種在圖形顯示裝 第二之方法，其中圖形顯示器包含第-記憶體、 ° ^ 1及/刀別與第-及第二記憶體耦合之資料轉送栌 對於影像資料内接續的每—對相鄰的像素，此方法包含 =閃素對應的第一像素資料、接收和第二像素對 將第二像素資料寫入第二記憶體。 弟肅且 干F f 施例中’本發明亦揭露—圖形顯示裝置。圖形顯 不裝置包含第-記憶體、第二記憶體以及分 轉送控制器。諸轉送控制器係組態為接二 第-後去2所對應的第—像素資料，接收第二像素所對應的 料’並同時地將第-像素資料寫入第-記憶體且將 第一像素資料寫入第二像素記憶體。 全而ίίι實施例中，係揭露—種在圖形顯示裝置内處理影像 二 方法。此方法包含存取第一及第二記憶體以 I出〜像旦面上母一對相鄰像素的像素資料，當影像晝面且 “門時二決定是否最終像素所對應的最終像素資料處 狀怨，當最終像素資料處於閃鎖的狀態時將最終像素 目貝料轉送控制器讀出。 小一在此所狀系統及方法至少一個優點^其可同時存取至 二二個記憶體以同步且成對地寫人像素資料。因此，可大 苜加記憶體總和存取的速度。 201142809 先前所述係為一概要簡介而不應理解為限縮申請專利範 圍之用。在此描述之操作及結構可以用許多種方式實現，且這 些變化及調整可以在不脫離本發明及其目地的範圍下實現。其 它的目的，技術特徵，及本發明之優點，如同由申請專利範圍 所定義，且由以下非限制性的實施方式揭露。 【實施方式】 第1圖係依據本發明之一實施例描述圖形顯示裝置100之 概要圖示。圖形顯示裝置100可為行動電話、個人數位助理、 遊戲裝置、個人電腦、筆記型電腦或其它任何可執行包含影像 顯示的一個或多個功能之裝置。依據一實施例，圖形顯示裝置 100可包含主處理器102、顯示控制器104、顯示驅動器106 以及顯示面板108。 主處理器102可執行由圖形顯示裝置100所要求的處理任 務。尤其，主處理器102可處理或將影像資料轉換像素資料以 在顯示面板108上呈現，並提供像素資料給顯示控制器104。 顯示驅動器106，其可包含時脈控制器、源極驅動器以及閘極 驅動器（在此未顯示），可自顯示控制器104接收像素資料， 並將像素資料轉換為驅動訊號以控制顯示面板108内的像素陣 列。 顯示控制器104係用於儲存由主處理器102所提供的像素 資料。並且，顯示控制器104亦可接管主處理器102所處理的 某些工作，以降低主處理器102的處理負載。如圖所示，顯示 控制器104可包含主介面112、資料轉送控制器114、以及第 201142809 -及第二記憶體116及118。在某—實施例中，第—及第二記 隐體116及118可為靜態隨機存取記憶體（SRAMs)。主介面 L12可從主處理器⑽接收並依續地儲存像素資料，並將像素 =流傳輸給資料轉送控制器114。資料轉送控制器ιΐ4分別 ”第-及第二記憶體116及118搞合，並可獨立驅動第一或201142809 VI. Description of the Invention: [Technical Field] The present invention relates to display devices, and more particularly to systems and methods for storing and accessing pixel data in a graphics display device. [Prior Art] A mobile device such as a mobile phone usually uses a liquid crystal display (LCD) panel to display video or static images. The LCD panel can typically be coupled to a display driver that can receive image data from the processor using a sync signal and perform drive control of the LCD panel. In some systems, the display controller can also be used to take over the image and sync signals supplied by the host processor. The display controller can also have a memory for storing pixel data of the graphic to be displayed. In order to effectively reduce the performance, the memory installed in the display controller is usually a static random access memory (SRAM), and other types of memory such as dynamic random access memory (DRAM) can be used. Although the access speed of the SRAM is slower than that of the processor connected to the processor, for the small size (10) panel, the use of high display "because the action device gradually adopts a larger size and has a more data, _ degree display The sillyness of the panel 'stored in the display controller will seriously hinder the higher resolution. SRAM limited access speed system and method'. It can be used more efficiently. 201142809 [Invention content] Finance ί The invention discloses a method for storing and accessing a pixel storage device in a graphic display device. In an embodiment, a method for displaying a second in a graphic display device is disclosed, wherein the graphic display comprises a first memory, ° ^ 1 and / knives are coupled with the first and second memory data transfer 栌 for each adjacent pair of pixels in the image data, this method includes = first pixel data corresponding to luciferin, receiving and The two pixel pair writes the second pixel data into the second memory. In the example of the invention, the invention also discloses a graphic display device. The graphic display device includes a first memory, a second memory, and a transfer controller. The transfer controller is configured to receive the second pixel corresponding to the second pixel data, receive the material corresponding to the second pixel and simultaneously write the first pixel data into the first memory and the first The pixel data is written to the second pixel memory. In the entire embodiment, the method of processing an image in a graphic display device is disclosed. The method comprises: accessing the first and second memory to extract the pixel data of the pair of adjacent pixels on the surface of the image, and when the image is on the surface and “the gate determines whether the final pixel corresponding to the final pixel is Resentment, when the final pixel data is in the state of flash lock, the final pixel is transferred to the controller for reading. The first system and method have at least one advantage, which can simultaneously access two or two memories. Synchronous and paired writing of human pixel data. Therefore, the speed of memory summation access can be greatly increased. 201142809 The foregoing description is a brief introduction and should not be construed as limiting the scope of the patent application. The operation and structure can be implemented in a variety of ways, and such changes and modifications can be made without departing from the scope of the invention and its objects. Other objects, features, and advantages of the invention are as defined by the scope of the claims. And the following non-limiting embodiments are disclosed. [Embodiment] FIG. 1 is a schematic diagram showing a graphic display device 100 according to an embodiment of the present invention. The device 100 can be a mobile phone, a personal digital assistant, a gaming device, a personal computer, a notebook computer, or any other device that can perform one or more functions including image display. According to an embodiment, the graphic display device 100 can include a main processing. The device 102, the display controller 104, the display driver 106, and the display panel 108. The main processor 102 can perform processing tasks required by the graphic display device 100. In particular, the main processor 102 can process or convert image data to pixel data. Displayed on display panel 108 and providing pixel data to display controller 104. Display driver 106, which may include a clock controller, a source driver, and a gate driver (not shown), may receive pixels from display controller 104 The data is converted into drive signals to control the array of pixels within display panel 108. Display controller 104 is used to store pixel data provided by host processor 102. Also, display controller 104 can take over the main processing. Some of the work handled by the processor 102 to reduce the processing load of the main processor 102. As shown, The controller 104 can include a main interface 112, a data transfer controller 114, and a 201142809 - and second memory 116 and 118. In an embodiment, the first and second hidden objects 116 and 118 can be statically random. Access memory (SRAMs). The main interface L12 can receive and continuously store pixel data from the main processor (10), and transmit the pixel=stream to the data transfer controller 114. The data transfer controller ιΐ4 respectively - the first and the The two memories 116 and 118 are combined and can drive the first or independently
::己憶體116及118中的任何-個。資料轉送控制器U4可组 態為接收並閃鎖第-像素(標記為L)所對應的第一像素資料、 接收並問鎖第二像素（標記為R)所對應的第二像素資料，並 =將第-像素資料寫入第一記憶體116且將第二像素資料 二i己憶體118。第—及第二像素為一個影像晝面上相鄰 Γ =二如可以是位於影像畫面上同一行或同-攔的相鄰像 ^ ^科轉运控制器114可將第一或第二記憶體116及ιΐ8其 同指派給自主介面112接收的像素資料，並藉由 /子取第-及第二記憶體116及118， 而【，面的像素資料儲存於第一及第二=;6 二二=像畫面上每一個給定的像素，其具有對應 的像素貝枓儲存於及第二記憶體116及118 存取被要;時，資料之另一個。另外’當像素資料的 二記憶體丄寫♦及第 —· 〇 ::2的存取命令後’資料轉送控制器114可自dj處= ⑽或顯㈣動㈣’並將像素㈣轉送給主處理器 201142809 第2圖係為描述資料轉送控制器114之一實施例的概要圖 示。資料轉送控制器114可包含一個上部記憶體控制器206、 第一及第二先入先出（First-In-First-Out，簡稱FIFO)緩衝器 208A及208B、位址控制器210、微指令集電腦（Minimal:: Any one of the memories 116 and 118. The data transfer controller U4 is configured to receive and flash the first pixel data corresponding to the first pixel (labeled as L), receive and lock the second pixel data corresponding to the second pixel (labeled as R), and = writing the first pixel data to the first memory 116 and the second pixel data to the second memory 118. The first and second pixels are adjacent to each other on the image side. If the image is on the same line of the image frame or the adjacent image of the same image, the first or second memory can be used. The pixels 116 and ι 8 are assigned to the pixel data received by the autonomous interface 112, and the first and second memories 116 and 118 are taken by /, and the pixel data of the surface is stored in the first and second = 6 Two or two = like each of the given pixels on the screen, with corresponding pixels stored in the second memory 116 and 118 access is required; In addition, 'when the two memory of the pixel data is written ♦ and the first -> 〇::2 access command, the data transfer controller 114 can be from dj = (10) or display (four) move (four) 'and transfer the pixel (four) to the main Processor 201142809 FIG. 2 is a schematic illustration depicting one embodiment of a data transfer controller 114. The data transfer controller 114 can include an upper memory controller 206, first and second first-in-first-out (FIFO) buffers 208A and 208B, an address controller 210, and a microinstruction set. Computer (Minimal
Instruction Set Computer ’ 簡稱 MISC )控制器 212、以及角落 控制器214。上部記憶體控制器206可接收各種訊號，包括控 制訊號’例如匯流排時脈訊號（bus clock signa卜在此標記為 BUS-CLK)、影像晝面的像素資料、以及與來自主介面U2之 影像畫面相關的畫面尺寸資料，並可將像素資料閂鎖於第一及 第二先入先出緩衝器208A及208B其中之一。位址控制器21〇 可才曰派給每一個像素一個第一及第二記憶體116及118其中之 的儲存位址，並傳輸此儲存位址給微指令集電腦控制器 212。微指令集電腦控制器212可存取第一及第二記憶體⑽ 及118以寫入或讀出像素資料。尤其，微指令集電腦控制器212 可以將像素貝料從先人先出緩衝器2G8A及2娜，與對應的 =空制訊號CLK_L及CLK_R同步地寫人至第—及第二記㈣ 而，118^而達到同時存取第一及第二記憶體116及118。故 ，，素資料可被同步且成雙地被寫人至第—及第 角了存取的速度。當觀 蚁像14可處理和此影像畫面的「角落」或最 的像。：工無法和下—個像素配對以寫入記憶體)所對庫 並且’在下一個指令週期:貝:：問鎖此最終像素資料。 ^被觸舍時，資料轉送控制器114可將 201142809 素資料釋放並寫入至第-記憶體ιΐ6。因此， 及時地將最攻^暫時地保留和最終像素資料相關的資訊，並 顯不驅動器106作為顯示之用。·..、 5己隐體成疋輸出、 如何將佥面為依據本發明之—實施例的概要圖示，其描述 ηΓ如=之!素資料儲存於第-及第二記憶體m及 (ij)，i中办像晝面F可被定義為像素資料的陣列Ρ 指定垂直攔二指定水平列的像素資料，J為一整數， 數η定義。旦而畫面F的尺寸可由總列數m及總攔 己=晝面F的像素資料或可依據不同的方向寫入^ 及弟一 5己憶體116及118。 第3B圖描述資料寫 料可依攄^“ R向。影像畫面F的像素資 或一欄接著-欄依續^皮^入X、—MY)的設定，一列接著一列 八别冲I . 、貝也被寫入。母一個參數MV、MX、MY可 I垂直、反水平、反垂直的掃描順序。 束於蚁點E3B^所述’寫人㈣_序可妙料點B並結 ί 2 例如，（Mv、MX、Μγ)為（0、〇、〇)之π 應畫面F之像素係以正常的方向，即由左至右存: (MV、MX、MY)為η Λ Λ、 I7田左至右存取。 係以另-個存取順岸、㈣μ之設定係對應晝面F之像素 1 w 序 至下存取。（mv、mx、my)為 即由右至應晝面^像素係以另—個存取順序， 對應另：：)為(°'。、1)之狀係 料窝存順序，即由下至上寫入。資 〜匕方向可能包括（Μν、Μχ、Μγ)為（〇、卜㈠ 201142809 之設定，其係對應晝面F之像素的存取順序為由右至左且由下 至上存取；（MV、Mx、MY)為（1、〇、1)之設定，其係對 應畫面F《像素的存取順序為由下至上且由左至右存取； (MV MX、MY)為（1、！、〇)之設定，其係對應畫面f之 像素的存取順序為由上至下且由右至左存取；（mv、mx、my) 1】）之0又疋，其係對應畫面F之像素的存取順序為 由下至上且由右至左存取。 無哪寫入的順序為何，影像畫面F的儲存需使得在同一棚 目鄰的像素資料以及在同—列相鄰的像素資料總是被儲存在 ==己憶體（如第3A圖所示，陣列的灰色方塊係對應被儲 ^第二記憶體118的像素資料，而白色方塊係對應被儲存在 116的像素資料）。例如，在同一水平列上相鄰的 ^叩’1)及（1，2)可分別被儲存在第一及第二記憶體116 同樣地在同一垂直攔上相鄰的像素資 可分別被儲存在第一及第二記悻體116及）及以2，1) 弗°己隐體116及118。因此，對於影 上母-給定的像素資料皆具有對應的像素㈣儲存在 第一及第二記憶體116及118的其中之一，每一和仏 鄰的像素皆具有對應的像素資料儲存抑體、 方向，'，不論資料寫入採用何種資料 對相鄰記憶體116及118總是可以同步地寫入每-打相磾的像素資料，進而同時地被存取。 第4圖係為時脈訊號的時間圖，其 ，地寫入第一及第二二==步 、枓轉墟制g 114可接收朗鎖__個像素㈣，例如影像畫 10 201142809 =像素資料吼丨），此動作可和匯流排時脈訊號则cm 的脈衝同步。在接著的時fa1t2,資料轉送控制器ιΐ4可接 -個像素f料，额切麟㈣騎㈣ :的像素資料叩，2)’並接著同時地存取第_及第‘= 排二二寫入二個相鄰的像素資料’此動作可和匯流 排時脈輯的二個同步脈衝c L K_L及CLK_R同步。 取方式可接續地重覆，例如在時間t3及t4時，以將每―下__ =相鄰2像素資料’例如影像畫面F的像素資料p⑽及 及;丨’:：第一及第二記憶體。當每一第—及第二記憶體Μ 及118的存取頻率相㈣，總和的存取頻率就可因此加倍。 然以上所述的方式可被應用於每—對相鄰的像素，有時 而、別的處理方式以處理角落像素及/或當要寫人之像素的 為奇^時的情況。為了更詳細的描述，第认圖係為二 要圖不，其描述當要寫入的像素數目為奇數時會發生 114可接收並_每一對像蝴 一象素貝枓，並接者將這些資料寫入實體的記憶體中，例如 :及第二記憶體116及118 ’如前所述。然而，當像素 ::奇f時，最終像素亦可能不被寫入實體的記憶體中二例：， I目刖有五個像素要被寫入第一及第二記憶體116及川中 則第五個像素可能被保存在資料轉送控制器114中。 处 :素對應的資料’可在下個-指令發出時被讀出或寫至第：： 第二記憶體116及118其中之一。 及 素溆！ 係為一概要圖示’其描述當要寫入主動視窗的像 -目為奇數時會發生邊角像素的範例。主動視窗可以是顯示 11 201142809 104所要處理的畫面其中一部份。顯示控制器刚 :也處理主動視窗中的各個像素，由第—個至最後—個， 理像素：更新主動視窗。除了在有與前述不同的處 工被指疋時’當主動視窗像素的數目為奇數時，主 第敢終像素及第-像素可被寫入相同的實體記憶體 第一记憶體116及118其中之一。仿诚一奈^ , J終像素可被保存在資料轉送控制器114，而二 =一=體m及118其令的任何一個。回應下一命令的發 ^呆存在資料轉送控制器114的資料可被讀出或寫人至卜 及第一記憶體116及118的其中之一。 及‘二由在下一個寫入命令時’僅有第一及第二記憶體116 114的：二：：：是需要被存取以寫入保存在資料轉送控制器 最炊傻。並且’在下一個寫入命令發出之前，若 t r要被顯示或是被其它程序使用，系統可以從資 /斗轉运控制杰114提取正確的最終像素資料。 ㈣第卜2、3A_B及8A-B圖’第5圖係描述將像素資 ^儲存於圖形齡裝置_賴行之方法步㈣流程圖。豆 ^圖、形顯示裝置⑽可包含第一記憶體116、第二記憶體m :別與第—及第二記憶體116及118耦合的資料轉送控制 ° 在此所述之方法步驟可由資料轉送控制器114執行以 田像素二貝才斗。在初始步驟501 _，資料轉送控制器114所採 的資料寫人方向-開始先被選定。如前所述’所選的資料寫 =方向Γ依據參數（MV、MX、MY)定義。在步驟502中， 貝料轉运控制器114可與匯流排時脈訊號bus—clk同步，接 12 201142809 收並閃鎖影像畫面之第—像素所對 的步驟504中，資料轉送控制器1、第一像素資料。在接續 BUS—CLK的下—個脈衝同步，=可與匯流排時脈訊號 像素資料，其中第一像素係與第一t和第二像素所對應的第二 可以是在影像畫面上的同一行或a s素相鄰。第一及第二像素 料轉送控制器114接著可與同同=攔。在步驟5〇6中，資 同步，同時將第一像素資料寫入第^讯號CLKJL及CLK_R 資料寫入第二記憶體118。在下一 + °己憶體116且將第二像素 器114可接著決定是否要處理下一508中，資料轉送控制 晝面為具有偶數個總像素，社固像素。如果沒有，則影像 當需要處理下-個像素時了2程序。 送控制器U4將蚊是否此下=續的步驟51()中，資料轉 之最終像素。當此下—個像素 素為正在處理的影像晝面 可用與先前所述相同的方式重^最終像素時，步驟 502-506 ，鄰像素。影像晝面之各對 執仃，以寫人接下來的一對 者所選的資料寫人方向處理。、、相鄰像素可用相同的方式沿 相反地，若接著要虑 像素係具有總數為奇數的像素。，為最終像素，則目前處理的 了，收和影像晝面之最終像 此情況下，角落控制器214 像素資料。在步驟512中，、二的最終像素資料，並問鎖此 、攻、、冬像素對應的像素資料 落控制器214可暫時地儲存 5二T -個命令趟期被觸發時及其相闕的館存位址 :如下所 /己憶體116。例如，當要最終像素資料可稍後被釋出 落控制器214的最終像素次*存取最終像素資料時，問鎖 、周科可被輸出，或寫入至第一記 201142809 憶體116以回應下一寫入命令的發生。 第6圖為一概要圖示’其描述 行，以釋放閃鎖於角落控制器214 器m所執 程。在步驟602中，最坎# 、·、像素貝料的步驟流 制器…之角落控制在資料轉送控 器114可偵測是否下一命令已被發出身料轉送控制 的存取被要求。下一命令可能為:或3最終像素資料 體116及118其中之一的命令寫)第—及第二記憶 當儲存在第-及第二記憶體116| 118些情況，例如 需被讀出以顯示在顯示面板 t旦面之像素資料必 會需要存料料靖4。如⑽理時，可能 以存取最終像辛資料，畏饮你主欠有偵J到下一個命令及需求 叫中。如it二在衫控制器 觸發時，在步驟606中7角落如當下-個命令週期被 —寫入第一及= 3素資料， =儲存在其中的影像畫面的資 ’以補 求時，在步驟608中，被寫入第一及第:的存取被要 像素資料可被輸出。 _及第一讀體U6及118的 鎖在=二素;=取被要求且又最終像素資料仍㈣ 以取代儲存在Ϊ = 器214的最終像素資料， 存位置的像=因:記憶體Μ及118… 〕像素貝枓。因此，可確保被讀出 依照前述之實施例，影像晝面的像素資料可因^^^且 14 201142809 力^地錯存在正相_料。因此，整體_存取速度可 其描=;二:：Γ及8A-B圖，第7圖係為-流程圖， 控所執行之方法步驟，其用於讀取 你乐及第一5己憶體116及118 蚩 資料轉送控制器114可回應指令. 存取儲存在第一及第二記憶體116 Λ m曰二：：求 料，執行在此所示之步驟流程。在初始步驟702 ;面=資 =制器114可由第-記憶體116讀出晝面之第一像辛； =步驟70”，資料轉送控制= 咖也;;需了解，由於資料轉送 驟702及704係可被互換，或同時地執：隐體116及118，步 出二…Μ可決定是否將讀 素，可結束此程序。則衫像畫面為具有偶數個總像 送控錢續的步驟別中，資料轉 之最終像素，是：::二素 料轉送控制器114可決定a 否則在步驟708中資 如果下-像素資料不是最^ ^”料為最終像素資料。 斌〜像素貝料，步驟702-700可用盥先 π6'ΐ Μ旦面接下來的—對相鄰像素。否則，可決定 15 201142809 =二有：一數:，。因此，在步驟-中，資料轉送 控制器2丨4的狀/中'7:否最终像素資料處於_在角落 料，以取_存在第^ 4可仙出料正柄最終像素資 素資料。第二記題116们18其中之-的像 表最坟像㈣11 214沒㈣鎖住最終像素資料，則代 角落控制器214中被釋放給第-及第」： ^ 。則在步驟714中，資料轉送控制器114可自 資料。—己憶體116及118其中之—讀取出正確的最終像素 方統及方法之至少—個優點為，其可以同時的 =式存取夕個記憶體’關步且成對地寫人像素資料。另外， 在此所述之系統及方法可成功地處理特殊的狀況，例如 不是成對時，例如第从及犯圖所示之影像晝面的角落像素^ 因此:’和傳、_介面相比’存取速率可有效地增為至少兩倍。 二，後，在不脫離本發明之精神及範圍内，如同以下所述之 申=範圍，在此領域中具有通常技㈣應能㈣地制本發明 揭露之概念及實關，以用於設計或改良其它架構，並用以達 成與本發日狀目的相狀功用。又，以±實施觸述之各別分 離的元件之結構及功能亦可整合在單一個組合的結構或元件 中。 【圖式簡單說明】 第1圖係依據本發明之一實施例描述圖形顯示裝置之概要 16 201142809 圖示； 第2圖為一概要圖示其依據一實施例描述第^ 形顯示裝置内所實施的資料轉送控制器； 不" 第3Α圖為-概要圖示其依據本發明之—實施例描述如何 含= 在第1圖所示之_顯示裝置内所包 方向第3Β圖係依據本發明之另一實施例描述不同的資料寫入 第4圖係為時脈訊號的時間圖，其描述像素資料如 且成對地寫人第3Α圖所示之第—及第二記憶體； y 執行據上發明之一實施例描述由資料轉送控制器所 執仃以寫人像素資料之方法步驟的流程圖； 第6圖為-概要圖示，其依據本發明之—實施例描 釋放閃鎖於資料轉送控制器内最終像素資料的流程；； 轅、、流程圖，其依據本發明之—實_描述由資料 轉^制器所執行以讀取出晝面的像素資料之方法步驟^ 8 A圖係為一概要圖示，盆描述♦要宫入的禮本知 奇數時將有角落像素的範例；以^田过田要寫入的像素數目為 像去f 8B圖係為一概要圖示’其描述當要寫入於主動視窗的 像素數目為奇數時將有角落像素的範例。 動視由的 【主要元件符號說明】 100 .圖形顯示裝置 J〇2 :主處理器 17 201142809 104 :顯示控制器 106 :顯示驅動器 m·顯示面板 112 .主介面 114 :資料轉送控制器 116 :第一記憶體 118 :第二記憶體 206 :上部記憶體控制器 208B:第二先入先出緩衝器The Instruction Set Computer ’ (referred to as MISC) controller 212, and the corner controller 214. The upper memory controller 206 can receive various signals, including control signals, such as bus clock signals (bus clock signa), pixel data of the image plane, and images from the main interface U2. The screen-related picture size data can be latched to one of the first and second first-in first-out buffers 208A and 208B. The address controller 21 can send a storage address of each of the first and second memories 116 and 118 to each pixel, and transmit the storage address to the microinstruction set computer controller 212. The microinstruction set computer controller 212 can access the first and second memories (10) and 118 to write or read pixel data. In particular, the microinstruction set computer controller 212 can write the pixel data from the ancestors first out buffers 2G8A and 2A, and write the same to the first and second records (4) in synchronization with the corresponding = null signals CLK_L and CLK_R. The first and second memories 116 and 118 are simultaneously accessed. Therefore, the prime data can be synchronized and double-written to the speed of access to the first and the third corner. When viewing the ant image 14, it can handle the "corner" or the most image of the image. : Worker can't pair with the next pixel to write to the memory) and in the next instruction cycle: Bay:: ask to lock this final pixel data. When the ^ is touched, the data transfer controller 114 can release and write the 201142809 element data to the first memory ι6. Therefore, the information relating to the final pixel data is temporarily retained in the most timely manner, and the drive 106 is shown as a display. ···, 5 隐 隐 疋 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要 概要Ij), i can be defined as an array of pixel data Ρ specify the pixel data of the specified horizontal column of the vertical barrier, J is an integer, the number η is defined. Once again, the size of the picture F can be written by the total number of columns m and the pixel data of the total block = face F or can be written in different directions ^ and the memories 1 and 116. Figure 3B depicts the data writing can be based on the "R direction. The pixel of the image frame F or a column followed by - column continued ^ skin ^ into X, - MY) settings, one column followed by a column of eight different I. The shell is also written. The parent parameter MV, MX, MY can be vertical, anti-horizontal, and anti-vertical scan order. The bundle is at the ant point E3B^The 'write person (four) _ order can be a good point B and tie ί 2 For example, (Mv, MX, Μγ) is π of (0, 〇, 〇). The pixel of the picture F is in the normal direction, that is, from left to right: (MV, MX, MY) is η Λ Λ, I7 Field left to right access. The other is to access the bank, and the (4) μ setting corresponds to the pixel 1 w of the face F to the next access. (mv, mx, my) is from right to right. ^Pixel is in another access order, corresponding to another::) is the order of (°'., 1), which is written from bottom to top. The direction of 匕~匕 may include (Μν, Μχ, Μγ) is (〇, 卜(一) 201142809, the access order of the pixels corresponding to the face F is from right to left and from bottom to top; (MV, Mx, MY) is (1, 〇, 1) ) setting, corresponding to the picture F "pixel The access order is from bottom to top and from left to right; (MV MX, MY) is set by (1, !, 〇), and the access order of the pixels corresponding to the picture f is from top to bottom and is Right to left access; (mv, mx, my) 1]) 0 and 疋, the access order of the pixels corresponding to the picture F is from bottom to top and from right to left access. Why, the storage of the image frame F is such that the pixel data adjacent to the same shed and the pixel data adjacent to the same column are always stored in the == memory (as shown in Figure 3A, the gray square of the array) Corresponding to the pixel data stored in the second memory 118, and the white squares correspond to the pixel data stored in 116. For example, adjacent 叩'1) and (1, 2) in the same horizontal column may be respectively The pixel resources stored in the first and second memory bodies 116 are similarly stored on the same vertical barrier, respectively, and are stored in the first and second recording bodies 116 and 2, respectively, and 2, 1) 116 and 118. Therefore, for the pixel-given pixel data, there are corresponding pixels (4) stored in the first and second memories 116 and 118. In one case, each pixel adjacent to the neighbor has a corresponding pixel data storage inhibitor, direction, 'whatever data is written, the adjacent memory 116 and 118 can always be written synchronously. The corresponding pixel data is simultaneously accessed. Figure 4 is a time chart of the clock signal, which is written into the first and second two == steps, and the g 114 can receive the lock __ pixels (four), for example, image 10 10,42,809, 809 = pixel data 吼丨), this action can be synchronized with the pulse of the bus clock signal, cm. At the next fa1t2, the data transfer controller ιΐ4 can be connected to a pixel f Material, the amount of cutting (four) riding (four): the pixel data 叩, 2) 'and then simultaneously access the _ and the first = row two two write two adjacent pixel data 'this action and bus time clock The two sync pulses c L K_L and CLK_R are synchronized. The fetching method can be repeated successively, for example, at time t3 and t4, to select each pixel data p(10) of the image data F of the next __ = adjacent __; 丨 ':: first and second Memory. When the access frequency of each of the first and second memories 118 and 118 is phased (four), the sum access frequency can be doubled. However, the above-described manner can be applied to each of the adjacent pixels, and sometimes, other processing methods to process the corner pixels and/or when the pixels to be written are odd. For a more detailed description, the first picture is a two-dimensional picture, which describes that when the number of pixels to be written is odd, 114 can be received and _ each pair is like a pixel, and the splicer will These data are written into the memory of the entity, for example: and the second memory 116 and 118' are as previously described. However, when the pixel:: odd f, the final pixel may not be written into the memory of the entity. In the case of I, there are five pixels to be written into the first and second memory 116 and the middle of the river. Five pixels may be stored in the data transfer controller 114. The information corresponding to the prime can be read or written to the next: - when the instruction is issued: one of the second memories 116 and 118. And Su Min! It is an outline illustration which describes an example of a corner pixel when an image to be written to the active window is odd. The active window can be part of the screen to be displayed by 11 201142809 104. The display controller just: also processes each pixel in the active window, from the first to the last, the pixel: update the active window. When the number of active window pixels is an odd number when there is a different workmanship than the foregoing, the main terminal pixel and the first pixel can be written to the same physical memory first memory 116 and 118. one of them. In the same way, the J final pixel can be saved in the data transfer controller 114, and the second = one = body m and 118 of any of its orders. The data of the data transfer controller 114 in response to the next command can be read or written to one of the first memories 116 and 118. And ‘two by the next write command ’ only the first and second memory 116 114: two::: is the most stupid to be saved to write to the data transfer controller. And before the next write command is issued, if t r is to be displayed or used by other programs, the system can extract the correct final pixel data from the asset/buyer control unit 114. (4) Diagrams 2, 3A_B and 8A-B FIG. 5 is a flow chart showing the method step (4) of storing the pixel data in the graphics age device. The bean display device (10) may include a first memory 116 and a second memory m: data transfer control coupled to the first and second memory devices 116 and 118. The method steps described herein may be transferred by data. The controller 114 executes the pixel of the field. In the initial step 501_, the data transfer controller 114 picks the direction in which the data is written - initially selected. As previously mentioned, the selected data is written = direction Γ defined by parameters (MV, MX, MY). In step 502, the billet transfer controller 114 can synchronize with the bus line clock signal bus-clk, and in step 504 of the pair of pixels of the 2011-12809 capture flash screen image, the data transfer controller 1 First pixel data. The next pulse synchronization of the BUS_CLK is connected to the bus signal pixel data of the bus, wherein the second pixel corresponding to the first pixel and the second pixel may be the same line on the image frame. Or as prime. The first and second pixel transfer controllers 114 can then be the same as =. In step 5〇6, the information is synchronized, and the first pixel data is written into the second signal 118 by writing the first signal CLKJL and CLK_R data. In the next + ° memory 116 and the second pixel 114 can then decide whether to process the next 508, the data transfer control face has an even number of total pixels, a solid pixel. If not, the image is 2 when it needs to process the next pixel. The controller U4 sends the data to the final pixel in step 51(). When the next pixel is the image being processed, the final pixel can be reproduced in the same manner as previously described, steps 502-506, adjacent pixels. Each pair of images is executed in the direction of the person selected by the next pair of writers. The adjacent pixels can be reversed in the same manner, if the pixel system has to be followed by a total number of odd-numbered pixels. For the final pixel, it is currently processed, and the final image of the image is captured. In this case, the corner controller 214 pixel data. In step 512, the final pixel data of the second and second, and the pixel data drop controller 214 corresponding to the lock, the attack, and the winter pixel may temporarily store 5 2 T - the command period is triggered and its corresponding Library address: The following / memory. For example, when the final pixel data can be later released to the final pixel data of the controller 214 to access the final pixel data, the lock can be output, or written to the first record 201142809 Respond to the occurrence of the next write command. Figure 6 is a schematic illustration of the description row to release the flash lock to the corner controller 214. In step 602, the corner of the step flow controller of the most suffix #,·, pixel beakers is controlled at the data transfer controller 114 to detect whether the next command has been requested to be sent by the body transfer control. The next command may be: or 3 command writes of one of the final pixel data bodies 116 and 118. The first and second memories are stored in the first and second memory 116|118, for example, to be read out. The pixel data displayed on the t-plane of the display panel must be stored in the material. For example, if (10) is reasonable, it may be possible to access the final information like Xin, and fear that your Lord will owe you to the next command and demand. If it is triggered by the shirt controller, in step 606, the corner of the 7th, if the current command cycle is - is written to the first and = 3 prime data, = the image of the image stored therein is supplemented by In step 608, the access to the desired pixel data that is written to the first and the first can be output. _ and the first reading body U6 and 118 are locked in = two primes; = take the required and final pixel data is still (4) to replace the final pixel data stored in Ϊ = 214, the image of the storage location = cause: memory Μ And 118... 〕 Pixel Bellow. Therefore, it can be ensured that according to the foregoing embodiment, the pixel data of the image surface can be positively phased due to the error of ^^^ and 14 201142809. Therefore, the overall _ access speed can be described as follows; two:: Γ and 8A-B diagram, the seventh diagram is - flow chart, the method steps performed by the control, which is used to read your music and the first five The memory transfer controller 114 can respond to the command. The access is stored in the first and second memory 116 Λ m曰 2:: the material is processed, and the flow of steps shown here is performed. In the initial step 702, the face=loader=114 can read the first image of the facet by the first memory 116; =step 70”, data transfer control=cafe;; The 704 series can be interchanged, or at the same time: the hidden bodies 116 and 118, step out of the second ... can decide whether to read the program, can end the procedure. The shirt image is the step of having an even number of total images to send money. In addition, the final pixel of the data is::: The two material transfer controller 114 can determine a. Otherwise, in step 708, if the pixel data is not the most ^^", it is the final pixel data. Bin ~ pixel beaker, steps 702-700 can be used first π6' ΐ Μ 面 接下来 next to the adjacent pixels. Otherwise, you can decide 15 201142809 = two have: one number:,. Therefore, in step -, the data transfer controller 2丨4's shape/middle '7: no final pixel data is in the corner material, to take the _ exist the fourth pixel can be the final handle pixel data. The second problem 116, 18 of which is the image of the most grave image (4) 11 214 (4) locks the final pixel data, and the generation of the corner controller 214 is released to the first and the first: ^. Then in step 714, the data transfer controller 114 can customize the data. - Among the memories 116 and 118 - at least one of the advantages of reading the correct final pixel system and method is that it can simultaneously access the memory and close the pair of pixels. data. In addition, the systems and methods described herein can successfully handle special situations, such as when not in pairs, such as the corner pixels of the image shown in the first and second figures. 'The access rate can be effectively increased by at least twice. Second, after that, without departing from the spirit and scope of the present invention, as in the following claims, the scope of the invention is as follows: (4) should be able to (4) to make the concepts and realities disclosed in the present invention for design Or improve other architectures and use them to achieve the same purpose as this one. Further, the structure and function of the elements separated by the ± implementation of the touch can be integrated into a single combined structure or element. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a graphic display device according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing an embodiment of a display device according to an embodiment. Data transfer controller; not " Figure 3 is a schematic diagram showing how it is contained in accordance with the present invention - the inclusion of the direction in the display device shown in Figure 1 is in accordance with the present invention. Another embodiment describes that different data is written in FIG. 4 as a time diagram of a clock signal, which describes pixel data as and in pairs, the first and second memories shown in FIG. 3; A flowchart of the method steps performed by the data transfer controller to write human pixel data is described in accordance with an embodiment of the present invention; FIG. 6 is a schematic illustration of a flash lock in accordance with an embodiment of the present invention. The process of transferring data to the final pixel data in the controller; 辕,, flow chart, according to the present invention - the method of performing the data processing by the data converter to read out the pixel data of the facet ^ 8 A The figure is a schematic illustration of the basin Description ♦ If you want to enter the book, you will have an example of a corner pixel. The number of pixels to be written by ^田田田 is like a f 8B image is a summary icon. Its description should be written in active An example of a corner pixel will be available when the number of pixels in the window is odd. [Main component symbol description] 100. Graphic display device J〇2: main processor 17 201142809 104: display controller 106: display driver m·display panel 112. main interface 114: data transfer controller 116: A memory 118: second memory 206: upper memory controller 208B: second first in first out buffer
第二 位址控制器 微指令集電腦控制器 角落控制器 選取像素資料的寫入方向 接收並閃鎖第一像素資料 接收第一像素資料 分別將第一及第二 是否有下—像素資^寫人第—及第二記1 最終像素資料 將最終資料問鎖在資料轉送控制器 偵測到存取最终：持閃鎖在資料轉送控制器t 當偵洌到下—二象素資料的下一命令或需求 記憶體其中之一 Ύ令時，將最終像素資料寫入第 210 212 214 501 502 504 506 508 510 512 602 604The second address controller micro-instruction set computer controller corner controller selects the pixel data in the writing direction to receive and flash locks the first pixel data to receive the first pixel data respectively, whether the first and second respectively have the next pixel-writing The first and second records of the final pixel data will lock the final data in the data transfer controller to detect the access end: holding the flash lock in the data transfer controller t when detecting the next - two pixel data The final pixel data is written to the 210 212 214 501 502 504 506 508 510 512 602 604 when one of the commands or the required memory is ordered.
J8 201142809 608 :當像素資料的存取被要求時，輸出被寫入第一及第 二記憶體的像素資料 702 :將第一像素所對應之第一像素資料自第一記憶體中 讀出 704 :將第二像素所對應之第二像素資料自第二記憶體中 讀出，其中第二像素與第一像素相鄰 706 :是否讀取下一像素資料 708 :是否為最終像素資料 710 :是否最終像素資料已被閂鎖 712:自資料轉送控制器獲得最終像素 714:自第一及第二記憶體獲得最終像素J8 201142809 608: when the access of the pixel data is requested, outputting the pixel data 702 written into the first and second memory: reading the first pixel data corresponding to the first pixel from the first memory 704 : reading the second pixel data corresponding to the second pixel from the second memory, wherein the second pixel is adjacent to the first pixel 706 : whether to read the next pixel data 708 : whether it is the final pixel data 710 : whether The final pixel data has been latched 712: the final pixel 714 is obtained from the data transfer controller: the final pixel is obtained from the first and second memory
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