TW201140780A - Packaging substrate structures and fabrication methods thereof - Google Patents

Abstract

Packaging substrate structures and fabrication methods for the packaging substrate structures are presented. A packaging substrate structure includes a substrate with a circuit layout. A stacked metallization structure is disposed on the substrate, wherein the stacked metallization structure includes pluralities of solder plating pads. A first insulation layer is applied on the stacked metallization structure and approximately at the same height with the solder plating pads. An interfacial layer is disposed on the solder plating regions. A plurality of first solder balls are mounted on the solder plating regions and covered with a capping layer. A second insulation layer disposed neighboring of the first solder balls includes a raising part of the second insulation layer along the curved sidewalls of the first solder balls, wherein the height of the raising part is lower than the height of the first solder balls.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate structure, and more particularly to a package substrate structure having a uniform and uniform solder ball to be printed surface and a method of fabricating the same. [Prior Art] The development trend of electronic products has gradually evolved into the fields of light, thin, short, small, high speed, high frequency and multifunctional. In order to meet the needs of practical applications, semiconductor packaging technology has gradually evolved from ball grid array (BGA) package and flip chip carrier (1) iP chip (FC) to three-dimensional (3D).

Stack = structure. Or, in the board surface package, the fc technology or the wire bond (4) R bond, referred to as WB) technology, will be a variety of package groups, functional structures. The formation of a crucible is more than that of the prior art, and the implant of the tin stock is coated on the substrate structure by soldering the solder layer (for example, green paint), and then proceeding to the step = the solder paste step is to be treated. On the surface of the printed substrate =, :r: in the open loop of the case, the step of the solder paste 6 is removed from the steel plate and the solder paste on the back is condensed into a spherical body. When the semi-conducting... solder ball (or copper column _, after the completion of the step, the junction = corresponding to the advanced semiconductor wafer fabrication technology / w construction of high-density I / O contact, making the cloth: Ding Zhong' The design has been dissolved and the structure of the horror line is _ intensive. Therefore, the seal brother

9024-A518S8-TW 201140780 For the substrate, the number of soldered conductive structures (bumps) on the side in contact with the wafer also needs to be greatly increased, resulting in a closer spacing between the conductive bumps. However, due to the limited spacing of the open loop of the steel sheet and the unevenness of the green paint coating on the substrate, the amount of tin in the solder paste step is unstable. If the amount of tin is too large, the phenomenon of tin bridge is likely to occur; if the amount of tin is too small, the volume of the solder ball is too small, and the coplanarity of the conductive bump is insufficient, so that the wafer cannot be electrically connected smoothly. SUMMARY OF THE INVENTION Embodiments of the present invention provide a package substrate structure including a substrate having a line layout, and a build-up line structure disposed on the substrate 5 wherein the build-up line structure has a plurality of ball-forming pads; An insulating layer is coated on the build-up line structure, and is substantially equal to the ball-forming pads; an interface layer is disposed on the ball-laying pads; and a plurality of first solder balls are disposed on the interface layer of the ball-pads The first solder balls are covered with a coating layer; and a second insulating layer is disposed around the first solder balls, and has a raised portion along the side curved surface of the first solder balls. Raising; wherein the raised portion of the second insulating layer is lower than the height of the first solder balls. An embodiment of the present invention further provides a package substrate structure including a substrate having a line layout, and a build-up line structure disposed on the substrate, wherein the build-up line structure has a plurality of ball-forming pads; a first insulating layer Applying on the build-up line structure, substantially equal to the ball-forming pads; an interface layer is disposed on the ball-laying pads; and a plurality of first solder balls are disposed on the interface layer of the ball-pads, The first solder balls are covered with a slope coating; a second insulating layer is disposed around the first solder balls, and has a rising portion along the

9024-A51888-TW 201140780 The side surface of the first solder ball is raised; a plurality of second solder balls are disposed on the top arc surface of the first solder balls; and a semiconductor wafer is oppositely disposed on the substrate, The semiconductor wafer has a plurality of columnar conductive contacts corresponding to and deep into the second solder balls, wherein a filling glue is filled between the semiconductor wafer and the substrate, and wherein the raised portion of the second insulating layer is lower than the Some of the first tin balls. The embodiment of the present invention further provides a method for fabricating a package substrate structure, comprising: providing a substrate having a line layout; forming a build-up line structure on the substrate, wherein the build-up line structure has a plurality of ball-forming pads; Optionally coating a first insulating layer on the build-up wiring structure, substantially equal to the ball-forming pads; patterning the first insulating layer to expose surfaces of the ball-forming pads; depositing an interface layer thereon Implanting a plurality of first solder balls on the interface layer of the ball implants, covering the first solder balls with a slope coating; and coating a second insulating layer on the first A tin ball is surrounded by a rising portion along a side arc surface of the first solder balls, wherein a raised portion of the second insulating layer is lower than a height of the first solder balls. The present invention will be described in detail below with reference to the accompanying drawings, in which: FIG. Reference basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. Furthermore, the parts of the various elements of the drawing 9024-A51888-TW 6 201140780 2 will be described separately, it is worth noting that the elements not shown or described in Fig. 2 are common knowledge in the art. The form of the invention is not to be construed as limiting the invention. In view of the above, embodiments of the present invention provide an area between the lines on the over-plate, filled with a solder resist material, or a printed surface, followed by a subsequent solder paste printing and review step. Because of the formation of the bump above the pad, the thickness and the uniformity of the south can be controlled only by the open ring on the steel plate. Furthermore, the coating-layer can be adjusted; the wide, ", · 彖 layer" controls the exposed area of the bump. By combining the coating insulation = can be formed - a new bump structure to achieve a uniform convex The block size and height, 'and, the spacing between the bump structures is controlled to be below 15Q_. The configuration of the sealing plate according to an embodiment of the present invention is shown in section (4) of the fourth stage. : Substrate for a single-layer board (4). Substrate (10) = two = suitable composite material. Substrate _ already used U-line structure, such as metal wiring, conductivity inspection, conduction ==^ughh handsome, then forming the structure of the structure (10) 〇b on the silk plate, the lower surface, wherein the ball pad 122. The library 睁 θ u H, the structure has a plurality of two == connection. In the following embodiments, only focus on the upper shoulder layer Description of the bump structure of the line structure 12GaJi. The image of the second insulating layer 13 is coated on the build-up line.

9024-A51888-TW 7 201140780 The structure is substantially equal to the ball-pads 122 and then subjected to an open-loop process such as plasma removal, laser drilling or exposure development to expose the ball pads 122. In one embodiment, the first insulating layer 13 can be selectively coated with a general solder resist layer (green paint), but the thickness of the coating is low. In other embodiments, the first insulating layer may be selected from other dielectric materials, such as epoxy resin (four), resin, bismaleimide triazine 'BT, polybendamine. (polyimide), ABF membrane (ajinom〇t〇build-up film), polyphenylene oxide (PPE), polypropylene (PP), polytetrafluoroethylene (PTFE), or methyl Polymethyl methacrylate (PMMA). The step of forming the first insulating layer 130 includes uniformly coating a first insulating layer on the build-up wiring structure such that the ball pad and the first insulating layer have substantially equal surfaces. Then, the first insulating layer is subjected to an opening step such as plasma cleaning, laser drilling or exposure development to expose the surface of the ball pad. For example, applying a solder resist layer (green paint), performing image transfer (or laser drilling, plasma cleaning) to complete the open loop on the ball pad, covering the solder resist layer only above the line, and then selectively Subsequent surface treatment steps are performed. Next, referring to Fig. 3, an interface layer 135 is formed on the ball bumps 122. The interfacial layer 135 can include a metal protective layer or an underlying catalytic metal layer, such as a chemical nickel boat gold. In one embodiment, the interface layer 13 5 may comprise: nickel, gold, tin, erbium, silver, chromium, tungsten, ge, shi, alloys, or any combination thereof. Referring to Figure 4, a plurality of first solder balls 140 are implanted on the interface layer 135 of the ball pads. For example, the first tin ball can be directly placed on the ball

9024-A51888-TW 201140780

On the mat, or by printing the paste on the ball to be printed by the steel plate printing process, after the reflow process, the desired joint solder ball structure is formed on the previous insulating layer 13G (four) step. The first insulating layer 130 of the surrounding area of the ball 塾/', is substantially the same as the degree:: surface, so when the steel plate is printed, the amount of the lower solder can be not received by the substrate. Both - to avoid the defects of the tin bridge phenomenon and the lack of surface properties of the conductive bumps. Next, the 'coating layer' can be selectively formed on the formed first tin ball as shown in Fig. 5. The cladding layer can be a layer: upper = protective layer 142, 144, wherein the first layer is an underlying catalytic metal layer. It should be understood that the material f of the metal protective layers 142, 144 may include: any combination of the above materials, such as recording, gold, tin, erroneous, inscription, silver, collateral, crane, liberty, lithograph, and alloys thereof. Figure 6, a coating - a second insulating layer 15Q (e.g., solder resist is insulated from the base structure). It should be noted that the second insulating layer 15 and the first insulating layer 13 on the surrounding region The affinity is better than the affinity of the second insulating layer/the cladding layer 144 on the first solder balls 140. Therefore, the thickness of the == layer 150 on the surrounding area is significantly greater than the coverage: - the thickness of the solder ball 14 。. Next, image transfer, plasma two or laser drilling to complete the open ring on the first solder ball (or called the second green paint 幵Γ ' 'make the second after the ring The insulating members 50 have a rising portion 153 and a side arc surface of the solder ball, and the second insulating layer 150 after the opening is opened to expose the top arc of the first solder balls. The surface area, such as the second insulating layer 15 of the open-loop after the opening of the ring, is lower than the height of the solder balls. Please refer to Figure 8, and then, a semiconductor wafer. 21〇 opposite direction

9024-A51888-TW 9 201140780 In the structure of the substrate, pressure and temperature are applied to combine the two. The semiconductor wafer 210 has a plurality of columnar conductive contacts 230 corresponding to and deep into the first solder balls 140, wherein a filling glue 220 is filled between the semiconductor wafer and the substrate. 9-10 are schematic cross-sectional views showing a method of fabricating a package substrate structure in accordance with another embodiment of the present invention. Referring to FIG. 9, using the package substrate structure shown in FIG. 7 , a plurality of top surface regions of the first solder balls 140 exposed by the opened second insulating layer 150 ′ are formed. Second tin ball 145. The second solder balls 145 can be formed by direct insertion to enhance the effect of the wafer package by adding a second ball implantation step. Next, referring to Fig. 10, a semiconductor wafer 210 is placed opposite to the substrate structure, and pressure and temperature are applied to combine the two. The semiconductor wafer 210 has a plurality of columnar conductive contacts 230 corresponding to and deep into the second solder balls 145 » wherein a filling glue 220 is filled between the semiconductor wafer and the substrate. According to the disclosed embodiment of the present invention, the main advantage is that a uniform and contoured surface to be printed can be provided after the prior coating step of the first insulating layer 130. The size of the ball pad can be precisely controlled by the patterning etching step. Since the size of the ball pad directly affects the pitch and size of the bump, precise control of the ball pad can improve the accuracy of the volume of the solder ball for printing or balling, and achieve the goal of fine pitch (below 150μηη, or Between ΙΟΟμπι and 140μπι). Compared to the prior art, the first solder ball Η0 on the package substrate structure of the present invention has a higher quality coplanarity with the conductive contact at the wafer end. Furthermore, by providing a second solder ball 145 on the top curved surface of the exposed first solder ball 140, sufficient soldering 9024-A51888-TW 10 201140780 can be provided to meet the future high height/spacing of the solder ball. demand. There is a concave arc shape, and the structure of the rotation 153 of the arc 1 is attached, so that the spring can be used to follow the first solder ball and the fine bonding force of the ball. Obtaining a better letter reveals as above, but it does not necessarily deviate from the essence of the invention; ^ collar t has the usual knowledge, in the decoration, and therefore the protection of the invention, Tian can make a little change and run Prevail. ...祀围# Attached to the _

[S1

9024-A51888-TW 201140780 BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-8 are schematic cross-sectional views showing a method of fabricating a package substrate structure according to an embodiment of the present invention at each process step. 9-10 are schematic cross-sectional views showing a method of fabricating a package substrate structure in accordance with another embodiment of the present invention. [Main component symbol description] 110~substrate; 120a, 120b~ build-up line structure; 122~ ball pad; 130~first insulating layer; 135~ interface layer; 140~first solder ball; 142, 144~ metal protection 145~second solder ball; 150~second insulating layer; 150'~second insulating layer after opening; 153~lifting part; 210~semiconductor wafer; 220~filling; 230~column conductive contact . 9024-A51888-TW 12

Claims (1)

201140780 ' VII. Patent application scope: 1. A package substrate structure comprising: a substrate having a circuit layout on the substrate; a build-up line structure disposed on the wire plate, wherein the build-up line structure has a plurality of implants a ball pad; a first insulating layer is coated on the layered circuit structure and is equal to the ball pad; an interface layer is disposed on the ball pad; • a plurality of first solder balls are disposed on the ball pad On the interface layer of the ball pad, the first solder balls are covered with a coating layer; and a second insulating layer is disposed around the first solder balls, and has a rising portion along the first The side arc surface of the solder ball rises; wherein the raised portion of the second insulating layer is lower than the height of the first solder balls. 2. The package substrate structure of claim 1, further comprising a semiconductor wafer disposed opposite to the substrate, the semiconductor wafer having a plurality of columnar conductive contacts corresponding to and deep into the first solder balls, A filler is filled between the semiconductor wafer and the substrate. [S1. 3. The package substrate structure of claim 1, wherein the rim layer is a dielectric material, including an epoxy resin, a double malayan gum %c- Bisnielide triazine (BT), polyimide, ajinomoto build-up film, polyphenylene oxide (PPE), polypropylene (PP), poly Polytetrafluorethylene (PTFE), or Polymethyl methacrylate (PMMA). 4. The package substrate structure of claim 1, wherein the interface layer is a metal protective layer comprising: nickel, gold, tin, lead, aluminum, silver, lanthanum, tungsten 5. The package substrate structure of claim 1, wherein the cladding layer comprises a first metal protection layer and a second metal protection layer. Floor. 6. The package substrate structure of claim 1, wherein the second insulating layer is a solder resist layer comprising epoxy resin, bismaleimide-triazabenzene resin (bismaleimide triazine, BT), polyimide, ajinomoto build-up film, polyphenylene oxide (PPE), polypropylene (PP), polytetrafluoroethylene (polytetrafluoroethylene) Polytetrafluorethylene ' PTFE), or Polymethyl methacrylate (PMMA). The package substrate structure of claim 1, wherein the second insulating layer has an affinity with the first insulating layer that is superior to the second insulating layer and the first solder ball The affinity of the coating. 8. The package substrate structure of claim 1, wherein the second insulating layer exposes a top arcuate region of the first solder balls. 9. The package substrate structure of claim 1, further comprising: a plurality of second solder balls disposed on a top arcuate region of the first solder balls; and a semiconductor wafer oppositely disposed on the substrate The semiconductor wafer has a plurality of columnar conductive contacts corresponding to and deep into the second solder balls, wherein the 9024-A51888-TW 14 201140780 semiconductor wafer is filled with a filling glue between the semiconductor wafer and the substrate. A method for manufacturing a package substrate structure, comprising: providing a substrate having a line layout; and forming on the substrate, wherein the build-up line junction forms a build-up line structure having a plurality of ball-forming pads; Ground coating—the first insulating layer is on the build-up line structure and is equal to the ball-forming mats; Patterning the first insulating layer to expose the surface of the ball pad; depositing an interface layer on the ball pad; and forming a first plurality of first solder balls on the interface layer of the ball pad Some of the tin balls are covered with a coating layer; and the outer two cloth edges are surrounded by the first-tin balls, and the side arc surface of the --second two-seat ball is raised, wherein the second insulating layer The phase portion is lower than the height of the first-tin balls. The ball is made of a finely-cut structure: H two-contact contact corresponds to and penetrates the first-tin" η 曰曰 与 与 与 与 与 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬 谬The step of fabricating the package substrate structure described in the second package includes the first solder ball on the interface layer of the ball ball mats on the interface layer of the ball ball mats, and the application of the turn-to-turn (four) material formation _. The step of fabricating the package substrate structure as described in the item / __iG includes coating the surrounding of the first - the ball - around the 9024-A5] 888-TW On the substrate, and applying image [car |] 5 201140780 shift, plasma cleaning or laser drilling to expose the top curved area of the first solder balls. 14. As claimed in item 13 The manufacturing method of the package substrate structure is characterized in that the affinity between the insulating layer and the first insulating layer is superior to the affinity of the second insulating layer and the coating layer on the first solder balls. The method for manufacturing a package substrate structure according to claim 13 , further comprising: forming a plurality of second solder balls a top surface of the first solder ball; and a semiconductor wafer bonded to the substrate, the semiconductor wafer having a plurality of columnar conductive contacts corresponding to and deep into the second solder balls, wherein the semiconductor wafer and the semiconductor wafer A method of manufacturing a package substrate structure according to claim 10, wherein the first insulating layer is a dielectric material, including an epoxy resin and a double horse. Bismaleimide triazine 'BT, polyimide, ajinomoto build-up film, polyphenylene oxide (PPE), polypropylene (polypropylene) 'PP), polytetrafluorethylene (PTFE)' or polymethyl methacrylate (PMMA). The method for manufacturing a package substrate structure according to claim 10, wherein The second insulating layer is a solder resist insulating layer, including epoxy resin, bismaleimide triazine (BT), polyimide (polyimide). ), ABF film (ajinomoto build-up film), polyphenylene oxide (PPE), polyacrylonitrile 9024-A51S88-TW 16 201140780 (polypropylene, PP),? Polytetrafluorethylene PTFE or Polymethyl methacrylate (PMMA). 9024-A51888-TW 17