201139235 、發明說明： 【發明所屬之技術領域】 本發明是有關於一種承載裝置，特別是指—種晶片承 載裝置。 s 【先前技術】 參閱圖1、2，現有晶片承載裝置包括一基座I〗、多數 間隔設置於該基座11之上表面U1上的第一擋壁丨2、多數 對應所述第一擋壁12而間隔設置於該基座u <下表面112201139235, DISCLOSURE OF THE INVENTION: TECHNICAL FIELD The present invention relates to a carrier device, and more particularly to a wafer carrier device. [Previous Technology] Referring to Figures 1 and 2, the conventional wafer carrier device includes a pedestal I, and a plurality of first barrier rafts 2 disposed on the upper surface U1 of the susceptor 11 and corresponding to the first barrier The wall 12 is spaced apart from the base u <lower surface 112
上的第二擋壁13,及一形成於該上表面lu的凹槽μ，其 中，所述第-擋壁12環繞界定出—用以似—球格陣列封 裝兀件（Ban Gdd Array，BAG) 1〇〇的容置空間15。該球 格陣列封裝元件100具有-本體1(H，及多數凸設於該本體 底面的接腳102。 參閱圖2、3,使用時，是將該球格陣列封裝元件_ :於：晶片承載裝置的容置空間15中，同時令該球格陣列 封裝7L件100的所述接腳102是容 疋令罝7、孩凹槽14内，以避 免所述接腳102與該上表面U1發 發生碰心而損壞。最後再以a second barrier wall 13 and a recess μ formed on the upper surface lu, wherein the first barrier 12 is circumferentially defined to be used as a ball grid package (Ban Gdd Array, BAG) ) 1 〇〇 of the accommodation space 15. The ball grid array package component 100 has a body 1 (H, and a plurality of pins 102 protruding from the bottom surface of the body. Referring to Figures 2 and 3, in use, the ball grid array package component is: In the accommodating space 15 of the device, at the same time, the pin 102 of the ball grid array package 7L member 100 is inside the accommodating case 7 and the child groove 14 to prevent the pin 102 and the upper surface U1 from being sent. It’s broken and it’s broken. Finally,
另一晶片承載裝置疊至於蜚淤古兮ι+. μ A 、戰敌有该球格陣列封裝元件100 的阳片承載裝置上，利用該二晶 曰片承載裝置相配合的第一 、二擋壁12 ' 13，以如圖3所 ^ . 所不之方式，將該球格陣列封 屐兀件1〇〇限制於該容置空間15中。 但疋，由於考量該二晶 Μ ^ 乃承載裝置相互疊合時的方便 性，所述第一、二擋壁12、13 _ 之間白形成有間距D，以利 所迷第-、二擋壁12、13的相互配合。 201139235 然而，所述第一、二擋壁1 > 土 、13有可能因外力而以所 述間距D發生位移，進而帶動 ▼動該球格陣列封裝元件100的 本體101移動至圖3中假相錄〜一， 心線所不位置，而損壞了該球格 陣列封裝元件H)0的本體1〇1或所述接腳iq2。 如何使所述第一、二擋壁 12 '13的相互配合更為簡單 ’又可以避免該球格陣列封梦开彼丨Λ Λ 干〜钌衮7L件100的損壞，成了相關 業者所欲改善的目標。 【發明内容】 因此，本發明之目的，g卩^^ |在徒供一種使用方便且穩定 度向的晶片承載裝置。 於是’本發明之晶片承遨奘 々枣戰裝置，包含一基座、一設置 於該基座上的限位單元，乃一 及也成於该限位單元上的結合 SH - 早7L。 該基座包括相反的一上表面盘 衣曲興下表面，及一環繞該 下表面周緣的環繞面；該限付置；—k β ^ β 茨1民位皁疋包括多數間隔設置 上 於該上表面上的撐壁，及客叙來 土及夕數對應每一擋壁而設置於該下 表面上的卡合壁，纟中’每一擋壁皆具有一與該上表面相 間隔的頂面、-連接該頂面與該上表面且面向該環繞面的 外壁面、一與該外壁面相間隔且自該頂面向下延伸的導引 面，及-自該導引面向下延伸並連接於該上表面的抵靠面 ，每-卡合壁皆具有一與該下表面相間隔的底面、一連接 該底面與該下表面且面向該環繞面的外周φ、—與該外周 面相間隔且自該底面朝該下表面方向延伸的第—導斜面， 及-自該第-導斜面朝該下表面方向延伸並連接於該下表 201139235 面上的第二導斜面。 該結合單元包括多數形成於每一擋壁上的第一楔面， 及多數對應所述第一楔面而形成於每一卡合壁上的第二楔 面’其中’每—第—楔面的周緣是分別與該頂面、外壁: 、上表面、導引面、抵靠面相連接，而每一第二楔面的周 緣是分別與該底面、外周面、下表面，及該第一、二導斜 面相連接。 y 本發明之功效在於利用形成於每一擋壁上的第一楔面The other wafer carrying device is stacked on the anode carrying device of the ball grid array package component 100, and the first and second gears are matched by the two wafer carrier device. The wall 12'13 is limited to the accommodating space 15 in a manner not shown in FIG. However, since the two crystals are considered to be convenient when the carrier devices are overlapped with each other, a space D is formed between the first and second barrier walls 12, 13 _ to facilitate the first and second gears. The mutual cooperation of the walls 12, 13. 201139235 However, the first and second barrier walls 1 > soil 13 may be displaced by the spacing D due to an external force, thereby driving the body 101 of the ball grid array package component 100 to move to the false phase in FIG. Recording ~1, the position of the heart line is not damaged, and the body 1〇1 or the pin iq2 of the ball grid array package component H)0 is damaged. How to make the mutual cooperation of the first and second retaining walls 12'13 easier? It is also possible to avoid the damage of the ball grid array and the damage of the 100L piece 100, which has become the desire of the relevant industry. The goal of improvement. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a wafer carrier that is easy to use and stable in orientation. Thus, the wafer carrier of the present invention comprises a base, a limiting unit disposed on the base, and a combination of SH and 7L which is also formed on the limiting unit. The base includes an opposite upper surface of the lower surface of the disk, and a surrounding surface surrounding the periphery of the lower surface; the limit payment; - k β ^ β 1 saponin comprises a plurality of spacers disposed thereon a supporting wall on the surface, and a locking wall disposed on the lower surface corresponding to each of the retaining walls, and each of the retaining walls has a top surface spaced apart from the upper surface Connecting an outer wall surface of the top surface and the upper surface facing the surrounding surface, a guiding surface spaced apart from the outer wall surface and extending downward from the top surface, and extending from the guiding surface and connected thereto An abutting surface of the upper surface, each of the engaging walls has a bottom surface spaced apart from the lower surface, a peripheral surface φ connecting the bottom surface and the lower surface facing the surrounding surface, spaced apart from the outer peripheral surface a first guide inclined surface extending from the bottom surface toward the lower surface, and a second lead inclined surface extending from the first guide inclined surface toward the lower surface and connected to the surface of the lower table 201139235. The bonding unit includes a plurality of first wedge faces formed on each of the barrier walls, and a plurality of second wedge faces formed on each of the engaging walls corresponding to the first wedge faces, wherein each of the first to the first wedge faces The peripheral edge is respectively connected to the top surface, the outer wall: the upper surface, the guiding surface, and the abutting surface, and the circumference of each of the second wedge surfaces is respectively associated with the bottom surface, the outer circumferential surface, the lower surface, and the first The two guide bevels are connected. y The effect of the invention is to utilize the first wedge surface formed on each of the barrier walls
，與相配合地形成於每一卡合壁上的第二楔面，以產生導 引作用使u承載裝置在相互疊合時更為迅速更可以 以所述第…二楔面有效分散外力，使相互疊合的晶片承 載裝置不會產生轉動或錯動’進而提高所承載之物件的穩 定度。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之六個較佳實施例的詳細說明中，將可 清楚的呈現。 在本發明被詳細描述之前，要注意的是，在以下的說 明内容中，類似的元件是以相同的編號來表示。 參閱圖4、5，本發明的晶片承載裝置2之第一較佳實 施例包含H 21、—設置於該基座21上的限位單元二 ，及一形成於該限位單元22上的結合單元25。 該基座21包括相反的一上表面211與一下表面212, 及一環繞該上、下表面211、212周緣的環繞面213。該限 201139235 =單7L 22包括二間隔設置於該上表面211上且概呈L形的 擋壁23，及二對應每一擋壁23而設置於該下表面us上且 亦概呈L形的卡合壁24。 參閱圖4、6，每一檔壁23皆具有一與該上表面2ιι相 間隔的頂面231、一連接該頂面231與該上表面211且面向 該環繞面213的外壁面232、一與該外壁面232相間隔且自 該頂面231傾斜向下延伸的導引面233,及一自該導引面 233傾斜向下延伸並連接於該上表面211的抵靠面。 每一擋壁23之導引面233與該上表面211間皆形成有 一夾角0 1，而每一擋壁23之抵靠面234與該上表面2ιι間 皆形成有一夾角02,其中，夾角01小於夹角02。 參閱圖5、6，每一卡合壁24皆具有一與該下表面212 相間隔的底面241、一連接該底面241與該下表面212且面 向該環繞面213的外周面242、一與該外周面242相間隔且 自該底面241朝該下表面212方向傾斜延伸的第一導斜面 2斗3，及一自该第一導斜面243朝該下表面212方向傾斜延 伸並連接於該下表面212上的第二導斜面244。 每一卡合壁24之第一導斜面243與該下表面212間皆 形成有一夾角01’而每一卡合壁24之第二導斜面244與 该下表面212間皆形成有一夾角0 2，其中，夾角0 j小於 夾角0 2。 在此要特別說明的是，每一擋壁23的導引面233與抵 靠面234也可以是垂直該上表面211;而每一卡合壁24之 第一、一導斜面243、244也是可以垂直該下表面212，依 201139235 . 然可以達成相同的效果。 參閱圖4、5’該結合單元25包括多數形成於每一撞壁 23上的第~模面251 ’及多數難所述第-楔面251而形 成於每一卡合壁24上的第二楔面252,其中，每一第一楔 面251的周緣是分別與該頂面231、外壁面232、上表面 211、導引面233、抵靠面234相連接，而每一第二楔面252 的周緣是分別與該底面241、外周面242、下表面212，及 該第一、二導斜φ 243、244相連接。於本較佳實施例中， φ 母擋壁23與每一結合壁24上’分別形成有兩個第-模 面251與兩個第二楔面252。 參閱圖7、8，實際應用時，是將一晶片3置於位於圖 7下方之晶片承載裝置2中，其中，該晶片3包括一本體 31 ’及多數凸設於該本體31底緣的接腳32。 當置放該晶片3時，每一擋壁23的導引面233可以導 引該晶片3的本體31，使該晶片3的本體31周緣能靠抵於 每一擋壁23之抵靠面234上，並令所述接腳32與該上表 φ 面2Η相間隔，避免所述接腳32與該上表面211相互碰撞 而發生損壞；之後再以位於圖8上方之晶片承載裝置2的 每一卡合壁24上的第二楔面252,與位於圖8下方之晶片 承載裝置2的每一擋壁23的上的第一楔面251相互配合， 使該二晶片承載裝置2相互疊置。 所述第一、二楔面25 1、252不但能於該二晶片承載裝 置2相互疊置時產生導引作用’使所述晶片承載裝置2的 結合更為迅速fel便’在該二晶片承載裝置2相互疊置後， [S1 7 201139235 所速第-、二楔面251、252更能用以分散外力，避免外力 造成邊m載裝置2產生相對位移或旋轉，確保所承 置之晶片3的完整性與良率’提高整體承置的穩定度。 再者’利用所述第…二模面251、252的延伸式設計 亦可以限能晶片3在該限位單元22中的旋㈣度，確保 所承置之晶片3置放位置不會過度偏移。 參閱圖9，本發明的晶片承載裝置2之第二較佳實施例 ’大致是與該第—較佳實施例相同，不相同的地方在於： 該基座21更包括—形成於該上表面2U的容置空間214, 而所述擋壁23是位於該容置空間214的周緣。 由於本較佳實施例的結構大致是與該第一較佳實施例 相同，因此’除了可以達成該第一較佳實施例的功效外， 更可以利用該容置空間214以容置該晶片3的所述接腳Μ ，並免所述接腳32與該上表面211發生碰撞而損壞。 參閱圖10、11，本發明的晶片承載裝置2之第三較佳 貫施例大致疋與該第一較佳實施例相同，不相同的地方 在於：該限位單元22包括四個間隔設置於該上表面211上 且概呈梯形的擋壁23，及四對應每一擋壁23而設置於該下 表面212上且亦概呈梯形的卡合壁24。於本較佳實施例中 ，每一擋壁23上僅形成有一第一楔面251，而每一卡合壁 24上亦僅形成有一第二楔面252。 由於本較佳實施例的結構大致是與該第一較佳實施例 相同，因此，除了可以達成該第一較佳實施例的功效外， 而且由於每一擋壁23與每一卡合壁24是相互間隔的型態 201139235 種不同於該第一較佳實 有利於開模成型’也提供使用者一 施例的態樣供使用者選擇。 參閱圖12，本發明的晶片承載裝置2之第四較佳實施 例，大致是與該第三較佳實施例相同，不相同的地方在於 :該基座21更包括一形成於該上表面2ιι的容置空間⑴ ’而所述播壁2 3是位於兮交罢允pq。 疋诅於該奋置空間214的周緣。藉此提供 另一態樣供使用者選擇》a second wedging surface formed on each of the engaging walls to cooperate to cause the u-bearing device to more effectively disperse the external force with the second wedge surface when superimposing each other, The wafer carrier that overlaps each other does not cause rotation or misalignment, thereby improving the stability of the loaded article. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the accompanying drawings. Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIGS. 4 and 5, a first preferred embodiment of the wafer carrier device 2 of the present invention includes H 21, a limiting unit 2 disposed on the base 21, and a combination formed on the limiting unit 22. Unit 25. The base 21 includes an opposite upper surface 211 and a lower surface 212, and a surrounding surface 213 surrounding the circumference of the upper and lower surfaces 211, 212. The limit 201139235=single 7L 22 includes two barrier walls 23 which are disposed on the upper surface 211 and are substantially L-shaped, and two corresponding to each barrier wall 23 are disposed on the lower surface us and are also L-shaped. Engagement wall 24. Referring to FIGS. 4 and 6, each of the partition walls 23 has a top surface 231 spaced apart from the upper surface 2, and an outer wall surface 232 connecting the top surface 231 and the upper surface 211 facing the surrounding surface 213. The outer wall surface 232 is spaced apart and has a guiding surface 233 extending obliquely downward from the top surface 231, and an abutting surface extending obliquely downward from the guiding surface 233 and connected to the upper surface 211. An angle θ 1 is formed between the guiding surface 233 of each of the retaining walls 23 and the upper surface 211, and an abutting angle 02 is formed between the abutting surface 234 of each retaining wall 23 and the upper surface 2 ι, wherein the angle 01 Less than the angle 02. Referring to FIGS. 5 and 6, each of the engaging walls 24 has a bottom surface 241 spaced apart from the lower surface 212, and an outer peripheral surface 242 connecting the bottom surface 241 and the lower surface 212 facing the surrounding surface 213. The first guiding surface 2 is spaced apart from the bottom surface 241 and extends obliquely toward the lower surface 212, and a first inclined surface 2 extending from the first guiding surface 243 toward the lower surface 212 and connected to the lower surface A second guide ramp 244 on 212. An angle 01' is formed between the first guiding surface 243 of each of the engaging walls 24 and the lower surface 212, and an angle 0 2 is formed between the second guiding surface 244 of each of the engaging walls 24 and the lower surface 212. Wherein, the angle 0 j is smaller than the angle 0 2 . It should be particularly noted that the guiding surface 233 and the abutting surface 234 of each of the retaining walls 23 may also be perpendicular to the upper surface 211; and the first and a guiding surfaces 243 and 244 of each of the engaging walls 24 are also The lower surface 212 can be perpendicular to, according to 201139235. The same effect can be achieved. Referring to FIGS. 4 and 5 ′, the coupling unit 25 includes a plurality of first die faces 251 ′ formed on each of the collision walls 23 and a second plurality of the first wedge faces 251 formed on each of the engagement walls 24 . a wedge surface 252, wherein a circumference of each of the first wedge surfaces 251 is respectively connected to the top surface 231, the outer wall surface 232, the upper surface 211, the guiding surface 233, and the abutting surface 234, and each second wedge surface The periphery of 252 is connected to the bottom surface 241, the outer peripheral surface 242, the lower surface 212, and the first and second guide yokes 243, 244, respectively. In the preferred embodiment, the φ female wall 23 and each of the bonding walls 24 are formed with two first-die faces 251 and two second wedge faces 252, respectively. Referring to FIGS. 7 and 8, in actual application, a wafer 3 is placed in the wafer carrier 2 located at the bottom of FIG. 7, wherein the wafer 3 includes a body 31' and a plurality of connections protruding from the bottom edge of the body 31. Feet 32. When the wafer 3 is placed, the guiding surface 233 of each of the barrier walls 23 can guide the body 31 of the wafer 3 so that the periphery of the body 31 of the wafer 3 can abut against the abutting surface 234 of each of the barrier walls 23. And the pin 32 is spaced apart from the upper surface φ surface 2Η to prevent the pin 32 from colliding with the upper surface 211 to cause damage; and then the wafer carrier device 2 located above the top of FIG. A second wedge surface 252 on a card wall 24 cooperates with a first wedge surface 251 on each of the barrier walls 23 of the wafer carrier device 2 at the bottom of FIG. 8 to overlap the two wafer carrier devices 2 . The first and second wedge faces 25 1 , 252 can not only guide the two wafer carrier devices 2 when they are stacked on each other, but also make the bonding of the wafer carrier device 2 more rapid. After the devices 2 are stacked on each other, [S1 7 201139235 speed-first and second wedge faces 251, 252 can be used to disperse external forces, avoiding external forces causing relative displacement or rotation of the side-loading device 2, ensuring the wafer 3 being placed. The integrity and yield 'increased the stability of the overall placement. Furthermore, the extended design of the second surface 251, 252 can also limit the spin of the wafer 3 in the limiting unit 22, ensuring that the placed wafer 3 is not excessively placed. shift. Referring to FIG. 9, a second preferred embodiment of the wafer carrier device 2 of the present invention is substantially the same as the first preferred embodiment. The difference is that the pedestal 21 further includes a second surface formed on the upper surface 2U. The accommodating space 214 is located at the periphery of the accommodating space 214. Since the structure of the preferred embodiment is substantially the same as that of the first preferred embodiment, the accommodating space 214 can be utilized to accommodate the wafer 3 in addition to the effect of the first preferred embodiment. The pin is not damaged by the collision of the pin 32 with the upper surface 211. Referring to Figures 10 and 11, the third preferred embodiment of the wafer carrier device 2 of the present invention is substantially the same as the first preferred embodiment. The difference is that the limiting unit 22 includes four intervals. The upper surface 211 has a trapezoidal retaining wall 23, and four engaging walls 24 corresponding to each of the retaining walls 23 and disposed on the lower surface 212 and also having a substantially trapezoidal shape. In the preferred embodiment, only one first wedge surface 251 is formed on each of the retaining walls 23, and only one second wedge surface 252 is formed on each of the engaging walls 24. Since the structure of the preferred embodiment is substantially the same as that of the first preferred embodiment, in addition to the effect of the first preferred embodiment, and because each of the barrier walls 23 and each of the engaging walls 24 The patterns of the mutually spaced patterns 201139235 differ from the first preferred ones for facilitating the opening of the mold to provide a user's choice for the user to select. Referring to FIG. 12, a fourth preferred embodiment of the wafer carrier device 2 of the present invention is substantially the same as the third preferred embodiment. The difference is that the base 21 further includes a surface formed on the upper surface. The accommodating space (1) 'and the sowing wall 2 3 is located at the 兮 罢 p 。 pq. It is on the periphery of the space 214. To provide another aspect for the user to choose"
參閱圖13，本發明的晶片承載裝置2之第五較佳實施 例，大致是與該第-較佳實施例相同，其中，不相同的地 方在於：每-擋壁23之導引面233與該上表面2ιι間的夾 角θ 1大於每一擋壁23之抵靠面234與該上表面叫間的 夾角Θ2;而每一卡合壁24之第一導斜面243與該下表面 川間的夾角〇大於每一卡合壁24之第二導斜面2叫與 該下表面212間的夹角藉此提供另一態樣供使用者選 擇。 2之弟六較佳實施 不相同的地方在於 252是呈階梯狀地 參閱圖14，本發明的晶片承載裝置 例，大致是與該第一較佳實施例相同， :該結合單元25的第一、二楔面251、 相互配& W用呈階梯狀的設計，增加所述第—、二模面 251、252相互配合時的摩擦力，更能有效避免相互堆疊之 晶片承載裝置2發生位移或是錯動。 S] 綜上所述，本發明的晶片承載裝置2利用形成於每一 擋壁23上的第-楔面251，與相配合地形成於每—卡合壁 24上的第二楔面252，以產生導引作用使二晶片承载裝置2 9 201139235 在相互疊合時更為迅速，更可以以所述第―、二模面w、 252有效分散外力，使相互疊合的晶片承载裝置2不會產生 轉動或錯動，提高所承載之物件的穩定度，故確實能達成 本發明之目的。 &惟以上所述者，僅為本發明之較佳實施例而已，當不 =以此限定本發明實施之範圍，即大凡依本發明中請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一立體圖’說明一現有的晶片承載裝置； 鲁 圖2是一剖視圖，說明該現有晶片承栽裝置的使 形； 圖3是一俯視圖，輔助說明圖2,其中，省略部分構件 9 圖4是一立體圖，說明本發明之晶片承載裝置的第一 較佳實施例； 圖5疋另一是視角的立體圖，輔助說明圖4; 圖6是-側視圖，說明該第一較佳實施例中所述夹角_ 的態樣； 圖7是一立體圖，說明該苐一較佳實施例使用時的熊 樣； " 圖8是一剖視圖，辅助說明圖7; 圖9是一剖視圖，說明本發明之晶片承載裝置的第二 較佳實施例； 10 201139235 圖ίο是一立體圖’說明本發明之晶片承載裝置的第三 較佳實施例； 圖11是另一是視角的立體圖，辅助說明圖10; 圖12是-立體圖’說明本發明之晶片承載|置的第四 較佳實施例， 圖13是一剖視圖，說明本發明之晶片承載裝置的第五 較佳實施例；及 圖14是-剖視圖，說明本發明之晶片承载|置的第六 較佳實施例。 201139235 【主要元件符號說明】 2 晶片承載裝置 241 底面 21 基座 242 外周面 211 上表面 243 第一導斜面 212 下表面 244 第二導斜面 213 環繞面 25 結合單元 214 容置空間 251 第一楔面 22 限位單元 252 第·一模面 23 擋壁 3 晶片 231 頂面 31 本體 232 外壁面 32 接腳 233 導引面 Θ 1 ' Θ 2夾角 234 抵靠面 φ 1 > 0 2夾角 24 卡合壁 12Referring to Figure 13, a fifth preferred embodiment of the wafer carrier device 2 of the present invention is substantially the same as the first preferred embodiment, wherein the difference is that the guiding surface 233 of each of the barrier walls 23 is The angle θ 1 between the upper surface 2 ιι is greater than the angle Θ 2 between the abutting surface 234 of each of the retaining walls 23 and the upper surface; and the angle between the first guiding slope 243 of each of the engaging walls 24 and the lower surface The angle between the second guide bevel 2 of each of the engagement walls 24 and the lower surface 212 is thereby provided for another selection for the user to select. The preferred embodiment of the second embodiment is that the 252 is stepped. Referring to FIG. 14, the wafer carrying device of the present invention is substantially the same as the first preferred embodiment: the first of the combining unit 25 The two wedge faces 251 and the mating design of the mutual matching & W increase the frictional force when the first and second die faces 251 and 252 cooperate with each other, and the displacement of the wafer carrier device 2 stacked on each other can be effectively prevented. Or wrong. S] In summary, the wafer carrier device 2 of the present invention utilizes a first wedge surface 251 formed on each of the barrier walls 23, and a second wedge surface 252 formed on each of the engagement walls 24 in cooperation with each other. In order to create a guiding effect, the two wafer carrier devices 2 9 201139235 are more rapidly overlapped with each other, and the external force can be effectively dispersed by the first and second die faces w and 252 so that the wafer carrier devices 2 stacked on each other are not The rotation or the displacement is generated to improve the stability of the carried article, so that the object of the present invention can be achieved. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the simple equivalent of the scope of the patent and the description of the invention in the present invention. Variations and modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a conventional wafer carrier; FIG. 2 is a cross-sectional view showing the shape of the conventional wafer carrier; FIG. 3 is a plan view, and FIG. FIG. 4 is a perspective view showing a first preferred embodiment of the wafer carrying device of the present invention; FIG. 5 is another perspective view of the viewing angle, and FIG. 4 is a side view, and FIG. 6 is a side view illustrating the FIG. 7 is a perspective view showing a bear sample when the preferred embodiment is used; " FIG. 8 is a cross-sectional view, which is a supplementary view of FIG. 9 is a cross-sectional view showing a second preferred embodiment of the wafer carrier of the present invention; 10 201139235 is a perspective view illustrating a third preferred embodiment of the wafer carrier of the present invention; and FIG. 11 is another perspective FIG. 12 is a perspective view showing a fourth preferred embodiment of the wafer carrier of the present invention, and FIG. 13 is a cross-sectional view showing a fifth preferred embodiment of the wafer carrier of the present invention. ; and Figure 14 A cross-sectional view showing a sixth preferred embodiment of the wafer carrier of the present invention. 201139235 [Description of main component symbols] 2 wafer carrier 241 bottom surface 21 pedestal 242 outer peripheral surface 211 upper surface 243 first guiding slope 212 lower surface 244 second guiding slope 213 surrounding surface 25 bonding unit 214 accommodating space 251 first wedge surface 22 Limiting unit 252 First die face 23 Barrier 3 Wafer 231 Top surface 31 Body 232 Outer wall surface 32 Pin 233 Guide surface Θ 1 ' Θ 2 Angle 234 Abutment surface φ 1 > 0 2 Angle 24 Wall 12