TW201138320A - Analog-to-digital converter with sub-range and method thereof - Google Patents

Abstract

An analog-to-digital converter with sub-range and method thereof is disclosed. By increasing overlapping capacitors within a MSB array of capacitor array, so as to reduce the accuracy requirement for comparators during the coarse conversion, as well as reduce a comparison time of the comparators heavily. The mechanism is help to improve the efficiency of conversion for analog-to-digital conversion.

Description

201138320 VI. Description of the invention: [Technical field to which the invention pertains] The method of the present invention is a method for changing the ratio of the surface ratio (10), and particularly to the method of increasing the overlapping capacitance in the capacitor array. ^ [Prior Art]

In recent years, with the development of digital Lotus, analog digital conversion devices (also known as analog digital converters) have played a key role. And how to make the analog digital conversion device have better _ change efficiency is the problem that each factory wants to solve - in general, the analogy number _ change device _ is the ratio of the input to the corresponding digital output, in the traditional Continuous approximation s (Successive

In the Approximation, SAR) analog-to-digital converter, in order to make a correct judgment for each bit, the freshness of the marriage for each bit also relatively consumes a relatively long comparison time. In order to improve the resolution, the longer the capacitor array is, the longer the system needs to be stable, and the complexity of the system and the peripheral circuits are also larger. Therefore, a non-Bary Successive Approximation ADC (Non-Bmary Successive Approximation ADC) has been proposed, such as: "F.

Kuttner, A 1.2V l〇b 20MSamples/s Non-Binary Successive Approximation ADC in G'13um CM〇s,” lsscc Tenghua also Shangqing PP. 176-177, 2002·”, to solve the above problems and achieve high speed effect. However, in this way, it is necessary to use a complex digital controller and a temperature code array to perform and correct the error. m 3 201138320 For this reason, if you can use a non-binary search algorithm and avoid using the reset controller and temperature code capacitor array, but also allow the correction when the highest bit turns wrong, it will help to improve Conversion efficiency. In other words, it can be seen that there has been a problem of poor conversion efficiency in the prior art - and it is therefore necessary to propose an improved technical means to solve this problem. SUMMARY OF THE INVENTION The present invention is disclosed in the prior art. The present invention discloses a sub-region ratio digital conversion device and a method thereof. The analog-to-digital conversion device of the sub-interval disclosed in the present invention comprises: a capacitor array module, a conversion module, a control module and an output module. The capacitor array module receives the analog signal, and stores the analog signal in the LSB array and the array to generate a capacitor array output. The LSB array includes the first light-combining capacitor, and the array includes the second light-combining capacitor and the overlapping capacitor. And the second surface-capacitor capacitor and the overlapping capacitor are connected in parallel; the conversion module is in the preset coarse-divided (c〇arse) clock cycle, and the n-amplitude capacitor array is excited through the first device, and is read out. The electric energy column output transmission repairs to the lock comparator comparator 'and generates a coarse quantile according to the comparison result of the question lock comparator, and sets the coarse quantile to the decision signal, and the preset subdivision (4) e) clock During the period, the output of the capacitor array is amplified by the first preamplifier and the second preamplifier, and the output of the f-column of the domain is transmitted, and the subdivision bit is generated according to the comparison result of the flash lock comparator, and The subdivision bit is set as the decision signal; the control mode _ is used to determine the control set of the shouting shed, and the LSB array and the MSB array are controlled by the control logic; the female group (10) is coarsely divided by the digital error positive circuit. Bit, The result of the comparison of the subdivided bits and the overlap region is digitally corrected to produce a digital output signal. 201138320 2 It is mandatory that the capacitor array is a binary capacitor array. 4 and the size of the fresh capacitor is "2 (7 · χ) · small is Ί" unit. In addition, the large control logic of 卞(四)丝w h includes the overlapping logic and standard logic. This = wheel = control 4 capacitors, while the standard logic takes care of (4) one. Then, the control card includes the same number of LS positive and negative 与 as the overlap capacitor and is used as a register and respectively controls the corresponding overlapping capacitors, wherein each D-type flip-flop is electrically connected to the corresponding multiplexer. In this practical implementation, the conversion module calculates the overlapping area through the overlapping logic in the subdivision period of the subday cycle (four), and controls the overlapping capacitance according to the re-f area. The first preamplifier and the second preamplifier can be sent to the capture comparator through the gain control after the power amplifier array is large. The steps of the second interval ratio digital age method of the present invention include: receiving Analog signal, and the ratio of the 瓣 瓣 u 龄 ( ( ( ( 四 四 ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨The output of the capacitor array is transmitted to the flash lock comparator' and the coarse quantile is generated according to the (10) taste (10) taste result, and the coarse position bit is set as the decision signal; in the preset subdivision (decay) clock cycle Through the first preamplifier And the second preamplifier amplifies the capacitor array output, and transmits the amplified capacitor array output to the latch comparator, and generates a subdivision bit according to the comparison result of the latch comparison state, and sets the subdivision bit to the decision Receiving a decision signal to execute a preset control logic, and generating an overlap region and controlling the LSB array and the MSB array through the control logic; comparing the coarse quantile, the subdivided bit, and the overlap region by a digital error correction circuit The result is digitally corrected to produce a digital output signal. 201138320 The control logic includes overlapping logic and a small amount of overlap logic used to control the overlapping capacitance 'and the standard logic _ to control the first-age capacitor and the second-side power. The size of the second recombination capacitor mentioned is "2 (7·χΜ, unit, the large J of the overlapping capacitance is 1 unit. In addition, the analog digital conversion method of the sub-interval of the present invention, includes, subdivided clock week When shooting the second clock cycle, through the overlapping logic meter, the output area 'and the weight 4 area according to the weight 4 area, and the first step amplification The second preamplifier amplifies the output of the capacitor array and transmits it to the comparator via the gain control. Then, the overlap capacitor is controlled by the same number of D-type flip-flops as the register, wherein each type is positive. The D terminal of the inverter is electrically connected to the corresponding multiplexer, and the multiplexer receives at least the decision signal. The LSB array and the MSB array form a binary capacitor array. The device and method disclosed by the present invention As above, the difference from the prior art is that the present invention is to increase the overlap capacitance in the MSB array of the capacitor array, so that the Coarse process towel reduces the correctness of the comparator. Comparing the time. The technical effect of the conversion efficiency of the new digits can be improved by the technical means of the present invention. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings and embodiments, thereby The process of applying technical means to solve technical problems and achieve technical efficacy can be fully understood and implemented. Before the analog digital conversion device and the method thereof in the sub-interval disclosed in the present invention, the nouns defined by the present invention are first described, and the overlapping capacitance (0LC) mentioned in the present invention is used. For the corrected capacitance and 201138320 is set in the MSB array 'these overlapped__ the corresponding register is controlled, the detailed circuit of the MSB array and the overlapping capacitor will be described later in conjunction with the drawing. The following is a description of the analog-to-digital conversion device and the method of the sub-interval of the present invention. First, the description will be made first for the analog-to-digital conversion device of the sub-interval of the present invention. Please refer to "1" and "1". The block diagram of the analog-to-digital conversion device of the sub-interval of the present invention comprises: a capacitor array module 1 (n, a conversion module 1〇2, a control module 103, and an output module 1〇4), wherein the capacitor array module 1 〇1 is used to receive the Lu analogy, and the capacitor array output is generated through the LSB array and the MSB array, and the LSB array includes the first coupling capacitor, and the MSB array includes the second coupling capacitor and the overlapping capacitor, and the second coupling capacitor In parallel with the overlapping capacitors, in actual implementation, the capacitor array module 101 is a binary-weighted capacitor array composed of an LSB array and an MSB array. The conversion module 102 is used for a preset coarse division ( Coarse), in the clock cycle, amplifying the output of the capacitor array through a first preamplifier (Pre-amplifier), and transmitting the amplified output of the electric Lugu array to a latch comparator, and According to the comparison result of the latch comparator, the coarse quantile is generated, and the coarse component is set as the decision signal; and in the preset sub-clock cycle, through the first preamplifier and the second The preamplifier amplifies the output of the capacitor array, and transmits the amplified capacitor array output to the latch comparator, and generates a subdivided bit according to the comparison result of the latch comparator and sets the subdivided bit as a decision signal. The digital signal that determines the signal is “〇,, or “1 '', is used to determine the calculation of the “add” or “minus” of the binary search algorithm. In practical implementation, the output of the capacitor array can pass through the first front The amplifier and the second preamplifier are divided into different stages for gain to reduce the input comparator's input-referred offset. For example, the capacitor array output is permeable during the coarse clock cycle. A first preamplifier performs gain, and during subdivided clock cycles, the capacitor array output is amplified by a first preamplifier and two second preamplifiers (ie, (b), the detailed circuit diagram of this part will be described in conjunction with the drawing. In particular, the amplified capacitor array output can be transmitted to the latch after passing through the Gain control multiplexer. The lock comparator enters the 4 lock and compares 'and the invention does not limit the number of the first preamplifier and the second preamplifier. The Lu control module 丨〇3 is used to receive the decision signal to perform the preset. The control logic controls 'and generates overlapping regions through the control logic and controls the LSB array and the MSB array. The control logic includes overlapping logic and standard logic, and the overlay logic is used to control overlapping capacitances, such as: "CL<0>==SC<N+1> | (SC<9>&〇LS<N>), CL<1 >==SC<N>", and standard logic is used to control the first coupling capacitor and the second consumption & Valley, for example, "CL<〇>== SC<N+1>, CL<1>==SC<N>", where n is a bit, CL is a control logic, SC is a state control, and 〇LS is Overlapping state, in real φ implementation, this overlapping logic is designed to be able to overlap As a result, the second sampling is performed, and the conversion module 1〇2 is provided to divide the overlapping region of the binary search algorithm through the overlapping logic in the second clock cycle period of the subdivided clock cycle, so as to control The module 103 controls the overlap capacitance based on this overlap region, while the standard logic control is the same as the conventional standard design. In particular, the present invention is not limited to the overlapping logic and the standard logic by the above examples, and the same functions composed of equivalent circuits are all of the embodiments without departing from the spirit and scope of the embodiments. Means can be implemented. In addition, the control module 1〇3 may include the same number of D-type flip-flops as the overlap capacitors as the registers and respectively control the respective overlapping capacitors. The D end of each D-type 201138320 flip-flop is electrically connected to a corresponding multiplexer, and the multiplexer receives at least the decision signal generated by the conversion module 102. The output module 104 is configured to perform digital correction on the comparison result of the coarse quantile, the subdivision-bit, and the overlap region by using a digital error correction circuit to generate a digital output signal. • In practice, use a binary search algorithm with overlapping regions to check for coarse tool bit errors and digital corrections for errors. In the binary search algorithm, a comparison process is performed in which the female inserts a heavy-duty region, and the overlap region is actually calculated by the capacitor array module 101 inputting a stable time, if a longer • stabilization time is required A large overlap area is required. As shown in FIG. 2, FIG. 2 is a flow chart of the analog-to-digital conversion method of the sub-interval of the present invention, and the steps include: receiving an analog signal, and storing the analog signal in the LSB array and the MSB array to generate Capacitor array output (step 21〇); in a predetermined coarse phase (Coarse) clock cycle, the capacitor array output is amplified by the first preamplifier, and the amplified capacitor array output is transmitted to the latch comparator, and Generating a coarse quantile according to the comparison result of the latch comparator, and setting the coarse component to a φ decision signal (step 220); in the preset sub-clock cycle, through the first front The magnifying ϋ and the second preamplifier H amplify the electric turn, and the enlarged electric material is sent to the voyage, and the root period is compared with the word comparison result. The subdivision bit is generated, and the subdivision bit is set. To determine the signal (step 23〇); receive the decision signal to implement the control touch, and generate the overlap region and control the LSB array and the MSB array through the fourth (step 24); the coarse error is determined by the digital error correction circuit Bits, subdivisions, and overlapping regions The comparison result is digitally corrected to generate a digital output signal (step 25A). In practical implementation, step 2 ι is to generate a capacitor array through the café array and the MSB array into a binary capacitor _ to generate a capacitor array input 201138320 and the LSB P train column includes a first-to-surface capacitance, the MSB array includes a second consuming capacitor and The electric grid is re-powered, and the first consumable capacitor and the overlapping capacitor are connected in parallel with each other. In addition, during the second clock cycle in the fine/knife clock cycle, the overlap region is calculated by the overlap logic and the overlap capacitance is controlled according to the overlap region (step, through the above steps, the array can be in the valley array) The overlapping capacitance is added to the MSB array to reduce the requirement of the ambiguous redness in the process of coarse division (c_e), thereby greatly reducing the comparison time of the succulent. The following is in conjunction with "3rd" to "5th". The method is as follows. Please refer to "3" and "3" for the circuit diagram of the capacitor array module to which the present invention is applied. The capacitor array module 1〇1 includes: analog signal input terminal 301 LSB P car The column 310, the first-combining capacitor 311, the MSB array 32〇, the second tapping valley 321 , the overlapping grid 322, and the capacitor array output terminal 33. In particular, the above description is '12 bits, The capacitor array is illustrated. However, the present invention does not limit the number and type of electronic components included in the capacitor array module 101. In addition, the integer capacitance 3_ can be connected between the LSB array 310 and the MSB array 32〇, For the sake of convenience Therefore, as shown in "Figure 3", it is possible to add an additional number of electric power f 300a ' to make the unit capacitance value of the integer capacitance lion maintain an integer. For example, the capacitance 30 〇a can be respectively and And "Vm,, the connection of the two light-combined capacitors, the two her combined capacitance is a total of thirty fresh capacitor values, the integer capacitance 3〇〇b through the conventional formula (for example "(32+3 〇y31=2,,. where = is the unit capacitance value of 31LS of the LSB array, “3〇, the unit electric valley value of the capacitance ^00a”, and then the integer capacitance bird is two For example, the capacitor array module 1〇1 of the “12” bit is used as an example. The capacitor array module receives 201138320 and receives the analog signal through the analog signal input terminal 301, and passes through the LSB array 31. And the MSB array 320 generates a capacitor array output, and the generated capacitor array output is output to the conversion module 1〇2 through the grid array output terminal 330, wherein the LSB array 31〇 includes a plurality of first consumable capacitors 311' And generate corresponding bits in "L1" to "L5", and MSB array 320 contains The second coupling capacitor 321 and the overlapping capacitor 322, and the second engaging capacitor 321 and the heavy capacitor 322 are connected in parallel with each other as shown in FIG. 3. As mentioned above, in the MSB array 320, the first "6" bit The element is formed by the second coupling capacitor 321 "Mx" and the overlapping capacitor 322 "OLx", wherein "x" represents the bit number. The size of the second light combining capacitor 321 "Μχ" is "Sizes". For the 2(7x)-l" unit, for example, the size of the second coupling capacitor 321 "M1" is "2 (^) - 1 = 63" unit, and the size of the second coupling capacitor 32 丨 "M2" is "2" (7·2) 1=3 i" The unit, ... and so on, the size of the second coupling capacitor 321 "M6" is "2 (7_6) - 1 = 1". Therefore, the second coupled valley 321 and the overlapping capacitor 322 of rMl+〇u" to "M6+〇L6" form a similar traditional continuous approximation; APPr〇ximati〇n, SAR) analog digital converter (Anal〇g_t〇_Digital c 〇nverter, ADC) A binary capacitor array. In the Coarse conversion process, the overlapping capacitance 322 "〇Lx" is the same as the other - the second coupling capacitance 32i "Mx" performs the binary search algorithm, and the result of the subdivision conversion of the second bit can be changed. A connection of overlapping capacitors 322 is performed to perform a repeat comparison. Taking the unary search algorithm as an example, suppose the analog input hierarchy is equivalent to the value 2020". After tracking, it is similar to the traditional continuous approximation analog digital conversion benefit, and its first decision point (Decisi〇np〇int) “2048” is half of the total wheeling range, and the control logic sets rM1” and r〇L1” to “Vrp” j 11 201138320. This causes the reference source to be changed by the large capacitive load. Therefore, the reference source and capacitor array output require coffee. stable. If the _ comparator is to resolve the bit it's when the output of the capacitor array has not been completed, it may result in a wrong decision. In this example, suppose an erroneous judgment occurs and the comparator result is "丨, instead of "〇". Keep "m" and "0L1" connected to "Vrp", "M2" and "(10)" are connected to "Vrp" to form the second decision point "3〇72". Because the residual voltage of the second decision point is large enough 'even if the output of the capacitor array is not stable, the flash lock comparator can also be cut off. "M2" and "OL2" are switched from "Vrp to Vm" after the second decision point is generated, and the remaining coarse conversion is repeated in the same manner. Starting from the seventh bit, the capacitor array output takes longer to stabilize and gain amplification; therefore, the analog circuit has high accuracy for accurate conversion. It is not allowed to have errors afterwards. After the seventh decision point is produced, the loser (ie: “2〇2〇”) is between 2143 and 2016. The seventh decision point is “2〇8〇” and the comparison is π and 〇. The seventh result indicates that the input should be between "2〇8〇,, and "2〇16", and in the coarse-segment conversion, the wrong decision is only possible at "2048". Therefore, it needs to be in the S8 position. Yuan ornaments check the material point "fibre". The seventh her-yuan comparator, the fruit makes the Μ7" gang Vrp seven knife change back to "Vm". The eighth bit result needs to be “〇”. ,, - An overlapping logic function is used to determine the first "ι and the first 0" in the coarse conversion result. In this example, the coarse quantile result is "100000". The first "1" is The bit--and the first "0" are in bit 2. This means that "〇Li" can be switched from "Vrp," to "Vm" through the LSB array 310 to reduce the decision point. Because 'the seventh bit result indicates that its input may be less than "2048" and not greater than "2080" 'its "OL1" register flash locks the eighth bit result and "(10)" is] 12 201138320 The state does not change. The eighth bit result is "〇, and its "〇L1" is switched from "Vrp" to "Vm". Then 'in the ninth bit result rL1' is switched from "Vm," to "Vrp." Since "0L1" lowers the decision point through the LSB array 31, the ninth to the twelfth bit result is checked by the conventional binary search algorithm to input "2〇2〇". Therefore, the error in the first bit will be fixed. After the twelfth second, the digital error correction circuit recomposes the coarse and subdivided bit results to form an output code of "12" bits. The subdivision conversion output is the result of the seventh bit result and the ninth to thirteenth bit result. Assuming that the error is due to a coarse-to-segment conversion, the digital error correction is checked using the seventh and eighth bit results. The function of its digital error correction circuit is as follows:

Output = Coarse*64+Fine-32 if 7th & 8th results are 00

Output = Coarse*64+Fine if 7th &8th results are 01 or l〇

Output = Coarse*64+Fine+32 if 7th & 8th results are 11 Although this method requires an extra bit to overlap, the stabilization time of the capacitor array rotation can be greatly reduced in the coarse conversion, which leads to higher Conversion speed. Next, please refer to "Fig. 4" and "Fig. 4" for a circuit diagram of a conversion group to which the present invention is applied. The conversion module 1〇2 includes an input terminal 4〇1, a first preamplifier 411, a second preamplifier 412, a latch comparator 43〇, and an output terminal 44〇. As mentioned above, the conversion module 102 can be divided into different stages for gain (i.e., signal amplification) through the first preamplifier 411 and the second preamplifier 412, and the actual connection manner is as shown in FIG. The input terminal 4〇1 and the capacitor array output terminal 'hybrid connection' of the capacitor array module 1〇1 receive the output of the electric energy column. In the county, the capacitor array output is amplified only by the pre-amplifier 411 in the coarse clock cycle to achieve fast conversion. Then, in the subdivided clock cycle, the first preamplifier is placed through the first preamplifier 201138320 and the second preamplifier is connected to the amplified capacitor array output, and the amplified capacitor array m is sent to the _ comparator. In actual implementation, the output of the amplified capacitor array can be received by the two sets of gain control multiplexers, and then outputted by the two sets of gain control multiplexers 42 to the lock comparator to generate a sigma number, and The feed_transmits the uncomfortable signal to the control module 103. - as shown in "5", "5th" is a circuit of the register of the present invention: the intention of the register 500 includes a multiplexer 5i, a D-type flip-flop and a control 1 ^520, wherein the "Holiday device 51" has three input lines for receiving the working voltage _), and is electrically connected to the output end of the conversion module 102 for receiving the decision signal generated by the conversion group 102 and D The other types of positive and negative poles are connected. In addition, the output line of the multiplexer 510 is electrically connected to the D terminal of the D-type flip-flop 530 and the control line is electrically connected to the control logic 52. In the case where the d-type positive 2 = is more like the "figure 5", it is intended to connect the time pulse and the sampling - handsome ^ actual implementation, the control logic is left to control the input of the multiplexer training, for example: , =L is " The 00" bit "N" state maintains the previous state; when Jiang is like the time, the decision signal of the output terminal 440 is sampled; when the river is "1", it is set to "1" (that is, it is connected with "Vdd" f Shushu 500 is reset to "〇,,. * When tracking" all temporary storage mentioned above, overlapping capacitor 322 through the corresponding register 5 (4) temporary storage ϋ 500 is the "figure 5" The schematic circuit is composed of: In the above, the overlapping capacitor 322 and the temporary storage _ have the same ^ The number of overlapping capacitances in the hypothetical array 为 is six, and the number of the same is six, each - The register (4) respectively controls the corresponding weight = IS1 14 201138320 322. - In summary, it can be seen that the difference between the present invention and the prior art is that the female component is read by adding the overlapping capacitance in the MSB array of the grid array ( C_e) In the process of 'falling down ratio (four) of the mixed requirements, by this - technical means can bribe the previous technology * surgery exists The title 'in turn greatly reduces the comparison time of the comparator, the technical effect of the conversion efficiency over the digital. 冋 Although the present invention is disclosed above in the above-mentioned real terms, it is intended to limit the hair of the present, any familiar artisan, Without departing from the spirit and scope of the present invention, the singularity of the singularity of the singularity of the present invention is determined by the scope of the patent application attached to the present specification. [Simplified illustration] The figure is a block diagram of the sub-region analog-to-digital conversion device of the present invention. Fig. 2 is a flow chart of the method for converting the number of digits of the a-type (four) of the present invention. Fig. 3 is a schematic diagram of the f-way of the Gubenfa_electric material group. The figure shows a circuit diagram of a conversion module to which the present invention is applied. Private figure 5 is a circuit diagram of a register to which the present invention is applied. [Main Symbol Description] 101 Capacitor Array Module 102 Conversion Module 103 Control Module 1〇 4 output module 300a to make up the number of capacitors 300b integer capacitance analog signal input terminal m 201138320

310 LSB array 311 first coupling capacitor 320 MSB array 321 second coupling capacitor 322 overlap capacitor 330 capacitor array output 401 input 411 first preamplifier 412 second preamplifier 420 gain control multiplexer 430 latch comparator 440 output terminal 5 〇〇 register 510 multiplexer 520 control logic 530 D-type flip-flop step 21G receive - analog signal 'and store the analog signal in an array and - MSB array' to generate a capacitor array output Step 220: in a preset coarse (C. woven) clock cycle, amplifying the capacitor array output through a first preamplifier, and transmitting the amplified capacitor array output to the -flash lock comparator, and according to The comparison result of the flash lock comparison state generates a coarse division bit, and the coarse division bit is set as a decision signal. Step 23 is in a preset sub-period (Fine) clock cycle, through the first pre-position The 201138320 amplifier and the at least one second preamplifier amplify the capacitor array output, and transmit the amplified capacitor array output to the latch comparator, and generate a subdivision according to the comparison result of the latch comparator And setting the subdivision bit to the second clock cycle in the subdivided clock cycle by the decision signal step 231, calculating the overlap region by the overlap logic and controlling the at least one overlap according to the overlap region The capacitor step 240 receives the decision signal to execute a predetermined control logic, and generates an overlap region through the control logic and controls the LSB array and the MSB array step 250 to transmit the coarse quantile through a digital error correction circuit. The comparison result of the subdivided bit and the overlapping area is digitally corrected to generate a digital output signal

IS] 17

Claims (1)

201138320 VII. Patent application scope: 1. A sub-interval analog-to-digital conversion device, including: - Capacitor array, rib receiving-analog signal and storing the analog signal in -LSB _ and -msb _, generating - capacitor Array output 'where the LSB array includes at least one first consumable capacitance, the MSB array includes at least one second coupling capacitor and at least one overlapping capacitor, and the at least one second coupling capacitor and the at least one overlapping capacitor are connected in parallel with each other; a conversion module for amplifying the electrical rotation through the -first preamplifier during a predetermined coarse clock period, and transmitting the amplified capacitor array to the - (10) a comparator, and generating a coarse register based on the comparison result of the lock master and setting the coarse component as a decision signal, and in a preset subdivision (Fine) clock cycle A, through the A preamplifier and at least one second preamplifier amplify the output of the capacitor array, and transmit the amplified output of the capacitor array to the latch comparator, and compare the H of the comparison lock according to the Q lock to generate a subdivision bit And the touch sub-division bit is set as the decision signal; a control module is configured to receive the decision signal to execute a preset control logic, and generate an overlap region and control the LSB array and the MSB array through the control logic And an output module 'for performing a digital correction on the comparison result of the coarse quantile, the delta subdivision bit, and the overlap region through a digital error correction circuit to generate a digital output signal. 2. The analog-to-digital conversion device of the sub-interval described in the scope of the patent application, wherein the capacitor array module is a binary capacitor array. 18 201138320 3. :ί (Representation of the analogy of the sub-interval described in item 1 of the patent scope) where the at least-second Hehe capacitors are installed with less than one overlapping capacitor size. 1 early position 'to 4 The class of the sub-interval described in item i of the patent application scope, wherein the control touch contains - overlapping, the logic is used to control the at least - overlapping capacitance; the logic 'the overlap is less than the first one Controlling the analog-to-digital conversion package of the sub-interval described in the &=== patent scope item!, the middle-mechanical group contains the at least-overlapped residual_(four) 6=reverse master^ is used as a temporary register The respective overlapping capacitors are respectively controlled. The D-end of each of the D-type flip-flops in the sub-interval described in Item 5 of the patent target is connected with the corresponding-multiplexer=λ, and the evening device receives at least the Determining the signal. ^申:: The second time interval in the subdivision clock cycle of the analogy digital converter in the sub-interval of the sub-interval described in item i of the interest range =, calculated by far overlapping logic The overlapping area, and controlling the at least one overlapping capacitance according to the control. The analogy of the sub-interval described in the scope of the patent item is that the output of the first preamplifier and the at least-second preamplifier capacitor array is amplified, and at least the polynomial latch comparator is added. The analog-to-digital conversion method of the sub-interval includes: receiving an analog signal and storing the analog signal in the -lsb array and an MSB array to generate a capacitor array output; 9 201138320 in a preset coarse coordinate (Coarse) In the clock cycle, the capacitor array output is amplified by a first preamplifier, and the amplified capacitor array output is transmitted to a latch comparator 'and a result is obtained according to the comparison result of the latch comparator. a quantile, and setting the coarse quantile as a decision signal; in a preset sub-clock cycle, the capacitor is amplified by the first preamplifier and the at least one second preamplifier Array output, and transmitting the amplified capacitor array output to the latch comparator, and generating a subdivided bit according to the comparison result of the latch comparator, and dividing the subdivision Set to _ the decision signal; receive the decision signal to execute a preset control logic, and generate the overlap region and control the LSB array and the MSB array through the control logic; and pass the coarse division through a digital error correction circuit The comparison result of the bit element, the subdivided bit and the overlapping area is digitally corrected to generate a digital output tonne. Φ 1〇', as in the analogy digital conversion of the sub-interval described in claim 9 of the patent scope, The control logic includes an overlay logic and a standard logic. The overlay logic rib controls at least the overlap capacitor. The standard logic controls the at least one first coupling capacitor and the at least one second coupling capacitor. u. If the analog digital conversion method of the sub-interval described in item 10 of the patent scope is applied, wherein the method further includes the second clock cycle in the subdivided clock cycle, the overlapping region is calculated by the overlapping logic. And controlling the at least one overlapping capacitance according to the overlapping area. 12. The analog-to-digital conversion side of the sub-interval described in item K) of the patent application 20 [S] 201138320 〃中^海At least one second light-to-weight# The size of the capacitor is I unit. The unit is small, and the method is as described in claim 5, wherein the at least one stack of capacitances is controlled by an analog digital conversion type flip-flop. * ", the same number of D register of the register, _13 job, which makes the D-terminal 1 digit conversion of each D-type flip-flop, the multiplexer receives at least the decision signal: Multiplexer electrical connection 15. Γ=1 The analog digital conversion method of the sub-interval described in item 9 of the range is to discuss that the LSB array and the MSB array form a binary capacitance array. 16. The analog-to-digital conversion method of the sub-interval described in claim 9 wherein the first preamplifier and the at least second preamplifier amplify the output of the capacitor array by transmitting at least one gain control The tool is transferred to the latch comparator. 21 [S]