201138046 六、發明說明： 【發明所屬之技術領域】 本發明係有關於—種半導體封裝件與其製法，尤指一 種能縮短導㈣晶片的輯之半導體封裝件及其製法。 【先前技術】 半¥體封I件常見之問題在於導線架之四邊形晶片 f(Die Pad)中’其四個角落對應之導腳因空間的因素而與 晶片的距離過大’使得銲線必須拉長而導致成本的增加。 再者，較長的銲線於封膠(m〇lding)時易發生鲜線偏移⑽π sweep)，也就是原本打好的鲜線因為封勝的衝速過大而 離或損壞。 第1圖係習知具有四邊形晶片座1〇2之半導體封穿件 1〇之示意圖。如圖所示’晶片座102上設置有晶片ι〇;， 且沿晶片座102周圍設置有導腳(〗ead)1〇3。晶片ι〇ι上的 接合墊(bonding pad)l〇ll透過銲線1〇4電性連接該導腳。 明顯地’因為晶片座102的空間關係，導腳1〇3無法向内 延伸，使得對應晶片座1〇2四個角落的導腳1〇3與晶片 上接合墊1011的距離較大，因此必須使用較長的銲線 1〇4。然而，銲線104長度的增加不但會提高半導體封裝件 W的製作成本，也容易發生銲線偏移的狀況。 、 第5，168,368號美國專利案揭露一種半導體封裝件， 係為了避免發生因銲線長度增加而產生的銲線偏移現象。 ^此件美國專利案中，利用一種具有環狀中間區域的導線 木，使得銲線可由導腳先連接至該導線架的環狀中間區域 111550 4 201138046 •的接合塾，再由該接合塾連接至晶片上。如此，將f知技 货中使用&U的銲線改良為使用兩段較短的銲線，因 -此大大減少銲線偏移發生的區域。然而，此種作法會增加 銲線的總使用量，因而大幅提高半導體封裝件的製作成 本，且仍未解決習知半導體封裝件因為晶片座的空間關係 而使導腳無法向内延伸的問題。 、疋、—士何解决上述銲線偏移問題，並降低銲線的使 用成本，實為目前亟欲解決的課題。 • 【發明内容】 鑒於以上所述先前技術之缺點，本發明提供一種且有 多邊形晶片座之半導體封襄件，包括：多邊形晶片座:係 具有至少五側邊，·複數導聊，係設於該多邊形晶片座之周 圍’且與該多邊形晶片座之側邊形成一預定之距離；晶片， ^㈣多邊形晶片座上’以藉由鲜線電性連接至該複數 數導腳與該晶片用以包覆該多邊形晶片座、該複 1於-較佳態樣中，上述之半導體封裝件可包括沿著該 多邊形晶片座之侧邊而連續或分段設置的接地環如麵d rhlg)，亦或是包括連接該多邊形晶片座或接地環之支撐條 g㈣。而料邊形晶片紅至少—側邊與其相 鄰側邊的夾角為鈍角。 本發明更提供一種半導體封裂件之製法，其步驟包括 提供一具有至少五側邊的多邊形晶片座：沿該多邊形晶片 座之周圍設置複數導腳，且該複數導腳與該多邊形晶片座 111550 5 201138046 之側邊形成一預定夕花絲·、，η 座上，以读、心 ’ 1及將晶片設於該多邊形晶片 太癸：將該晶片之接合塾電性連接該複數導腳。 本毛月又提供—種導線架結構，包括··多邊型 座’係具有至少五側邊以月適金道 曰曰 曰 ，複數導腳，係設於該多邊型 j座之周圍，且與該多邊型晶片座之側邊形成一預定之 距離。 由上述說明可知，本發明利用多邊形晶片座取代透習 知的四邊形晶片座’使晶片座周圍的導腳可向内延伸，縮 短導腳與晶片的距離，因此可使用較習知技術更短的銲線· 來連接導腳與晶片。由於銲線的使用量減少，故可降低降 低半導體封裝件的製造成本。此外’還可減少銲線偏移發 生的機率。 【實施方式】 以下係藉由特定的具體實施例說明本創作之實施方 式，所屬技術領域中具有通常知識者可由本說明書所揭示 之内容輕易地瞭解本創作之其他優點與功效。 睛參閱第2圖，係本發明之具有多邊形晶片座之半導 # 體封裝件之構造圖。如圖所示，半導體封裝件2〇包括具有 至少五側邊的多邊形晶片座202、設於該多邊形晶片座2〇2 之周圍且與該多邊形晶片座202之側邊形成一預定之距離 的複數導腳203、設於該多邊形晶片座202上以藉由輝線 2〇4電性連接至該複數導腳203的晶片2〇1以及用以包覆 該多邊形晶片座202、該複數導腳203與該晶片201之封 震膠體（未予以圖示）。本實施例之半導體封裝件2〇具有八 Π1550 6 201138046 邊形之晶片座202，其主要的原理是透過對習知的四邊形 晶片座的四個角落進行切角（chamfer)，使四個角落所對應 之導腳203能朝向晶片201延伸，因此能縮短銲線204長 度。 請同時參閱第1圖及第2圖，於第1圖中，習知晶片 座102的四個角落所對應的導腳103必須使用最長的銲線 (例如使用金線或銅線）與晶片上的接合墊1011電性連接。 而於第2圖之本發明的半導體封裝件中，透過對晶片座202 •四邊切角，使四個角落所對應的導腳203所需的銲線長度 縮短，且相較於其他導腳，四個角落對應之導腳203所需 的銲線不再是最長的銲線，因此能大幅降低銲線使用的成 本，同時，也能減少發生銲線偏移的機率。 於一較佳實施例中，如第2圖所示，本發明之具有多 邊形晶片座之半導體封裝件20復包括接地環205,係沿著 該八邊形晶片座202之側邊而連續設置。然而，該接地環 I 205尚可以分段方式設置，且該接地環205可呈對稱或非 對稱的形狀。另外，半導體封裝件20復包括支撐條206， 用以連接並支撐該八邊形晶片座202及接地環205,其中， 該八邊形晶片座202之形狀可為對稱或非對稱。 於另一較佳實施例中，複數導腳203可依據對應之該 銲線204長度與該八邊形晶片座202之側邊形成不同的距 離。如第2圖所示，導腳203與晶片座202的距離標示為 d，然而，距離d可依據不同導腳203所需的銲線204長度 進行調整，亦即，某一導腳203與晶片座202的距離與其 7 111550 201138046 他導腳與晶片座202的距離玎為相同或不相同，完全由設 計上的需求來決定。 請參閱第3圖，係第2圖之具有多邊形晶片座之半導 體封裝件的示意圖。為了清楚地表示出本發明之半導體封 裝件的架構，因此本圖中旅未繪示出銲線。如圖所示，半 導體封裝件30包括八邊形晶片座302、設於該八邊形晶片 座302之周圍且與該八邊形晶片座302之側邊形成一預定 之距離的複數導腳303、設於該八邊形晶片座上的晶 片301、沿著該八邊形晶片座302之側邊設置之接地環305 以及用以連接並支撐該八邊形晶片座302及接地環305之 支撐條306。由於晶片座302各邊對應之導腳303與晶片 3〇1的距離差距不大，因此能縮短銲線的使用長度。 於一較佳實施例中，該晶片301可為對應該多邊形晶 片座之多邊形。例如’若使用八邊形晶片座302，則晶片 301可使用八邊形晶片’則可更進一步縮短銲線的使用長 度。 請參閱第4A及4B圖’係本發明具有多邊形晶片座 之半導體封裝件的其他具體實施例之示意圖。 於第4A圖中，半導體封裝件具有晶片4〇1、五邊形 晶片座402、對應該五邊形晶片座402之接地環405以及 連接該接地環4〇5之支樓條406。於第4B圖中，半導體封 裝件具有晶片4〇1 ’、六邊形晶片座搬，、對應該六邊形晶 片座402，之接_ 405,以及連接接地環4〇5，之支樓條 406’。透過該些具體實施例可知，晶片座的設計可配合晶 111550 8 201138046 • 片上接合墊的線路布局（layout)，決定是否將其—角戋多角 進行切角，以形成至少五邊之晶片座，而該多邊形晶=座 之至少一側邊與其相鄰側邊的夾角為鈍角。以第4a圖為 例，該晶片座於左上方形成一切角的斜邊，則至少會有二 側邊(該斜邊)與其相鄰側邊的夾角為鈍角。 g - 請參閱第5圖，係本發明具有多邊形晶片座之半導體 封裝件的再-具體實施例之示意圖。如圖卿，半導體封 袭件50具有晶片5()1、十二邊晶片座5〇2、導腳$的及支 撐條5〇6(為清楚起見並未繪示出銲線）。此實施例的設計原 理在於，當對習知四邊形晶片座進行切角時，可藉由調整 導腳的位置來縮短鮮線長度，然而，當某一角進行切角後 2會形成兩個新的角，而靠近此兩個新的角的導腳可能會 南要較長的銲線，若對此兩個新的角再進行切角，理論上 可再縮短銲線長度。換句話說，當晶片座越多邊時，其所 需的總銲線長度會越少。因此，相較於前述五邊形、六邊 形或八邊形的晶片座，本實施例之十二邊晶片座5〇2所需 的總鲜線長度會最少。 另外本發明更提供一種半導體封裝件之製法，其步 驟，括:提供一具有至少五側邊的多邊形晶片座；沿該多邊 曰> 曰片座之周m複數導腳，且該複數導腳與該多邊形 =座之側邊形成—預定之距離；將晶片設於該多邊形晶 以透過銲線將該晶片之接合墊電性連接該複數導 =及利用封裝膠體包覆該多邊形晶月座、該複數導腳 興该日日片。 111550 9 201138046 包括」著二又例中’本發明之半導體封裳件之製法復 的步ί。5 乂夕邊形晶片座之側邊而連續或分段設置接地環 提供Γ種導線架結構，包括具有至少五㈣ 多邊型曰及'於該多邊型晶片座之周圍且與該 士片座之側邊形成—預定之距離的複數導腳，其 ’該多邊形晶片座之形狀可為對稱或非對稱，且該多邊 形W座之至少-側邊與其相鄰側邊的夹角為純角。於一 較佳貫施例中，該導線架結構復包括沿著該多邊形晶片座 =側邊而連續或分段設置的接地環，而該接地環可連接支 #條。另外，此種導線架結構亦可包括連接該多邊形晶片 座之支撐條。透過此種多邊形導線架結構’可縮短銲塾與 晶片的距離，以減少銲線的使用量。 由上述說明可知，本發明利用多邊形晶片座取代習知 的四邊形晶片座’使晶片座周圍的導聊可向内延伸，縮短 導腳與晶片的距離，因此可使用較習知技術更短的銲線來 連接導腳與晶片。由於銲線的使用量減少，故可降低降低 半導版封褒件的製造成本。此外，還可減少銲線偏移發生 的機率。 以上所述之具體實施例，僅係用以例釋本發明之特點 及功效，而非用以限定本發明之可實施料，在太 發明上揭之精神與技術範訂，任何運用本發明所揭示= 谷而完成之等效改變及修飾’均仍應為下述之申請專利 圍所涵蓋。 111550 10 201138046 【圖式簡單說明】 第1圖係習知半導體封裝件之構造圖； 第2圖係本發明具有多邊形晶片座之半導體封裝件的 一具體實施例之構造圖； 第3圖係第2圖之具有多邊形晶片座之半導體封裝件 的不意圖， 第4A及4B圖係本發明具有多邊形晶片座之半導體 封裝件的其他具體實施例之示意圖；以及 第5圖係本發明具有多邊形晶片座之半導體封裝件的 再一具體實施例之示意圖。 【主要元件符號說明】 10 半導體封裝件 101、201、301、401、401’、 501 晶片 102 四邊形晶片座 103 、 203 、 303 、 503 導腳 104 、 204 銲線 1011 接合墊 20 、 30 ' 50 半導體封裝件 202 、 302 八邊形晶片座 205 ' 305 、 405 、 405’ 接地環 206、306、406、406’、506 支撐條 402 五邊形晶片座 402， 六邊形晶片座 502 十二邊形晶片座 11 111550201138046 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package capable of shortening a semiconductor wafer and a method of fabricating the same. [Prior Art] A common problem with a half-body seal I piece is that in the quadrilateral wafer f (Die Pad) of the lead frame, the lead pins corresponding to the four corners of the lead frame are too large due to space factors, so that the wire must be pulled. Long resulting in increased costs. Furthermore, the longer wire bond is prone to fresh line offset (10) π sweep when it is sealed, that is, the fresh wire that was originally wounded is damaged or damaged because the speed of the seal is too large. Fig. 1 is a schematic view of a conventional semiconductor package member having a quadrilateral wafer holder 1?. As shown in the figure, the wafer holder 102 is provided with a wafer ι; and a lead (1 ead) 1 〇 3 is provided around the wafer holder 102. A bonding pad 101 of the wafer ι is electrically connected to the lead through the bonding wire 1〇4. Obviously, because of the spatial relationship of the wafer holder 102, the lead pins 1〇3 cannot extend inward, so that the distance between the lead pins 1〇3 corresponding to the four corners of the wafer holder 1〇2 and the bonding pads 1011 on the wafer is large, so it is necessary to Use a longer wire bond 1〇4. However, the increase in the length of the bonding wire 104 not only increases the manufacturing cost of the semiconductor package W, but also tends to cause the wire to be offset. U.S. Patent No. 5,168,368 discloses a semiconductor package for avoiding wire bond deflection due to increased wire length. ^ In this U.S. patent, a wire having an annular intermediate portion is utilized such that the wire can be first connected to the annular intermediate portion of the lead frame by the lead pin 111550 4 201138046 • and then joined by the joint On the wafer. In this way, the wire used in & U is improved to use two shorter wire bonds, which greatly reduces the area where the wire deviation occurs. However, this practice increases the total amount of bonding wires used, thereby greatly increasing the manufacturing cost of the semiconductor package, and still does not solve the problem that the conventional semiconductor package cannot extend inward due to the spatial relationship of the wafer holder.疋 — — — 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决 解决The present invention provides a semiconductor package having a polygonal wafer holder, comprising: a polygonal wafer holder having at least five sides, a plurality of guides, and The periphery of the polygonal wafer holder is formed at a predetermined distance from the side of the polygonal wafer holder; the wafer is mounted on the polygon wafer holder to electrically connect to the plurality of leads and the wafer by a fresh wire Covering the polygonal wafer holder, the semiconductor package may include a ground ring (such as a surface d rhlg) continuously or in sections along a side of the polygonal wafer holder. Or include a support strip g (4) connecting the polygonal wafer holder or the grounding ring. The edge-shaped wafer red is at least—the angle between the side edges and the adjacent sides is an obtuse angle. The invention further provides a method for fabricating a semiconductor cracker, the method comprising the steps of: providing a polygonal wafer holder having at least five sides: a plurality of lead pins disposed around the polygonal wafer holder, and the plurality of lead legs and the polygonal wafer holder 111550 5 The side of the 201138046 is formed on a predetermined stencil, the n-seat, to read, the core '1 and the wafer is placed on the polygonal wafer too: the junction of the wafer is electrically connected to the plurality of leads. This month also provides a kind of lead frame structure, including ··Multilateral seat's with at least five sides to the moon, and multiple guide feet, which are arranged around the multilateral j-seat, and The sides of the polygonal wafer holder form a predetermined distance. As can be seen from the above description, the present invention utilizes a polygonal wafer holder instead of a transparent quadrilateral wafer holder to extend the guide pins around the wafer holder inwardly, shortening the distance between the guide pins and the wafer, and thus can be shorter using conventional techniques. Wire bonding · To connect the lead and the wafer. Since the amount of use of the bonding wire is reduced, the manufacturing cost of the semiconductor package can be reduced. In addition, the probability of wire bond offset can be reduced. [Embodiment] The following describes the implementation of the present invention by way of specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention by the contents disclosed in the present specification. Referring to Fig. 2, there is shown a structural view of a semiconductor package having a polygonal wafer holder of the present invention. As shown, the semiconductor package 2 includes a polygonal wafer holder 202 having at least five sides, a plurality of polygonal wafer holders 202 disposed around the polygonal wafer holder 2〇2 and forming a predetermined distance from the sides of the polygonal wafer holder 202. a lead 203, a wafer 2〇1 disposed on the polygonal wafer holder 202 to be electrically connected to the plurality of leads 203 by a bright wire 2〇4, and a cover for the polygonal wafer holder 202 and the plurality of leads 203 The sealing gel of the wafer 201 (not shown). The semiconductor package 2 of the present embodiment has a wafer holder 202 of a rectangular shape of 1550 6 201138046, the main principle of which is to chamfer the four corners of the conventional quadrilateral wafer holder, so that the four corners are The corresponding lead 203 can extend toward the wafer 201, thereby shortening the length of the bonding wire 204. Please refer to FIG. 1 and FIG. 2 at the same time. In FIG. 1 , the lead pins 103 corresponding to the four corners of the wafer holder 102 must use the longest bonding wire (for example, using gold wire or copper wire) and the wafer. The bonding pads 1011 are electrically connected. In the semiconductor package of the present invention in FIG. 2, the length of the bonding wire required for the lead pins 203 corresponding to the four corners is shortened by the four corners of the wafer holder 202, and compared with other lead pins. The wire required for the lead pins 203 corresponding to the four corners is no longer the longest wire bond, so the cost of the wire bond can be greatly reduced, and the probability of wire bond offset can be reduced. In a preferred embodiment, as shown in FIG. 2, the semiconductor package 20 having a polygonal wafer holder of the present invention includes a grounding ring 205 which is continuously disposed along the sides of the octagonal wafer holder 202. However, the grounding ring I 205 can still be arranged in a segmented manner, and the grounding ring 205 can be in a symmetrical or asymmetrical shape. In addition, the semiconductor package 20 further includes a support strip 206 for connecting and supporting the octagonal wafer holder 202 and the grounding ring 205. The shape of the octagonal wafer holder 202 may be symmetrical or asymmetrical. In another preferred embodiment, the plurality of leads 203 can form different distances from the sides of the octagonal wafer holder 202 according to the length of the corresponding bonding wires 204. As shown in FIG. 2, the distance between the lead 203 and the wafer holder 202 is denoted as d. However, the distance d can be adjusted according to the length of the bonding wire 204 required by the different guiding pins 203, that is, a certain guiding pin 203 and the wafer. The distance between the seat 202 and its 7 111550 201138046 is the same or different from the distance between the lead and the wafer holder 202, which is completely determined by the design requirements. Referring to Figure 3, there is shown a schematic view of a semiconductor package having a polygonal wafer holder in Figure 2. In order to clearly show the architecture of the semiconductor package of the present invention, the bonding wires are not shown in the figure. As shown, the semiconductor package 30 includes an octagonal wafer holder 302, a plurality of leads 303 disposed around the octagonal wafer holder 302 and forming a predetermined distance from the sides of the octagonal wafer holder 302. a wafer 301 disposed on the octagonal wafer holder, a grounding ring 305 disposed along a side of the octagonal wafer holder 302, and a support for connecting and supporting the octagonal wafer holder 302 and the grounding ring 305 Article 306. Since the distance between the lead 303 corresponding to each side of the wafer holder 302 and the wafer 3〇1 is not large, the length of use of the bonding wire can be shortened. In a preferred embodiment, the wafer 301 can be a polygon corresponding to a polygonal wafer holder. For example, if an octagonal wafer holder 302 is used, the wafer 301 can use an octagonal wafer, and the length of use of the bonding wire can be further shortened. 4A and 4B are schematic views of other specific embodiments of a semiconductor package having a polygonal wafer holder of the present invention. In Fig. 4A, the semiconductor package has a wafer 4, a pentagon wafer holder 402, a ground ring 405 corresponding to the pentode wafer holder 402, and a branch 406 connecting the ground ring 〇5. In FIG. 4B, the semiconductor package has a wafer 4'1', a hexagonal wafer carrier, a corresponding hexagonal wafer holder 402, an interface _405, and a grounding strip 4〇5. 406'. Through the specific embodiments, the design of the wafer holder can be matched with the layout of the wafer 111550 8 201138046 • the on-chip bonding pad, and whether or not to cut the corners of the corners to form a wafer holder of at least five sides. The angle between the at least one side of the polygon=seat and its adjacent side is an obtuse angle. Taking Fig. 4a as an example, the wafer holder forms a beveled edge of all corners on the upper left side, and at least two sides (the oblique side) have an obtuse angle with the adjacent side. g - See Fig. 5 is a schematic view of a further embodiment of a semiconductor package having a polygonal wafer holder of the present invention. As shown in Fig., the semiconductor encapsulating member 50 has a wafer 5 () 1, a twelve-sided wafer holder 5 〇 2, a guide pin $, and a support strip 5 〇 6 (the bonding wires are not shown for the sake of clarity). The design principle of this embodiment is that when the conventional quadrilateral wafer holder is chamfered, the length of the fresh line can be shortened by adjusting the position of the guide pin. However, when a corner is chamfered, two new ones are formed. The angle, and the guide feet near the two new corners may have a longer weld line in the south. If the two new corners are chamfered, the length of the weld line can theoretically be shortened. In other words, when the wafer holder is more multilateral, the total wire length required will be less. Therefore, the total length of the fresh line required for the twelve-sided wafer holder 5〇2 of the present embodiment is the smallest compared to the aforementioned pentagon, hexagonal or octagonal wafer holder. In addition, the present invention further provides a method for fabricating a semiconductor package, the method comprising: providing a polygonal wafer holder having at least five sides; and a plurality of guide legs along the circumference of the multi-sided 曰 曰 , , Forming a predetermined distance from the side of the polygon=seat; placing the wafer on the polygon crystal to electrically connect the bond pads of the wafer to the plurality of conductors through the bonding wire= and coating the polygonal crystal seat with the encapsulant, The plural guides will make the Japanese film. 111550 9 201138046 Included in the second and subsequent examples of the method of manufacturing the semiconductor package of the present invention. 5 arranging the grounding ring continuously or in sections on the side of the wafer-shaped wafer holder to provide a leadframe structure comprising at least five (four) polygonal profiles and 'around the polygonal wafer holder and with the strip holder The sides form a plurality of guide legs of a predetermined distance, and the shape of the polygonal wafer holder may be symmetrical or asymmetrical, and an angle between at least a side of the polygon W seat and an adjacent side thereof is a pure angle. In a preferred embodiment, the leadframe structure includes a grounding ring disposed continuously or in sections along the polygonal wafer holder = side, and the grounding ring can be connected to the branch. Additionally, such a leadframe structure can also include a support strip that connects the polygonal wafer holder. The distance between the solder fillet and the wafer can be shortened by the polygonal lead frame structure to reduce the amount of wire used. As can be seen from the above description, the present invention utilizes a polygonal wafer holder instead of a conventional quadrilateral wafer holder to extend the guide around the wafer holder inwardly, shortening the distance between the lead and the wafer, and thus can be soldered using a shorter technique than conventional techniques. Wires connect the leads to the wafer. Since the amount of use of the bonding wire is reduced, the manufacturing cost of the semiconductor package can be reduced. In addition, the chance of wire bond offsets is reduced. The specific embodiments described above are only used to illustrate the features and functions of the present invention, and are not intended to limit the implementable materials of the present invention. Revelation = the equivalent change and modification of the Valley is still covered by the following patent application. 111550 10 201138046 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural view of a conventional semiconductor package; FIG. 2 is a structural view of a specific embodiment of a semiconductor package having a polygonal wafer holder; 2 is a schematic view of a semiconductor package having a polygonal wafer holder, and FIGS. 4A and 4B are schematic views of other specific embodiments of a semiconductor package having a polygonal wafer holder; and FIG. 5 is a polygonal wafer holder of the present invention. A schematic diagram of yet another embodiment of a semiconductor package. [Major component symbol description] 10 semiconductor package 101, 201, 301, 401, 401', 501 wafer 102 quadrilateral wafer holder 103, 203, 303, 503 lead 104, 204 bonding wire 1011 bonding pad 20, 30' 50 semiconductor Package 202, 302 octagonal wafer holder 205' 305, 405, 405' grounding ring 206, 306, 406, 406', 506 support strip 402 pentagon wafer holder 402, hexagonal wafer holder 502 dodecagonal Wafer holder 11 111550