201137442 六、發明說明： 【發明所屬之技術領域】 本發明有關於一種液晶顯示裝置，尤指一種可避免開機 畫面發生雜訊現象之液晶顯示裝置。 【先前技術】 液晶顯示裝置(Liquid Crystal Display ; LCD)具有外型輕薄、省 電以及低輻射等優點，因此已被廣泛地應用於電腦螢幕、行動電話、 個人數位助理（PDA)、平面電視、以及其他通訊/娛樂設備等電子 產品上。液晶顯示裝置的工作原理係利用改變液晶層兩端的電壓差 來改變液晶層内之液晶分子的排列狀態，據以改變液晶層的透光 性，再配合背光模組所提供的光源以顯示影像。第丨圖為習知液晶 •顯示裝置的示意圖。如第1圖所示，液晶顯示裝置10包含具有複數 畫素PX之晝素陣列單元100、源極驅動器1〇4、閘極驅動器1〇6、 以及閘極脈波調變(Gate Pulse Modulation)單元120。源極驅動器1〇4 係用來提供複數資料訊號至晝素陣列單元1〇〇。閘極驅動器〗〇6係 用來根據高準位閘極訊號調變電壓VGHM與低準位閘極訊號參考 電壓VGL以提供複數閘極訊號至畫素陣列單元1〇〇,而晝素陣列單 το 100即根據複數資料訊號與複數閘極訊號以顯示影像。閘極驅動 器106另可根據重置訊號χ〇Ν對晝素陣列單元1〇〇執行關機殘影 201137442 衰減運作。 問極脈波调變單元！2〇係用來提供高準位閘極訊號調變電壓 VGHM。然而，於液晶顯示裝置1〇開機後之預定時段内，在具波形 削角功能關極脈波調變單元12〇之運作巾，用來提供波形削角功 此之箝位賴可以很快地上昇至高準位並饋人閘極驅鮮，但 此時低準侧極訊齡考賴VGL尚核立王作準位，所以間極驅 動器106無法執行正常邏輯運作，因而產生複數類雜訊⑽ise_Hke) 閘極訊號。又由於此時之重置喊χ〇Ν會致能閘極驅動器1〇6將 所有閘極减同時輸出至晝素陣列單元刚，亦即閘極驅動器應 於開機後之預定時段_產生之複數獅簡極減均會饋入畫素 陣列單元100，如此會導致開機晝面之雜訊現象。 【發明内容】 依據本發明之實施例揭露一種可避免開機晝面發生雜訊現 象之液晶顯示裝置’其包含源極驅動器、閘極驅動器、晝素陣列單 元、以及閘極脈波調變單元。源極驅動器_來提供複數資料訊號。 Ρ甲1極驅動H係肖來根據jij準位卩碰訊號調變電壓以提供複數問極訊 號。畫素_單元電連接於雜驅動H與·，絲根據複 數=貝料sfl號與複數閘極§孔號以顯示影像。閘極脈波調變單元電連接 於閘極驅動n，用來提供高準位閘極織調變電壓。閘極脈波調變 單元包含第-電晶體、第二電晶體、電阻、第三電晶體、以及二極 201137442 體。第—電晶體包含第一端、第二端與間極 知用來輸出高準位間極訊號調變·。第二電晶體包含第 一端與閘極端，其中第一端電連接於第一 雷魅认够 《電曰曰體之第二端，閘極端 端絲去晶體之·端。f_電連接於第二電日日日體之第二 考電位之間。第三電晶體包含第一端、第二端與間極端，其 ㈣一端絲接收箝位電壓，_端電連接於第—電晶體之間極、 &。-極體包含正極端與負極端，其中正極端電連接於第三電晶體 之第二端’負極端電連接於第二電晶體之第二端或第—電晶體之第 二端。在液晶顯示襄置的運作中，第一電晶體、第二電晶體與電阻 係用來根據削角控制訊號與高準位閘極訊號參考電壓以提供高準位 閘極訊號調變電壓，進而根據高準位閘極訊號調變電壓對複數間極 訊號執行波形削角運作，二極體之單向傳輸特性可使波形削角運作 具有電壓箝位魏’第三電晶體侧來根制肖控概號以致能/ 除能電壓箝位功能。 【實施方式】 下文依本發明之液晶顯示裝置特舉實施例配合所附圖式作詳 細說明’但所提供之實酬並不狀限制本發明所涵蓋的範圍。 第2圖為本發明液晶顯示裝置之第一實施例的結構示意圖。如 第2圖所示’液晶顯示裝12()包含具有複數4^ρχ之晝素陣列單 201137442 兀200 L源極驅動益204、閘極驅動器206、電容cg、以及閘極脈 波調，單元220。源極驅動器2()4係用來提供複數資料訊號至晝素 車列單元2〇0 ^極驅動器2〇6係用來根據高準位間極訊號調變電 5 VGHM與低準賴_號參考電壓VGL以提供複數閑極訊號至 素陣列早疋200’而畫素陣列單元·即根據複數資料訊號與複 閘極訊號驅動複數晝素狀以顯示影像。閉極驅動器撕另可根 據重置訊號X⑽對晝素_單元執行關機殘影衰減運作，至 於重置訊號XON的運作_波形係為習知技藝，不再費述。 閘極錢簡單元22G _來提供高準簡極城調變電壓 =HM。間極脈波調變單元现包含第一電晶體现、第二電晶體 料、二極體225、以及第三電晶體250。第一電晶㈣ 曰-4膜電晶體或ρ型場效電晶體，第二電晶體235盘第三f 薄膜電晶體或N型場效電晶體。第-電晶體: 號:老二第一端與閘極端，其中第一端用來接收高準位閘極訊201137442 VI. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which can avoid occurrence of noise in a boot screen. [Prior Art] A liquid crystal display (LCD) has advantages such as slimness, power saving, and low radiation, and has been widely used in computer screens, mobile phones, personal digital assistants (PDAs), and flat televisions. And other electronic products such as communication/entertainment equipment. The working principle of the liquid crystal display device is to change the arrangement state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference between the liquid crystal layers, thereby changing the light transmittance of the liquid crystal layer, and then matching the light source provided by the backlight module to display an image. The figure is a schematic diagram of a conventional liquid crystal display device. As shown in FIG. 1, the liquid crystal display device 10 includes a pixel array unit 100 having a plurality of pixels PX, a source driver 1〇4, a gate driver 1〇6, and a gate pulse modulation (Gate Pulse Modulation). Unit 120. The source driver 1〇4 is used to provide a plurality of data signals to the pixel array unit. The gate driver 〇6 is used to provide a complex gate signal to the pixel array unit 1〇〇 according to the high level gate signal modulation voltage VGHM and the low level gate signal reference voltage VGL, and the pixel array is Το 100 displays images based on complex data signals and complex gate signals. The gate driver 106 can also perform a shutdown operation on the pixel array unit 1 according to the reset signal 2011 201137442 attenuation operation. Ask the pole pulse modulation unit! 2〇 is used to provide high-level gate signal modulation voltage VGHM. However, in a predetermined period of time after the liquid crystal display device 1 is turned on, the operation wiper having the waveform chamfering function is used to provide the waveform chamfering function. Rise to a high level and feed the gate to drive the fresh, but at this time the low-precision side of the age of the test VGL is still the king of the king, so the inter-pole driver 106 can not perform normal logic operation, thus generating complex noise (10)ise_Hke) Gate signal. And because the resetting of the shouting at this time will enable the gate driver 1〇6 to simultaneously output all the gates to the pixel array unit, that is, the gate driver should be in the predetermined period after the power-on_generation The lion's minimal reduction will be fed into the pixel array unit 100, which will cause noise in the boot. SUMMARY OF THE INVENTION In accordance with an embodiment of the present invention, a liquid crystal display device that avoids the occurrence of noise on a turn-on surface includes a source driver, a gate driver, a pixel array unit, and a gate pulse modulation unit. The source driver _ provides a complex data signal. The armor 1 pole drives the H-series to adjust the voltage according to the jij level to provide a complex signal. The pixel_cell is electrically connected to the miscellaneous drive H and ·, and the wire displays the image according to the complex = bedding sfl number and the complex gate § hole number. The gate pulse modulation unit is electrically connected to the gate drive n to provide a high-level gate-polar modulation voltage. The gate pulse modulation unit includes a first transistor, a second transistor, a resistor, a third transistor, and a diode 201137442 body. The first-transistor includes a first end, a second end, and a mutual polarity for outputting a high-level inter-polar signal modulation. The second transistor comprises a first end and a gate terminal, wherein the first end is electrically connected to the first end of the electric body, and the second end of the gate end is removed from the end of the crystal. The f_ is electrically connected between the second test potential of the second electric day and day. The third transistor comprises a first end, a second end and an intermediate end, wherein (4) one end of the wire receives the clamping voltage, and the _ terminal is electrically connected to the inter-electrode between the poles, & The pole body includes a positive end and a negative end, wherein the positive end is electrically connected to the second end of the third transistor. The negative end is electrically connected to the second end of the second transistor or the second end of the first transistor. In the operation of the liquid crystal display device, the first transistor, the second transistor and the resistor are used to provide a high-level gate signal modulation voltage according to the chamfer control signal and the high-level gate signal reference voltage, thereby According to the high-level gate signal modulation voltage, the waveform is chamfered by the inter-polar signal, and the one-way transmission characteristic of the diode can make the waveform chamfering operation have a voltage clamp Wei's third transistor side to root Shaw The control number enables/disables the voltage clamping function. [Embodiment] The following is a detailed description of the preferred embodiments of the liquid crystal display device in accordance with the present invention, and the present invention is not limited to the scope of the present invention. 2 is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention. As shown in Fig. 2, the liquid crystal display device 12 () includes a pixel array with a plurality of 4^ρχ. 201137442 兀200 L source driver benefit 204, gate driver 206, capacitor cg, and gate pulse wave modulation, unit 220. The source driver 2 () 4 is used to provide a complex data signal to the Alien train unit 2 〇 0 ^ pole driver 2 〇 6 is used to adjust the power according to the high level inter-polar signal 5 VGHM and low-rate _ The reference voltage VGL is to provide a plurality of idle signals to the prime array as early as 200', and the pixel array unit drives the plurality of elements according to the complex data signal and the complex gate signal to display the image. The closed-end driver can also perform the shutdown after-image attenuation operation on the pixel_unit according to the reset signal X(10). As for the operation of resetting the signal XON, the waveform is a conventional technique and will not be described. The gate money unit 22G _ to provide high-precision Jianji city modulation voltage = HM. The interpole pulse modulation unit now includes a first transistor, a second transistor, a diode 225, and a third transistor 250. The first electro-crystal (4) 曰-4 film transistor or p-type field effect transistor, the second transistor 235 disk third f-film transistor or N-type field effect transistor. The first transistor: No.: the first end of the second child and the gate terminal, wherein the first end is used to receive the high level gate
Vref ^ 性 一-叫一。〜乐一觸興 之間。第三電晶體250包含第一端、第二端與閘極端 綠1 rGH’閘極制來触㈣控制職vflk，第二端用 間極訊號調變電壓VGHM至閘極驅動器。電容 系電連接於第—電晶體23()之第二端與參考電位财之間。在 -姐施Γ中，參考電位Vref係為接地電位。第二電晶體235包含第 、-端與閘極端，其+第一端電連接於第一電晶體现之第 ;=問，接於第一電晶體23。之閑極端，第二端電連接於 =㈣Rx係電連接於第二電晶體235之第二端與參考電位 rer之間。兹：带曰诚Λ Λ θ人松 其中 201137442 一端用來接收箝位賴vdamp，___ ==二端電連接於二極體225。二極體225包含正 μ㈣議術細25g之第二端， 負極鈿電連接於第一電晶體230之第二端。 第一電晶體230、第二電晶體23s與電阻^組合為波形削角 電路，用來提供高準位閘極訊號調變電壓VGHM，據以對複數閘極 汛號執行波形削角運作。此外，二極體 嵇體225之早向傳輸特性可使波 形削角電路所執行之波形削角運作具有電壓箝位功能。削角控制訊 唬VFLK可用來控制第三電晶體25〇之導通/截止狀態，進而控制箝 位電壓Vdamp饋入二極體225的運作，亦即第三電晶體25〇可根 據削角控制訊號VFLK以致能/除能電壓箝位功能。高準位閘極訊號 參考電壓VGH可經由第-電晶體23〇對電容Cg執行快速充電運 作，使高準位閘極訊號調變電壓VGHM快速上昇至高準位閘極訊號 參考電壓VGH。或者，參考電位Vref可經由第二電晶體235與電 阻Rx對電S Cg執減電運作’從崎低冑麵.職調變電壓 VGHM ’其中電阻κχ係用來控制放電速率。在電容Cg的放電運作 中，第二電晶體250係在導通狀態以致能電壓箝位功能，所以當高 準位閘極訊號調變電壓VGHM下降至箝位電壓Vciamp時，二極體 225即順向導通’據以使高準位閘極訊號調變電壓VGHM大體上保 持在箝位電壓Vciamp直到執行後續充電運作。 在液晶顯示裝置20的運作中，於開機後之預定時段内，削角 201137442 控制5fl號VFLK係保持於第~~狀態，據以截止第三電晶體25〇而除 能電壓箝位功能，所以雖然箝位電壓Vdamp很快地上昇至高準位， 但此時箝位電壓\^1卿無法經由第三電晶體25〇饋入至二極體奶 之正極％，亦即具尚準位之箝位電壓Vclamp在預定時段内無法饋 入至閘極驅動器206，所以閘極驅動器206不會產生複數類雜訊閘 極=號。也就是說，即使重置峨XON在預定時段内致能閘極驅 動器2〇6將所有閘極訊號同時輸出至晝素陣列單元2〇〇,開機畫面 所以第三 之雜訊現象並不會發生。於預定時段後之波形㈣時段内， 削角控制訊號VFLK切換為異於第—狀態之第二狀態，據以導 通第二電晶體而致能電壓箝位功能。在預定時段後，由於削角控 :訊號WLK係在第-狀態與第二狀態之間職性切換，使 第二電晶體25G在截止狀態鱗通狀態之間週期性切換， 電晶體250係週期性除能/致能電壓箝位功能。 第3圖為本發晶顯示裝置之第二實施例的結構示意圖。— 圖所示’液晶顯示裝置3〇包含蚩音睡 2〇4、閘極驅_惠^ 陣列卓凡测、源極痛 f甲動器 206、電容 f σ、LV s 脈…閘極脈波調變單元320。閘才」 ’調變單το 320係、類似於第2圖戶斤干之問 $明不之_脈波機單元220， 要差異在於將二極體225置換為―榀# 1 极㈣3 A s 谀马一極體325。二極體325包含正 柽知與負極端，其中正極端電 3正 極端電連接於第-電曰體體250之第二端，負 參如m H。也就是說，二鋪325之 負極知係電連接於第：電晶體攻與電體5之 顯示襄置3G的運作中，之連接~點。在液晶 田執仃電谷Cg的放電運作時，第三電晶體 201137442 250係在導通狀態以致能電壓箝位功能，當第二電晶體235與電阻 .Rx之連接節關節點下降絲位電壓Vdamp時，三極體325 即順向導通’據以使南準位閘極訊號調變電壓大體上保持在 箝位電壓Vclamp直到執行後續充電運作。除上述關於二極體奶 的運作外’液晶:裝置30之其餘運作係同於液晶顯示裝置2〇， 不再贅述。 φ 帛4圖為本發明液晶顯示裝置之第三實施例的結構示意圖。如 第4圖所示，液晶顯示裝置40包含晝素陣列單元綱、源極驅動器 204閘極驅動器2〇6、電容eg、以及閘極脈波調變單元42〇。閘極 脈波》周變單tl 420係類似於第2圖所示之閘極脈波調變單元22〇， 主要差異在於將第三電晶體25〇置換為第三電晶體45〇，以及另設 置反相器445。反相器祕包含輸入端與輸出端，其中輸入端電連 接於第-電晶體230之閘極端，輸出端電連接於第三電晶體·。 第三電晶體450係為P型薄膜電晶體0型場效電晶體。第三電晶 體450包含第一端、第二端與閘極端，其中第一端用來接收籍位電 壓Vdamp ’閘極端電連接於反相_州之輸出端，第二端電連接於 二極體225之正極端。由反相器445對削角控制訊號執行反 相運作所產生之反相電壓可用來控制第三電晶體450之導通/截止狀 態，進而控制箝位電壓Vclamp饋入二極體225的運作，亦即第三 電晶體450係根據削角控制訊號VFLK之反相電壓以致能/除能電壓 箝位功能。除上述根據削角控制訊號WLK之反相電堡以致能/除能 電壓批位功能的運作外，液晶顯示裝置4〇之其餘運作係同於液晶顯 201137442 示裝置20，不再贅述。 第5圖為本發明液晶顯示裝置之第四實施例的結構示意圖。如 第頂所示，液晶顯示裝置5〇包含晝素陣列單元朋、源極驅朗 204、閑極驅動器206、電容Cg、以及閘極脈波調變單元52〇。閑極 脈波調變單元520係類似於第3圖所示之閘極脈波調變單元32〇， 主要差異在於將第三電晶體250置換為第三電晶體55〇，以及另設 置反相器545。反相器545包含輸入端與輸出端，其中輸入端電連 接於第-電晶體230之閘極端，輸出端電連接於第三電晶體別。 第三電晶體550係為P型薄膜電晶體或p型場效電晶體。第 體550包含第-端、第二端與閘極端，其中第一端 ㈣曰 壓她叫，間極端電連接於反相器⑷之輸出端，第二端電連接^ -極體325之正極端。由反相器地對削角控制訊號執行反 相運作所產生之反相電麼可用來控制第三電晶體之導通纖止狀 態，進而控制箝位電壓Vclamp饋入二極體奶的運作，亦即第三 係根據削角控制訊號VFLK之反相電壓以致能/除能輕 工此。除上述根據削角控制訊號VFLK之反 ==^外，液晶顯示裝置5〇之其餘運作係同 不裝置30，不再贅述。 综上所述，在本發明液晶顯示裝置的運作中， 據肖__停錄人__作，據以除能 贫工月匕’所以雖然箝位電壓很快地上昇至高準位，但具高準 12 201137442 位之籍位電壓在預定時段内並無法饋入至閘極驅動器，而閘極驅動 器也就不會產生複數類雜訊閘極訊號。因此即使用來衰減關機殘影 之重置sfl號在預定時段内致能閘極驅動器將所有閘極訊號同時輪出 至畫素陣列單元，開機晝面之雜訊現象並不會發生。 雖然本發明已以實施例揭露如上，然其並非用以限定本發明， 任何具有本發明所屬技術領域之通常知識者，在不脫離本發明之精 春神和範圍内’當可作各種更動與潤飾，因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為習知液晶顯示裝置的示意圖。 第2圖為本發明液晶顯禾裝置之第一實施例的結構示意圖。 •第3圖為本發明液晶顯示裝置之第二實施例的結構示意圖。 第4圖為本發明液晶顯示裝置之第三實施例的結構示意圖。 第5圖為本發明液晶顯示裝置之第四實施例的結構示意圖。 【主要元件符號說明】 10、20、30、40、50 液晶顯示裝置 100、200 畫素陣列單元 13 201137442 104 、 204 106 ' 206 120、220、320、420、 520 225 ' 325 230 235 445 ' 545 250、450、550 PX RxVref ^ Sex One - called one. ~ Le one touches between. The third transistor 250 includes a first end, a second end, and a gate terminal. The green 1 rGH' gate is made to touch (4) the control vflk, and the second end is modulated by the interpole signal VGHM to the gate driver. The capacitor is electrically connected between the second end of the first transistor 23() and the reference potential. In the sister, the reference potential Vref is the ground potential. The second transistor 235 includes a first end, a - terminal and a gate terminal, and the + first end is electrically connected to the first transistor, and is connected to the first transistor 23. The second end is electrically connected to the (four) Rx system electrically connected between the second end of the second transistor 235 and the reference potential rer. Here: With 曰 Λ Λ θ 人松 where 201137442 one end is used to receive the clamp 赖 vdamp, ___ == two ends are electrically connected to the diode 225. The diode 225 includes a second end of the positive μ (4) thin 25g, and the negative electrode is electrically connected to the second end of the first transistor 230. The first transistor 230, the second transistor 23s and the resistor are combined into a waveform chamfering circuit for providing a high-level gate signal modulation voltage VGHM, and the waveform chamfering operation is performed on the complex gate nickname. In addition, the early transmission characteristic of the diode body 225 allows the waveform chamfering operation performed by the waveform chamfering circuit to have a voltage clamping function. The chamfer control signal VFLK can be used to control the on/off state of the third transistor 25〇, thereby controlling the operation of the clamp voltage Vdamp to be fed into the diode 225, that is, the third transistor 25 can control the signal according to the chamfer angle VFLK enables/disables voltage clamping. The high-level gate signal reference voltage VGH can perform a fast charging operation on the capacitor Cg via the first transistor 23〇, so that the high-level gate signal modulation voltage VGHM rapidly rises to the high-level gate signal reference voltage VGH. Alternatively, the reference potential Vref can be subjected to a power-down operation via the second transistor 235 and the resistor Rx to the electric S Cg. The resistance κχ is used to control the discharge rate. During the discharge operation of the capacitor Cg, the second transistor 250 is in an on state to enable the voltage clamping function, so when the high level gate signal modulation voltage VGHM drops to the clamp voltage Vciamp, the diode 225 is smooth. The guide is configured to maintain the high-level gate signal modulation voltage VGHM substantially at the clamp voltage Vciamp until a subsequent charging operation is performed. In the operation of the liquid crystal display device 20, within a predetermined period of time after the power-on, the chamfering 201137442 controls the VFLK system of the 5fl number to remain in the ~~ state, and according to the third transistor 25〇, the voltage clamping function is disabled, so Although the clamp voltage Vdamp rises rapidly to a high level, at this time, the clamp voltage cannot be fed to the positive electrode % of the diode milk via the third transistor 25〇, that is, the clamp with the standard position. The bit voltage Vclamp cannot be fed to the gate driver 206 for a predetermined period of time, so the gate driver 206 does not generate a complex type of noise gate = number. That is to say, even if the reset 峨XON enables the gate driver 2〇6 to simultaneously output all the gate signals to the pixel array unit 2 within a predetermined period of time, the third noise phenomenon does not occur at the startup screen. . During the waveform (four) period after the predetermined period of time, the chamfer control signal VFLK is switched to a second state different from the first state, and the voltage clamping function is enabled by turning on the second transistor. After the predetermined period of time, due to the chamfering control: the signal WLK is switched between the first state and the second state, so that the second transistor 25G is periodically switched between the off-state states, and the transistor 250 is cycled. Scaling/enable voltage clamping function. FIG. 3 is a schematic structural view of a second embodiment of the crystal display device. — The picture shows 'Liquid crystal display device 3〇 contains 蚩 sound sleep 2〇4, gate drive _惠^ array Zhuo Fan measurement, source pain f-armor 206, capacitance f σ, LV s pulse... gate pulse wave Modulation unit 320.闸才" 'Transformation single το 320 series, similar to the second figure of the household 问 $ $ 明 _ 脉 脉 脉 脉 脉 脉 脉 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Hummer a polar body 325. The diode 325 includes a positive terminal and a negative terminal, wherein the positive terminal 3 is electrically connected to the second end of the first body body 250, and the negative electrode is m h . That is to say, the negative electrode of the second shop 325 is electrically connected to the operation of the third transistor and the display device 3G of the electric body 5, and is connected to the point. When the liquid crystal field performs the discharge operation of the electric valley Cg, the third transistor 201137442 250 is in an on state to enable the voltage clamping function, and when the second transistor 235 and the resistor. Rx are connected, the joint point is lowered by the wire voltage Vdamp. At the same time, the triode 325 is forward-passed so that the south-level gate signal modulation voltage is substantially maintained at the clamp voltage Vclamp until a subsequent charging operation is performed. Except for the above-mentioned operation of the diode milk, the liquid crystal: the rest of the operation of the device 30 is the same as that of the liquid crystal display device 2, and will not be described again. The φ 帛 4 diagram is a schematic structural view of a third embodiment of the liquid crystal display device of the present invention. As shown in Fig. 4, the liquid crystal display device 40 includes a pixel array unit, a source driver 204 gate driver 2〇6, a capacitor eg, and a gate pulse modulation unit 42A. The gate pulse wave is a similar to the gate pulse modulation unit 22〇 shown in Fig. 2, the main difference being that the third transistor 25〇 is replaced by the third transistor 45〇, and another An inverter 445 is provided. The inverter comprises an input terminal and an output terminal, wherein the input terminal is electrically connected to the gate terminal of the first transistor 230, and the output terminal is electrically connected to the third transistor. The third transistor 450 is a P-type thin film transistor type 0 field effect transistor. The third transistor 450 includes a first end, a second end and a gate terminal, wherein the first end is used to receive the home voltage Vdamp 'the gate terminal is electrically connected to the output end of the inversion state, and the second end is electrically connected to the second pole The positive end of body 225. The inverting voltage generated by the inverting operation of the chamfering control signal by the inverter 445 can be used to control the on/off state of the third transistor 450, thereby controlling the operation of the clamping voltage Vclamp to feed the diode 225. That is, the third transistor 450 is based on the inversion voltage of the chamfer control signal VFLK to enable/disable the voltage clamping function. The operation of the liquid crystal display device 4 is the same as that of the LCD display device 20, except for the operation of the inverting electric bunker according to the chamfering control signal WLK. Fig. 5 is a schematic structural view showing a fourth embodiment of the liquid crystal display device of the present invention. As shown in the top, the liquid crystal display device 5 includes a pixel array unit, a source drive 204, a idle driver 206, a capacitor Cg, and a gate pulse modulation unit 52A. The idle pole pulse modulation unit 520 is similar to the gate pulse modulation unit 32〇 shown in FIG. 3, and the main difference is that the third transistor 250 is replaced with the third transistor 55〇, and another reverse phase is set. 545. The inverter 545 includes an input terminal and an output terminal, wherein the input terminal is electrically connected to the gate terminal of the first transistor 230, and the output terminal is electrically connected to the third transistor. The third transistor 550 is a P-type thin film transistor or a p-type field effect transistor. The first body 550 includes a first end, a second end and a gate terminal, wherein the first end (four) is pressed against her, and the first end is electrically connected to the output end of the inverter (4), and the second end is electrically connected to the positive electrode 325. extreme. The inverting current generated by the inverting operation of the chamfering control signal by the inverter can be used to control the conduction state of the third transistor, thereby controlling the operation of the clamping voltage Vclamp to feed the diode milk. That is, the third system controls the inversion voltage according to the chamfering control signal VFLK to enable/disable the light. Except for the above-mentioned inverse of the chamfering control signal VFLK ==^, the rest of the operation of the liquid crystal display device 5 is not the same as the device 30, and will not be described again. In summary, in the operation of the liquid crystal display device of the present invention, according to the Xiao _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The base voltage of Micro Motion 12 201137442 is not fed to the gate driver for a predetermined period of time, and the gate driver does not generate a plurality of types of noise gate signals. Therefore, even if the reset sfl number used to attenuate the afterimage of the shutdown enables the gate driver to rotate all the gate signals to the pixel array unit at the same time within a predetermined period of time, the noise phenomenon at the startup surface does not occur. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any person having ordinary knowledge in the art to which the present invention pertains can be made to various changes without departing from the scope of the present invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a conventional liquid crystal display device. Fig. 2 is a schematic view showing the structure of a first embodiment of the liquid crystal display device of the present invention. Figure 3 is a schematic view showing the structure of a second embodiment of the liquid crystal display device of the present invention. Fig. 4 is a view showing the structure of a third embodiment of the liquid crystal display device of the present invention. Fig. 5 is a schematic structural view showing a fourth embodiment of the liquid crystal display device of the present invention. [Description of main component symbols] 10, 20, 30, 40, 50 Liquid crystal display device 100, 200 pixel array unit 13 201137442 104 , 204 106 ' 206 120, 220, 320, 420, 520 225 ' 325 230 235 445 ' 545 250, 450, 550 PX Rx
VclampVclamp
VFLKVFLK
VGHVGH
VGHMVGHM
VGLVGL
Vref XON 源極驅動器 閘極驅動器 閘極脈波調變單元 二極體 第一電晶體 第二電晶體 反相器 第三電晶體 晝素 電阻 箝位電壓 削角控制訊號 高準位閘極訊號參考電壓 高準位閘極訊號調變電壓 低準位閘極訊號參考電壓 參考電位 重置訊號Vref XON source driver gate driver gate pulse modulation unit diode first transistor second transistor inverter third transistor pixel resistance clamp voltage chamfer control signal high level gate signal reference Voltage high level gate signal modulation voltage low level gate signal reference voltage reference potential reset signal
1414