201133936 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種基板結構以及應用此種基板結構戶斤 製成的一種發光二極體裝置，尤其是關於一種具有半導體 奈米結構的發光二極體裝置及其基板结構的製作方法。 【先前技術】 半導體奈米結構於形成奈米柱狀結構時，由於結構本 身側向成長時可以釋放結構本身的應力並減少缺陷產生的 特性，於藍寶石基板（Sapphire)或矽（Silicon)基板上形成氮 化鎵(Gallium Nitride，GaN)半導體奈米柱結構已成為—種 引人關注的技術。於半導體奈米結構上成長氮化鎵材料可 達到更高的蟲晶結構品質。然而，就製造發光二極體結構 的角度而言’較傾向於平面之上成長發光二極體結構的半 導體磊晶層。因此’如何在氮化鎵半導體奈米結構上進行 癒合成長（coalescence overgrowth)的技術成為一個重要的 議題。氮化鎵半導體奈米結構可藉由分子束磊晶法(MBE) 及金屬有機化學氣相沉積法（MOCVD)搭配自我組織成 長、於選擇性光罩上進行再成長、或催化劑輔助成長等方 式形成。 為了以金屬有機化學氣相沉積法形成半導體奈米結 201133936 構’一般會搭配圖案化成長。藉由金屬有機化學氣相沉積 機台以干涉微影技術(interferometric lithography)的方式圖 案化形成規律排列地氮化鎵奈米結構已經實驗證明為可 仃。此外’亦可透過分子束▲晶法於半導體奈*結構成長 後進行側向再成長的結構。另外’可”基板上透過分子 =晶法自我組織形成半導體奈米結構後再以金屬有機化 干氣相沉積法進行㈣減長。“，於這些技術中，再 成長層的品質仍然需要進一步的改善。 【發明内容】 一★本發明提供一種發光二極體裳置，包含一基板，具有 -第-成長表面與一相對應於第一成長表面的一底面一 介電層’設置於第-成長表面上，具有複數開口 ；複數半 導體奈米結構，形成於基板上並突出於上述複數開口；一 半導體層’形成於上述半導體奈米結構上，且有實質平行 於底面的-第二成長表面；以及1光二極體結構，、形成 於第二成長表面；其中，至少—開D具有—第—直徑小於 250奈米，一奈米結構相對應於上述至少一開口，且具有 大於第一直徑的一第二直徑。 本發明另-方面在提供-種基板結構的形成方法，包 含提供-基板’具有-第-絲表面；形成—介電層於第 5 201133936 一成長表面上，具有複數開口；形成一半導體材料於第一 成長表面上的複數開口内；以及以脈衝成長模式形成複數 半導體奈米柱於半導體材料上並突出於上述複數開口；其 中，脈衝成長模式的成長溫度介於850。(：與950°C之間。 【實施方式】 依本發明之一貫施例’包含提供一成長發光二極體的 成長基板’其中成長基板之材質係可包含但不限於鍺 (germanium, Ge)、珅化鎵(gallium arsenide，GaAs)、鱗化銦 (indium phosphide, InP)、藍寶石（sapphire)、碳化矽（silicon carbide)、石夕（silicon)、氧化裡铭（lithium aluminum oxide， LiAl〇2)、氧化鋅（zinc oxide, ZnO)、氮化鎵(gallium nitride， GaN)、氮化紹（aluminum nitride)等等。 如圖1所示，欲形成如圖中所示，於氮化鎵模板2上 形成具有半導體奈米柱5的半導體奈米結構，其製作過程 如下.首先’於藍寶石基板1的c平面上先形成一氮化蘇 模板2。其中，形成氮化鎵模板2包含先以530°C的成長溫 度成長一層高約40奈米的氮化鎵成核層（圖未示），再以 1050°C的成長溫度成長一層厚度約2微米（μηι)的氮化鎵薄 膜緩衝層201，接著，再以300°C的成長溫度藉由電漿輔助 式化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)的方式沉積生長一層厚度約80奈米之 6 201133936 二氧化矽光罩介電層203。除了二氧化矽之外，光罩介電 層203也可以採用例如氮化矽（SiNx)、氧化鋁(Al2〇3)等其 他材料組成。 接著，藉由奈米壓印黃光技術(nanoimprint lithography) 於二氧化矽光罩介電層203中形成以六角形排列的複數個 直徑約250奈米且間距約500奈米（兩最近開口的中心距離) 的圓形開口 205。其中圓形開口 205的形狀並不限於圓形， 而單一光罩上的開口亦不以單一相同形狀為限，可由複數 不同形狀的開口所構成。 接著’於金屬有機化學氣相沉積法(M0CVD)成長製程 開始時’設定製程溫度為1〇5〇。〇，成長系統腔體壓力設定 為1〇〇陶爾（ton·)，而V族/E[族比值（氨氣氣體(Nh3，五族 元素）的莫耳濃度與三甲基鎵(trimethylgallium，TMGa，三 族元素）氣體的莫耳濃度比值）設定為11〇〇。 上述成長製程進行五秒鐘之後’以非脈衝模式同時注 入三甲基鎵氣體1000〇 SCCM(SCCM代表在標準溫度與壓 力（stp)條件下每分鐘立方公分的流量單位)及氨氣氣體15 SCCM ’藉以形成一薄層的氮化鎵基底層（圖未示）。最後， 、長模式由非脈衝模式轉換為脈衝模式’即藉由調控注入 成長氣體的開關以交替注入三甲基鎵氣體及氨氣氣體的方 ^成半‘體奈料主5。上述的氣體交錯注人的脈衝成長 模式循環其步驟細節如下述及圖2所示： 201133936 [步驟一]:氨氣氣體關閉’三甲基鎵氣體關閉’ tl = l5秒； [步驟二]:氨氣氣體開啟，三甲基鎵氣體關閉’ t2=l5秒， 氨氣氣體流量=2500 SCCM ; [步驟三]:氨氣氣體關閉，三甲基鎵氣體關閉，t3 = l5秒； [步驟四]:氨氣氣體關閉’三曱基鎵氣體開啟，t4=l5秒， 三甲基鎵氣體流量=12 SCCM。 根據上述的成長條件’以下分別於脈衝成長模式中控 制四種不同成長溫度，包含以850。〇871。〇925。(：及95〇。(： 分別進行成長。圖3A至3D顯示分別透過上述不同成長溫 度生成六角形排列的氮化鎵半導體奈米柱5基板的掃插式 電子顯微鏡上視圖。如圖中所示，當脈衝成長模式成長溫 度較低(如圖3A所示，成長溫度低於850。〇時，半導體奈 米柱5的形狀變得較低且較寬，且{ 10-11 }傾斜面301變 得較明顯° (10-11}傾斜面301為氮化鎵晶體結構的一個 成長晶面’傾斜面301會抑制半導體奈米柱5向上成長並 降低基板本身的品質及均勻性。當脈衝成長模式成長溫度 婕咼（如圖所示，成長溫度高於850。〇時，半導體奈米 柱5的成長表面（頂面）3〇3變得較平，而半導體奈米柱$也 變得幸又長。因此，半導體奈米柱5的結構品質也變得較好。 f而丄當脈衝成長模式成長溫度過高(如圖3D所示，成長 义门於95〇C)時’半導體奈米柱5會再次變得較短且較 8 201133936 寬。 當脈衝成長模式成長溫度低於85(TC時，流動氣體中鎵 元素的表面遷移率降低，也就是說，可移動至半導體奈米 柱5成長表面（頂面）3〇3的鎵元素含量減少並導致 {lo-ii}傾斜面301的生成，而傾斜面3〇1會抑制半導體 奈米柱5的向上成長。當脈衝成長模式成長溫度上升時， 流動氣體中鎵元素的表面遷移率上升，也就是說，鎵元素 移動至半導體奈米柱5成長表面（頂面）3〇3的機率上升，存 在於二氧切光罩介㈣2〇3上_元素被半導體奈米柱 5側壁捕捉的機會下降(大量的鎵元素被半導體奈米柱$的 側壁捕捉會使半導體奈米柱5的寬度變寬），因此半導體奈 米柱5長度變錢具有平坦喊絲面（頂面_。然而: 當脈衝成長模式成長溫度過高(如圖3D所示，成長溫度高 於950 C)時’氮化鎵會產生分解。因此，根據本實驗結果 所示，半導體奈妹5較佳的成長條件為在_成長模式 中控制成長溫度在85〇。(：與950T：之間。 此外，無氣體注入步驟(如上述氣體交錯注入的脈衝成 長模式循環其步驟細節中步驟一與步驟三）的間隔時間（如 圖2中U及t3)長短亦被嘗試調整。其中，間隔時間分別 被控：為3秒、9秒、15秒、及24秒。如圖4A至w所 不，當延長無氣體注入步驟的間隔時間，半導體奈米枉5 的成長面自丨10-11}傾斜面301改變為平坦的頂面。在此 9 201133936 合& 減乂間隔時間代表減少鎵元素的表面擴散長度， 二每成ί 1〇_11丨傾斜面3G1的生成並抑制半導體奈米柱5 ;成長因此，根據實驗結果所示，半導體奈米柱5較 ^的成長條件為控制無氣體注人步驟的間隔時間長於b 私此外’由於半導體奈米柱5的成長溫度較高(於脈衝成 長^約8耽至㈣t)㈣使氮倾結财生分解。 因此’控制無氣體注人步驟的間隔時間 小於的秒)以避免生成的半導趙奈米柱5分解。長因(== f本實驗結果所示，半導财錄5較佳的成長條件為控 制無氣體注入步驟的間隔時間在15秒與6〇秒之間。 如圖5所示，圖5顯示一氮化鎵半導體奈米結構5底 部的橫切面圖。由时所見，二氧切光罩介電層（厚度約 8〇奈米）㈣口兩側因製程特性而具有傾斜的側壁，在此定 義光罩介電層開口（h〇le)的尺寸為側壁的底部，為⑽奈米 (如圖5中所標示）；而生成的半導體奈米結構的寬度則因 為側向成長的因素而略大於開口的尺寸(3〇〇奈米）。 在形成半導體奈米結構5後，進行癒合再成長的步 驟。腔體的壓力及V族/瓜族比值分別更改為陶爾（㈣ 及3900,而成長溫度則維持在i㈣。c。三甲基鎵 氣氣體的連續流量分別控制在每分鐘35微莫耳/('3^ μηιοΐ/min)及l500 SCCM。在這樣的成長條件之下成長速 率約為每小時1.3微米（1.3 μηι/hour)。因此，如圖6所示\ 201133936 約90分鐘崎合再成長的步㈣會生成約2微米的再成長 層6。 藉由比較不同的二氧化石夕光罩介電層的開口尺寸及間 距，可觀察生長於半導體奈米結構5上方療合再成長層的 品質，包含結構内部穿隨缺陷的生成行為。以下分別比較 四種具有不同二氧化石夕光罩介電層開口尺寸的半導體奈米 結構及氮化鎵模板2。其中，模板2為透過與上述相向的 方法製成。首先，於藍寶石基板1的c平面上先形成一層 厚度約2微米（μηι)的氮化鎵薄膜緩衝層2〇1，接著，藉由 奈米壓印貫光技術(nanoimprint lithography)於氮化鎵薄膜 缓衝層201上厚度約8〇奈米的二氧化石夕光罩介電層2〇3的 内部形成複數個六角形排列的開口 205。其中，開口 205 的直徑分別包含250奈米、3〇〇奈米、45〇奈米、及6〇0奈 米。而相對應開口 205尺寸的相鄰開口間距則分別為5〇〇 奈米、600奈米、900奈米、及12〇〇奈米，如圖7A至7Ό 所示’分別依序被定義為樣品A、B、c、D。此外，依據 樣品A-D成長癒合再成長層的結構則分別被相對定義為樣 品 AO-DO。 圖8A與8B分別顯示不同樣品歸一化光致發光強度對 溫度的關係圖。在室溫下歸一化整合強度對凯氏溫度1 〇度 下歸一化整合強度的比值可視為内部量子效率（internal quantum efficiency，IQE)的表現’與樣品中的缺陷密度相 11 5 201133936 關。如圖8A與8B所示，分別為半導體奈米結構樣品(Μ) 與再成長層樣品（AO-DO)的歸一化光致發光強度對溫度的 關係圖。其中，每張圖並分別與沒有成長半導體奈米結構 的氮化鎵模板樣品E進行比較。 由圖中所示，不論在半導體奈米結構樣品（A_D)或再成 長層樣品(AO-DO)的關係圖中，當半導體奈米結構的尺寸 變大時’内部量子效率(I(jE)會下降。在所有的半導體奈米 結構樣品(A-D)或再成長層樣品(AO-DO)中，其内部量子效 率（IQE)的值皆高於無成長半導體奈米結構的氮化鎵模板 結構（1.1%) ’亦即半導體奈米結構及其接續成長的癒合再 成長層皆具有較好的磊晶品質。並且，在所有尺寸的半導 體奈米結構中，其癒合再成長樣品的内部量子效率皆比其 相對應同尺寸的半導體奈米結構樣品的内部量子效率低。 換句話說，進行癒合再成長時，新的缺陷會再度生成。當 開口尺寸為250奈米時，半導體奈米結構樣品a的内部量 子效率為9.9%，為氮化鎵模板樣品e的九倍，而其相對應 的癒合再成長層樣品AO的内部量子效率為6.7%，則大約 為氮化鎵模板樣品E的六倍。 接著，如圖9 A與9B所示，在品質經過改良且不同尺 寸癒合再成長樣品氮化鎵模板2的頂面上，分別製成具有 氮化鎵銦與氮化鎵(InGaN/GaN)的複數量子井結構100以 及量子井發光二極體結構200，用以比較不同尺寸大小對 12 201133936 於發光效率的影響。如圖9A所示，包含五對交替重疊配 置的量子井層與量子能障層所組成的複數量子井結構7 (multiple quantum well，MQW)成長於氮化鎵模板2之上。 在其中一個較佳的實施例之中，這五對交替重疊配置的結 構分別包含以675 C成長溫度成長具有厚度3奈米的氮化 鎵銦量子井層以及以850。(：成長溫度成長具有厚纟15奈求 的氮化鎵直子能障層。成長量子井發光二極體結構2〇〇於 具有1微米厚度的半導體奈米結構5上時，其步驟包含依 序成長一厚度1微米的無摻雜氮化鎵層8、以溫度1〇5〇〇c 成長一厚度4微米具有矽摻雜的n型氮化鎵層9、成長如 月’J述五對父替重疊配置的量子井層與量子能障層所組成的 複數量子井結構7、以及以93(TC成長一厚度120奈米的Ρ 型氮化鎵層10。 在製作具有不同主放光波長的發光二極體結構2〇〇 時’成長複數量子井結構7的溫度也會不同。舉例來說， 成長藍光(綠光)發光二極體結構200時，成長厚度3奈米 的氮化鎵銦量子井層以及厚度15奈米的氮化鎵量子能障 層的溫度分別為715(675)。(：以及850(850) °C，分別可產生 具有約460(約520)奈米的主放光波長，如圖9B所示。除 此之外，這些結構的成長基板表面都可以被進一步的粗化 以達到增加光萃取效率的效果。 圖10A顯示的是建置在分別具有250、300、450、600 13 3 201133936 奈米等不同開口直徑半導體奈米結構基板上的複數量子井 結構100的光致發光強度對溫度的關係圖。為方便比較， 成長於不具半導體奈米結構氮化鎵模板的複數量子井結構 亦被製作為參考基準。由實驗的結果可定義，在凱氏溫度 300度下整合光致發光強度對於凱氏溫度1〇度下整合光致 發光強度的比值可視為内部量子效率（internai quantum efficiency ’ IQE)的表現’對應於半導體奈米結構基板開口 直徑250、300、450、600奈米的複數量子井結構1〇〇其内 部量子效率分別為21.2%、19.0%、16_5%、及15.3%。其 中，所有的内部量子效率皆高於參考基準的12.4%。此結 果顯示藉由癒合再成長於具有半導體奈米結構的結構可以 有效地減少線差排（threading dislocation)密度並增加蟲晶 結構的品質’而較佳品質的癒合再成長結構則可以使生成 於癒合再成長層上方的量子井結構具有較高的發光強度。 圖10B顯示的是生成於具有3〇〇、450、600奈米等不 同開口直徑半導體奈米結構基板上的發光二極體結構200 其光致發光強度對溫度的關係圖。同樣地，成長於不具半 導體奈米結構氮化嫁模板的發光二極體結構亦被製作為參 考基準。在本實驗中，對應於半導體奈米結構基板開口直 徑300、450、600奈米的發光二極體結構200其標準化的 内部量子效率分別為49.2%、36.6%、及19.2%。相較於參 考基準具有20.1%的的内部量子效率，我們可以發現，除 了開口直徑為600奈米的結構之外，其餘發光二極體結構 201133936 的放光效率皆有增強。因此，透過具有較小開口直徑的介 電層光罩結構所形成的半導體奈米結構基板，其上方形成 的發光二極體結構具有較佳的效率。 圖10C顯示對應於半導體奈米結構基板開口直徑 300、450、600奈米的不同發光二極體結構2〇〇 (Light-enutting Diode，LED)結構電致發光強度對注入電流 (Z-/ curves)的關係圖。由實驗結果，我們可以發現，當使 用具有半導體奈米結構的基板癒合再成長的模板製作發光 二極體結構時，可以獲得較佳的發光二極體結構輸出強 度。當注入電流為60毫安培(mA)時，具有300奈米開口直 徑的發光二極體結構可以得到比基板中無半導體奈米結構 的參考基準高出約兩倍的輸出強度。 以發光一極體結構為例，結構所產生的放光光譜性質 可以藉由調整結構中單一層或複數層材料的物理或化學性 質來達成。其中’一般常見的材料為磷化鋁鎵銦(AlGalnP) 系列材料、氮化鋁鎵銦(AlGalnN)系列材料、氧化鋅（ZnO) 系列材料等等。而活性層的結構亦可以依據發光二極體結 構的差異而不同，如單異質結構（single heterostructure， SH)、雙異質結構(double heterostructure，DH)、雙層雙異 質結構（double-side double heterostructure，DDH)、或複數 量子井結構(multiple quantum well，MQW)。此外，除了上 述調整成長溫度的方式，發光二極體結構主放光波長的長 15 201133936 短還可以藉由調整 發光二極體結構本身量子井層與量子能 早層的對數來達成。本發明中半導 礦結構皆 狀並不受限於實施例所述，凡可構的材質與形 可使用。 21凡了構成/、角纖維鋅 並非用 本發明所列舉之各實施例僅用以說明本發明， 【圖式簡單說明】 =為—示意圖’顯示—上方具有複數半導體奈米結構的 圖2為一代表程序，包含採用本發 式形成複數半導體奈米結構及/或一半 的製作程序； +導體奈未結構陣列 =3A’3D為掃描式電子顯微鏡影像圖，分购示透過 2溫度生成的半導體奈米結構基板的上視圖；〇 淨化^時為子顯微鏡影像圖，分別顯示透過不同 圖5 +導體奈米結構基板的上視圖； 米結導體奈 圖6為一示意圖，顯示-上方具有複吻體奈米結構以 201133936 及一癒合再成長層的基板； 圖7A-7D為掃描式電子顯微鏡影像圖，分別顯示具有不同 開口尺寸的二氧化矽介電層結構的上視圖； 圖8A-8B為圖表，分別顯示不同樣品歸一化光致發光強度 對溫度的關係圖； 圖9A為一示意圖，顯示一内部具有半導體奈米結構的複 數量子井結構(multiple quantum well, MQW); 圖9A為一示意圖，顯示一内部具有半導體奈米結構的複 數量子井（multiple quantum well，MQW)發光二極體 (Light-emitting Diode，LED)結構； 圖10A為一圖表，顯示不同量子井結構(quantum well，QW) 光致發光強度對溫度的關係圖； 圖10B為一圖表，顯示不同發光二極體（Light-emitting Diode，LED)結構光致發光強度對溫度的關係圖； 圖10C為一圖表，顯示不同發光二極體（Light-emitting Diode, LED)結構電致發光強度對注入電流的關係圖。 17 5 201133936 【主要元件符號說明】 1 :基板； 2:氮化鎵模板； 5:半導體奈米柱； 6 :再成長層； 7:複數量子井結構； 8 :中性氮化鎵(u-GaN)層； 9 : η型氮化鎵(n-GaN)層； 10 : P型氮化鎵(p-GaN)層； 100 ： 複數量子井結構； 200 ： 發光二極體結構； 201 ： 氮化鎵薄膜層； 203 ： 二氧化矽介電層； 205 ： 圓形開口； 301 ： 傾斜面； 303 ： 成長表面。 18201133936 VI. Description of the Invention: [Technical Field] The present invention relates to a substrate structure and a light-emitting diode device manufactured by using such a substrate structure, and more particularly to a light-emitting diode having a semiconductor nanostructure A polar body device and a method of fabricating the same. [Prior Art] When forming a nano-columnar structure, the semiconductor nanostructure can release the stress of the structure itself and reduce the characteristics of defects due to the lateral growth of the structure itself, on a sapphire substrate or a sapphire substrate. The formation of a Gallium Nitride (GaN) semiconductor nanocolumn structure has become a attracting technology. The growth of gallium nitride material on the semiconductor nanostructure can achieve a higher quality of the insect crystal structure. However, in terms of fabricating the structure of the light-emitting diode, the semiconductor epitaxial layer of the light-emitting diode structure is grown on the plane. Therefore, the technology of how to perform coalescence overgrowth on a GaN semiconductor nanostructure has become an important issue. The GaN semiconductor nanostructure can be self-organized by molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD), re-growth on a selective mask, or catalyst-assisted growth. form. In order to form a semiconductor nano-junction by metal organic chemical vapor deposition, the structure will generally grow with patterning. The formation of a regularly arranged GaN nanostructure by means of an intermetallic spectroscopic lithography by a metal organic chemical vapor deposition machine has been experimentally proved to be measurable. In addition, it is also possible to carry out lateral re-growth after growth of the semiconductor nep* structure by the molecular beam ▲ crystal method. On the other hand, the semiconductor substrate can be self-organized by molecular = crystallography to form a semiconductor nanostructure, and then subjected to metal organic dry vapor deposition (4) to reduce the length. "In these technologies, the quality of the re-grown layer still needs further improve. SUMMARY OF THE INVENTION The present invention provides a light-emitting diode skirt comprising a substrate having a -first-growth surface and a bottom surface-dielectric layer corresponding to the first growth surface disposed on the first growth surface And having a plurality of openings; a plurality of semiconductor nanostructures formed on the substrate and protruding from the plurality of openings; a semiconductor layer 'formed on the semiconductor nanostructure and having a second growth surface substantially parallel to the bottom surface; a photodiode structure formed on the second growth surface; wherein, at least - D has a - first diameter of less than 250 nm, a nanostructure corresponding to the at least one opening, and having a larger than the first diameter Second diameter. A further aspect of the present invention provides a method of forming a substrate structure comprising: providing a substrate having a surface of a --filament; forming a dielectric layer on a growing surface of 5201133936 having a plurality of openings; forming a semiconductor material a plurality of semiconductor nano-pillars on the first growth surface; and a plurality of semiconductor nano-pillars on the semiconductor material and protruding from the plurality of openings; wherein the pulse growth mode has a growth temperature of 850. (: Between 950 ° C and 950 ° C. [Embodiment] A consistent embodiment of the present invention includes a growth substrate that provides a growth light-emitting diode. The material of the growth substrate may include, but is not limited to, germanium (Ge). , gallium arsenide (GaAs), indium phosphide (InP), sapphire, silicon carbide, silicon, lithium aluminum oxide (LiAl〇2) ), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride, etc. As shown in Figure 1, to form a gallium nitride template as shown in the figure Forming a semiconductor nanostructure having a semiconductor nanocolumn 5 on the second surface, the fabrication process is as follows. First, a nitridium template 2 is formed on the c-plane of the sapphire substrate 1. The gallium nitride template 2 is formed first. A GaN nucleation layer (not shown) with a height of about 40 nm is grown at a growth temperature of 530 ° C, and a gallium nitride thin film buffer layer having a thickness of about 2 μm is grown at a growth temperature of 1050 ° C. 201, and then, by the growth temperature of 300 ° C by A plasma-assisted chemical vapor deposition (PECVD) method is used to deposit a 6201133936 cerium oxide photomask dielectric layer 203 with a thickness of about 80 nm. In addition to cerium oxide, the mask is introduced. The electric layer 203 may also be composed of other materials such as tantalum nitride (SiNx), aluminum oxide (Al2〇3), etc. Next, the nano-imprint lithography is applied to the ceria photomask dielectric layer 203 by nanoimprint lithography. Forming a plurality of circular openings 205 having a diameter of about 250 nm and a pitch of about 500 nm (the center distance of the two nearest openings) arranged in a hexagonal shape. The shape of the circular opening 205 is not limited to a circular shape, but a single light The opening on the cover is not limited to a single identical shape, and may be formed by a plurality of openings of different shapes. Next, 'the process temperature is set to 1〇5〇 at the beginning of the metal organic chemical vapor deposition (M0CVD) growth process. The growth system cavity pressure is set to 1 Torr (ton·), while the V group/E [community ratio (ammonia gas (Nh3, Group 5) molar concentration and trimethylgallium (TMGa) ,three The elemental gas molar concentration ratio is set to 11 〇〇. After the above growth process is carried out for five seconds, 'three-methyl gallium gas is injected simultaneously in a non-pulse mode 1000 〇 SCCM (SCCM stands for standard temperature and pressure (stp) conditions The flow unit of cubic centimeters per minute) and the ammonia gas 15 SCCM 'by forming a thin layer of gallium nitride base layer (not shown). Finally, the long mode is switched from the non-pulse mode to the pulse mode ‘that is, by regulating the switch for injecting the growth gas to alternately inject the trimethylgallium gas and the ammonia gas into a half-body. The above-mentioned gas interleaved pulse growth mode cycle details of the steps are as follows and shown in Figure 2: 201133936 [Step 1]: Ammonia gas off 'Trimethyl gallium gas off' tl = l5 seconds; [Step 2]: The ammonia gas is turned on, the trimethylgallium gas is turned off 't2=l5 seconds, the ammonia gas flow rate is 2500 SCCM; [Step 3]: the ammonia gas is turned off, the trimethylgallium gas is turned off, t3 = l5 seconds; [Step 4 ]: Ammonia gas off 'Triyl-based gallium gas is turned on, t4 = l5 seconds, trimethyl gallium gas flow = 12 SCCM. According to the above growth conditions, the following four different growth temperatures are controlled in the pulse growth mode, respectively, including 850. 〇871. 〇 925. (: and 95〇. (: The growth is performed separately. Figures 3A to 3D show the top view of the scanning electron microscope of the gallium nitride semiconductor nanopillar 5 substrate which is hexagonally arranged by the above different growth temperatures, respectively. It is shown that when the pulse growth mode has a low growth temperature (as shown in FIG. 3A, when the growth temperature is lower than 850 Å, the shape of the semiconductor nano-pillar 5 becomes lower and wider, and the { 10-11 } inclined surface 301 It becomes more obvious. (10-11} The inclined surface 301 is a growth plane of the gallium nitride crystal structure. The inclined surface 301 suppresses the growth of the semiconductor nano-pillar 5 and reduces the quality and uniformity of the substrate itself. Mode growth temperature 婕咼 (As shown in the figure, the growth temperature is higher than 850. When 〇, the growth surface (top surface) of the semiconductor nanocolumn 5 becomes 3 〇 3, and the semiconductor nano column $ is also fortunate. Therefore, the structural quality of the semiconductor nanocolumn 5 is also better. f While the pulse growth mode growth temperature is too high (as shown in Figure 3D, the growth of the door at 95 ° C) 'semiconductor nano Column 5 will again become shorter and wider than 8 201133936. When the mode growth temperature is lower than 85 (TC, the surface mobility of the gallium element in the flowing gas is lowered, that is, the gallium element content which can be moved to the growth surface (top surface) of the semiconductor nanocolumn 5 is reduced by 3〇3 and causes { Lo-ii} the formation of the inclined surface 301, and the inclined surface 3〇1 suppresses the upward growth of the semiconductor nanocolumn 5. When the growth temperature of the pulse growth mode rises, the surface mobility of the gallium element in the flowing gas rises, that is, The probability of the gallium element moving to the growth surface (top surface) of the semiconductor nanocolumn 5 is increased by 3〇3, and there is a chance that the element is trapped by the side wall of the semiconductor nanocolumn 5 on the dioxin mask (4) 2〇3. The gallium element is captured by the sidewall of the semiconductor nanocolumn to widen the width of the semiconductor nanocolumn 5), so the length of the semiconductor nanocolumn 5 is changed to have a flat shim surface (top surface _. However: when the pulse growth mode When the growth temperature is too high (as shown in Figure 3D, the growth temperature is higher than 950 C), GaN will decompose. Therefore, according to the results of this experiment, the better growth condition of the semiconductor nanometer 5 is in the _ growth mode. Medium growth temperature Between 85 〇. (: and 950T: In addition, there is no gas injection step (such as the pulse growth mode cycle of the above gas staggered injection step 1 and step 3 in the step details) interval (such as U and t3 in Figure 2) The length is also tried to adjust. The interval time is controlled separately: 3 seconds, 9 seconds, 15 seconds, and 24 seconds. As shown in Figures 4A to w, when the interval of the gas-free injection step is extended, the semiconductor nanometer The growth surface of 枉5 is changed from the 丨10-11} slanted surface 301 to a flat top surface. Here, the distance between the 2011 amp amp 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表 代表The formation of the inclined surface 3G1 suppresses the semiconductor nanocolumn 5; growth, therefore, according to the experimental results, the growth condition of the semiconductor nanocolumn 5 is longer than the interval of controlling the gas-free injection step. The growth temperature of the rice column 5 is higher (in the pulse growth ^ about 8 耽 to (four) t) (four) to make the nitrogen decantation decomposition. Therefore, the interval between the steps of controlling the gas-free injection step is less than the second to avoid decomposition of the generated semi-conductive Zhao Nian column 5. Long factor (== f The results of this experiment show that the preferred growth condition of the semi-conductive book 5 is that the interval between the steps of controlling the gas-free injection step is between 15 seconds and 6 seconds. As shown in Fig. 5, Fig. 5 shows A cross-sectional view of the bottom of a gallium nitride semiconductor nanostructure 5. As seen from the above, the dielectric layer of the dioxoscopic mask (about 8 nanometers in thickness) has a slanted sidewall on both sides of the process due to process characteristics. The size of the reticle dielectric layer opening is defined as the bottom of the sidewall, which is (10) nanometer (as indicated in Figure 5); and the width of the resulting semiconductor nanostructure is slightly due to lateral growth factors. It is larger than the size of the opening (3 〇〇 nanometer). After the formation of the semiconductor nanostructure 5, the step of healing and re-growth is carried out. The pressure of the cavity and the V-group/cucumber ratio are changed to Taor ((4) and 3900, respectively). The growth temperature is maintained at i(4). c. The continuous flow rate of trimethylgallium gas is controlled at 35 micromoles per minute ('3^μηιοΐ/min) and l500 SCCM. Under such growth conditions, the growth rate is about It is 1.3 microns (1.3 μηι/hour) per hour. Therefore, as shown in Figure 6, \201133936 is about 90 minutes. The second step of the growth of Zhong Qihe will generate a re-growth layer of about 2 microns. By comparing the opening size and spacing of the different dielectric layers of the dioxide dioxide mask, it is possible to observe the growth above the semiconductor nanostructure 5. The quality of the re-grown layer, including the formation behavior of the internal wear-through defects of the structure. The following four semiconductor nanostructures and GaN template 2 having different opening sizes of the dichroic oxide mask dielectric layer are respectively compared. In order to pass through the above-mentioned opposite method, first, a gallium nitride thin film buffer layer 2〇1 having a thickness of about 2 μm is formed on the c-plane of the sapphire substrate 1, and then, by nano-imprinting through the light. A plurality of hexagonal array openings 205 are formed in the interior of the gallium oxide mask dielectric layer 2〇3 having a thickness of about 8 nanometers on the gallium nitride thin film buffer layer 201. The opening 205 is formed by a nanoimprint lithography. The diameters are respectively 250 nm, 3 〇〇 nanometer, 45 〇 nanometer, and 6 〇 0 nm, and the adjacent opening spacing corresponding to the opening 205 size is 5 〇〇 nm, 600 nm, respectively. 900 nm, and 12〇〇 The nanometers, as shown in Figs. 7A to 7B, are defined as samples A, B, c, and D, respectively. In addition, the structures of the re-growth layer according to the growth of the sample AD are respectively defined as the sample AO-DO. 8A and 8B show the normalized photoluminescence intensity versus temperature for different samples. The ratio of normalized integrated intensity to normalized integrated intensity at 1 degree Kelvin at room temperature can be regarded as internal quantum efficiency ( The performance of internal quantum efficiency (IQE) is related to the defect density in the sample 11 5 201133936. As shown in Figs. 8A and 8B, there are graphs of normalized photoluminescence intensity versus temperature for a semiconductor nanostructure sample (Μ) and a regrown layer sample (AO-DO), respectively. Among them, each of the figures was compared with a gallium nitride template sample E having no grown semiconductor nanostructure. As shown in the figure, the internal quantum efficiency (I(jE)) when the size of the semiconductor nanostructure becomes large, regardless of the relationship between the semiconductor nanostructure sample (A_D) or the regrown layer sample (AO-DO) It will decrease. In all semiconductor nanostructured samples (AD) or regrown layer samples (AO-DO), the internal quantum efficiency (IQE) values are higher than those of non-growth semiconductor nanostructures. (1.1%) 'The semiconductor nanostructure and its successively grown healing and re-grown layers all have good epitaxial quality. Moreover, the internal quantum efficiency of the healed and re-growth samples in all sizes of semiconductor nanostructures The internal quantum efficiency of the semiconductor nanostructure samples of the same size is lower. In other words, when healing and growth, new defects are re-generated. When the opening size is 250 nm, the semiconductor nanostructure sample The internal quantum efficiency of a is 9.9%, which is nine times that of the gallium nitride template sample e, and the internal quantum efficiency of the corresponding healing regrown layer sample AO is 6.7%, which is approximately six of the gallium nitride template sample E. Times. Then As shown in FIGS. 9A and 9B, a complex quantum of indium gallium nitride and gallium nitride (InGaN/GaN) is formed on the top surface of the gallium nitride template 2 with improved quality and different size healing and re-growth samples. The well structure 100 and the quantum well light emitting diode structure 200 are used to compare the effects of different sizes on the luminous efficiency of 12 201133936. As shown in FIG. 9A, a quantum well layer and a quantum energy barrier layer comprising five pairs of alternate overlapping configurations are shown. The plurality of quantum well structures (MQW) are grown on the gallium nitride template 2. In one preferred embodiment, the five pairs of alternately overlapping structures respectively comprise a growth temperature of 675 C. The growth of a gallium nitride indium quantum well layer having a thickness of 3 nm and a GaN gallium energy barrier layer having a thickness of 15 Å. The growth quantum well light-emitting diode structure is grown at a temperature of 850. When the semiconductor nanostructure 5 having a thickness of 1 μm is used, the step includes sequentially growing an undoped gallium nitride layer 8 having a thickness of 1 μm, growing at a temperature of 1〇5〇〇c, and having a thickness of 4 μm and having germanium doping. N-type gallium nitride layer 9, Long as the month 'J's five pairs of fathers for the overlapping of the quantum well layer and the quantum energy barrier layer composed of a complex number of sub-well structures 7, and 93 (TC grows a thickness of 120 nm of the Ρ-type gallium nitride layer 10 When the light-emitting diode structure having different main light-emitting wavelengths is produced, the temperature of the growth-re-quantity sub-well structure 7 will be different. For example, when the blue light (green light) light-emitting diode structure 200 is grown, the thickness is grown. The temperature of the 3 nm gallium nitride indium quantum well layer and the 15 nm thick gallium nitride quantum barrier layer are 715 (675), respectively (: and 850 (850) ° C, respectively, yielding about 460 ( About 520) The main light-emitting wavelength of the nanometer is as shown in Fig. 9B. In addition, the surface of the growth substrate of these structures can be further roughened to achieve an effect of increasing light extraction efficiency. Figure 10A is a graph showing photoluminescence intensity vs. temperature for a complex number of sub-well structures 100 constructed on semiconductor nanostructure substrates having different opening diameters of 250, 300, 450, 600 13 3 201133936 nm, respectively. For ease of comparison, a complex number of well structures grown in a semiconductor nanostructured gallium nitride template was also fabricated as a reference. From the experimental results, it can be defined that the integrated photoluminescence intensity at 300 degrees Kelvin temperature for the integrated photoluminescence intensity at 1 degree Kelvin temperature can be regarded as the performance of the internal quantum efficiency (internai quantum efficiency 'IQE'' The quantum quantum efficiency of the semiconductor nanostructure substrate with a diameter of 250, 300, 450, and 600 nm is 21.2%, 19.0%, 16_5%, and 15.3%, respectively. Among them, all internal quantum efficiency is higher than 12.4% of the reference. This result shows that by healing and growing in a structure having a semiconductor nanostructure, the threading dislocation density can be effectively reduced and the quality of the crystal structure can be increased, and a better quality healing re-growth structure can be generated. The quantum well structure above the healing re-growth layer has a higher luminous intensity. Fig. 10B is a graph showing the relationship between photoluminescence intensity and temperature of a light-emitting diode structure 200 formed on a semiconductor nanostructure substrate having different opening diameters of 3 Å, 450, and 600 nm. Similarly, a light-emitting diode structure grown on a semiconductor nitride structure without a semiconductor nanostructure was also prepared as a reference. In this experiment, the normalized internal quantum efficiencies of the light-emitting diode structures 200 corresponding to the semiconductor nanostructure substrate opening diameters of 300, 450, and 600 nm were 49.2%, 36.6%, and 19.2%, respectively. Compared with the reference standard, which has an internal quantum efficiency of 20.1%, we can find that the light-emitting efficiency of the other LED structure 201133936 is enhanced except for the structure with an opening diameter of 600 nm. Therefore, the semiconductor nanostructure substrate formed by the dielectric layer mask structure having a small opening diameter has a light-emitting diode structure formed thereon with better efficiency. FIG. 10C shows the electroluminescence intensity versus injection current (Z-/ curves) of different light-emitting diode structures (LED-structures) corresponding to the semiconductor nanostructure substrate opening diameters of 300, 450, and 600 nm. ) diagram of the relationship. From the experimental results, we can find that when a light-emitting diode structure is fabricated using a template having a semiconductor nanostructure to heal and re-grow, a better output intensity of the light-emitting diode structure can be obtained. When the injection current is 60 milliamperes (mA), a light-emitting diode structure having an opening diameter of 300 nm can obtain an output intensity about twice higher than that of a reference without a semiconductor nanostructure in the substrate. Taking the luminescent body structure as an example, the spectral properties of the luminescence produced by the structure can be achieved by adjusting the physical or chemical properties of a single layer or a plurality of layers of material in the structure. Among them, 'commonly used materials are aluminum gallium indium phosphide (AlGalnP) series materials, aluminum gallium indium (AlGalnN) series materials, zinc oxide (ZnO) series materials and so on. The structure of the active layer may also differ depending on the structure of the light-emitting diode, such as single heterostructure (SH), double heterostructure (DH), double-sided double heterostructure (double-side double heterostructure) , DDH), or multiple quantum well (MQW). In addition, in addition to the above method of adjusting the growth temperature, the length of the main light-emitting wavelength of the light-emitting diode structure can be achieved by adjusting the logarithm of the quantum well layer of the light-emitting diode structure and the early layer of the quantum energy. In the present invention, the semi-conductive structure is uniform and is not limited to the embodiment, and any material and shape can be used. 21 Where the composition/angle fiber zinc is not used in the embodiments of the present invention, it is only used to illustrate the invention, [Simplified description of the figure] = - schematic diagram display - Figure 2 with multiple semiconductor nanostructures above is A representative program includes a fabrication process for forming a plurality of semiconductor nanostructures and/or half using the present invention; + a conductor nanostructure array = 3A'3D is a scanning electron microscope image map, and a semiconductor infrared pattern generated by 2 temperatures is separately purchased. The top view of the rice structure substrate; the sub-microscope image of the 〇 purification ^, respectively showing the upper view through the different Figure 5 + conductor nanostructure substrate; the rice junction conductor Nye 6 is a schematic view, showing - above the complex body The nanostructures are 201133936 and a substrate that heals and re-growth layers; Figures 7A-7D are scanning electron microscope image views showing the top view of the ceria dielectric layer structure with different opening sizes; Figure 8A-8B is a chart , respectively, showing the normalized photoluminescence intensity versus temperature for different samples; FIG. 9A is a schematic view showing a complex internal semiconductor nanostructure A quantum well structure ( MQW); FIG. 9A is a schematic diagram showing a multiple quantum well (MQW) light-emitting diode (LED) structure having a semiconductor nanostructure therein; Figure 10A is a graph showing the relationship between the photoluminescence intensity of different quantum well structures (QW) versus temperature; Figure 10B is a graph showing the structure of different light-emitting diodes (LEDs). Graph of luminous intensity versus temperature; Figure 10C is a graph showing the relationship between electroluminescence intensity and injection current of different light-emitting diode (LED) structures. 17 5 201133936 [Description of main components] 1 : substrate; 2: gallium nitride template; 5: semiconductor nano column; 6: re-grown layer; 7: complex number of sub-well structures; 8: neutral gallium nitride (u- GaN) layer; 9: n-type gallium nitride (n-GaN) layer; 10: p-type gallium nitride (p-GaN) layer; 100: complex number of sub-well structures; 200: light-emitting diode structure; 201: nitrogen Gallium nitride film layer; 203: germanium dioxide dielectric layer; 205: circular opening; 301: inclined surface; 303: growth surface. 18