TW201133504A - Current sink system based on sample and hold for source side sensing - Google Patents

Abstract

Source side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of an operating voltage between first and second nodes. During a first time interval, the operating voltage is set in response to a magnitude of the reference current using a feedback path. During a second time interval following the first. time interval, the operating voltage is held independent of the feedback path. The data value stored in the memory cell is determined based on a difference in current between the read current and a sink current during the second time interval.

Description

201133504 VI. Description of the Invention: [Technical Field of the Invention] The data sensing of the memory device is particularly concerned with the prevention of interference in the sensing operation caused by noise in the memory device. [Prior Art] There is a material stored in the charge-type memory to the volatile memory, and the memory is stored between the channel and the _ of the field effect transistor. The number of stored charges is the critical value of the transistor, which can be sensed. Two types of charge storage memory cells are called floating gate memory cells. In the floating = memory cell, the f load is stored between the channel and the gate of the field effect transistor. The change in threshold voltage stores or removes charge at a layer by applying a suitable voltage. Another type of memory cell is called an electron cell, which uses a dielectric charge trapping layer instead of a floating gate. When reading, or sensing the operation of storing data values in a memory cell, a suitable voltage is applied to induce current from the 汲 terminal of the memory cell to the source terminal. This current depends on the threshold voltage of the transistor and therefore indicates the data stored in it. “—Determining the value of the data stored in a memory cell can be performed using a sense amplifier that senses the current flowing through the memory cell and compares the sensed current to an appropriate value. Figure 1 The implementation of a conventional technique of the sense amplifier 17A is not intended to sense the value of a data stored in a selected memory cell 110. The memory cell is a representative memory cell in a memory array. The memory array package has millions or billions of memory cells. The word line 12〇 is coupled to the gate terminal of the memory cell 11〇. The bit lines 13〇, 132 and the source and the channel of the memory cell 11〇 The pole terminals 112', 114 are coupled. The row select transistor 140 is responsive to a SEL signal to selectively couple the bit = line 130 to the data line 15 coupled to the sense amplifier 170 sense input 172. In the sensing operation of the cell 110, applying a suitable voltage to the word line and the bit line 丨32 induces a read current Icell from the drain terminal U4 to the source terminal U2 and into the bit line 130. This read current ICELL is supplied to the data line 15 via the row selection cell 201133504 body 140. 17 0 sense transmission Into 17 2 to the first class (four) Dulei six, the community? = 3 π. The traitor 戟 谷 谷 CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL CL The magnitude of the current ICELL is related to the threshold voltage of the memory cell u〇. A lower threshold voltage can cause a larger current. Therefore, the voltage of the sensing input 17 ^ will change faster, if so The memory cell ii G is in a lower critical state rather than a higher critical state. In the ms, a reference current 1 is used to provide a sense input 172 at the sense amplification 170 as a reference value. In the illustrated example, the cell 210 is used to provide a reference current Iref. "

The word line 220 is coupled to the gate terminal of the reference cell 21A. The bit lines 23A, 232 are coupled to the source and drain terminals 2A2, 214 of the reference cell 210. The transistor 142 is coupled to selectively connect the bit line 23 to the sense amplifier 17 参考 the reference line 16 of the reference input 174. A suitable voltage is applied to word line 220 and bit line 232 to induce a reference current Iref from drain terminal 214 to source terminal 212 and to bit line 230. This reference current IREF is supplied to the reference line 160 via the row selection transistor M2. The reference current IREF charges the equivalent load capacitance cLOAD2 at the reference input port 4 of the sense amplifier 17A, causing the voltage of the reference input 174 to convert the reference current Iref to a reference voltage. The sense amplifier 170 is triggered by the sense enable signal sen during the sensing operation. The sense amplifier 170 is responsive to a voltage difference between the sense input 172 and the reference input 174 to generate an output signal 176 for storage in the selected memory cell 11A. ~ Fig. 2 is a schematic diagram showing the relationship between the voltage change of the sense input 172 and the 夂 input 174 and the time when the memory cell 110 is in the sensing operation. The curve 25 〇 ' 示 假 § § 忆 忆 忆 1 ί 忆 忆 忆 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感 感The voltage changes. The difference between curves 250 and 260, when T1 is used to distinguish whether the memory cell is in a lower or higher critical state, is 201133504 ίί J2, the interval. In order to distinguish between higher and lower critical states, it is necessary to have more than two critical states in the embodiment of the cell, with a sensing interval therebetween. Strictly, the line Γ〇 shows that the memory cell 110 refers to the power of the input 174 during the sensing operation. In this illustration, the curve 27G* time T1 has - between the J boundary, the curve 250 and the higher critical state curve 26 A voltage between the 〇, such as the threshold voltage of the 21G of the cell is between the right octet and the *critical state of the memory cell to achieve 'such reference current I qing and has " Yu 汜 胞 no low and higher critical state The read current is sized. In another example, this can be achieved by applying different voltages to the turns 120 and 220' and/or applying different voltages to the bit lines 132 and 23. The sense amplifier 170 produces an output signal 176 having a value 而 depending on the voltage at which the sense input 172 is greater or less than the reference input = 174 at time T1, thus indicating the amount of money stored in the selected memory cell.値0, ' This sensing process may cause problems due to the influence of the sense amplifier 17〇. In particular, the noise in the sensing operation affects the sense input Π2 and the reference input 174. Voltage difference, which increases the sense amplifier 17 The complexity or the time required for sensing. In the example shown in Figure 1, the memory cell 110 is isolated from the reference cell 21〇, and the read current ICELL and the reference current Iref are not dependent on each other. As a result, the memory cell 110 can be exposed to a different noise than the reference cell 21, which can result in a change in the read current ICELL from the reference current Iref. The result is a wider sense input Π2 and reference input. The voltage difference between 174 varies, which inhibits the sense amplifier 17A from correctly sensing the data stored in the selected memory cell 110. In the above-described embodiment, the sense input 172 of the sense amplifier 170 The source terminal 112 of the signal cell 110 is switched (source terminal sensing). As a result, the voltage on the source terminal 112 is also increased by a number 201133504 that is off from the read current IcEu^a. Thus, the voltage increase on the pole terminal 112 is reduced and the pole-to-source effect 'which is therefore reduced by the memory" because of the environmental variation of the operation, and also because of ===; the threshold voltage of the f cell will be in the array (10) change between tti" When the array 1〇5 stores the same data, the read current wcl includes the read current change caused by the increase of the source voltage. 丨=the amount of voltage increase is related to the read current W, and the inductive sensing circuit is added. Complexity or required: Since the data line is light - 祉 _ secret end = Q = because the source of electricity and the ancient method 'which can solve the problem of η grade pain during operation' and have The invention has the high tolerance of the noise. [Invention] The source-source sensing technology is based on the memory source terminal ΐΐίίί: the difference between the inrush currents introduced by the read current Ϊ ΐΐΐ Ξ Ξ Ξ Data value. This inrush current is introduced in response to the operating voltage of -. In the first time interval, set the Yang (4)-Qing yin to quickly use a capacitor to lose the feedback path between the two and the operating voltage is favorable. The λ 赖 区域 财 is basically a fixed value in the interval is basically similar to the n operation _ two time to take the data value in the cell is based on the second _ district 201133504 will not be = fixed. Therefore, the correctness of this difference basically uses the read turbulent flow, which reduces the difference in the sensing operation, rather than the entire reading power. This is the change. As a result, this reduces the read current and the current distribution becomes tighter during the original extreme sensing. Μ δ2 ί ί 的 ί ί 或 或 或 或 或 或 或 或 ί ί ί ί ί ί ί ί ί ί ί ί 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取 选取The reference current source current source can respond to the immersed current source between the first:/the first light|妾, which is small and is introduced from the data line and the incoming power: 3 is a large voltage ί 1^; :r; The gate is ^~voltage-reducing--capacitor is in the first-and-th-section^2: month::Hai feedback path, and after the first time interval] i and - sense amplifier circuit In response to the difference between the second time dry current and the unmanned current, the output signal is used to refer to the data value of the selected memory cell. The cell contains the self-memory cell method. a voltage is applied to the voltage between the first and second points of the memory, and after the first time interval, the voltage is applied between the first and the second node and the feedback path, according to a difference between the read current and the 汲 motor in the second time interval is determined to be stored in the memory A data value in the section. The features and embodiments in the section will be in the following embodiment of the chapter 201133504. [Embodiment] The embodiment of the present invention is described in detail with the following figures 3 to 9. FIG. 3 shows an integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS A schematic block diagram of a sample and hold-in current circuit 310' for use in a memory array 32A as described herein can be used to sense storage in memory cells and cells. The data value is coupled to the mt 324 in the direction of the memory array 32. The row decoder 326 and the plurality of bit lines arranged along the memory ^ 3 〇仃 direction The 328 is coupled to the sense of the array: the eraser. The memory cells in the memory array 320 can be arranged in parallel, or in a virtual ground. The structure in the block 330 is in this example. According to the data convergence (4) 旳, 隹二! ^, in more detail, a memory of the memory array 320 is selected "^__" when the appropriate application is applied | 32G - the source of the selected memory cell ^ response If·!, no one current circuit 31G and data 332 is coupled to the magnitude of the operating voltage between the second, the *, and the second node, and is used to refer to the noun used herein, the operating voltage, and usually refers to a point between And the first node of the current input circuit 3ig and the second node change, and establish: the magnitude of the response reference current 1 coffee is changed according to the following - change the voltage of the inrush current 1 · size. The routing path can be operated with (4) the current circuit, including the back-to-one node and the second reference current 1REF, and the operating voltage is set between the sampling interval (the sampling interval). The first time pressure. In the sense of the bamboo pole, this feedback path is enabled to quickly set the operation to be disabled, and one, the last name: the second time interval (hold interval), this feedback The path maintains this operation. The capacitor is coupled between the first node and the second node to have a constant value and is therefore substantially free of noise. 201133504 In the embodiment described herein, this operation The load transistor terminal of the current input circuit 3H) t =: the conduction terminal (for example, the pole or the source terminal) = -Dr Ϊ reference current Iref. This holding capacitor is used to apply - roughly control - turn-on terminal voltage (eg gate = under-react = fine current here keeps the heart ^ 33 ^ 2 electric Ϊ 1 眶 and reference current " the difference between The sense amplifier circuit is provided. The sense amplifier circuit responds to the output signal of a data value in the selected memory cell in response to the second time. In the case of the i, the sampled and held immersed current The circuit 310 also supplies the reference 冤~IREFk generated by the reference _ 34G t reference cell to the sampled and held mash current circuit 31. Alternatively, other techniques can be used to generate the reference current IREF. The reference current REF may be based on a reference current based on more than one reference cell. The column decoder 344 is coupled to a word 345 arranged in the direction of the reference array 34. The row decoder 342 is along The reference array 34 is coupled to the bit line 343 in the row direction. In this exemplary embodiment, the reference array 34 is separated from the row of columns 320 and includes separate column and row decoders 344, 342°. f generation, the reference array 340 can be A portion of the memory array 32A, and the decoders are shared among the arrays 320, 340. The address is provided to the row decoders 326, 342 and the column solutions = 322, 344 through the bus bar 35. The data is integrated. The input/output port on circuit 3 is transmitted through input line 352 to the data input structure of block 330. In the illustrated example, other circuits 360 are also included in the integrated circuit 3, for example, eight-way processing. Or a special-purpose circuit' or a group 5 module supported by the memory array to provide a single-chip system function. The data is transmitted from the sense output in block 330 to the integrated body through the data output line 354. Input/output on circuit 300 or other data destinations within or outside of integrated circuit 300. This integrated circuit 300 includes controller 369 to sense, program, and erase memory array 320 memory cells and reference array 34 The reference cell in the cymbal. The controller 369, in the example, is a bias adjustment state mechanism that controls the bias voltage generated by the block 368 to adjust the supply voltage or provide a read, stylized or block to block 368. Wipe off the voltage. This control The application of the device 369 can be implemented using techniques well known in the art, such as special purpose logic circuits. In another embodiment, the controller 369 includes a general purpose processor that can be implemented on the same integrated circuit. carried out

First, a brain program to control the operation of the device. In another embodiment, a combination of a special purpose logic circuit and a general purpose processor can be used to implement the controller 369. Figure 4 shows a method of selecting a memory cell for sensing operation in the memory array. 400 flowchart, which may be executed by controller 369. At block 410, a read bias is applied to the selected memory cell to induce from the source terminal of the selected memory cell - the read current w to the data is 332 ° in 10,000 volts from a reference current source Provide - reference current IREF. In the H embodiment of Figure 3, this reference current is provided by applying a combined voltage to a reference cell in reference array 340. As described earlier, since the data line 332 is responsive to this, the line-in current circuit 31 is clamped (block; the operating voltage between the first-point and the-point-point is large (block example, The sample and hold line current circuit 3m diameter can be used to respond to the large reference voltage lREF: the operating voltage of the point and the second node = will be described in more detail below = the current = the path can be quickly sampled and maintained The occupation of the line current circuit includes quickly setting the operating pressure between the first node and the second node. 201133504 This operating voltage is in a second time interval (block 440) after the first time interval. Is maintained between the first node and the second node regardless of the feedback path. At block 450', a difference between the read current ICELL and the inrush current iSINK in the first time interval is determined to be stored in the The data values in the selected memory cells. Fig. 5 is a schematic diagram showing the sampling and holding of the inrush current circuit 31A used in a memory array 320 according to the first embodiment of the present invention, which can be used to sense storage. Memory selected by memory array 320 The data value in cell 510. Word line 324a is coupled to the gate of selected memory cell 510. Bit line 328a, 328b is coupled to drain terminal 511 and source terminal 512 of memory cell 510, respectively.

Capricorn pick up. When a sensing operation of the memory cell 5 is performed, an appropriate voltage is applied to the word line 324a and the bit line 328a to induce a read current Icell from the drain terminal 511 to the source terminal 512 and the entry bit. Yuan line 328b. This read current iCEU is supplied to the data line 332a via the row decoder 326. In the illustrated example, reference cell 560 of reference array 340 is used to provide a reference current IREF. The word line 345a is coupled to the gate terminal of the reference cell 560. The bit lines 343a, 343b are respectively coupled to the drain terminal 561 and the source terminal 562 of the reference cell 560.

Seven voltages are applied to word line 345a and bit line 343a to induce a reference <5 stream IrEF from drain terminal 561 to source terminal 562 and into bit line 3^^ this reference current iREF via row decoder 342 It is provided to reference line 346a. The sampled and held immersed current circuit includes a transistor, and the pole terminal is consuming with a reference line 3 shirt to receive a reference current 丨. The switch is selectively coupled to the reference line 346a via the changeover switch 526. The example switch 52^ uses a single pass transistor to have a gate coupling 5, and other alternative techniques can be used. For example, the switch 526 can be turned on using a set of complementary passes. The path and provide complementary gate control signals.八12 201133504 和电 S 3L526 transistor 522 is a diode connection to form a current mirror 520 with the electric solar 524, the electric crystal read a 2*, = 524 into 5 hai; and the current iSINK, and this ;: and the human current Isink has a function of the magnitude of the magnitude current Iref. For example, the size of the intrusion factory _, ', and two can be roughly equal to the magnitude of the reference current IREF. In the illustrated example, current mirror 52A is implemented by transistors 522, 52. Alternatively, other techniques can be used to implement the current mirror 52A. The holding capacitor C1 525 is coupled to the 526 5 of the transistors 522, 524.

The hold M Cl 525 is established and maintained at the ends of the transistors 522, 524. The size of this holding capacitor H C1 525 is large enough _ early

The bias voltage is maintained between the gates of the transistors 522, 524, so the transistors 522, 524 remain on, and the current difference between the inrush current IsiNK and the reference current IREF (if any) The interval remains approximately constant. It is understood that maintaining the bias voltage by the holding capacitor C1 525 between the gate terminal and the source terminal of the transistors 522, 524 may be due to charge in the hold time interval. The leakage and the instantaneous noise of the switch 526 are turned on. The load transistor 530 has a drain terminal coupled to the primary terminal of the transistors 522, 524. The load transistor 530 has a source terminal and a negative rise. The voltage regulator/circuit 532 is coupled 'which provides a negative bias voltage. The current through the load transistor 530 is a combination of the reference electrical Iref of the transistor 522 and the inrush current ISENK of the transistor 524. The current of the transistor = 530 is obtained by the load transistor 530 converting the voltage of one of the terminals of the transistors 522, 524: the sum of the sample and hold j: and the current input circuit 31 can also include an operational amplifier 540. The supply voltage VDD and the negative booster circuit 532 provide a bias voltage to the operational amplifier 540. In this illustration, the operational amplifier 54A has a negative 13 201133504 input 544 that is grounded to ground. This operational pay line 346a is coupled. The effect of the two sides of the positive input 540 and the reference voltage 546 and the reference ground on the reference reference line 346a is the ground potential. This noun, the large f, the ^EF ^ amp 540 bias and 546 Because the operation is placed to represent the difference between the two input terminals 544, the voltage is generated by a non-zero input offset. The load is made by the switch 57 and the 570 is a single pass. The switching switch in the illustration can use other alternative technologies, and the sound is coupled to the control signal § 1. Also, the switch can be used as an example. The cut diameter and the complementary gate signal are provided in parallel. The turn-off path of the turn-off switch _ 570 establishes a negative from 542 to the positive input 546, and the output of the operational wind amplifier 540 of the off-air X state 540 is turned off. The gate of the ^ ^ is turned off, 苴 can be reduced! L. Electric a is biased to the load transistor In the section sampling time interval, the operating voltage between the points 572a, 572b is quickly set. 540 "Explained by the following description. The increase in the operational amplifier 匕 = causes the voltage of the output 542 to increase, and = Ϊ The galvanic voltage is increased, which results in the source voltage of the hi-electric drop bodies 522, 524 of the load transistor 530 bungee. Thus, the thunder voltage of the θ body 522 is reduced by the θ 曰 body 522. The positive input 546 of 540 is connected such that the voltage at amplifier 540 positive input 546 is reduced. This will be the opposite of the original tenant's positive input 546 voltage change. Thus, the feedback is that the negative container C2 574 is coupled between the gate terminal of the load transistor 530 and the first conductive terminal. When the switch 570 is turned on, the feedback path 14 201133504 °572a ^ to the source terminal thereby maintaining the gate of the carrier 530 can prevent the operation amplification, and the switch 5 7 is opened to the node correction room. Internal Cause ^!Ιΐ! Z:7: u ^ , ,, , — n Not between D/Zb. The holding capacitor C2 574 is thundered: the gate-to-source voltage is applied to the load transistor 530, so the current through the "electric, body > 530 remains substantially constant over the hold interval.

The operating voltage between the 疋 郎 朗 points 572a and 572b and thus the p 1 of the load cell crystal may change slightly during the hold time interval, perhaps as the charge $drain and the instant noise of the switch 526. The sense amplifier 571 has a reference input or node 595 coupled to the multi-test line 346a and has a sense input or node 59 〇 coupled to the data line 332 & As previously described, the reference voltage on reference line 346a and reference input 595 are biased by operational amplifier 54 to Vtref, which in this example is ground. The sense current iSENSE, which is a difference between the read current Icell and the inrush current Isink, is provided to the sense node 59A of the sense amplifier 571. The sense current ISENSE is converted into a voltage of the sense node 590 by charging the equivalent load capacitance Q (3adi) during the hold time interval. The sense amplifier 570 is responsive to the voltage difference between the sense input 590 and the reference input 595. The value is generated to indicate an output signal 576 stored in the selected memory cell 510, which is triggered by the sensing enable signal SEN. The discharge transistor 580 is coupled to the data line 332a. The gate of the discharge transistor 580 The pole is coupled to a discharge 2 signal 582 for coupling the data line 332a and thus grounding the sense wheel 590. Alternatively, a bias voltage other than ground can also be used. Discharge transistor 584 and reference line 346a is coupled. The gate of the discharge transistor 584 is coupled to a discharge 1 signal 586, which is used to couple the reference line 346a, 15 201133504 and thus ground the reference input 595. Alternatively, it is also possible to use a bias other than ground. Fig. 6 shows a timing chart for operating the sample and hold current input circuit 310 shown in Fig. 5 to sense a data value stored in the selected memory cell 51〇. It is understood that , when in Figure 6 The sequence diagram is simplified and not shown to scale. At time T0, a discharge 1 signal 586 is asserted to turn on the discharge transistor and coupled to reference line 346a, and thus ground reference input 595. Discharge 2 signal 582 Is emitted to turn on the discharge transistor 58A and coupled to the data line 332a, and thus ground the sense input 590. At time T1, the column decoder 322 applies a read bias voltage VwwlEAD to the address in response to the address signal. The selected memory cell 510 gate coupled word line 324a 'the row decoder 326 applies a read bias voltage Vblread to the bit line 328a coupled to the selected memory cell 510 drain terminal 511 in response to the address signal. And coupling the bit line 328b to the data line 332a. The bias applied to the word line \24a and the bit line 328a induces a read current IcELL from the drain terminal 511 to the source terminal 512' and enters the bit Line 328b and data line 332a. ' As shown in Fig. 6, 'discharge 2 signal 582 continues to be emitted so that discharge transistor 580 is continuously turned on, and data line 332a and sense input 59 〇 continue to be sampled: time T1 and T2 are sampled The interval remains grounded. ' ;1 column decoding state The 344 applies a read bias pin to the word line 345a coupled to the gate of the selected reference cell 560 in response to the address signal, and the device 342 applies a read bias voltage Vblref to the selected address in response to the address signal. ^ The bit line 343a' coupled to the cell 560 drain terminal 561 and the bit line 343b are coupled to the data line 346a. The word line 345a and the bit line 343a are applied to the voltage source to induce a reference current IREF. The terminal 561 to the source terminal 562 7 to: the source line 343b enter the word line 346a. The discharge 1 signal 586 turns off the discharge transistor 584 and the control signal is issued to turn off the switches 526 and 570. This will establish the operating point of this sample and hold sub 16 201133504, which includes setting the node 572 a body = ϊϊϊί f6 to make the diode in the current mirror 52G connected to the diode 曰 ί = lightly connected to the pure reference current w The reference current w in the current mirror 520 crystal 522 can be used to establish the negative feedback path of the operational amplifier 540 by directing the incoming and outgoing currents 1· in response to the electrical current. The output 542 of the operational amplifier 540 is Ϊ = pressed to the node core 'to set the node 572a, 572b to the end i = " is connected to the gate terminal of the load transistor 530 and the source 屯 & and forced positive input 546 The voltage is approximately equal to the negative, etc. to reduce its chain. This allows the sampling and holding/and operation of the motor circuit 310 to be established quickly. Switching off the transistor 522 connected by Ϊ i 2 Ϊ ί Switch 526 = the direct path of the gate to the drain terminal of the galvanic body 522 to reduce the closed loop reaction time of the 杈 (4). In addition, the capacitor α still provides the AC of the 522, 524 closed-end terminal to the second conductive terminal. The signal, eight, , and five paths also reduce the closed loop response time of this feedback path. Switching, and capacitors C1 525 and C2 574 also provide operational amplification path stability. Stability of this feedback path The system and the self-positive input consist of three poles 'the most important pole in the operation of the amplifier Figure 5: 〇ϋ and because the capacitor C1 525 spear switch 526 pole. The pole at 542 is the most important because of the operation Gate IGBT ^ f53G The relatively large equivalent capacitance 525 of the valley and capacitor C2... and the diverter switch 526 also provide a positive supply path for the source to the drain of the transistor 522, so the equivalent of the transistor 522 to the source of the source 17 201133504 resistance It is relatively small. As a result, the pole caused by the capacitor is far from the most important pole, 5 and the switch 526. It improves the stability of this closed loop. In this case, the sample and keep-off from time Ti $ The current circuit 31〇's “2 2^ interval” can be achieved by using this feedback path to establish this access point. After the operation point of 310, at time τ 2, this '3 hold' and Current circuit ""526

526 ^ J body 522, 524 gate terminal dust voltage: Second, = live electric crystal source is extremely polarized to the transistor 522, 524, = fb, the gate to the next 掊卩 1 匕 electricity day body 522, 524 keep Q open between times at time T2 (four). It can be understood that the bias voltage held by the 52 5 may change slightly during the hold time interval and the noise of the switch 526 is turned on. ' 接, Ϊ = = 出 Τ 控制 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 572 Between the node and his, the operation is maintained by the electric C2 574. The holding capacitor C2 574 applies a force: the gate-to-source bias fixed to the load cell 530 is so negative that the current of the body 530 remains substantially constant during the hold interval. It can be understood that the operating voltage held by the control node 572a, and thus the current of the load transistor 530, may vary somewhat during this hold time interval due to charge leakage and transient noise of the switch 570 being turned on.

The sense current iSENSE', which is a difference between the read current iCELL and the sink current IslNK, is provided to the sense input 590 of the sense amplifier 571. This sense current ISENSE is converted to a voltage of the sense input 590 by charging the equivalent load capacitance Ck)adl. The voltage across sense input 590 will be along curve 600 such that memory cell 510 is selected to be in a lower critical state, and along curve 610, if memory cell 510 is selected to be in a higher critical state. 18 201133504 In time T3, in response to the voltage difference between the sense amplifier 590 and the two 595', the sense amplifier 570 is generated to indicate that the data in the selected recorder L is worth an output signal VOUT. In Fig. 6, ν Γ 2 second voltage 620 is thus selected as the memory cell 51 〇 is at a lower side: the second voltage is taken off so that the selected memory cell is in a “because of the intrusion of sampling and retention The commons provided by the current circuit 31〇 is that the negative booster 532 noise does not substantially have any effect on the voltage comparison between the sensed input and sense input 595. Negative 56 “Thunder: Any F The noise will cause the memory cell 510 to change with the reference cell I^, so the reading current 1 and the immersed current Γ, κ 二 φ ϊ are substantially constant in the holding interval. This annihilation capacitor (4) still... (7) applies a substantially fixed source bias voltage to transistors 522, 524, and 530, so that any noise injected into the gate will cause the gate voltage to change similarly. The above is kept constant, and the accuracy is therefore 'the existence of noise. The positive result of the comparison result = the amplification of the voltage of 571. The voltage of the input 590 and the reading of the cloth will become tighter. If the input 590 is sensed, the current input circuit 590 and the held current circuit 310 are used to offset the reference input = high ^ degrees. When using the reference current voltage correlation: therefore, the slice, the time required for the test and the critical power of the reference cell are not performed for a while. Using the Sampling and Protection 19 201133504 bias reference node, the reference input 595 is charged quickly when the time required to reach the reference is obtained. Using the reference current circuit, the second practical off-sampling and holding-in current circuit 310 is not to be considered. It is implemented in the PMOS transistor in Fig. 7. The *=== of the operational amplifier 54〇 is connected to the reference, and the negative feedback path between the output 542 and the negative input 544. Fig. 8 is a schematic view showing the second circuit 31A of the third embodiment of the present invention. In Fig. 8, the electric day f current is selectively connected to the ground by the switch 526, and the second $2 is connected instead of the input of the operational amplifier 546. The coupled capacitor is used to improve the reaction time of the closed loop. , 'a Figure 9 shows a schematic diagram of the circuit of the fourth embodiment of the present invention, which includes: == === to set the voltage of the input 546, 544 to phase ί?ί and 906 to signal two : Kai. It is: the negative input 544 is coupled to the ground and the positive output 546 is coupled to the ^. The voltage across the capacitor C3 9〇〇 is the same as the input 546, 54. The switch 9〇2 and 9〇6 are then turned off and the switch _ is turned on. Thus, node 9〇8 is connected to _, which provides a specialization path through '^=3, so the voltage of input 544 and the voltage of input 546 are set. Although the invention has been described with reference to the embodiments, The inventive creations are not limited by the detailed description thereof. The alternatives and modifications to the styles are already in place, and the alternatives and modifications will be familiar to this person. In particular, all of the materials that are substantially identical to the present invention to achieve substantially the same results as the present invention are not intended to be used in the present invention. This patent is defined by the scope of the patent and its equivalent. 20 201133504 [Simplified description of the drawings] The present invention is defined by the scope of the patent application. The features, and embodiments, will be described in the following embodiments, in which: the early matching pattern is shown in Figure 1 by the schematic diagram of the conventional memory device diagram of the surface extreme sensing mechanism. The voltage change of the sense input of the amp and the time of the third figure shows a brief block of the integrated circuit. The description is used to describe the source-end sensing technique: and hold (b) one of the four methods In the column of the record, the memory cell is selected for the sensing operation. Fig. 5 is a schematic view showing the circuit for sinking and holding the current sample used in the first embodiment of the present invention. . The ^ diagram shows the timing diagram of the sampled and held no-current circuit shown in Figure 5.

Fig. 7 is a schematic view showing a circuit for sinking and holding the sampling and holding in the memory array according to the second embodiment of the present invention. Fig. 8 is a schematic view showing a sampling and holding current input circuit used in a memory array according to a third embodiment of the present invention. Fig. 9 is a view showing sampling used in a memory array according to a fourth embodiment of the present invention. A schematic diagram of the current input circuit. [Main component symbol description] 110, 510: Select memory cell 112 '212, 511: source terminal, 114, 214, 512: drain terminal 120, 220: word line 130, 132, 230, 232: bit line 21 201133504 140, 142: row select transistor 150: data line 160: reference line 170, 544, 571: sense amplifier 172, 590: sense input 174, 595: reference Inputs 176, 596: Sensing Output 210: Reference Cell 300: Integrated Circuit 310, 520: Sampling and Holding Inrush Current Circuit 320: Memory Array 324: Word Lines 322, 344: Column Decoder 328: Bit Line 332: data bus 326, 342: row decoder 330: source extreme sense amplifier / data input structure 340: reference array 343: reference bit line 345: reference word line 346, 350: bus 352: data input line 354: data output line 360: other electricity 368: Adjusting the bias supply voltage 369: controller 522, 524: transistor 525: holding capacitor C1 526, 570: switching switch 530: load transistor 22 201133504 532: negative booster 544: negative input 546: positive input 560 : reference cell 561: reference cell's drain terminal 562: reference cell source terminal 572a, 572b: node 574: holding capacitor C2 576: output signal 580, 584: discharge transistor 586: discharge 1 582: discharge 2

Claims (1)

201133504 VII. Patent Application Range·· 1. A 5 memory device comprising: a memory array having a data line and a reference current line; a φ2t input current circuit including coupling to the data line via a switch Connected to a battery, and a sense amplifier circuit coupled to the data line and the reference current line. 2. The memory device of claim 1, wherein the inrush current circuit further comprises a second switch selectively coupled to the reference current line. 3. The memory device of claim 1, wherein the memory device of the first aspect is further configured to provide a reference current to the reference current line, and wherein the memory array is arranged to provide - read Taking the current from the column and taking the memory cell to the data line; T Ray can be used in response to an operation between the first node and the second node, the feedback path f can be used to respond to the magnitude of the reference current]; S5 Z and The first is the operating voltage, the 11th round of the capacitor is at the first disc === the voltage of the sang, and the switch can be used to cause the i-phased path during the -first time, and in the Disabling the feedback path in a time interval; and the sense, the amplification circuit responds to the difference between the inrush currents in the second time interval, and the production seat instructs the child to read the motor, and recalls The (four) value of the cell loses $ money. ... stored in the selected memory 4 includes a memory device as described in the patent application model _3, the source current source 201133504 at the second f flow mirror 'which is connected to the data line and the reference current source, the current The mirror reference current source f receives the reference current, and can introduce the inrush current from the data line in response to the reference power "α size; the second transistor has a first and second conduction terminal and a control circuit End, the electric catch and the m electric μ, wherein the capacitor is turned on between the terminals to be in the second time interval with the jth transistor; and the ntp is maintained at the negative cut-off operational amplifier, the operation put *Cry 1 ancient knot _ 接 '- the second input and the reference current work and = through the switch and the load transistor of the control end ^ ^ out selection 5. As claimed in the fourth item In the memory device, the current mirror includes a first transistor and a second electrical terminal, each control terminal and the first and second conductive terminals, and the first terminal has a control terminal 1 including the second transistor. = H-terminal is lightly connected to the reference current source, and the first guide of the body The second conductive terminal of the first transistor of the second transistor is coupled to the second conductive terminal of the first conductive terminal of the first conductive terminal of the cathode; and The control circuit of the first transistor and the second transistor further includes a second second transistor coupled to the == between the first terminal and the conductive terminal. The second 6. The memory path of the first transistor, as described in claim 4, further includes - the second switching - can be switched in the middle of the current - and the control terminal of the second transistor is switched The operation between the first and the voltages is used to deactivate the first and second voltages. The memory device of claim 6, wherein the control terminal of the first and second transistors is selectively coupled to the second switch via the second switch The second round of the computing device is engaged. 8. A method of sensing a memory cell, the method comprising: applying a bias voltage to the memory cell to induce a read current from the memory cell to a data line; providing a reference current from a reference current source; Introducing an inrush current from the data line between the first and second nodes, comprising: using a feedback path to respond to the magnitude of the reference current in a first time interval The operating voltage between the first and second nodes; and maintaining the operating voltage between the first and second nodes independent of the feedback path in a second time interval subsequent to the first time interval And determining a data value stored in the memory cell in the first time interval according to a difference between the read current and the inrush current. 9. For example, the method described in claim 8 of the patent scope further includes: ## In the second time interval, according to the ratio between the read current and the inrush current, the voltage on the sensing node is set, and the bias voltage - reference node to a reference is I and the decision is made therein The step of storing the data value in the memory cell includes a difference between the voltage and the reference voltage of the reference node to determine the stored data value. 1〇. A memory device comprising: 驭Φ recall array can be selected from the memory array to select a memory cell to read current to the data line; a reference current source can provide a reference current; 26 201133504 An inrush current circuit coupled to the data line, the inrush current circuit can introduce an inrush current from the data line, and the inrush current circuit can be used to enable a feedback path in a first interval Establishing the inrush current, and disabling the feedback path and maintaining the current, and the B current in a second time interval after the first 'interval, and - the sense amplifying circuit is coupled to the data line, The difference-g between the read current and the inrush current in the second time interval of the sensed amplification soil is generated by the -four-valued round-out signal stored in the selected memory cell. 27