201131959 六、發明說明： 【發明所屬之技術領域】 於本專利文件中所描述的技術大致關係於交換式電源 供應器。 【先前技術】 在典型交換式電源供應器中，交換頻率係爲固定的或 可以隨著負載變輕而增加，經常造成在輕負載時的效率低 落及平均效率低落。交換式電源供應器典型也包含電流控 制器，其將峰値電流限制爲一固定値，經常造成在輕負載 時的音響雜訊。 【發明內容】 依據於此之教導，提供了具有多模控制器之交換式電 源供應器。交換式電源供應器可以包含變壓器，其具有一 次繞組及二次繞組，以供電給負載。也可以包含一回授電 路，以產生相關於在二次繞組上之負載變化的回授信號。 該多模控制器可以包含交換電路、頻率控制電路及電流限 制電路。交換電路可以耦接至該一次繞組，以控制流經該 一次繞組的電流。該頻率控制電路可以根據該回授信號， 控制該交換電路的交換頻率。該電流限制電路可以藉由使 得當流經該一次繞組的電流到達根據該回授信號所設定的 峰値電流限制時，暫停該電流，而限制流經該一次繞組的 電流。 -5- 201131959 一種控制交換式電源供應器的方法可以包含以下步驟 :藉由以一交換頻率，而交換變壓器的導通及關斷，而調 節該交換式電源供應器的輸出電壓；產生一回授信號，其 係相關於耦接至該輸出電壓的負載而變化；根據該回授信 號，而控制該交換頻率；及根據該回授信號，限制流經該 變壓器的一次繞組的峰値電流。 【實施方式】 圖1爲具有多模控制器1 02的例示交換式電源供應器 100的電路圖。該交換式電源供應器100包含整流器橋 104、變壓器106、回授電路108及多模控制器102。在此 例子中，該變壓器1 06包含一次繞組1 1 0、主二次繞組 112、及次二次繞組114。操作中，整流器橋104接收一 交流輸入電壓（VAC)，其被轉換爲變壓器106的一次繞 組〗1 〇所接收的直流輸入電壓》變壓器1 06係爲多模控制 器102所控制，以在變壓器1〇6的二次繞組112、114上 產生直流輸出電壓。多模控制器1 02控制流經變壓器的一 次繞組1 1 0的電流，以有效地切換變壓器1 06爲導通及關 斷。主二次繞組112供給輸出電壓（V0UT)至負載1 10及 次二次繞組1 1 4提供直流電壓源（Vcc )至多模控制器 102。如於圖1所示有：輸入電容（ClN)，其儲存及濾波 直流輸入電壓；LC電路（L,、C!、C2)，儲存及濾波直 流輸出電壓（ ν〇υτ);二極體電路，其防止電流流回至一 次繞組1 1 2、1 1 4 ;及RCD緩衝器電路，連接於一次繞組 201131959 1 1 0之間。 回授電路108產生回授信號（FB )，其係反比於變 壓器1 06的主二次繞組1 1 2上的負載1 1 0。如以下所詳述 ，回授信號（FB )係爲多模控制器1 02所使用，以控制 變壓器106的交換頻率及峰値電流成爲負載的函數。另外 ，回授電路108提供電壓調整器，其可以用以調整該直流 輸出電壓（V0UT )至想要位準。更明確地說，回授電路 108包含分路調整器118及光耦合器120、122。想要直流 電壓輸出（V0UT)可以藉由改變在分路調整器118中之電 阻値加以設定。光耦合器包含光二極體1 20及光電晶體 122。在操作中，爲光二極體120所發射的光之強度係反 比於負載116。當光二極體120的強度增加時，使得光電 晶體122導通，而產生回授信號（FB)。因此，回授信 號（FB)係反比於負載116，即當負載116變輕時，回授 信號增加，及當負載116變重時，則回授信號降低。然而 ，應了解的是，在其他例子中回授電路108及多模控制器 1 02可以被組態使得回授信號（FB )正比於負載，或相關 於該負載改變。 多模控制器1 0 2包含交換電路，其控制流經變壓器 1 06的一次繞組1 1 〇的電流。因此，供給至負載1 1 6的功 率可以藉由改變交換電路交換流經一次繞組1 1 0的電流的 導通與關斷的頻率而加以控制。這經常被稱爲變壓器的交 換頻率。多模控制器1 02更包含頻率控制電路，其控制交 換頻率成爲回授信號（FB)的函數，該回授信號係反比 201131959 於在變壓器主二次繞組112上的負載116。另外，多模控 制器1 02包含電流限制電路，其藉由使得當電流到達峰値 電流限制時’交換電路暫停流經一次繞組1 1 0的電流，而 設定最大峰値電流，該峰値電流限制係被控制爲回授信號 (FB)的函數。以此方式，交換頻率及最大峰値電流可 以根據負載1 1 6加以調整，以改良系統效能。例如，多模 控制器1 02可以組態以使得交換頻率隨著負載n 6變輕而 降低’以在較輕負載提供高效率及高平均效率。多模控制 器1 02可以更被組態以設定峰値電流限制，成比例於負載 116’以防止在較輕的負載的變壓器1〇6的機械諧振。 圖2描繪例示多模控制器200，其可以被使用於圖1 的交換式多模控制器1 00。該多模控制器200包含一交換 電路202、頻率控制電路204、電流限制電路206及叢發 模式控制電路 208、210、228»交換電路 202包含一 MOSFET開關211、RS正反器212、邏輯閘215及驅動器 217。頻率控制電路204包含電流源213、電子開關214( 例如MOSFET開關）、比較器216、齊納二極體218、電 壓除法器220及延遲電路221。頻率控制電路204同時也 包含如圖1所示之外部電容（Ct )。電流限制電路206包 含前緣遮沒（LEB )電路2U、比較器224、電壓參考（ VSENSE) 226及電壓減法器228。電流限制電路206更包 含如圖1所示之外部電阻（Rsense )。叢發模式控制電路 包含一史密特觸發器比較器208、電壓參考210及電壓減 法器228。 201131959 在操作中，頻率控制電路204提供電壓控制振盪器， 其根據在節點230的電壓，控制MOSFET211的交換頻率 。明確地說，當RS正反器212的Q輸出於邏輯低狀態時 ，MOSFET開關21 1及電子開關214均爲斷開。這使得電 流源2 1 3充電外部電容（Ct )，藉以增加在比較器2 1 6的 正端的電壓。當此電壓到達在節點23 0的臨限電壓時，邏 輯高信號係由比較器216輸出至正反器212的S輸入，使 得Q輸出轉移至邏輯高狀態。當RS正反器212的Q輸出 轉移至邏輯高狀態時，MOSFET開關21 1閉合預設時間（ Tpulse )，使得外部電容（Ct)放電至零。因此， MOSFET開關21 1的交換頻率可以藉由改變在節點23 0的 電壓而加以控制。取決於如下參考圖3及圖4所述之控制 器200的操作模式，在節點23 0的電壓可以爲回授信號（ FB)或齊納二極體218的崩潰電壓（VZENER)所決定。 電流限制電路206藉由比較多模控制器200的源極端 處的電壓（即外部RSENSE電阻間之電壓）與在節點240 的臨限電壓，控制經由一次繞組的峰値電流。LEB電路 222係爲已知電路，其藉由引入一短延遲，而降低在信號 中之尖波。當在比較器224的正端的電壓到達在節點240 的臨限電壓時，邏輯高信號係由比較器224輸出至正反器 2 12的R輸入，使得MOSFET開關212斷開並暫停電流流 經一次繞組。取決於如下所述之控制器200的操作模式， 在節點240的電壓可以藉由回授信號（VSUB-VFB )或參考 電壓（Vsense) 226加以決定。 ς -9- 201131959 叢發模式控制電路208、210、22 8使得MOSFET開 關2 1 1斷開，暫停電流流經一次繞組，當回授信號（FB )表示在變壓器主二次繞組上的負載已經下降低於預定最 小負載臨限（Vbrl )。在操作中，史密特觸發器比較器 208比較電壓減法器228的輸出（VSUB-VFB)與電壓參考 210。當電壓減法器輸出（VSUB-VFB)下降低於電壓參考 値VBRL (即，史密特觸發器比較器208的導通電壓）時 ，邏輯高信號係由比較器20 8輸出至交換電路2 02中之邏 輯閘215，這旁路交換脈衝（fs )並使得MOSFET開關 211斷開。當電壓減法器輸出（Vsub-Vfb)，則上升超出 VBRH (即，史密特觸發器比較器208的關斷電壓）時，則 交換脈衝（fs)將再導通。此操作將持續，以一週期爲基 礎地交換脈衝（fs )導通及關斷，直到電源供應器關斷或 者負載增加’使得Vsub-Vfb保持超出Vbrh" 圖3及4分別顯示圖2的多模控制器200的四模式及 三模式操作。多模控制器200可以如被組態以藉由選擇用 於齊納二極體218、電壓減法器228及叢發模式電壓參考 (Vbr) 210的適當値，而操作爲四模或三模控制器。明 確地說，示於圖3的四模操作3 00可以藉由選擇用於多模 控制器200的設計參數，使得Vsub-Vzener>VBRl，其中 VZENER爲齊納二極體218的崩潰電壓，而提供如圖3所示 之四模操作300。示於圖4的三模操作400可以藉由選擇 設計參數》使得Vsub-VzenerCVbrl而加以提供。 首先，參考圖3，此圖3 00包含兩圖表，其分別描繪 -10- 201131959 圖2的多模控制器200如何使得交換頻率（fs )及峰値電 流相關於在四操作模式中之負載改變。在用於最重負載的 操作模式1中，交換頻率改變成爲負載的函數及峰値電流 保持不變。參考圖2，在操作模式1期間，反比於負載的 回授信號電壓（VFB)係低於齊納二極體218崩潰電壓（ 即，Vfb<Vzener)。因此，模式1中，在圖2的頻率控制 電路204中的節點23 0的電壓係由回授信號（FB )決定 ，及交換頻率（fs)係相關於在圖3中之參考310所示的 負載改變。同時，在模式1中，電壓減法器228的輸出係 大於圖2的電流限制電路206的參考電壓（VSENSE )(即 Vsub-Vfb>Vsense)。因此，在模式1中，在節點240的 電壓係爲參考電壓（V SENSE)所決定，及峰値電流保持不 變，如圖3中之參考312所示。明確地說，在模式1中， 交換頻率可以被表示爲：fs=l/[(Ct*VFB/ICt) +TPULSE]。 在如圖3的操作模式2期間，交換頻率及峰値電流改 變成爲負載的函數。參考圖2，在操作模式2中，回授信 號電壓（VFB)保持低於齊納二極體218的崩潰電壓（即 VFB<VZENER) ’因此，交換頻率（fs)相關於如圖3所示 之參考314的負載改變。明確地說，在操作模式2中，交 換頻率可以被表示爲：fs=l/[ ( Ct*VFB/ICt ) +TPULSE]。同 時，在操作模式2中’電壓減法器228(VSUB-VFB)下降 低於電流限制電路206中的參考電壓（vSENSE)(即， VSUB-VFB<VSENSE)。因此，在操作模式2中，在節點240 之電壓爲回授信號（Vsub-Vfb)的函數，及峰値電流相關 -11 - 201131959 於圖3之參考316所示之負載加以改變。 如圖3所示，在操作模式3期間，峰値電流改變爲負 載的函數及交換頻率（fs)保持不變。參考圖2，在操作 模式3中，回授信號電壓（VFB)變成大於齊納二極體 218的崩潰電壓（即，VFB>VZENER)，因此，齊納二極體 218將在節點230的電壓嵌位於其崩潰電壓（VZENER)。 這使得交換頻率（fs)保持不變，如圖3中之參考318所 示。明確地說，在模式3中，交換頻率可以被表示爲： fs=l/[Ct*VZENER/ (let) +TpuLSE]。同時，在操作模式 3 中，電壓減法器228的輸出（VSUB-VFB)保持低於參考電 壓（VsENSE)(即 ’ VsUB-Vi：B<VsENSE)。因此，峰値電 流相關於圖3中之參考320所示之負載改變。 當負載下降低於最小負載臨限時，多模控制器進入叢 發模式，這係如圖3中之操作模式4所示。參考圖2，在 操作模式4 (即，叢發模式），電壓減法器228的輸出（ Vsub-Vfb)下降低於 VBRL (即，Vsub-Vfb<Vbrl)。這使 得在圖2中之MOSFET開關211斷開，造成沒有交換脈 衝（fs)或電流流經一次繞組，如圖3之參考322及324 所不。當電壓減法益輸出（Vsub_Vfb)上升超出Vbrh， 交換脈衝（fs )將再導通。 現參考圖4，此圖400包含兩圖表，其分別描述圖2 的多模控制器200使得交換頻率（fs )及峰値電流相關於 三操作模式中之負載而改變。示於圖4的三模式操作係類 似於參考圖3所述之四模式操作，除了當負載減少時，多 -12- 201131959 模控制器1 02直接由模式2轉移至叢發模式。如上所解釋 ，如圖4所示之多模控制器200的三模操作可以藉由選擇 設計參數使得Vsub-Vzener<Vbrl加以完成。 圖5爲另一例示多模控制器500的圖，其可以用於圖 1之交換式電源供應器1 00中。此例係類似於參考圖2所 述之多模控制器200，除了齊納二極體係以電壓參考（ Voffset ) 5 02替換，及一信號選擇電路（在圖中以兩二極 體504、506表示）以修改頻率控制電路5 08的操作。另 外，信號選擇電路509、51 1的方向係相反，以修改電流 限制電路5 1 3的操作。明確地說，在此例子5 00中，取決 於控制器500的操作模式，在控制M0SFET開關512的 交換頻率之節點510之臨限電壓係由回授信號（FB)或 電壓參考（V0FFSET) 502決定。即，信號選擇電路504、 5〇6使得在節點510的電壓係爲電壓參考（V0FFSET) 502 或回授信號電壓（VFB)中之較大者。同時，控制峰値電 流限制之在節點516的臨限電壓係爲回授信號（VSUB-VFB )或電壓參考（Vs ENSE) 520之較大者所決定。 圖6及7分別顯示圖5的多模控制器500的四模及三 模操作。例如，多模控制器500可以被組態藉由選擇用於 電壓參考（V0FFSET) 502、電壓減法器514及電壓參考（ VsENSE ) 520的適當値，而操作爲四模或三模控制器。明 確地說，如圖7所示之三模操作700可以藉由選擇設計參 數使得Vsub-V〇ffset = Vsense而加以提供。示於圖6的四 模操作 600可以藉由選擇設計參數使得 VsuB- -13- 201131959 V〇ffset〉Vsense而加以提供。 首先，參考圖6，此圖6 00包含兩圖表，分別描繪圖 5的多模控制器5 00如何使得交換頻率（fs )及峰値電流 相關於四操作模式中的負載而改變。在用於最重負載的操 作模式1中，峰値電流改變成爲負載的函數及交換頻率保 持不變。參考圖2，在操作模式1中，反比於負載的回授 信號的電壓（VFB)係低於電壓參考（V0FFSET)。因此， 在模式1中，在節點510的電壓係被電壓參考（V0FFSET )所嵌位於固定値，及交換頻率（fs)保持不變，如圖6 中之參考610所示。明確地說，在模式1中，交換頻率可 以表示爲：fs=l/[ ( Ct*V0FFSET/ICt) +TPULSE]。同時，在 操作模式1中’電壓減法器（VSUB-VFB) 514的輸出大於 電壓參考（VsENSE) 520 (即 ’ VsuB-VfbSVsENSE)。因此 ’在模式1中，在電流限制電路中之節點5 1 6的電壓係爲 回授信號（VSUB-VFB )的函數，及峰値電流相關於示於圖 6的參考612之負載而改變。 在操作模式2中，如圖6所示，交換頻率（fs)及峰 値電流均改變爲負載的函數。參考圖5，在操作模式2中 ’回授信號的電壓（VFB)上升超出電壓參考（vOFFSET) ’因此’在節點5 1 0的電壓係爲回授信號（FB )所決定 ’使得交換頻率（fs)相關於圖6之參考614所示之負載 改變。明確地說，在操作模式2中，交換頻率（fs )可以 被表示爲：fs=l/[ ( Ct*V0FFSET/lCt ) +TPULSE]。同時，在 模式2中’電壓減法器514的輸出（vsub_Vfb)保持大於 •14- 201131959 電壓參考（VSENSE) 520，因此，峰値電流持續相關於圖6 之參考6 1 6所示之負載改變。 在操作模式3中，如圖6所示，交換頻率（fs)改變 爲負載的函數及峰値電流爲不變。參考圖5’在操作模式 3中，回授信號的電壓（VFB)保持於電壓參考（V0FFSET )之上，因此，交換頻率（fs)持續相關圖6之參考618 所示之負載改變。同時，在操作模式3中，電壓減法器 514的輸出（VSUB-VFB)下降低於電壓參考（VSENSE) 520 ，因此，峰値電流係爲電壓參考（Vsense) 520所嵌位於 固定値，如圖6的參考620所示。 當負載下降低於最小負載臨限時，多模控制器進入叢 發模式，其係如圖6之操作模式4所示。參考圖5，在操 作模式4(即叢發模式）中，電壓減法器514的輸出下降 低於電壓參考値 Vbrl522 (即，Vsub_Vfb<Vbrl)。這使 得MOSFET開關512斷開，造成沒有交換脈衝（fs)或電 流流經一次繞組，如圖6的參考6 2 2及6 2 4所示。當電壓 減法器輸出（VSUB-VFB)上升超出vBRH時，交換頻率（ fs)將再導通。 現參考圖7’此圖7 00包含兩圖表，分別描繪圖5的 多模控制器5 0 0如何使交換頻率（fs )及峰値電流在三個 操作模式中相關於負載作改變。示於圖7的三模操作係類 似於參考圖6所述之四模操作，而沒有一模式，其中交換 頻率（fs)及峰値電流係同時改變爲負載的函數。換句話 說’圖6的操作模式2並未提供在圖7所示之三模操作中 -15- 201131959 。如上所解釋，如圖7所示之多模控制器5 00的三模操作 可以藉由選擇設計參數，使得VsUB-V〇FFSET = VsENSE加以 執行。 此文中之說明使用例子，以揭示包含最佳模式之本發 明，同時使熟習於本技藝者完成及使用本發明。本發明之 可專利範圍可以包含爲熟習於本技藝者所知之其他例子。 【圖式簡單說明】 圖1爲具有多模控制器的例示交換式電源供應器電路 圖。 圖2爲用於交換式電源供應器的例示多模控制器的電 路圖。 圖3爲圖2的多模控制器的例示四模式操作圖。 圖4爲圖2的多模控制器的例示三模式操作圖。 圖5爲用於一交換式電源供應器的另一例示多模控制 器電路圖。 圖6爲圖5的多模控制器的例示四模式操作圖。 圖7爲圖5的多模控制器的例示三模式操作圖。 【主要元件符號說明】 1〇〇 :交換式電源供應器 102 :多模控制器 104 :整流橋 106 :變壓器 •16- 201131959 1 08 :回授電路 1 1 〇 : —次繞組 1 1 2 :主二次繞組 1 1 4 :次二次繞組 1 16 :負載 1 1 8 :分路調整器 120 :光二極體 1 2 2 :光電晶體 2 0 0 :多模控制器 202 :交換電路 204 :頻率控制電路 206 :電流限制電路 208 :叢發模式控制電路 2 1 0 :叢發模式控制電路 2 11： MOSFET 開關 2 1 2 : RS正反器 2 1 3 :電流源 2 1 4 :電子開關 2 1 5 :邏輯閘 2 1 6 :比較器 2 1 7 :驅動器 2 1 8 :齊納二極體 220:電壓除法器 221 :延遲電路 -17 201131959 222:前緣遮沒電路 224 :比較器 226 :電壓參考 228:電壓減法器 2 3 0 :節點 2 4 0 :節點 5 00 :多模控制器 5 02 :電壓參考 5 04 :二極體 5 06 :二極體 5 0 9 :信號選擇電路 5 1 0 :節點 5 1 1 :信號選擇電路 5 12： MOSFET 開關 5 1 3 :電流限制電路 514 :電壓減法器 5 1 6 :節點 5 20 :電壓參考 5 2 2 :電壓參考値201131959 VI. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The technology described in this patent document is roughly related to an exchange power supply. [Prior Art] In a typical switched power supply, the switching frequency is fixed or can be increased as the load becomes lighter, often resulting in low efficiency and low efficiency at light loads. Switched power supplies typically also include a current controller that limits the peak 値 current to a fixed 値, often resulting in acoustic noise at light loads. SUMMARY OF THE INVENTION In accordance with the teachings herein, a switched power supply having a multimode controller is provided. The switched power supply can include a transformer having a primary winding and a secondary winding to supply power to the load. A feedback circuit can also be included to generate a feedback signal related to load changes on the secondary winding. The multimode controller can include a switching circuit, a frequency control circuit, and a current limiting circuit. A switching circuit can be coupled to the primary winding to control the current flowing through the primary winding. The frequency control circuit can control the switching frequency of the switching circuit according to the feedback signal. The current limiting circuit can limit the current flowing through the primary winding by causing the current flowing through the primary winding to reach a peak current limit set according to the feedback signal. -5- 201131959 A method of controlling a switched power supply can include the steps of: adjusting an output voltage of the switched power supply by switching the turn-on and turn-off of the transformer at a switching frequency; generating a credit No., which is related to a load coupled to the output voltage; controlling the switching frequency according to the feedback signal; and limiting a peak current flowing through the primary winding of the transformer according to the feedback signal. [Embodiment] FIG. 1 is a circuit diagram of an exemplary switched power supply 100 having a multimode controller 102. The switched power supply 100 includes a rectifier bridge 104, a transformer 106, a feedback circuit 108, and a multimode controller 102. In this example, the transformer 106 includes a primary winding 110, a primary secondary winding 112, and a secondary secondary winding 114. In operation, the rectifier bridge 104 receives an AC input voltage (VAC) that is converted to the primary winding of the transformer 106. The received DC input voltage is controlled by the multimode controller 102 to be in the transformer. A DC output voltage is generated across the secondary windings 112, 114 of 1〇6. The multimode controller 102 controls the current flowing through the primary winding 1 10 of the transformer to effectively switch the transformer 106 to be turned "on" and "off". The primary secondary winding 112 supplies an output voltage (VOUT) to the load 1 10 and the secondary secondary winding 1 1 4 provides a DC voltage source (Vcc) to the multimode controller 102. As shown in Figure 1, there is an input capacitor (ClN) that stores and filters the DC input voltage; LC circuits (L, C, C2), which store and filter the DC output voltage ( ν 〇υ τ); , which prevents current from flowing back to the primary winding 1 1 2, 1 1 4 ; and the RCD snubber circuit, connected between the primary winding 201131959 1 1 0. The feedback circuit 108 generates a feedback signal (FB) which is inversely proportional to the load 1 1 0 on the primary secondary winding 1 1 2 of the transformer 106. As detailed below, the feedback signal (FB) is used by the multimode controller 102 to control the switching frequency and peak current of the transformer 106 as a function of load. Additionally, feedback circuit 108 provides a voltage regulator that can be used to adjust the DC output voltage (VOUT) to a desired level. More specifically, the feedback circuit 108 includes a shunt regulator 118 and optocouplers 120,122. The desired DC voltage output (VOUT) can be set by changing the resistance in the shunt regulator 118. The optical coupler includes a photodiode 1 20 and a phototransistor 122. In operation, the intensity of the light emitted by the photodiode 120 is inversely proportional to the load 116. When the intensity of the photodiode 120 is increased, the phototransistor 122 is turned on to generate a feedback signal (FB). Therefore, the feedback signal (FB) is inversely proportional to the load 116, i.e., when the load 116 becomes lighter, the feedback signal increases, and when the load 116 becomes heavier, the feedback signal decreases. However, it should be understood that in other examples the feedback circuit 108 and the multimode controller 102 can be configured such that the feedback signal (FB) is proportional to the load or is related to the load change. The multimode controller 102 includes a switching circuit that controls the current flowing through the primary winding 1 1 变压器 of the transformer 106. Therefore, the power supplied to the load 1 16 can be controlled by changing the frequency at which the switching circuit switches the conduction and the off current flowing through the primary winding 110. This is often referred to as the switching frequency of the transformer. The multimode controller 102 further includes a frequency control circuit that controls the switching frequency as a function of the feedback signal (FB), which is inversely proportional to the load 116 on the primary secondary winding 112 of the transformer. In addition, the multimode controller 102 includes a current limiting circuit that sets a maximum peak current, which is set by causing the switching circuit to suspend the current flowing through the primary winding 1 1 0 when the current reaches the peak current limit. The restriction is controlled as a function of the feedback signal (FB). In this way, the switching frequency and maximum peak current can be adjusted according to the load 1 16 to improve system performance. For example, the multimode controller 102 can be configured to reduce the switching frequency as the load n6 becomes lighter to provide high efficiency and high average efficiency at lighter loads. The multimode controller 102 can be more configured to set the peak current limit, proportional to the load 116' to prevent mechanical resonance of the transformer 1〇6 at the lighter load. 2 depicts an exemplary multimode controller 200 that can be used with the switched multimode controller 100 of FIG. The multimode controller 200 includes a switching circuit 202, a frequency control circuit 204, a current limiting circuit 206, and a burst mode control circuit 208, 210, 228. The switching circuit 202 includes a MOSFET switch 211, an RS flip flop 212, and a logic gate. 215 and driver 217. The frequency control circuit 204 includes a current source 213, an electronic switch 214 (e.g., a MOSFET switch), a comparator 216, a Zener diode 218, a voltage divider 220, and a delay circuit 221. The frequency control circuit 204 also includes an external capacitor (Ct) as shown in FIG. The current limiting circuit 206 includes a leading edge blanking (LEB) circuit 2U, a comparator 224, a voltage reference (VSENSE) 226, and a voltage subtractor 228. The current limiting circuit 206 further includes an external resistor (Rsense) as shown in FIG. The burst mode control circuit includes a Schmitt trigger comparator 208, a voltage reference 210, and a voltage subtractor 228. In operation, frequency control circuit 204 provides a voltage controlled oscillator that controls the switching frequency of MOSFET 211 based on the voltage at node 230. Specifically, when the Q output of the RS flip-flop 212 is in a logic low state, both the MOSFET switch 21 1 and the electronic switch 214 are turned off. This causes the current source 2 1 3 to charge the external capacitor (Ct ), thereby increasing the voltage at the positive terminal of the comparator 2 16 . When this voltage reaches the threshold voltage at node 23 0, the logic high signal is output by comparator 216 to the S input of flip flop 212, causing the Q output to transition to a logic high state. When the Q output of the RS flip-flop 212 transitions to the logic high state, the MOSFET switch 21 1 is turned off for a preset time (Tpulse), causing the external capacitor (Ct) to discharge to zero. Therefore, the switching frequency of the MOSFET switch 21 1 can be controlled by changing the voltage at the node 23 0 . Depending on the mode of operation of controller 200 as described below with reference to Figures 3 and 4, the voltage at node 23 0 can be determined by the feedback signal (FB) or the breakdown voltage (VZENER) of Zener diode 218. The current limiting circuit 206 controls the peak current through the primary winding by comparing the voltage at the source terminal of the multimode controller 200 (i.e., the voltage between the external RSENSE resistors) with the threshold voltage at node 240. The LEB circuit 222 is a known circuit that reduces sharp waves in the signal by introducing a short delay. When the voltage at the positive terminal of comparator 224 reaches the threshold voltage at node 240, the logic high signal is output by comparator 224 to the R input of flip-flop 2 12 such that MOSFET switch 212 is turned off and the current is allowed to flow through once. Winding. The voltage at node 240 can be determined by a feedback signal (VSUB-VFB) or a reference voltage (Vsense) 226, depending on the mode of operation of controller 200 as described below. -9 -9- 201131959 The burst mode control circuits 208, 210, 22 8 cause the MOSFET switch 2 1 1 to be turned off, and the current is suspended through the primary winding. When the feedback signal (FB ) indicates that the load on the main secondary winding of the transformer has been The drop is below the predetermined minimum load threshold (Vbrl). In operation, the Schmitt trigger comparator 208 compares the output of the voltage subtractor 228 (VSUB-VFB) with the voltage reference 210. When the voltage subtractor output (VSUB-VFB) falls below the voltage reference 値VBRL (ie, the turn-on voltage of the Schmitt trigger comparator 208), the logic high signal is output by the comparator 208 to the switching circuit 202. The logic gate 215 bypasses the switching pulse (fs) and causes the MOSFET switch 211 to open. When the voltage subtractor output (Vsub-Vfb) rises above VBRH (i.e., the shutdown voltage of the Schmitt trigger comparator 208), the swap pulse (fs) will re-conduct. This operation will continue, switching the pulse (fs) on and off on a cycle until the power supply is turned off or the load is increased 'so that Vsub-Vfb remains above Vbrh". Figures 3 and 4 show the multimode of Figure 2, respectively. The four modes and three modes of operation of the controller 200. The multimode controller 200 can be configured to operate as a four or three mode control by selecting appropriate turns for the Zener diode 218, voltage subtractor 228, and burst mode voltage reference (Vbr) 210. Device. In particular, the four-mode operation 300 shown in FIG. 3 can be made by selecting the design parameters for the multimode controller 200 such that Vsub-Vzener>VBR1, where VZENER is the breakdown voltage of the Zener diode 218, and A four mode operation 300 as shown in FIG. 3 is provided. The three-mode operation 400 shown in Fig. 4 can be provided by selecting the design parameter "Vsub-VzenerCVbrl." First, referring to FIG. 3, this FIG. 3 00 includes two graphs respectively depicting -10-201131959. How the multimode controller 200 of FIG. 2 relates the switching frequency (fs) and the peak 値 current to the load change in the four operating modes. . In Operation Mode 1 for the heaviest load, the switching frequency changes as a function of the load and the peak current remains unchanged. Referring to Figure 2, during operation mode 1, the feedback signal voltage (VFB) inversely proportional to the load is lower than the Zener diode 218 breakdown voltage (i.e., Vfb < Vzener). Therefore, in mode 1, the voltage of the node 23 0 in the frequency control circuit 204 of FIG. 2 is determined by the feedback signal (FB), and the switching frequency (fs) is related to the reference 310 shown in FIG. The load changes. Meanwhile, in mode 1, the output of the voltage subtractor 228 is larger than the reference voltage (VSENSE) of the current limit circuit 206 of Fig. 2 (i.e., Vsub-Vfb > Vsense). Therefore, in Mode 1, the voltage at node 240 is determined by the reference voltage (V SENSE), and the peak-to-peak current remains unchanged, as shown by reference 312 in FIG. Specifically, in mode 1, the switching frequency can be expressed as: fs = l / [(Ct * VFB / ICt) + TPULSE]. During operation mode 2 of Figure 3, the switching frequency and peak-to-peak current change become a function of the load. Referring to FIG. 2, in operation mode 2, the feedback signal voltage (VFB) remains lower than the breakdown voltage of the Zener diode 218 (ie, VFB < VZENER) '. Therefore, the switching frequency (fs) is related to that shown in FIG. The load of reference 314 changes. Specifically, in operation mode 2, the exchange frequency can be expressed as: fs = l / [( Ct * VFB / ICt ) + TPULSE]. At the same time, in operation mode 2, the voltage subtractor 228 (VSUB-VFB) falls below the reference voltage (vSENSE) in the current limit circuit 206 (i.e., VSUB-VFB < VSENSE). Thus, in mode 2, the voltage at node 240 is a function of the feedback signal (Vsub-Vfb), and the peak-to-peak current correlation -11 - 201131959 is varied at the load shown in reference 316 of FIG. As shown in Fig. 3, during operation mode 3, the function of changing the peak current to the load and the switching frequency (fs) remain unchanged. Referring to FIG. 2, in operation mode 3, the feedback signal voltage (VFB) becomes greater than the breakdown voltage of the Zener diode 218 (ie, VFB > VZENER), and therefore, the Zener diode 218 will be at the voltage of the node 230. Embedded in its breakdown voltage (VZENER). This keeps the switching frequency (fs) unchanged, as shown by reference 318 in Figure 3. Specifically, in mode 3, the switching frequency can be expressed as: fs = l / [Ct * VZENER / (let) + TpuLSE]. Meanwhile, in the operation mode 3, the output of the voltage subtractor 228 (VSUB-VFB) is kept lower than the reference voltage (VsENSE) (i.e., 'VsUB-Vi: B<VsENSE). Therefore, the peak current is related to the load change shown by reference 320 in FIG. When the load drops below the minimum load threshold, the multimode controller enters the burst mode, as shown in operation mode 4 in Figure 3. Referring to Figure 2, in mode of operation 4 (i.e., burst mode), the output of voltage subtractor 228 (Vsub-Vfb) drops below VBRL (i.e., Vsub-Vfb < Vbrl). This causes the MOSFET switch 211 in Figure 2 to open, causing no switching pulses (fs) or current to flow through the primary winding, as indicated by references 322 and 324 of Figure 3. When the voltage subtraction gain output (Vsub_Vfb) rises above Vbrh, the switching pulse (fs) will turn back on. Referring now to Figure 4, this diagram 400 includes two graphs that respectively depict the multimode controller 200 of Figure 2 such that the switching frequency (fs) and the peak chirp current are varied in relation to the load in the three modes of operation. The three mode operation shown in Fig. 4 is similar to the four mode operation described with reference to Fig. 3, except that when the load is reduced, the multi-12-201131959 mode controller 102 directly shifts from mode 2 to the burst mode. As explained above, the three-mode operation of the multimode controller 200 as shown in Fig. 4 can be accomplished by selecting design parameters such that Vsub-Vzener < Vbrl. FIG. 5 is a diagram of another exemplary multimode controller 500 that can be used in the switched power supply 100 of FIG. This example is similar to the multimode controller 200 described with reference to FIG. 2, except that the Zener diode system is replaced with a voltage reference (Voffset) 052, and a signal selection circuit (in the figure, two diodes 504, 506 are used). Represented) to modify the operation of frequency control circuit 508. In addition, the direction of the signal selection circuits 509, 51 1 is reversed to modify the operation of the current limiting circuit 51. In particular, in this example 500, depending on the mode of operation of controller 500, the threshold voltage at node 510 that controls the switching frequency of MOSFET switch 512 is either a feedback signal (FB) or a voltage reference (V0FFSET) 502. Decide. That is, the signal selection circuits 504, 5〇6 cause the voltage at the node 510 to be the greater of the voltage reference (V0FFSET) 502 or the feedback signal voltage (VFB). At the same time, the threshold voltage at node 516 that controls the peak current limit is determined by the larger of the feedback signal (VSUB-VFB) or the voltage reference (Vs ENSE) 520. Figures 6 and 7 show the four-mode and three-mode operation of the multimode controller 500 of Figure 5, respectively. For example, multimode controller 500 can be configured to operate as a four or three mode controller by selecting appropriate turns for voltage reference (V0FFSET) 502, voltage subtractor 514, and voltage reference (VsENSE) 520. Specifically, the three-mode operation 700 as shown in Figure 7 can be provided by selecting design parameters such that Vsub-V 〇 ffset = Vsense. The four-mode operation 600 shown in Fig. 6 can be provided by selecting design parameters such that VsuB--13-201131959 V〇ffset>Vsense. First, referring to Fig. 6, this Fig. 6 00 includes two graphs respectively depicting how the multimode controller 5 00 of Fig. 5 changes the switching frequency (fs) and the peak chirp current in relation to the load in the four operating modes. In Operation Mode 1 for the heaviest load, the peak-to-peak current change becomes a function of the load and the switching frequency remains unchanged. Referring to Fig. 2, in operation mode 1, the voltage (VFB) of the feedback signal inversely proportional to the load is lower than the voltage reference (V0FFSET). Therefore, in mode 1, the voltage at node 510 is embedded in the fixed voltage by the voltage reference (V0FFSET), and the switching frequency (fs) remains unchanged, as shown by reference 610 in FIG. Specifically, in mode 1, the switching frequency can be expressed as: fs = l / [( Ct * V0FFSET / ICt) + TPULSE]. At the same time, the output of the 'Voltage Subtractor (VSUB-VFB) 514 in Operation Mode 1 is greater than the Voltage Reference (VsENSE) 520 (i.e., 'VsuB-VfbSVsENSE). Thus, in mode 1, the voltage at node 5 16 in the current limiting circuit is a function of the feedback signal (VSUB-VFB) and the peak current is varied with respect to the load of reference 612 shown in FIG. In operation mode 2, as shown in Fig. 6, the switching frequency (fs) and the peak current are both changed as a function of the load. Referring to FIG. 5, in operation mode 2, the voltage of the feedback signal (VFB) rises beyond the voltage reference (vOFFSET) 'so the voltage at the node 5 10 is determined by the feedback signal (FB)' such that the switching frequency ( Fs) The load change shown in reference 614 of FIG. Specifically, in operation mode 2, the switching frequency (fs) can be expressed as: fs = l / [( Ct * V0FFSET / lCt ) + TPULSE]. At the same time, the output (vsub_Vfb) of the voltage subtractor 514 in mode 2 remains greater than the •14-201131959 voltage reference (VSENSE) 520, so the peak-to-peak current continues to be related to the load change shown in reference 61 of Figure 6. In operation mode 3, as shown in Fig. 6, the switching frequency (fs) is changed to a function of the load and the peak current is constant. Referring to Figure 5' in mode of operation 3, the voltage (VFB) of the feedback signal remains above the voltage reference (V0FFSET), and therefore, the switching frequency (fs) continues to vary with the load shown in reference 618 of Figure 6. Meanwhile, in the operation mode 3, the output of the voltage subtractor 514 (VSUB-VFB) falls below the voltage reference (VSENSE) 520, and therefore, the peak current is the voltage reference (Vsense) 520 embedded in the fixed port, as shown in the figure. Reference 620 of 6 is shown. When the load drops below the minimum load threshold, the multimode controller enters the burst mode, which is shown in operation mode 4 of Figure 6. Referring to Fig. 5, in operation mode 4 (i.e., burst mode), the output of voltage subtractor 514 falls below voltage reference 値 Vbrl 522 (i.e., Vsub_Vfb < Vbrl). This causes the MOSFET switch 512 to open, causing no switching pulses (fs) or current to flow through the primary winding, as shown in references 6 2 2 and 6 24 of Figure 6. When the voltage subtractor output (VSUB-VFB) rises above vBRH, the switching frequency (fs) will turn back on. Referring now to Figure 7', Figure 7 00 includes two graphs depicting how the multimode controller 500 of Figure 5 causes the switching frequency (fs) and the peak chirp current to change in relation to the load in three modes of operation. The three-mode operation shown in Figure 7 is similar to the four-mode operation described with reference to Figure 6, without a mode in which the switching frequency (fs) and the peak-to-peak current are simultaneously changed as a function of load. In other words, the operation mode 2 of Fig. 6 is not provided in the three-mode operation shown in Fig. 7 -15-201131959. As explained above, the three-mode operation of the multimode controller 500 as shown in Fig. 7 can be performed by selecting the design parameters such that VsUB-V 〇 FFSET = VsENSE. The description herein uses examples to disclose the invention, including the best mode of the invention, and the skilled in the art. The patentable scope of the invention may be embodied in other examples that are known to those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of an exemplary switched power supply with a multimode controller. 2 is a circuit diagram of an exemplary multimode controller for a switched power supply. 3 is an exemplary four mode operation diagram of the multimode controller of FIG. 2. 4 is an exemplary three mode operation diagram of the multimode controller of FIG. 2. Figure 5 is a circuit diagram of another exemplary multimode controller for an alternate power supply. 6 is an illustration of an exemplary four mode operation of the multimode controller of FIG. 5. 7 is an exemplary three-mode operation diagram of the multimode controller of FIG. 5. [Main component symbol description] 1〇〇: Switching power supply 102: Multimode controller 104: Rectifier bridge 106: Transformer • 16- 201131959 1 08: Feedback circuit 1 1 〇: - Secondary winding 1 1 2 : Main Secondary winding 1 1 4 : secondary secondary winding 1 16 : load 1 1 8 : shunt regulator 120 : photodiode 1 2 2 : optoelectronic crystal 2 0 0 : multimode controller 202 : switching circuit 204 : frequency control Circuit 206: current limiting circuit 208: burst mode control circuit 2 1 0: burst mode control circuit 2 11: MOSFET switch 2 1 2 : RS flip-flop 2 1 3 : current source 2 1 4 : electronic switch 2 1 5 : Logic gate 2 1 6 : Comparator 2 1 7 : Driver 2 1 8 : Zener diode 220 : Voltage divider 221 : Delay circuit -17 201131959 222 : Leading edge blanking circuit 224 : Comparator 226 : Voltage reference 228: Voltage subtractor 2 3 0 : Node 2 4 0 : Node 5 00 : Multimode controller 5 02 : Voltage reference 5 04 : Dipole 5 06 : Diode 5 0 9 : Signal selection circuit 5 1 0 : Node 5 1 1 : Signal selection circuit 5 12: MOSFET switch 5 1 3 : Current limit circuit 514 : Voltage subtractor 5 1 6 : Node 5 20 : Voltage reference 5 2 2: Voltage reference値