201131825 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種晶圓級封裝之方法，特別是關於半導體 發光元件之封裝方法。 【先前技術】 [0002] 隨著半導體發光元件之需求量日益增加，其封裝之產能 需求也越來越高。因此，許多的技術被揭露出來之目的 在於增加半導體發光元件封裝產能以及生產效率，例如 〇 [0003]201131825 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a method of wafer level packaging, and more particularly to a method of packaging a semiconductor light emitting element. [Prior Art] [0002] As the demand for semiconductor light-emitting elements increases, the demand for packaging capacity is also increasing. Therefore, many technologies have been exposed to increase the packaging capacity and production efficiency of semiconductor light-emitting devices, such as 〇 [0003]
晶圓級封裝（wafer level packa.ge，WLP)技術結合微 機電系統（micro-electromecha.nical 'system, MEMS)，利用黃光（photolithography process)以及 微影技術（1 i thography)將電路設計與晶圓切割在晶圓 級完成以提高產效率以及大量製造，同時亦可以將封裝 結構體積縮小’是符合現代化需求的一.項技術。 然而’晶圓級封裝製程仍有需多問題須待改善。例如美 國專利公開號2007/0202623之技術，其利用晶圓級封裝 • ... ：. .V . 技術製造表面黏著（surf ace齡pjlt)之發光二極體封裝 結構。該項先技藝利用覆晶（flip chip)的技術將發光 二極體晶粒固著於封裝基板上，惟固晶的接著點（bump) 之高度與大小往往不同而造成焊接不良或空銲，導致封 裝元件的失效以及降低製程的良率。 [0004]為解決上述技術之缺失，有一項技術利用底部填充膠 (underfill)來改善上述問題，請參照美國專利公開號 2009/0230409。此項先前技藝利用毛細現象使得封裝膠 滲入晶粒與封裴基板之間的空間中，但其晶粒與封裝基 099106684 表單編號A0101 第3頁/共27頁 0992012096-0 201131825 [0005] [0006] [0007] [0008] 099106684 板之間仍然會有縫隙產生，且造成元件封農不完成且影 響長期可靠㈣，現今仍m新的技術以 克服上述習知技藝的缺失。 【發明内容】 馨於上述發明背景’本發明之目的為提供—晶圓級封裝 之方法，能提升晶圓與封I基板之密合度與—致性。 本發明揭露—種晶圓級封I之方法，包含提供_暫時基 板；形成-半導體元件於該暫時基板上，其中該半導體 元件包含複數個發光單元，並且每-個發光單元具有至 少-正電極以及n極；分別形成複數個凸塊於該發 光單元之該正電極以及該負電極上；形成—第_封裝層 於該暫時基板上並覆蓋該半導體元件；設置~„基板 覆蓋該封裝層’其中該封裝純連結職數個凸塊t移 除該暫時基板；形成1二封裝層於料導體元件上， 其中該第二封裝層與該料基板分職於該半導體元件 之相對兩端；以及，切刻兮、如人 -I该複數個發光單元，形成複數 個半導體發光元件封裳結構。珉複数 藉由上述晶圓級封跋之方法 密合度進而提升製程的良率 【實施方式】 本發明在此所探討的方向 馮種晶圓級封裝之方法。A 了能徹底地瞭解本發明 走馮 步驟及其組成。顯然地，本㈣列的描述中提出詳盡的 體封裝結構之技藝者所熟習的特殊細節。另一 所周知的組成或步驟並去 π曲’承 表單編號顯 h田34於細節中，以避免造成本 共27頁 可增加晶圓與封裴基板之 201131825 [0009] [0010] Ο [0011] G [0012] 發明不必要之限制。本發明的較佳實施例會詳細描述如 下’然而除了這些詳細描述之外，本發明還可以廣泛地 施行在其他的實施例中，且本發明的範圍不受限定，其 以之後的專利範圍為準。 下文將配合圖示與範例’詳細說明本發明提供之各個較 佳實施例及技術内容。 本發明揭露一種晶圓級封裝之方法，能提升晶圓與封裝 基板之岔合度與一致性，其晶圓級封裝之步驟如下所述 請參照圖1 ’首先提供一暫.時基板1〇，其中暫時基板1〇可 以為磊晶基板’例如藍寶石（Al2〇3)基板、碳化矽（Sic) 基板、鋁酸鋰基板（LiAlO )、鎵酸鋰基板（LiGaO )、矽 (Si)基板、氮化鎵（GaN)基板、氧化辞（2n〇)基板、氧化 鋁辞基板（AIZnO)、砷化鎵（GaAs)基板、磷化鎵（GaP) 基板、録化鎵基板（GaSb)、碟化铜（inp)基板、神化銦 (InAs)基板或磁化鋅（ZnSe)基板。 請參照圖2，接著形成一半導體元件丨丨於暫時基板1〇上， 其中半導體元件11可以利用化學氣相沉積法（chemical vapor deposition，CVD)形成，例如有機金屬化學氣 相沉積（metal organic chemicai vapor deposition, M0CVD) 機台或是分子束磊晶 （m〇lecuiar beam epitaxy，MBE)。於本發明較佳的實施例中，半導體元 件11更包含一 P型半導體層111，至少一發光層112以及 一η型半導體層113。而半導體元件n可以為ΠΙ_ν族化 099106684 表單編號Α0101 第5頁/共27頁 0992012096-0 201131825 β物半V體或ιι-νι族化合物半導體。另外，發光層112 包含一單層單異質結構、雙異質結構、單量子井層或多 重量子井層結構，可以發出至少一種波長之光線。 [0013] [0014] [0015] 凊參照圖3，接著將半導體元件n形成複數個發光單元 u〇，其中複數個發光單元HO可以利用黃光及微影技術 形成。此外每一個發光單元11()具有至少一正電極114以 及一負電極115，並且正電極114係電性連結p型半導體層 ill，而負電極115係電性連結n型半導體層113。於本發 明較佳實施例中，正電極114以及負電極115是鎳（Ni)、 鉻（Cr)、金（Au)、銀（Ag>、鉑（Pt)、銅（Cu)、鋅（Zn) 、鈦（T i )、石夕（s i )或其組成的合金，並且利用蒸鍵 (evoaporat ion)或減錄（sputtering)的技術以及钮刻 (etching)技術形成。 請參照圖4 ’接著形成複數個凸塊12a於發光單元11〇之正 電極114上以及複數個凸塊丨2b於負電極11 5上。複數個 凸塊12a與複數個凸塊12b被此不相鄰，並且其材質包含 鎳（Ni)、錫（Sn)、鉻（Cr)、綱（€ir)、金（Au)、銀（Ag) 、斜（Pb)、鉑（Pt)、鋅（Zn)、鈦（Ti)、矽（Si)或其組 成的合金，可以利用鋼板印刷（stencil printing)的 技術製程來形成。 請參照圖5 ’接著形成一第一封裝層13於暫時基板1〇上並 覆蓋複數個發光單元11 0。於本發明一較佳實施例中，第 一封裝層13的材質為環氧樹脂（epoxy)、矽膠 (silicone)或其組合或改質的膠材，並且利用轉注成型 (transfer molding)、旋轉塗佈（spin coating)或 099106684 表單編號A0101 第6頁/共27頁 0992012096-0 201131825 [0016] 〇 [00Π] ❹ [0018] 099106684 注射成型（lnjectlon m〇Iding)之手段形成。 清參照圖6，接著利用研磨HGG研磨（grinding)第― 封裝層13之表面131，使得第一封裝層13之表面ΐ3ι形成 一光滑之平面。值得說明的是，複數個凸塊l2a、12b可 以藉由研磨之步驟，外露出第—封裝層13之表面i3i並形 成平整之外露面；或者’於形成第-封裝層13之步驟時 ’便外露出第-封錢13之表面13卜再藉由研磨之步驟 形成平整之表面。 請參照®7A ’接著提供-封錄板14固定於第-封裝層 13之表面131 ’其中封裝觀14與暫時基板1()分別位於 第-封裝層13之姆兩侧 '封裝基板14包含—電路結構 141 ’其由複數個第-電路結構141&以及複數個第二電路 結構141b所構成。此外，複數個第-電路結構141a與複 數個第二電路結構141b彼此對應且電性連結，其中複數 個發光單元11〇之正、負電極114、115可以分別藉由複 數個凸塊12a、12b以及電路結構141電性導通至封裝基 板14表面之第二電路結構141卜於本發明較佳實施例中 ，封裝基板14可以是印刷電路板（printed circuit board，PCB)、陶究（ceramic)基板、矽（siHc〇n)基 板、金屬基板、氧化矽（Si0)或絕緣膠材等。再者，電路 結構141則為導電材料所組成，例如銅（Cu)、鎳（Ni)、 金（Au)、銀（Ag)或其組合。 請參照圖7B ’於本發明另-較佳實施例中，是利用一黏 著層20將封裝基板14固定於表面131之手段。值得說明的 是，黏著層20可以為異方性導電（anis〇tr〇pic c〇n 表單編號A0101 第7頁/共27頁 0992012096-0 201131825 ductive)的薄膜（film)、膠（gel)或膏（paste)，利用 熱壓轉印（thermal transfer printing)之手段开》成 於第一封裝層13之表面131上。值得說明的是，異方性導 電的材料為導電粒子均勻的散佈在有機樹脂材料中，利 用適當的壓力、溫度及時間使得有機材料開始流動而達 到不同材質相互連結且能夠緊密結合連結材料，同時具 有垂直電性導通而水平電性絕緣的特性。 [0019] [0020] 請參照圖8，接著將暫時基板1〇從複數個發光單元11{)以 及第一封裝層13之底面移除。於本發明較佳的實施例中 ，移除暫時基板10之手段包含了剝離技術（Uft 〇ff)、 蝕刻技術（etching)、切割（cutting)或研磨 (grinding) 〇 請參照圖9A以及圖9B，接著形成一第二封裝層15於複數 個發光單元110以及第一封裝層13之底面上其中第二封 裝層15與封裝基板14分別位於第一封裝層丨3之相對兩侧 。第二封裝層15之材質包含環氧樹脂、矽膠或其組合或 改質的材料’可以·轉注成型、注射成型或旋轉塗佈 之手段形成。再者，第二封裝層15可以包含至少一種波 長轉換單元151，其中波長轉換單元151受到發光單元 11〇之光線激發並發出另一波長之光線。於本發明較佳的 實施例中，波長轉換單元151可以為釔鋁石榴石（YM)、 轼紹石增石（TAG)、料鹽、氮化物、氮氡化物、填化物 、硫化物或其組合。值得說明的是，波長轉換單元151可 以為粉末狀且均勻地摻雜於第二封裝層15中如圖9A所 示；或者，為層狀（layer)之波長轉換單元152且均勾地 099106684 表單編號A0101 第8頁/共27頁 0992012096-0 201131825 [0021] Ο Ο [0022] [0023] 099106684 覆蓋發光單元110之底面，如圖9Β所示，其中波長轉換單 元152可以為薄膜（film)、貼片（patch)或螢光片 (Lumiramic plate)，利用塗覆（coating)、膠 (paste)或喷霧（spray)之手段形成。 請參照圖10A以及圖10B，沿著複數條切割線16切割上述 結構’以形成複數個半導體發光元件封裝結構1，其中每 一個半導體發光元件封裝結構丨包含封裝基板14具有電路 結構141、發光單元11〇、第一封裝層13、波長轉換單元 152以及第二封裝層15。於本發明另一較佳的實施例中， 第二半導體發光禾命封裝結構是包含複數個發光單元所 組成（圖未顯示），以形成高功率之封琴1元件..。值得說明 的是，電路結構141之第一電路結構i4la可以分別藉由導 通道17電性連結於電路結構141之第二電路結構141匕， 使得半導體發光元件封裝結構1形成一表面黏著元件。然 而’熟知本項技藝者皆知，導通道17不僅可以設置於封 裝基板14内部（如圖10B) ’亦可以位於封裝基板14之側 邊並露出半導體發光元件封填結構丨之外（圖未顯示）。 從本發明之手段與具有的功效中，可以得到本發明具有 諸多的優點。首先，利用本發明所揭露的製程以及結構 ，所製作出的半導體發光元件封裝結構，不僅能有效的 增加晶圓與封裝基板之密合度進而提升封裝製程的良率 。再者，藉由本發明的手段亦可以縮小封裝結構厚度， 以減少元件所占用之體積與縮短封裝結構之散熱路徑。 顯然地，依照上面實施例中的描述，本發明可能有許多 的修正與差異。因此需要在其附加的權利要求項之範圍 表單編號A0101 第9頁/共27頁 0992012096-0 201131825 内加以理解，除了上述詳細的描述外，本發明還可以廣 泛地在其他的實施例中施行。上述僅為本發明之較佳實 施例而已，並非用以限定本發明之申請專利範圍；凡其 它未脫離本發明所揭示之精神下所完成的等效改變或修 飾，均應包含在下述申請專利範圍内。 【圖式簡單說明】 [0024] 圖1至圖1 0A顯示本發明所揭露之晶圓級封裝方法之製程 示意圖，其中圖9A和圖9B係顯示二種不同實施態樣；以 及 [0025] 圖10B顯示依本發明所揭露製程所獲得之一種半導體發光 元件封裝結構的放大剖面示意圖。 【主要元件符號說明】 [0026] 1 :半導體發光元件封裝結構 [0027] 11 0 :發光單元 [0028] 10 :暫時基板 [0029] 111 : p型半導體層 [0030] 11 :半導體元件 [0031] 112:發光層 [0032] 12a、12b :凸塊 [0033] 113 : η型半導體層 [0034] 1 3 :第一封裝層 [0035] 114 :正電極 099106684 表單編號Α0101 第10頁/共27頁 0992012096-0 201131825 [0036] 14 :封裝基板 [0037] 115 :負電極 [0038] 15 :第二封裝層 [0039] 1 31 :表面 [0040] 16 :切割線 [0041] 141 :電路結構 [0042] 17 :導通道 [0043] 141a ··第一電路結構 ' [0044] 20 :黏著層 [0045] 141b :第二電路結構 [0046] 100 :研磨工具 [0047] 151、152 :波長轉換單元 〇 099106684 表單編號A0101 第11頁/共27頁 0992012096-0Wafer-level package (wafer level packa.ge, WLP) technology combined with micro-electromecha.nical 'system (MEMS), using photolithography process and lithography technology to design the circuit Wafer cutting is done at the wafer level to increase productivity and mass production, while also shrinking the package structure' is a technology that meets modern needs. However, there are still many issues that need to be improved in the wafer level packaging process. For example, the technique of U.S. Patent Publication No. 2007/0202623 utilizes wafer level packaging (...) to produce a surface mount (surf ace age pjlt) light emitting diode package structure. The first technique uses flip chip technology to fix the LED dies on the package substrate, but the height and size of the bumps of the solid crystal are often different, resulting in poor soldering or void soldering. Lead to failure of package components and reduced process yield. To address the deficiencies of the above techniques, a technique utilizes an underfill to improve the above problems. See U.S. Patent Publication No. 2009/0230409. This prior art utilizes capillary phenomenon to cause the encapsulant to penetrate into the space between the die and the package substrate, but its die and package base 099106684 Form No. A0101 Page 3 / Total 27 Pages 0992012096-0 201131825 [0005] [0006 [0007] [0008] 099106684 There is still a gap between the plates, and the component is not completed and affects long-term reliability (4). Nowadays, new technologies are still being overcome to overcome the above-mentioned lack of prior art. SUMMARY OF THE INVENTION The present invention is directed to a method of providing a wafer level package that improves the adhesion and conformance of a wafer to an I substrate. The invention discloses a method for wafer level sealing I, comprising: providing a temporary substrate; forming a semiconductor element on the temporary substrate, wherein the semiconductor element comprises a plurality of light emitting units, and each of the light emitting units has at least a positive electrode And n poles; respectively forming a plurality of bumps on the positive electrode and the negative electrode of the light emitting unit; forming a first encapsulation layer on the temporary substrate and covering the semiconductor component; and setting a substrate to cover the encapsulation layer The package is purely connected to the plurality of bumps t to remove the temporary substrate; forming a second encapsulation layer on the material conductor element, wherein the second encapsulation layer and the substrate are assigned to opposite ends of the semiconductor element; Cutting a plurality of light-emitting units such as a human-I to form a plurality of semiconductor light-emitting device sealing structures. The plurality of semiconductor wafers are sealed by the method of sealing the wafer level to improve the yield of the process. In the direction discussed here, the method of von wafer level packaging. A can thoroughly understand the steps of the invention and its composition. Obviously, the description of this (four) column Special details familiar to those skilled in the art of packaged structures. Another well-known composition or step is to go to the details of the form number to avoid creating a total of 27 pages of wafers. And the sealed substrate 201131825 [0009] [0010] G [0012] The invention is not necessarily limited. The preferred embodiment of the present invention will be described in detail below. However, in addition to these detailed descriptions, the present invention can be widely applied. The present invention is not limited by the scope of the following patents, and the preferred embodiments and technical contents provided by the present invention will be described in detail below with reference to the drawings and examples. The invention discloses a wafer level packaging method, which can improve the compatibility and consistency of the wafer and the package substrate. The steps of the wafer level packaging are as follows. Please refer to FIG. 1 'Firstly provide a temporary substrate 1 〇, The temporary substrate 1〇 may be an epitaxial substrate such as a sapphire (Al2〇3) substrate, a tantalum carbide (Sic) substrate, a lithium aluminate substrate (LiAlO), a lithium gallate substrate (LiGaO), a germanium (Si) substrate. Gallium nitride (GaN) substrate, oxidized (2n〇) substrate, alumina substrate (AIZnO), gallium arsenide (GaAs) substrate, gallium phosphide (GaP) substrate, recorded gallium substrate (GaSb), and dish a copper (inp) substrate, an indium (InAs) substrate, or a magnetized zinc (ZnSe) substrate. Referring to FIG. 2, a semiconductor device is formed on the temporary substrate 1 , wherein the semiconductor device 11 can be formed by chemical vapor deposition. (chemical vapor deposition, CVD) formation, such as metal organic chemicai vapor deposition (M0CVD) machine or molecular beam epitaxy (MBE). In a preferred embodiment of the present invention, the semiconductor device 11 further includes a P-type semiconductor layer 111, at least one light-emitting layer 112, and an n-type semiconductor layer 113. The semiconductor component n can be ΠΙ_ν grouping 099106684 Form number Α0101 Page 5 of 27 0992012096-0 201131825 Beta half V body or ιι-νι compound semiconductor. In addition, the luminescent layer 112 comprises a single layer of single heterostructure, a double heterostructure, a single quantum well layer or a multi-weight sub-well structure that emits light of at least one wavelength. [0015] Referring to FIG. 3, the semiconductor element n is then formed into a plurality of light emitting units u, wherein a plurality of light emitting units HO can be formed using yellow light and lithography techniques. In addition, each of the light-emitting units 11 () has at least one positive electrode 114 and one negative electrode 115, and the positive electrode 114 is electrically connected to the p-type semiconductor layer ill, and the negative electrode 115 is electrically connected to the n-type semiconductor layer 113. In a preferred embodiment of the invention, the positive electrode 114 and the negative electrode 115 are nickel (Ni), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), copper (Cu), zinc (Zn). , Titanium (T i ), Shi Xi (si ) or an alloy thereof, and formed by a technique of evoaporat ion or sputtering, and an etching technique. A plurality of bumps 12a are formed on the positive electrode 114 of the light emitting unit 11A and a plurality of bumps 2b are on the negative electrode 11 5. The plurality of bumps 12a and the plurality of bumps 12b are not adjacent to each other, and the material thereof is Contains nickel (Ni), tin (Sn), chromium (Cr), (€ir), gold (Au), silver (Ag), oblique (Pb), platinum (Pt), zinc (Zn), titanium (Ti An alloy of bismuth (Si) or a composition thereof can be formed by a stencil printing technique. Referring to FIG. 5, a first encapsulation layer 13 is formed on the temporary substrate 1 and covered with a plurality of luminescences. In a preferred embodiment of the present invention, the first encapsulation layer 13 is made of epoxy, silicone or a combination thereof or modified glue. Material, and by transfer molding, spin coating or 099106684 Form No. A0101 Page 6 / Total 27 Pages 0992012096-0 201131825 [0016] 〇[00Π] ❹ [0018] 099106684 Injection molding (lnjectlon The method of m〇Iding) is formed. Referring to FIG. 6, the surface 131 of the first encapsulation layer 13 is then ground by grinding HGG so that the surface ΐ3 of the first encapsulation layer 13 forms a smooth plane. It is worth noting that The plurality of bumps l2a, 12b may be exposed to expose the surface i3i of the first encapsulation layer 13 and form a flat exposed surface; or 'the step of forming the first encapsulation layer 13' may expose the first-sealing The surface 13 of the money 13 is further formed into a flat surface by the step of grinding. Please refer to ® 7A 'and then provide - the sealing plate 14 is fixed to the surface 131 of the first package layer 13 ' wherein the package view 14 and the temporary substrate 1 () The package substrate 14 includes a circuit structure 141' which is composed of a plurality of first-circuit structures 141 & and a plurality of second circuit structures 141b. Further, a plurality of first-circuits are provided on both sides of the first package layer 13 The structure 141a and the plurality of second circuit structures 141b are electrically connected to each other, and the positive and negative electrodes 114 and 115 of the plurality of light-emitting units 11 can be electrically connected by the plurality of bumps 12a and 12b and the circuit structure 141, respectively. The second circuit structure 141 to the surface of the package substrate 14 is a preferred embodiment of the present invention. The package substrate 14 may be a printed circuit board (PCB), a ceramic substrate, or a germanium (siHc〇n). Substrate, metal substrate, yttria (Si0) or insulating rubber. Further, the circuit structure 141 is composed of a conductive material such as copper (Cu), nickel (Ni), gold (Au), silver (Ag) or a combination thereof. Referring to Figure 7B', in another preferred embodiment of the present invention, a method of securing the package substrate 14 to the surface 131 by means of an adhesive layer 20 is provided. It is worth noting that the adhesive layer 20 can be a film, glue or anisotropic conductive (anis〇tr〇pic c〇n form number A0101 page 7/27 pages 0992012096-0 201131825 ductive) A paste is formed on the surface 131 of the first encapsulation layer 13 by means of thermal transfer printing. It is worth noting that the anisotropic conductive material is uniformly dispersed in the organic resin material, and the organic material starts to flow by using appropriate pressure, temperature and time, and the different materials are connected to each other and can be closely combined with the bonding material. It has the characteristics of vertical electrical conduction and horizontal electrical insulation. [0020] Referring to FIG. 8, the temporary substrate 1 is then removed from the plurality of light emitting units 11{) and the bottom surface of the first encapsulation layer 13. In a preferred embodiment of the present invention, the means for removing the temporary substrate 10 includes a peeling technique (Uft 〇 ff), etching, cutting, or grinding. Referring to FIG. 9A and FIG. 9B Then, a second encapsulation layer 15 is formed on the bottom surfaces of the plurality of light emitting units 110 and the first encapsulation layer 13 , wherein the second encapsulation layer 15 and the package substrate 14 are respectively located on opposite sides of the first encapsulation layer 3 . The material of the second encapsulating layer 15 comprising epoxy resin, silicone rubber or a combination or modified material thereof can be formed by means of transfer molding, injection molding or spin coating. Furthermore, the second encapsulation layer 15 may comprise at least one wavelength conversion unit 151, wherein the wavelength conversion unit 151 is excited by the light of the illumination unit 11 and emits light of another wavelength. In a preferred embodiment of the present invention, the wavelength conversion unit 151 may be yttrium aluminum garnet (YM), strontium stone (TAG), salt, nitride, nitrogen telluride, filler, sulfide or combination. It should be noted that the wavelength conversion unit 151 may be powdered and uniformly doped in the second encapsulation layer 15 as shown in FIG. 9A; or, is a layer wavelength conversion unit 152 and both are in the form of 099106684 No. A0101, page 8 / total 27 pages 0992012096-0 201131825 [0021] [0023] 099106684 covers the bottom surface of the light emitting unit 110, as shown in FIG. 9A, wherein the wavelength conversion unit 152 can be a film, A patch or a Lumiramic plate is formed by means of coating, paste or spray. Referring to FIG. 10A and FIG. 10B, the above structure ' is cut along a plurality of dicing lines 16 to form a plurality of semiconductor light emitting element package structures 1, wherein each of the semiconductor light emitting element package structures 封装 includes a package substrate 14 having a circuit structure 141 and a light emitting unit. 11〇, the first encapsulation layer 13, the wavelength conversion unit 152, and the second encapsulation layer 15. In another preferred embodiment of the present invention, the second semiconductor light emitting package structure comprises a plurality of light emitting units (not shown) to form a high power sealed 1 component. It is to be noted that the first circuit structure i4la of the circuit structure 141 can be electrically connected to the second circuit structure 141 of the circuit structure 141 by the conductive channel 17, respectively, so that the semiconductor light emitting device package structure 1 forms a surface adhesive component. However, it is well known to those skilled in the art that the channel 17 can be disposed not only inside the package substrate 14 (as shown in FIG. 10B) but also on the side of the package substrate 14 and exposing the semiconductor light-emitting device sealing structure (Fig. display). The present invention has many advantages from the means and effects of the present invention. Firstly, by using the process and structure disclosed in the present invention, the semiconductor light emitting device package structure can not only effectively increase the adhesion between the wafer and the package substrate, but also improve the yield of the packaging process. Moreover, the thickness of the package structure can also be reduced by the means of the present invention to reduce the volume occupied by the components and shorten the heat dissipation path of the package structure. Obviously, many modifications and differences may be made to the invention in light of the above description. Therefore, it is to be understood that the scope of the appended claims is in the scope of the appended claims. FIG. The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the claims of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following claims. Within the scope. BRIEF DESCRIPTION OF THE DRAWINGS [0024] FIG. 1 to FIG. 10A are schematic diagrams showing a process of a wafer level packaging method disclosed in the present invention, wherein FIGS. 9A and 9B show two different embodiments; and [0025] 10B shows an enlarged schematic cross-sectional view of a semiconductor light emitting device package structure obtained by the process disclosed in the present invention. [Description of Main Element Symbols] [0026] 1 : Semiconductor Light Emitting Element Package Structure [0027] 11 0 : Light Emitting Unit [0028] 10 : Temporary Substrate [0029] 111 : p-type Semiconductor Layer [0030] 11 : Semiconductor Element [0031] 112: light-emitting layer [0032] 12a, 12b: bump [0033] 113: n-type semiconductor layer [0034] 1 3 : first package layer [0035] 114: positive electrode 099106684 form number Α 0101 page 10 / total 27 pages 0992012096-0 201131825 [0036] 14 : package substrate [0037] 115 : negative electrode [0038] 15 : second encapsulation layer [0039] 1 31 : surface [0040] 16 : cutting line [0041] 141 : circuit structure [0042 17: Conductor channel [0043] 141a · First circuit structure '[0044] 20: Adhesive layer [0045] 141b: Second circuit structure [0046] 100: Abrasive tool [0047] 151, 152: Wavelength conversion unit 099106684 Form No. A0101 Page 11 / Total 27 Pages 0992012096-0