TW201131747A - Memory device and method for fabricating the same - Google Patents

Abstract

A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of first and second dopant regions and a plurality of first and second cell dopant regions. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.

Description

201131747 i 32287ΐλνf.doc/π VI. Description of the Invention: [Technical Field] The present invention relates to a memory element and a method of fabricating the same, and a memory element and method thereof . ,,clothes. [Prior Art] Memory is a semiconductor designed to store information or data. The function of the brain microprocessor is getting stronger and stronger, and the program performed by the software is increased. Therefore, the capacity requirements of the memory are getting higher and higher. ^ Among all kinds of memory products, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Based on the money, non-volatile memory has become a kind of memory widely used in personal computers and electronic devices. Electrocable Erasable Programmable Read Only Memory ( EEPR0M) has the ability to store, read, erase, etc. multiple data, and save The incoming data does not disappear after power failure, so it has become a memory component widely used in personal computers and electronic devices. A typical wire-optic and programmable vocal memory system with doped polycrystalline stone = Floating Gate and Control Gate (Gate). When the memory is programmed (pr〇gram), the electrons injected into the floating interpole are evenly distributed throughout the polysilicon floating gate layer. However, when there is (4) the presence of the latent layer under the polysilicon floating interpole layer, the leakage current of the component 201131747 32287t\vf.d〇c/n is affected, which affects the reliability of the component. Therefore, in order to solve the problem of electrically erasing the programmable current, a conventional method is known as a drain. ^ ϋΓ ) Asking the pole structure to replace the polycrystalline stone floating gate The other advantage of replacing the multiple (four) floating _ in the component layer is that the electron is only stored in the channel near the source or the pole. Therefore, when stylizing, _ is applied to the source region and the control gate at one end, and:: Layer: The distribution of the nesian layer in the 产生 匕 layer that produces the Gaussian distribution. The voltage applied to the source/drain region is changed; the change is the electron of the cloth or there is no electron. Therefore, this kind of ^>^ has a slashed knife::: chest flash memory 'can be in a single heart:: $ to enhance the single-memory cell bit field, f know technology has vertical memory cell memory The structure is a single type of "bks/丨eell"'s memory. However, this has a memory structure that easily occurs between vertically adjacent two-dimensional elements: "punch through" phenomenon, and The memory structure of the vertical vertical memory cell that produces severe leakage current also has an asymmetric starting voltage and = 201131747... r7〇uu:7u j2287tAvf. doc/π is called the stylized speed and so on, so that it has vertical memory cells. The performance of the memory component is reduced. Therefore, how to achieve higher memory density and solve the above problems to maintain a certain level of component performance of memory components is still an extremely important issue at present. SUMMARY OF THE INVENTION In view of the above, the present invention provides a memory device having better component performance. The present invention provides a method of fabricating a memory device that effectively solves the electrical problem of a memory device having vertical memory cells. An embodiment of the invention provides a memory device including a substrate, a conductor layer, a charge storage layer, a plurality of first doped regions, a plurality of second doped regions, and a plurality of memory cell doped regions. There are multiple trenches in the substrate. The conductor layer is disposed on the substrate and fills the trench. The charge storage layer is disposed between the substrate and the conductor layer. The first doped regions are respectively disposed in the substrate below the bottom of the trench and have a first conductivity type. The second doped regions are respectively disposed in the substrate between the adjacent two trenches and have a first conductivity type. The memory cell doped regions are respectively disposed in the substrate between the side surfaces of the trench and have a second conductivity type. Wherein, the first conductivity type and the second conductivity type are different doping types. According to an embodiment of the invention, the memory device further includes a well region disposed in the substrate below the first doped region and having a second conductivity type. According to an embodiment of the present invention, in the memory element 201131747 32287 twf.doc/r, the width of each of the first doped regions is larger than each of the trenches according to an embodiment of the present invention, in the above The 'memory doped region includes a plurality of first memory cells for the 2 body element: the recalled f-doped region. The first-memory cell doped regions are respectively arranged; two: one second: in the substrate between the portions. The second memory cell doped regions are respectively arranged in the base of the bottom of the doped region; - placed adjacent to the embodiment according to the invention, further comprising a bottom dielectric layer and a top dielectric layer. The bottom dielectric layer is matched between the component ^ and the substrate. The TI dielectric is disposed in the charge core layer and the conductive region. According to an embodiment of the present invention, a metal silicide layer is further disposed on the conductor layer. 5 Completion of the component The component is then formed into a plurality of surfaces; the surface: the surface, and the memory cell doped region is located in the side surface 2 and the plurality of defects in the substrate. Treasury - doping ^ with multiple second pods. Junction: Miscellaneous "Do not be placed in the base below the lower surface. The flute is placed under the upper surface of the Gan + _ Zhong Di two doping distinguishes the electric type, while the first - memory blister: disc:: two doping The region has a first-conducting conductivity type, and the first-conducting type disc; after the cell-doped region has a second, i::di is formed on the substrate to have different doping types. The bulk layer, the conductor layer covers the electricity; : Layer. Further, 'the storage layer is formed on the substrate. According to the ~f4 poor example of the present invention, in the above-mentioned memory element 201131747... 32287t\vf.d〇c/n method, δ The memory cell doped region includes a plurality of memory-cell replacement regions and a plurality of second memory cell doped regions. The first memory cell doped regions are respectively disposed in the substrate between the lower portions of the surface. The impurity regions are respectively disposed in the substrate near the bottom of the first doped region. First, the soil is further included in the method for fabricating the memory device according to an embodiment of the present invention. Before the area, the well area is formed in the basement while the well area is located below the memory cell doped area. According to an embodiment of the invention, in the method of fabricating a memory, a plurality of trenches are formed in a substrate for forming a side surface, an upper surface, and a lower surface. According to the embodiment of the present invention, the memory is described above. In the method of forming a trench, the method for forming a trench includes performing a patterning process on the substrate to remove a portion of the substrate having the memory cell doped region. /, in accordance with an embodiment of the present invention, in the memory described above In the manufacturing method of the body member, the width of each of the first doping regions is larger than the width of each of the lower surfaces. According to the embodiment of the present invention, in the method for manufacturing the memory device described above, the first doping region and The method for forming the second doping region comprises the following steps: forming a sacrificial oxide layer conformally on the substrate and the trench surface, and then performing an ion implantation process on the substrate. Then, removing the sacrificial oxide layer. In the above-described method for fabricating a memory device, the method of forming the first doped region and the second doped region includes the following: first forming a side surface in the substrate The bottoms of the side surfaces each have 201131747 ^ i. jo\j\jj \j 32287twf.doc/n - an inclination Φ. Then, the conformal secret base is formed on the surface of the silk, and then the substrate is subjected to a material balance. Next | = 匕Layer. The other embodiment of the present invention provides a memory bottom, a conductor layer, a charge storage layer, a plurality of first doped regions, a plurality of complementary regions, and a plurality of memory cell doping. The substrate has a plurality of upper surfaces and a plurality of lower surfaces, and the conductor layer is disposed on the substrate.

Between the body layers. The first doped regions are respectively assigned = lower:: having the first conductivity type. The second doped regions are respectively disposed in the substrate below the upper surface, and have the first guiding regions respectively disposed in the substrate between the side surfaces, and have a type: the first conductive type and the second conductive type are different Doping type. According to another embodiment of the invention, in the above memory element; the == region is disposed in the substrate below the first impurity-changing region, and according to another embodiment of the present invention, in the above The width of each of the first doped regions in the memory element is greater than the width of each of the lower surfaces. According to another embodiment of the present invention, in the memory device, the memory cell doped region includes a plurality of first memory cell doped regions and a plurality of second memory cell doped regions. The first memory cell doped regions are respectively disposed on the substrate towels between the lower portions of the side surfaces. The second memory cell doped regions are respectively disposed in the substrate adjacent to the bottom of the second doped region. According to another embodiment of the present invention, in the memory device, the bottom dielectric layer and the top dielectric layer are further included. The bottom dielectric layer is disposed in the charge casting 201131747 32287lwf.doc/n = between the layer and the base red. In the top dielectric layer arrangement (4), the storage layer and the conductor layer are further described. In another embodiment, the metal element layer is further included in the memory element, and is disposed on the conductor layer. The memory component that is memorized in the ^^ example has a ―voltage, which can be generated, thus having a symmetrical start. Furthermore, the effectiveness of the body component. Time 'can prevent the record at the top' ===Ideity: = has a symmetrical stylized speed, two: 1: ground solution: ί right t 制造 The manufacturing method of the memory element of the embodiment can be useful; The electrical problem of the memory component of the memory cell, because: the method of manufacturing the memory component of the attack can be more advanced ~ inflammation] (the size of the cell to increase the storage density. 乂 'example, for the Γ 返 feature And the advantages can be more obvious, the following is a detailed description of the example of the sub-combination. The embodiment is as follows: oxidation of the embodiment of the invention - Figure: = selective The material of the substrate 10, the upper, and the hungry layer 102 is, for example, yttrium oxide. The method for forming the oxide layer 102 of 201131747 i^yauuyt, 32287wf.doc/n is, for example, a thermal oxidation method. The well region 1〇4 is formed in 100. The formation method of the well region 1〇4 is, for example, ion implantation, and the implanted ions are, for example, p-type dopants, so that the well region 104 has a P-type conductivity type. The ion implantation energy of 1〇4 is, for example, 250 KeV to 350 KeV, and the implant ion concentration is, for example, lxl〇1 3/Cm2 to 5xl〇13/cm2. Then, a first memory cell doped region 106 is formed in the substrate 100 above the well region 104, and the first memory cell doped region 1〇6 and the well region 1〇4 are separated from each other. The first memory cell doped region 106 is formed by, for example, ion implantation, wherein the implanted ions are, for example, P-type dopants, such that the first memory cell replacement region 106 has a P-type conductivity. The energy of the memory cell doped region 106 is, for example, 6 〇 KeV to 8 G KeV ' and the ion implantation concentration is, for example, 疋lxl 〇] 3 / Cm 2 to 1 x 1 〇 14 / cm 2 , and is 'under the first - memory cell doped region 106 In the basement = Chengdi, the cell doping region 108' is recalled and the second memory cell doping region (10) 盥 = = the cell doping region 106 is separated from each other. The second memory cell doping region 108 is an ion implantation method, The ion implanted is, for example, p-type ^* such that the memory cell doped region 108 has a p-type conductivity type. The ion implantation energy of the cell (10) is, for example, 10 Kev and the ion implantation concentration is, for example. Yes—2 to remove the sacrificial oxide layer 1G2. The removal method of the sacrificial oxide layer 102 is, for example, a wet core engraving method. Further, a plurality of sides are formed on the substrate 1GG t Surface UGA, a plurality of the above table 201131747 ry〇Kjxjy\j 32287twf.doc/n face 110b and a plurality of lower surfaces] 10C. The side surface] i〇a, the upper surface 11〇b and the lower surface 110c are formed, for example, in A plurality of trenches 110 are formed in the substrate 1 and the trenches 110 include a side surface U〇a and a lower surface 11〇c. The first memory cell doped region 106 and the second memory cell doped region 1〇8 are located on the side surface 110a. Between the base 100. The first memory cell doped region]% is located between the lower portions of the side surfaces 110a of the trenches 110. The method of forming the trench 11〇 is, for example, performing a patterning process on the substrate 100 to remove the first memory.

The cell doping region 106 is formed with a portion of the substrate buffer (10) of the second memory cell doping region 1〇8. Subsequently, the sacrificial oxide layer 112 is formed conformally on the surface of the substrate 100 and the trench 110. The thickness of the sacrificial oxide layer 112 is, for example, 5 () angstroms to angstroms. The material of the sacrificial oxide layer 112 is, for example, oxidized hair. The formation method of the sacrificial oxide layer u is, for example, a reoxidation method. * When the thickness of the sacrificial oxide layer 112 is 5 〇 to 1 〇〇, the ionic implant method is used to form the first-buried-type junction region ((4) in Figure W) 14) Doped region (marked in Figure lc

The first buried doping region 盥 _ ' ' Γ ^ is avoided to avoid bridging the first dragged doped region. The multi-hybrid zone has a preferred extension 5 ^ between the substrate 1 to form the lower surface "6 in the substrate (10). In the basin, the second buried type of 2%>

J is implanted from the (four) H buried doped region 114 and the second buried bead, so that

The doped region 116 has N 12 201131747 rysuuyo 32287 twf.doc / n concentration is, for example, a talk-type (10)-type conductivity type as long as the first-buried electrical type, the well region 104 - the multi-hybrid 116 has the same first guide The region (10) has the same; the miscellaneous; the type is different from the doping type, that is, the W3L and the first conductor; and is not limited by the disclosure. The width of the (10)) can be made such that the first channel 11G (or the lower surface extension range. The flute: the doped region 114 has a larger:: the extension of the doped region 114 prevents the top portion from being extended The temperature decreases, and the memory element has a symmetry h' to further improve the margin of the recording element. The younger-embedded doping region 丨148 is in the substrate 100. The second buried A_J is disposed in the lower trench below the trench 110 The doped regions of the gates of the 11th gate are respectively disposed in the adjacent two (10) adjacent to the upper portion of the first 100th and the second memory cell doped region - the bottom of the buried doping region 116. The doped region 106 and the second memory cell doped region (10) are perpendicular to the t (four) row to promote the generation of hot electrons and prevent the breakdown charge of the charge generation, thereby effectively removing the sacrificial oxide layer 112. Sacrificial oxidation The removal of the layer 112 201131747 r^uuyo 32287twrdoc / n method is, for example, a wet etching method. Next, please refer to the circle 1D, conformally forming the bottom dielectric chip on the surface ^ 岑 on the substrate 〇〇 and the ditch 〗 】 Electrical layer 122. _, bottom dielectric layer IIs, charge storage layer 120 and The top dielectric layer is formed. The bottom dielectric layer 118B8 and the top dielectric layer 122 are selectively electrically constant materials. In the embodiment, if it is a low dielectric constant or a high dielectric form or based on a gap electrical engineering layer It may be a material example of the bottom dielectric layer m of a single-layer junction: a structural form, a single-layer structure (HfAlO), a multilayer structure, a rolled ruthenium or an aluminum lanthanum dielectric, and a high-constant material. Stacked structure, such as = 匕石夕/ oxygen cut or oxygen cut / oxidized singular oxygen cut. Guangsuke ^ spoon two into Guanga is a thermal oxidation method. Charge storage her two;

Second material: it is, for example, emulsified stone. The method of forming the charge storage layer 120 is, for example, a chemical vapor deposition method. The top dielectric layer U dielectric material, which is, for example, oxidized, oxidized or oxidized _203). The formation method of the top dielectric layer 122 is, for example, a germanium chemical vapor deposition method. Thereafter, a conductor layer 124 is formed on the substrate 100. The conductor layer 124 covers the top dielectric layer 22 and fills the trench Π0. The material of the conductor layer 124 is, for example, doped polysilicon. The second method of forming the conductor layer 24 is a vapor phase deposition method. Next, a metal lithium 14 201131747 32287 twf.d 〇 c/n layer 126 may be selectively formed on the conductor layer m to lower the resistance and increase the conductivity. Today's materials are, for example, tungsten telluride. The method for forming the chemical vapor phase deposition layer 126 of the entire servant layer 126 is, for example, a component of the right example, which is known from the above-mentioned manufacturing method: 记; Γ; The second memory cell is doped = U, this Zfe body element has a symmetrical start

= occurs between vertically adjacent two bits; it can effectively improve the performance of the recording element. The advantage of the temple is 'u〇(m' and when the width of the first-buried type 1 114 is larger than that of the ditch), it can prevent the width of the I-bit; ^1) (meaning that it has a large extended range of memory cells) The speed of the system is reduced, and the operating margin is made. The speed of the singularization increases the S-question of the memory component. In this case, the memory cell storage density of the vertical memory cell is further reduced to further reduce the memory cell size. The gully Iwtr makes the width of the (four)-buried-type doping 114 to be larger. The method of forming the width of the ridge, =^Ge) is not limited to the upper zone 11 technique, the second burying person t other embodiments, say (four) - burying Other ways of forming the doped doped regions 116. Fig. 2A to Fig. 2B are given to recognize L ◊ A, which will not be the first burial of another embodiment of the present invention.

ψ π — A cross-sectional view of the manufacturing process of the buried doped region. I dry, the same surname μ as in Figure 1A, the description of the components use the same label 'while omitted 15 201131747 ry&wyo 32287t\vf.doc/n first 't month reference to Figure 2A' in the implementation of Figure 1A The oxide layer 102 is sacrificed after the step. The method of removing the sacrificial oxide layer 1 〇 2 is, for example, a wet money engraving method. "',,, 'in the base (10), the surface 2lQa, the upper surface 丽 =, the surface 2H) C, and the side surface 21〇a including the side surface (10) and the lower surface collapse channel 210 may be formed at the bottom The oblique S memory cell doped region 1〇6 is located between the lower portions of the side surface a of the trench 21G. The trench (4) is formed by a process such as a process to remove the doped cell doped region 108 having the first memory cell doped region ι6 A portion of the substrate (10) is formed. The inclined pin of =1 = 1 is formed conformally on the surface of the substrate 1 and the trench 210 by the surface (four) pin adjustment side. The thickness of the oxide layer 212 is, for example, 5 () The material of the ruthenium layer 212 is, for example, ruthenium oxide. The formation method of the sacrificial ruthenium is, for example, a reoxidation method. The ruthenium layer 212 Subsequently, please refer to FIG. 2B, and the substrate 1 〇 The second = buried doped region 214 below the surface 鸠 has a larger width than the trench 21 〇 = ΐ is disposed at the bottom of the trench 210, and the second buried trench 216 is disposed adjacent to the trench The base between the woods 210] the phase of the phase 108 is adjacent to the first-buried m... the brother of a 5 blister-doped area, the younger-buried type Zone 216 bottom 16 201131747 ryouuyo 32287twf.doc/n The ion is, for example, an N-type dopant, and the second buried doped region 216 Μ π i + type snail push S 2U and the first implantation method is, for example, a tilt angle ion implantation Method = into ί ion 2 Η and second buried W doped earth doped region Κ ... 5KeV sub-implant energy is, for example, ω 5xl015 / cm 2 . The spread is, for example, lxl 〇 5 / cm 2 to then remove The method of sacrificial oxide layer 212 is, for example, a method. The removal of the secret layer 212 is known from the above embodiment, and it can be made by * 丽's help in the second circumstance of the second: The first-embedded doped region 214 has a larger size; the extended parametiform to the ^C_ is shown as a further embodiment of the present invention - the first buried, the second; the V,: - the buried doped region A cross-section of the manufacturing process. The same components are denoted by the same reference numerals, and the etching method is removed after the step of sacrificing the layer = ^ 2; the removal method of the Wei layer is, for example, wet and under Γ 形成 形成 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在(10) Between the lower portions of mri0-a. The method of forming the trench 310 is, for example, a soiling process to remove the first memory cell doping 17 201131747 32287t\vf.doc/n miscellaneous zone 106 and the second The memory cell is doped. Then, the modified emulsion layer 302 is formed conformally on the surface of the substrate 100 and the trench 31. In the process of forming the modified oxide layer 3〇2, the combination of the groove =:= =:=: It is an oxide layer = shift === layer 3 ° 2, oxygen sacrificial = layer 31 is formed on the surface. Sacrificial oxide layer 3f2 ^ ^ 3, the column is 50 angstroms, for example, if it is = oxygen final sacrificial oxide layer - please perform - ion implantation 3 ^ and the first - buried m surface 3 under the hire The second buried type is mixed. The first buried doping ==== is greater than the width of the trench _ in the substrate 100. The second knife is disposed at the bottom of the ditch 310 at the bottom of the ditch. The second should be adjacent to the second buried; the second brother-memory cell impurity region ion is, for example, N-type doped bottom/middle, and the implanted two buried doped region 3161 enables the embedded one to be embedded. The miscellaneous region 3] 4 and the implantation method are, for example, a tilt angle = type conductivity type. The ion channel and the second buried doping region used above. The ion implantation energy of the first-buried type impurity region 316 is, for example, 1〇18 32287twfd〇c/n 201131747 to 25^, and the ion implantation concentration is, for example, 1><1〇15/coffee 5x1 (3 /cm) Then, the sacrificial oxide layer 312 is removed. The method of sacrificing the oxide layer 312 is, for example, a wet etching method. " ★ As can be seen from the above embodiment, since the bottom of the trench 31 is rounded, the ion implantation method is used to form the first buried When the doped region 314 is implanted, the first buried doped region 314 can have a larger extent. Below the device, the (4) 1D is used to introduce the memory of the present invention. FIG. The substrate includes a substrate, a plurality of first memory cell doped regions 106, a plurality of second memory cell doped regions, a plurality of first buried doped regions 114, and a plurality of second buried doped regions. Ϊ́6, charge storage=0 and conductor layer 124. The substrate 丨(8) has a plurality of trenches 11 including a plurality of surface surfaces, a surface mb and a plurality of lower surfaces 11Ge, and a lower surface 11c having a side surface 11a|| The conductive layer 124 is disposed on the substrate 100 and fills the trench 110. The charge storage layer 120 is disposed between the gate and the conductor layer 124. The first buried doped region 114 is respectively disposed in the substrate (10) below the bottom of the trench no (ie, the base KK of the lower surface), and has a first conductivity type. The width of the first buried layer 4 For example, it is larger than the width of the trench m. The second buried type = 116 is respectively disposed in the upper portion of the substrate 1 between the adjacent two trenches 110 (ie, in the substrate 100 below the upper surface 1.10b), and has the first - Conductive type. The base memory between the first memory cell region 106 and the second memory cell #zab region 108 is located between the side surface 110a. The first memory cell is in the dorm area 19 32287twf.d〇c/n 201131747 respectively The base (10) disposed between the lower portion of the trench 110 and having the second conductive type side 11a is adjacent to the second buried pine second memory cell lion region 1 (38 is respectively configured with the second conductivity type The base of the bottom of the region 116 is just in the middle and has a doped state. The memory device is different from the first: conductivity type 118, the top dielectric layer 122 and the gold: the well region 104, the bottom dielectric a layer m-doped region layer 126. The well region 104 is disposed in an electrical type, and has a second guide in the substrate 100.

The gate 1 θ is disposed between the charge storage layer 120 and the substrate 100. Top dielectric layer 〖22 with 垂 _ _

Pe. M A is disposed on the conductor layer 124 of the second furnace layer 126 of the storage layer 120 and the conductor layer 124. The memory element I:: tree, the formation mode and its function have been described in the previous examples, and are not described here. It can be seen from the above embodiment that since the first memory cell 〇6(4) and the two memory cell surface (10) of the memory element can control the characteristics of the upper and lower bits in the straight memory cell, the performance of the memory device can be improved. .

In addition, when the width of the first buried doped region 114 is greater than the visibility of the trench, the memory element can have a symmetrical stylized speed, thereby increasing the operational margin of the memory device. In summary, the memory device of the above embodiment and the method of fabricating the same have at least the following advantages: L. Since the memory device has the first memory cell doped region and the second memory cell doped region, the memory can be effectively improved. The performance of the component. 2. When the width of the first buried doped region in the memory element is greater than the width of the trench (or lower surface), the operational margin of the memory device can be increased. 20 201131747 rysuuyo 32287twf.doc/n 3. Since the memory element can effectively solve the electrical problem of the memory element having the vertical memory cell, the memory cell size can be further reduced to increase the storage density. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are cross-sectional views showing a manufacturing process of a memory device according to an embodiment of the present invention. 2A-2B are cross-sectional views showing a manufacturing process of a first buried doped region and a second buried doped region according to another embodiment of the present invention. 3A to 3C are cross-sectional views showing a manufacturing process of a first buried doped region and a second buried doped region according to still another embodiment of the present invention. [Main component symbol description] 100: substrate 102, 112, 212, 312: sacrificial oxide layer 104: well region 106: first memory cell doped region 108: second memory cell doped region 110, 210, 310: trench 110a 210a, 310a: side surface 21 201131747 κνδυυνό 32287t\vf.doc/n 110b, 210b, 310b: upper surface 110c, 210c, 310c: lower surface 114, 214, 314: first buried doped region 116, 216 316: second buried doped region Π8: bottom dielectric layer 120: charge storage layer 122: top dielectric layer] 24: conductor layer 126: metal telluride layer 210d: side surface 302: modified oxide layer

twenty two

Claims (1)

201131747 rvsuuyo 32287twf.doc/n VII. Patent Application Range: 1. A memory component comprising: a substrate having a plurality of trenches therein; a conductor layer disposed on the substrate and filling the trenches; a charge storage layer ′ is disposed between the substrate and the conductor layer; a plurality of first doped regions are respectively disposed in the substrate below the bottom of the trenches, and have a first conductivity type; a plurality of second doping The regions are respectively disposed in the substrate between the adjacent two trenches and have the first conductivity type; and the plurality of memory cell replacement regions are respectively disposed in the substrate between the side surfaces of the trenches And having a second conductivity type, wherein the first conductivity type and the second conductivity type are different doping types. 2. The memory component of claim 1, further comprising a well region disposed in the substrate below the first doped regions and having the second conductivity type. 3. The memory device of claim 1, wherein each of the first doped regions has a width greater than a width of each of the trenches. 4. The memory device of claim 1, wherein the memory doped regions comprise: a plurality of first memory cell doped regions disposed between the lower portions of the side surfaces of the trenches respectively And a plurality of second memory cell doped regions respectively disposed in the substrate adjacent to the bottom of the second doped regions. A method of fabricating a memory device, the method comprising: 23 201131747 ι^δυυ^ό 32287t\vf.doc/n forming a plurality of memory cell doped regions in a substrate; forming a plurality of side surfaces in the substrate a plurality of upper surfaces and a plurality of lower surfaces, wherein the memory cell doped regions are located in the substrate between the side surfaces; forming a plurality of first doped regions and a plurality of second dopings in the substrate a region, the first doped regions are respectively disposed in the substrate under the lower surfaces, and the second doped regions are respectively disposed on the upper surfaces, wherein the doped regions are Having a first conductivity type; and the second memory cell doped region has a second conductivity type, and the second and second conductivity types are different doping types; " on the substrate Cutting into a charge storage layer; and forming a conductor layer on the substrate, the conductor layer covering the charge storage 6 as in the patent application range M %~ method, the memory component described in the above Manufacturing a 〒 哀 些 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Between the silk scarf; and ~~彳 placed in the lower part of the financial surface, the first έ 忆 recalled ρ. ν doped in the bottom of the substrate. The knife - has been placed adjacent to the second 7) If the method of claim 5th method is further included in the formation of the _^ memory element, the well region is formed, and the well is before the cell region, and the substrate 8 is as claimed in the patent. The method of manufacturing the memory element described in the item 5 includes the formation of the surface of the wire and the formation of the lower surface 24 32287 twf.doc/n 201131747 9' The memory method of claim 5, wherein the width of the first-doped display is greater than the width of each of the lower surfaces = iU. - a memory element, comprising: a further lower surface: a substrate in the substrate Having a plurality of side surfaces, a plurality of upper surfaces and a multi-conductor layer 'disposed on the substrate; °. / 3⁄4 . L-, 7" storage layer 'disposed between the substrate and the conductor layer; Miscellaneous regions are respectively disposed in the base exhibit below the lower surfaces and have a first conductivity type; The doped regions are respectively disposed in the substrate under the upper surfaces, and have the first conductivity type; and the 5th memory cell doped regions are respectively disposed between the side surfaces and There is a second conductivity type, wherein the first conductivity type and the first-V type are different doping types. 11·. The memory device of claim 10, further comprising a region, disposed in the substrate below the first doped regions, and having a second conductivity type of 5 hai. The memory device of claim 10, wherein the width of the first doped region of k is greater than the width of each of the lower surfaces. 13. The memory device of claim 1, wherein the memory doped region comprises: a first memory cell doped region, respectively disposed in the substrate of the lower surface of the side surfaces; And the second memory cell doped regions are respectively disposed in the substrate adjacent to the bottoms of the second 25 201131747 i 32287hvf.doc/n doped regions. 14. The memory device of claim 10, further comprising: a bottom dielectric layer disposed between the charge storage layer and the substrate; and a top dielectric layer disposed on the charge storage layer And between the conductor layers. 26