201131406 六、發明說明： 【發明所屬之技術領域】 本發明提供一種訊號分析方法’尤指一種用於具有一晶片 模型（on-chip network)與一非晶片模型（0ff_chip network) 之一電子裝置的訊號分析方法。 【先前技術】 請參考第1圖與第2圖，第1圖所續示的係為傳統的具有一 晶片模型（on-chip network) 110與一非晶片模型（〇ff_chip network) 120之一電子裝置100之示意圖，第2圖所繪示的係 為用於電子裝置100的一種傳統訊號分析方法之流程圖。如 第1圖與第2圖所示，該傳統訊號分析方法包含下列步驟： 步驟200:在晶片模型110中定義X個第一電源接點pii〜ριχ 與Y個第一接地接點G11〜Gly。 步驟210:在非晶片模型120中定義X個第二電源接點 P21〜P2x與Y個第二接地接點G21〜G2y。 步驟 220:利用一準電磁模擬（quasi-static electromagnetic simulation)來分析非晶片模型120。 201131406 然而，由於這種傳統訊號分析方法在分析高頻訊號時，訊 號的相位並科確，所以這種傳統訊齡析方法無法在兩個 不同介面之間提供精確的電氣特性。請參考第3_第4圖， 第3圖所繪示的係為傳統的具有—晶片模型31〇與一非晶片模 型320之一電子裝置300之矛立固资/ 下思圖，第4圖所繪示的係為用於 電子裝置300的-種傳統訊號分析方法之流程圖。如第3圖與 第4圖所示’該傳統訊號分析方法包含下列步驟： 步驟400:在晶片模型310中定義χ個第一電源接點pu〜ρΐχ 與¥個第一接地接點G11〜Gly。 步驟410:利用一全波電磁模擬（fullwaveelectr〇magnetic simulation)來分析非晶片模型320以取得晶片模 型320中的X個第一結果接點p21〜ρ2χ。 然而’這種傳統all號分析方法無法在兩個不同介面之間提 供完整的電氣連接。 【發明内容】 有鑑於此’本發明之目的之一在於提供一種可以用於具 有一晶片模型（on-chip network)與一非晶另模型（0ff-chip network)之一電子裝置的訊號分析方法，以解決上述的問題。 201131406 依據本發明之中請專利範圍，其係猶 晶片模型與一非晶片模型之一電子裝置的訊號分析方;有包 含.在該晶片模型中定義x個第-電源接點與γ個第一接 地接點，其中乂與丫為正整數；在該非晶片.模型令定義x ㈣二電源接點與γ個第二接地接點；將該些第一接地接點 其中之—指派為H考接點；將該些第二接地接點其中 之才日派為一第一參考接點；利用一全波電磁模擬（full wave el__agnetic simu】ati〇n )來分析該非晶片模型以取得該晶 片模型中的（Χ+Υ_υ個第一結果接點與該非晶片模型中的 (二+Y-l)個第二結果接點，其中每一第一結果接點係從該 一參考接點以及該些第一電源接點與該些第一接地接點 中除二該第-參考接點之外的一對應接點之間的一電壓差 :取传’以及每—第二結果接點係從該第二參考接點以及該 ^第—電源接點與該些第二接地接點巾除了該第二參考接 點之外的-對應接點之_―電壓差所取得；以及將該非晶 模3L中的δ亥些第二結果接點與該晶片模型中的該些第一 結果接點做一完整電氣連接。 —相，於傳統的用於具有__晶片模型與一非晶片模型之 電子裝置的訊號分析方法，本發明揭露的訊號分析方法可以 、有a曰片模型與一非晶片模型之一電子裝置提供完整 的電氣連接以及精確的電氣特性。 201131406 【實施方式】 在本說明書以及後續的申請專利範圍當中使用了某些詞囊來指 稱特定的元件，而所屬領域中具有通常知識者應可理解，硬體製造 商可能會用不同的名詞來财同一個元件，本說明書及後續的申嗜 專利範不以名_差異來作為區分元件的方式，岐以元件在 功能上的差異來作為區分的準則，在通篇說明書及後續的請求項當 令所提觸&含有」係為—開放式的用語，故應解釋成「包 但不限定於」。 明參考第5圖與第6圖’第5圖所繪示的係為依據本發明一實 施例的具有—晶片模型與-非“模型52〇之一電子裝 置之示意圖，其中晶片模型51〇可以為一積體電路^ t非晶片模型520可以為一電路板。第6圖靖示的係為本發 鲁用於電子裝置’的—種訊號分析方法之流程圖。如第$圖 與第6圖所示，本發明之訊號分析方法包含下列步驟： 步驟600:在晶片j曾开 i 51 〇中疋義X個第一電源接點pn〜 與Υ個第一接地接點G11〜Gly，其中χ與γ為 正整數。 '、 ’ 步驟61〇_在非晶片模型520中定義X個第二電源接點Ρ21〜Ρ2χ與 第二接地接點 G21 〜G2y 〇 步驟620.將第―接地接點G11〜Gly其中之-指派為—第一參考接 201131406 點R1 ; 步驟630:將第二接地接點G2]〜G2y其中之一指派為一第二參考接 點R2 ; 步驟640:细-全波電磁模擬 simulation)來分析非晶片模型52〇以取得晶片模型51〇 中的（X+Y_1)個第一結果接點Nil〜Nl(x+y-l)與非 晶片模型520中的（χ+γ^)個第二結果接點 N21〜N2(x+y-l) ’其中每一第一結果接點係從第一 參考接點R1以及第一電源接點P11〜Plx與第一接 地接點G11〜Gly中除了第一參考接點R1之外的一 對應接點之間的一電壓差所取得，以及每一第二 結果接點係從第二參考接點R2以及第二電源接 點P21〜P2x與第二接地接點G21〜G2y中除了第二 參考接點R2之外的一對應接點之間的一電壓差 所取得。 步驟敵將非晶片模型52G中的第二結果接點簡〜卿+^) 與晶片模型510中的第一結果接點 做一完整電氣連接。 舉例來說’本發明之訊號分析方法可以先在晶片模型51〇 中疋義3個第一電源接點ριρρυ與3個第一接地接點 GU〜G13’以及在非晶片模型520中定義3個第二電源接點p2i〜p23 與3個第二接地接％ G21〜G23。接著’本發明之訊號分析方法將 201131406 第一接地接點GU指派為一第—參考接點R1，以及將第二接地接 點G21指派為一第二參考接點似。接著，本發明之訊號分析方法 利用-全波電磁模擬㈤lwaveelectlOmagneticsimulati〇n)來分析 非晶片模型520以取得晶片模型51〇中的5個第一結果接點 Nil〜N15與非晶片模型52〇中的5個第二結果接點 Ν21-Ν25» /、中第、纟°果接點Nil係從第一參考接點R1以及第一電源 接點pii之間的_電壓差所取得，第一結果接點ni2係從第 〃考接點R1以及第—電源接點之間的—電壓差戶斤取 得第、'’。果接點N13係從第一參考接點R1以及第一電源 接點P13之間的—電壓差所取得，第一結果接點剛係從第 -參考接點ri以及第―接地接點G12之間的—電壓差所取 得’第-結果接點N15係從第—參考接點^以及第一接地 接點G13之_ —電壓差所取得，第二結果接點皿係從第 二參考接點R2以及第二電源接點p21之間的—電壓差所取 得，第二結果接點體係從第二參考接點R2以及第二電源 接點P22之間的—電壓差所取得，第二結果接點肋係從第 -參考接點R2以及H源接點p23之間的—電壓差所取 得，第二結果接點腿係從第二參考接點R2以及第二接地 接點G22之間的—電壓差所 冤I是所取侍，以及第二結果接點N25係 從第二參考接點R 2以及第二接地接點㈤3之間的一電壓差 所取得。接著，本發明之訊號分析方法將非晶片模型WO中的 第二結果接點N21〜N25與晶片模型51〇中的第—結果接點 Nil〜N15做一完整電氣連接。 201131406 在此請注意，上述的實施例僅作為本發明的舉例說明，而不是 本發明的限制條件。相較於傳統的用於具有—晶片模型與一非 晶片模型之-電子裝置的訊號分析方法，本發明揭露的訊號 分析方法可以對具有一晶片模型與一非晶片模型之一電子裴 置提供完整的電氣連接以及精確的電氣特性。 戶u上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 斤做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 ^圖所曰繪示的係為傳統的具有一晶片模型（on-chip network ) 第2非日日片模型（off-chiP network)之—電子裝置之示意圖。 圖所繪示的係為用於電子裝置的—種傳統訊 法之 成裎圖。 圖所緣示的係為傳統的具有 電子裝置之示意圖201131406 VI. Description of the Invention: [Technical Field] The present invention provides a signal analysis method, particularly for an electronic device having an on-chip network and a non-chip model (0ff_chip network) Signal analysis method. [Prior Art] Referring to FIG. 1 and FIG. 2, the continuation of FIG. 1 is a conventional one having an on-chip network 110 and a non-wafer model (〇ff_chip network) 120. A schematic diagram of device 100, depicted in FIG. 2, is a flow diagram of a conventional signal analysis method for electronic device 100. As shown in FIG. 1 and FIG. 2, the conventional signal analysis method includes the following steps: Step 200: Define X first power contacts pii~ριχ and Y first ground contacts G11~Gly in the wafer model 110. . Step 210: Define X second power contacts P21 P P2x and Y second ground contacts G21 G G2y in the non-wafer model 120. Step 220: Analyze the non-wafer model 120 using a quasi-static electromagnetic simulation. 201131406 However, since this traditional signal analysis method analyzes the high-frequency signal and the phase of the signal is well-defined, this traditional method of age analysis cannot provide accurate electrical characteristics between two different interfaces. Please refer to FIG. 3_4. FIG. 3 is a diagram of a conventional electronic device 300 having a wafer model 31〇 and a non-wafer model 320. FIG. The figure is a flow chart of a conventional signal analysis method for the electronic device 300. As shown in FIG. 3 and FIG. 4, the conventional signal analysis method includes the following steps: Step 400: Define one first power contact point pu~ρΐχ and one first ground contact point G11~Gly in the wafer model 310. . Step 410: Analyze the non-wafer model 320 using a full-wave electromagnetic simulation to obtain the X first result contacts p21 ρ ρ2 晶片 in the wafer model 320. However, this traditional all-number analysis method does not provide a complete electrical connection between two different interfaces. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a signal analysis method that can be used in an electronic device having an on-chip network and an amorphous-mode network. To solve the above problem. 201131406 According to the scope of the patent application of the present invention, it is a signal analysis method of an electronic device of one of the semiconductor chip model and a non-wafer model; there is included: x first power supply contacts and γ first are defined in the wafer model a ground contact, wherein 乂 and 丫 are positive integers; in the non-wafer. The model defines x (four) two power contacts and γ second ground contacts; assigning the first ground contacts to the H test a point; the second ground contact is assigned as a first reference contact; the full wave electromagnetic simulation (full wave el__agnetic simu) ati〇n is used to analyze the non-wafer model to obtain the wafer model (Χ+Υ_υ first result contact and (2+Yl) second result contacts in the non-wafer model, wherein each first result contact is from the one reference contact and the first power supply a voltage difference between the contact and a corresponding one of the first ground contacts except the first reference contact: the pass and the second to the second result are from the second reference a contact point and the ^ first power contact and the second ground contact towel Obtaining a voltage difference from the corresponding contact point other than the second reference contact; and selecting a second result contact point of the amorphous mode 3L and the first result contacts in the wafer model To make a complete electrical connection. The phase signal is analyzed by a conventional signal analysis method for an electronic device having a __chip model and a non-wafer model. The signal analysis method disclosed in the present invention can have a chip model and a non-wafer. One of the models of the electronic device provides a complete electrical connection as well as precise electrical characteristics. 201131406 [Embodiment] Certain terms are used in this specification and the following claims to refer to a particular component, and the general knowledge in the field It should be understood that hardware manufacturers may use different nouns to finance the same component. This specification and subsequent application patents do not use the name _ difference as the way to distinguish components, but the functional differences between components. As a criterion for distinguishing, in the entire specification and subsequent claims, the reference to & containment is an open-ended term, so it should be interpreted as "packaged but Illustrated with reference to FIG. 5 and FIG. 6 ' FIG. 5 is a schematic diagram of an electronic device having a wafer model and a non-"model 52" according to an embodiment of the present invention, wherein The chip model 51 can be an integrated circuit. The non-wafer model 520 can be a circuit board. The figure shown in Fig. 6 is a flow chart of the signal analysis method used by the electronic device for the electronic device. As shown in FIG. 6 and FIG. 6, the signal analysis method of the present invention comprises the following steps: Step 600: In the wafer j, the first power contacts pn~ and the first ground contacts are separated from each other. G11~Gly, where χ and γ are positive integers. ', 'Step 61〇_In the non-wafer model 520, X second power contacts Ρ21~Ρ2χ and second ground contacts G21~G2y are defined. Step 620. The first ground contact G11 to Gly is assigned - the first reference is connected to 201131406 point R1; step 630: one of the second ground contacts G2] G G2y is assigned as a second reference contact R2; : Fine-to-wave electromagnetic simulation (simulation) to analyze the non-wafer model 52〇 to obtain the wafer model 51〇 (X+Y_1) first result contacts Nil~Nl(x+yl) and (χ+γ^) second result contacts N21~N2(x+yl) ' in each of the non-wafer models 520 The first result contact is between the first reference contact R1 and a first power contact P11 PPlx and a corresponding one of the first ground contacts G11 G Gly except the first reference contact R1. The voltage difference is obtained, and each second result contact is from the second reference contact R2 and the second power contacts P21 P P2x and the second ground contacts G21 G G2y except for the second reference contact R2 A voltage difference between a corresponding contact is obtained. The second result contact in the non-wafer model 52G is a complete electrical connection with the first result contact in the wafer model 510. For example, the signal analysis method of the present invention can first define three first power contacts ριρρυ and three first ground contacts GU~G13' in the chip model 51〇 and three in the non-wafer model 520. The second power contacts p2i to p23 and the three second grounds are connected to % G21 to G23. Next, the signal analysis method of the present invention assigns the 201131406 first ground contact GU as a first reference junction R1 and the second ground contact G21 as a second reference junction. Next, the signal analysis method of the present invention analyzes the non-wafer model 520 by using the full-wave electromagnetic simulation (5) lwaveelectlOmagneticsimul〇n) to obtain the five first result contacts Nil~N15 and the non-wafer model 52〇 in the wafer model 51〇. The five second result contacts Ν21-Ν25» /, the middle, and the 接° contact Nil are obtained from the _ voltage difference between the first reference contact R1 and the first power contact pii, and the first result is Point ni2 obtains the first, '' from the voltage difference between the first reference contact R1 and the first power contact. The contact point N13 is obtained from the voltage difference between the first reference contact R1 and the first power contact P13, and the first result contact is just from the first reference contact ri and the first ground contact G12. The first-to-result contact N15 is obtained from the voltage difference between the first reference contact and the first ground contact G13, and the second result is from the second reference contact. The voltage difference between R2 and the second power contact p21 is obtained, and the second result contact system is obtained from the voltage difference between the second reference contact R2 and the second power contact P22, and the second result is connected. The point rib is obtained from the voltage difference between the first reference contact R2 and the H source contact p23, and the second resultant contact leg is between the second reference contact R2 and the second ground contact G22. The voltage difference 冤I is taken, and the second result contact N25 is obtained from a voltage difference between the second reference contact R 2 and the second ground contact (5) 3. Next, the signal analysis method of the present invention makes a complete electrical connection between the second result contacts N21 to N25 in the non-wafer model WO and the first result contacts Nil to N15 in the wafer model 51. It is noted that the above-described embodiments are merely illustrative of the invention and are not limiting of the invention. Compared with the conventional signal analysis method for an electronic device having a chip model and a non-wafer model, the signal analysis method disclosed in the present invention can provide complete electronic devices having a wafer model and a non-wafer model. Electrical connections and precise electrical characteristics. The above description is only the preferred embodiment of the present invention, and all the equivalent variations and modifications of the patent application scope of the present invention should fall within the scope of the present invention. [Simple Description of the Drawings] The figure is a schematic diagram of a conventional electronic device having an on-chip network (off-chiP network). The figure shows a diagram of a conventional technique for an electronic device. The figure is a schematic diagram of a conventional electronic device.
4衣夏之示意圖。 :二::繪示的係為用於電子裝置的-種傳統訊號分析: 非晶的係為依據本發明—實施例的具有一晶片模型與一 曰曰吴型之一電子裝置之示意圖。 圖斤、'曰不的係為本發明用於電子裝置的—種訊號分析方法 10 201131406 之流程圖。 【主要元件符號說明】 100、300、500 :電子裝置 110、310、510 :晶片模型 120、320、520 :非晶片模型 P11〜Plx:第一電源接點 Gll~Gly :第一接地接點 P21〜P2x :第二電源接點 G21~G2y :第二接地接點 R1 :第一參考接點 R2 :第二參考接點 Nil〜Nl(x+y-l):第一結果接點 N21〜N2(x+y-l):第二結果接點 P21〜P2x :第一結果接點 114 schematic diagram of clothing summer. The second:: is a conventional signal analysis for an electronic device: The amorphous system is a schematic diagram of an electronic device having a wafer model and a 曰曰-type according to the present invention. FIG. 1 is a flow chart of a signal analysis method for an electronic device 10 201131406. [Main component symbol description] 100, 300, 500: electronic device 110, 310, 510: wafer model 120, 320, 520: non-wafer model P11 ~ Plx: first power contact Gll ~ Gly: first ground contact P21 ~P2x: second power contact G21~G2y: second ground contact R1: first reference contact R2: second reference contact Nil~Nl(x+yl): first result contact N21~N2(x +yl): second result contact P21~P2x: first result contact 11