TW201130060A - Method for forming bumps - Google Patents

Method for forming bumps

Info

Publication number
TW201130060A
TW201130060A TW99105175A TW99105175A TW201130060A TW 201130060 A TW201130060 A TW 201130060A TW 99105175 A TW99105175 A TW 99105175A TW 99105175 A TW99105175 A TW 99105175A TW 201130060 A TW201130060 A TW 201130060A
Authority
TW
Taiwan
Prior art keywords
chip
protective layer
temporary protective
bumps
forming bumps
Prior art date
Application number
TW99105175A
Other languages
Chinese (zh)
Inventor
Hung-Hsin Hsu
Chih-Ming Ko
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW99105175A priority Critical patent/TW201130060A/en
Publication of TW201130060A publication Critical patent/TW201130060A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

Disclosed is a method for forming bumps. Initially, a chip is provided. Next, a temporary protective layer is formed on a surface of the chip, and then a plurality of through holes are formed to penetrate the temporary protective layer and the chip. Next, a plurality of metal pillars are formed in the through holes. A plurality of bumps are formed on the metal pillars to protrude from the temporary protective layer, and then the temporary protective layer is removed to provide a chip-bonding gap to make the bumps away from the chip. Accordingly, the filling space for underfiling is increased. There can be solved the conventional problem unable to filling TSV chip-bonding gap. It is not easy to form void.
TW99105175A 2010-02-23 2010-02-23 Method for forming bumps TW201130060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW99105175A TW201130060A (en) 2010-02-23 2010-02-23 Method for forming bumps

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW99105175A TW201130060A (en) 2010-02-23 2010-02-23 Method for forming bumps

Publications (1)

Publication Number Publication Date
TW201130060A true TW201130060A (en) 2011-09-01

Family

ID=50180096

Family Applications (1)

Application Number Title Priority Date Filing Date
TW99105175A TW201130060A (en) 2010-02-23 2010-02-23 Method for forming bumps

Country Status (1)

Country Link
TW (1) TW201130060A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700595A (en) * 2013-12-17 2014-04-02 中国电子科技集团公司第五十八研究所 Wafer level high-aspect-ratio TSV (through silicon via) package substrate preparation method
TWI661521B (en) * 2017-12-22 2019-06-01 美商美光科技公司 Semiconductor devices having electrically and optically conductive vias, and associated systems and methods

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700595A (en) * 2013-12-17 2014-04-02 中国电子科技集团公司第五十八研究所 Wafer level high-aspect-ratio TSV (through silicon via) package substrate preparation method
CN103700595B (en) * 2013-12-17 2016-07-06 中国电子科技集团公司第五十八研究所 A kind of wafer scale high-aspect-ratio TSV base plate for packaging preparation method
TWI661521B (en) * 2017-12-22 2019-06-01 美商美光科技公司 Semiconductor devices having electrically and optically conductive vias, and associated systems and methods
US10529659B2 (en) 2017-12-22 2020-01-07 Micron Technology, Inc. Semiconductor devices having electrically and optically conductive vias, and associated systems and methods
US11069612B2 (en) 2017-12-22 2021-07-20 Micron Technology, Inc. Semiconductor devices having electrically and optically conductive vias, and associated systems and methods

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