201126499 六、發明說明： 【發明所屬之技術頜 [0001] 本發明涉及一種移位暫存電路及利用該種移位暫存電路 構建的閘極踢動電路尤其係一種具有雙向傳輸功能的 閘極驅動電路。 [0002] 【先前技術】 目前，薄膜電晶體（Thin Fiim Transistor, TFT)液 晶顯示裝置已逐漸成為各種數位產品的標準輸出設備。 Λ [0003] 〇 〇 通常，液晶顯示裝置的驅動電路包括一資料驅動電路和 一掃描驅動電路。資料壤動電路用來控制每一圖元單元 的顯示輝度，閘極驅動電路則用來控制薄膜電晶體的導 通和截止。現有的整合至破璃基板上的閛極驅動電路以 移位暫存器作為核心電路單元，其將啟動脈衝訊號按照 一固定方向（上掃或下掃）逐行提供給各知圖元單元的薄 膜電晶體，依次導通各行的薄膜電晶體。然而，整合至 玻璃基板上之m閘極驅動電路的單向傳輸功能不能滿足 各種不同面板的需求。 [0004] 有鑒於此，有必要提供一種移位暫存電路及用該移位暫 存電路構建的具有雙向傳輸功能的閘極驅動電路，其在 搭配不同面板時有更多彈性空間。 【發明内容】 剛以下將以實_制-種純暫存祕及㈣移位暫存 電路構建的具有雙向傳輸功能的閘極驅動電路。 _6]-種移位兀寄存電路，其包括—個開關單元、—個預充 099101706 表單編號A0101 第3頁/共40頁 0992003304-0 201126499 電單元、一個脈衡訊號輸出單元、 jg - 疋 個低電平訊號控制 平兀、以及一個驅動訊號輪出 $小 °玄開關早元用於接收 v〜外部啟動訊號和一高電平， _ , δ亥開關早元在該至少 啟動訊號為高電平時開啟祐骑兮^ 〗驭並將該尚電平輸出至該 充電單元；該預充電單元用於拉你 於接收—時鐘脈衝訊號和201126499 VI. Description of the Invention: [Technical Jaw of the Invention] [0001] The present invention relates to a shift register circuit and a gate kick circuit constructed using the shift register circuit, in particular, a gate having a bidirectional transmission function Drive circuit. [Prior Art] At present, a thin film transistor (TFT) liquid crystal display device has gradually become a standard output device for various digital products. 0003 [0003] Generally, a driving circuit of a liquid crystal display device includes a data driving circuit and a scanning driving circuit. The data driving circuit is used to control the display luminance of each picture element, and the gate driving circuit is used to control the conduction and turn-off of the thin film transistor. The existing drain driving circuit integrated on the glass substrate uses a shift register as a core circuit unit, and the start pulse signal is provided to each known pixel unit row by row in a fixed direction (up sweep or down sweep). The thin film transistor sequentially turns on the thin film transistors of each row. However, the one-way transmission function of the m-gate drive circuit integrated on the glass substrate cannot meet the requirements of various panels. In view of the above, it is necessary to provide a shift register circuit and a gate drive circuit having a bidirectional transfer function constructed using the shift register circuit, which has more flexibility when matched with different panels. SUMMARY OF THE INVENTION A gate drive circuit having a bidirectional transmission function, which is constructed as follows, is constructed by a real-time temporary storage secret (4) shift temporary storage circuit. _6]-shift 兀 register circuit, including - switch unit, - precharge 099101706 form number A0101 page 3 / total 40 page 0992003304-0 201126499 electric unit, a pulse signal output unit, jg - 疋The low level signal control level, and a driving signal wheel out $ small ° Xuan switch early element is used to receive v ~ external start signal and a high level, _, δ hai switch early in the at least start signal for high power Usually open the ride 兮 ^ 〗 驭 and output the level to the charging unit; the pre-charge unit is used to pull you on the receiving - clock signal and
反向時鐘脈衝訊號，該預充電單元在接收到的反向時 ，里脈衡訊號為高電平時開始被該高電平預充電，該預充 電早元在接收到的時鐘脈衝簡為高電平時開始放電； 該脈衝訊號輸出單元用於接收該時鐘脈衝訊號，並在預 充電單元被預充電以後、放電完成之前將該時鐘脈衝訊 號輪出至驅動訊號輸出端；該低電平訊號控制單元用於 接收一時鐘脈衝訊號和反向時鐘脈衝訊號，並在預充電 單元放電完畢後根據反向時鐘脈衝訊號的高電平和時鐘 脈衝訊號的高電平交替將驅動訊號輸出端拉至一低電平 [0007] [0008] [0009] [0010] [0011] [0012] [0013] 一種閑極驅動電路，其包括依次電連接的m(m為大於1的 整數）個移位暫存單元， 第一個移位暫存單元包括： 一第一電平輸入端，用於接收第一電平訊號， 一第二電平輸入端，用於接收第二電平訊號， 一低電平輸入端，用於接收外部的低電平訊號， 一第一時鐘脈衝訊號輸入端，用於接收時鐘脈衝訊號’ 一第二時鐘脈衝訊號輸入端，用於接收反向時鐘脈衝訊 099101706 表單編號A0101 0992003304-0 201126499 號， [0014] 一第一啟動訊號輸入端，用於接收外部的第一啟動脈衝 訊號， [0015] —驅動訊號輸出端，用於輸出一第一驅動訊號， [0016] —第二啟動訊號輸入端，其耦合於第二個移位暫存單元 的參考電平結點， [0017] —參考電平結點，其連接至後一級移位暫存單元的第一 啟動訊號輸入端； 〇 [0018] 第n(n為大於1的偶數，且η小於m)個移位暫存單元包括： [0019] 一第一電平輸入端，用於接收第二電平訊號， [0020] —第二電平輸入端，用於接收第一電平訊號， [0021] 一低電平輸入端，用於接收外部的低電平訊號， [0022] 一第一時鐘脈衝訊號輸入端，用於接收反向時鐘脈衝訊 eJs. wt ’ ❹ [0023] 一第二時鐘脈衝訊號輸入端，用於接收時鐘脈衝訊號， [0024] 一第一啟動訊號輸入端，其耦合於第（n-1)個移位暫存單 元的參考電平結點’ [0025] 一第二啟動訊號輸入端，其耦合於第（n + 1)個移位暫存單 元的參考電平結點5 [0026] —驅動訊號輸出端，用於輸出一第η驅動訊號； [0027] 第ρ(ρ為大於1的奇數，且ρ小於m)個移位暫存單元包括： 099101706 表單編號A0101 第5頁/共40頁 0992003304-0 201126499 [0028] 一 第一命 q> ；Lv 电千輸入端，用於接收第一電平訊號， [0029] -第二電平輪人端，用於接收第二電平訊號， [0030] 一 低雷 | '千輸入编，用於接收外部的低電平訊號， 第時釦脈衝訊號輸入端，用於接收時鐘脈衝訊號， 剛-第二時鐘脈衝訊號輸入端，用於接收反向時鐘脈衝訊 號， 第啟動訊號輸入端，其轉合於第（p-l)個移位暫存單 元的參考電平結點， [0034] 第—啟動訊號輪入端，其耦合於第（p + 1 )個移位暫存單 元的參考電平結點， [0035] 一驅動訊號輪出端，用於輸出一第口驅動訊號； [0036] 第m個移位暫存單元包括： [0〇37] —第一電平輸入端，用於接收第—電平惠號， [0038] 一第二電平輸入端，用於接收第二電平訊號， [0039] —低電平輸入端，用於接收外部的低電平訊號， [0040] 一第一時鐘脈衝訊號輸入端’用於接收時鐘脈衝訊號， [0041] 一第二時鐘脈衝訊號輸入端，用於接收反向時鐘脈衝訊 號， [0042] 一第一啟動訊就輸入端，其耗合於第（m-Ι)個移位暫存單 元的參考電平結點， [0043] 099101706 一第二啟動訊號輸入端，用於接收外部的第二啟動脈衝 表單.编號A0101 第6頁/共40頁 0992003304-0 201126499 [0044] [0045] Ο [0046] [0047] [0048] ❹ 訊號， 號輸出端，用於輪出—第_動訊號。 相較於切技術，財㈣實施 的閉極驅動電路，其可從第—個移位=存電路構建 移位元寄存單元的職訊號輪出端依::存單元至第m個 外部電路，也可從第„個移位元寄存單人/出一二電平到 寄存單元_訊_端依⑽:—個移位元 路，誃雜a神认 π電千到外部電 板時二使該動電路在搭配不同面 【實施方式】 下面將結合_對本發明作進—步詳細說明。 = ，圖1係本發明_提供的問極驅 =路_電路框架示意圖，圖㈣接驅動電路ι〇的電路 結構示意圖。 本發明實施方式提供的_驅動電路1G，其包括_為大 於的整數）個電路結構相同的移位暫存單元S1〜S⑷’ 該多個移位暫存單元Sl〜s(m)依錢連接。每—個移位 暫存單元 一 〜1各m)包括一第一電平輸入端VCIN， 電平輸入端VCINB，一低電平輪入端VGL，一第一 時鐘脈衝訊號輪人端CL〇CK，-第二時鐘脈衝訊號輸入端 CL0CKB 第—啟動訊號輸入端STVA，一第二啟動訊號 輸入端STVB，以及~驅動訊號輸出端V0UT，-參考電平 結點N (i )。 099101706 該移位暫存單仙的第-電平輸人端VC IN連接至外部電 第7頁/共40頁 表單編號A0101 0992003304-0 [0049] 201126499 路以接收第一電平訊號代1 ;該移位暫存單元S1的第二電 平輸入端VCINB連接至外部電路以接收第二電平訊號VC2 ’遠移位暫存單元si的低電平輸入端VGL連接至外部電路 以接收低電平錢；該錢暫存單元S1的第—時鐘輯 訊號輪入端CLOCK用於接枚時鐘脈衝訊號cu ;該移位暫 存單^cSl的第二時鐘脈衝訊號輸入端CL〇CKB用於接收反 向時鐘脈衝訊號CLKB ;該移位暫存單⑽的第—啟動訊 號輸入端sm用於接收-外部的啟動脈^TV1 ;該移位 暫存單7GS1的第二啟動訊號輸入端STVB連接至後一級移 位暫存單AS2轉考冑平結點N2 ;鮮位暫存uSi的 〇 驅動讯號輸出端V0UT用於輪出一電平訊號〇ϋτ1至外部電 路；該移位暫存單⑽的參考電平結麵連接至後—級 移位暫存單7^2的第-啟動訊號輪人端抓八。 [0050] 該移位暫存單Μ(η)(η為大於i的偶數，且时㈣的帛 一電平輸入端VCIN連接至夕卜部電路以接收第一電平訊號 VC1 ’該移位暫存單元的第二電平輸入端連接 至外部電路以接㈣二電平訊號VG2 :該移位暫存單元 S(n)的低電平輸人端VGL連接至外部電路以接收低電平訊 U 號玄移位暫存單元s⑷的第一時鐘脈衝訊號輸入端 CLOCK用於接收反向時鐘脈衝訊號CL〇 ;該移位暫存單 Μ(η)的第二時鐘脈衝訊號輸入端CL〇CKB用於接收時鐘 脈衝訊號CLK ;該移位暫存單元s(n)的第一啟動訊號輸入 端STVA連接至前'級移位暫存單元δ(η_υ的參考電平結 點NU-1);該移位暫存單元8⑷的第二啟動訊號輪入端 STVB連接至後一級移位暫存單元仏+1)的參考電平結點 099101706 表單編號Α0101 第8頁/共4〇頁 0992003304-0 201126499 Ν(η + 1);該移位暫存單元s(n)的驅動訊號輸出端ν〇υτ用 於輸出—電平訊號〇UT(n)至外部電路；該移位暫存單元 S(n)的參考電平結點N(n)連接至後一級移位暫存單元 S(n + 1)的第一啟動訊號輸入端STVA，並連接到前一級移 位暫存單元S(n-i)的第二啟動訊號輸入端STVB。 [0051] Ο 該移位暫存單元s(p)(p為大於i的奇數，且p小於m)的第 一電平輸入端VCIN連接至外部電路以接收第—電平訊號 vci ;該移位暫存單元s(p)的第二電平輸入端vcinb連接 至外部電路以接收第二電平訊號VC2 ;該移位暫存單元 S(P)的低電平輸入端VGL連接至外部電路以接收低電平訊 號；該移位暫存單Μ(ρ)的第—時鐘脈衝訊號輸入端° CLOCK用於接收時鐘脈衝訊號ακ ;該移位暫存單元以口） 的第—時鐘脈衝訊號輸人端⑽⑽用於接收時鐘脈衝訊 號CLKB ;該移位㈣單元s(p)的第—雜訊號輸入端 STVA連接至前-級移位暫存單元的參考電平結點 ο Ν(ρ-ι);該移位暫存單元s(p)的第二啟動訊號輪入端 STVB連接至後一級移位暫存單元s(p⑴的參考電平結點 N(P+1);該移位暫存單元s(p)的驅動訊號輪出端用 於輸出-電平訊號〇υτ(ρ)至外部電路；該移位暫存單元 S(p)的參考電平結點Ν(ρ)連接至後—級移位暫存單元 S(P+1)的第-啟動訊號輸人端sm，並連接到前一級 暫存單itS(p-l)的第二啟動訊號輸人端奶^。 [0052] 099101706 «亥移位暫存早以⑷的第_電平輸人端乂⑽連 電路以接收第一電平批士 外邛 乐1：十訊戒VC1 ;該移位暫存單元5( -電平輸人端VCINB連接至外部電路以接收第二電平訊號 表單編號A0101 « 0 第9頁/共40頁 0992003304h 201126499 VC2 ;該移位暫存單元s(m)的低電平輸入端VGL連接至外 部電路以接收低電平訊號；該移位暫存單元S(m)的第— 啟動訊號輸入端STVA連接至前一級移位暫存單元S(m-i) 的參考電平結點N(m-l);該移位暫存單元S(m)的驅動訊 號輸出端VOUT用於輪出一電平訊號〇UT(m)至外部電路； 該移位暫存單元S(m)的第二啟動訊號輸入端STVB用於接 收一外部的啟動脈衝STV2。當m為奇數時’該移位暫存單 元S(m)的第一時鐘脈衝訊號輸入端CLOCK用於接收時鐘 脈衝訊號CLK ;該移位暫存單元s(m)的第二時鐘脈衝訊號 輸入端CL0CKB用於接收反向時鐘脈衡訊號CLKB。當m為 偶數時，該移位暫存單元S(m)的第一時鐘脈衝訊號輸入 端CLOCK用於接收反向時鐘脈衝訊號CLKB ;該移位暫存 單元S(m)的第二時鐘脈衝訊號輸入端cl〇ckb用於接收時 鐘脈衝訊號CLK。 [0053] [0054] 參見圖3，上述閘極驅動電路1〇的每一個移位暫存單元 S(i)包括一個開關單元u、一個預充電單元12、一個脈 衝訊號輸出單元13、一個低電平訊號控制單元14以及一 個驅動訊號輸出端V0UT。 該開關單元11包括第-電晶體M1、第二電晶麵、第三 電晶體M3及第四電晶體μ。該移位暫存單元犯）的第一 電平輸入端vci·由第二電晶體M2的祕和源極、第一 電晶體Ml的祕和源極連接至第—啟動訊號輸人端stva 。該移位暫存單元S⑴的該第二電平輸入跳⑽經由 第四電晶舰較極和源極、第三電晶體_没極和源 極連接至第：啟動訊號輸人糾㈣。該第_電晶體们的 099101706 表單編號A0101 第10頁/共40頁 0992003304-0 201126499 閘極連接至第一啟動訊號輸入端STVA。該第三電晶體M3 的閑極連接至第一啟動訊號輸入端STVB。該第一電晶體The reverse clock signal, the pre-charging unit starts to be pre-charged by the high level when the pulse-balance signal is high in the received reverse direction, and the pre-charging early element is simply high in the received clock pulse. The pulse signal output unit is configured to receive the clock signal, and the clock signal is output to the driving signal output terminal after the pre-charging unit is pre-charged and before the discharging is completed; the low-level signal control unit It is configured to receive a clock pulse signal and a reverse clock pulse signal, and after the pre-charge unit is discharged, alternately drive the signal output terminal to a low voltage according to the high level of the reverse clock pulse signal and the high level of the clock pulse signal. [0012] [0013] [0013] [0013] [0013] [0013] [0013] A sleeper drive circuit, comprising sequentially electrically connected m (m is an integer greater than 1) shift temporary storage unit, The first shift register unit includes: a first level input terminal for receiving the first level signal, and a second level input terminal for receiving the second level signal, a low level input terminal For picking up Receiving an external low-level signal, a first clock pulse signal input terminal for receiving a clock pulse signal 'a second clock pulse signal input terminal for receiving a reverse clock pulse signal 099101706 Form No. A0101 0992003304-0 201126499 [0014] a first start signal input end for receiving an external first start pulse signal, [0015] a drive signal output end for outputting a first drive signal, [0016] - a second start signal input a reference level node coupled to the second shift register unit, [0017] a reference level node connected to the first enable signal input terminal of the subsequent stage shift register unit; 0018] The nth (n is an even number greater than 1, and η is less than m) shift register units include: [0019] a first level input terminal for receiving the second level signal, [0020] - a two-level input terminal for receiving a first level signal, [0021] a low level input terminal for receiving an external low level signal, [0022] a first clock pulse signal input terminal for receiving Reverse clock pulse eJs. wt ' ❹ [0023] a second clock signal input terminal for receiving a clock signal, [0024] a first start signal input coupled to the reference level node of the (n-1)th shift register unit [0025] a second enable signal input terminal coupled to the reference level node 5 of the (n + 1)th shift register unit [0026] - a drive signal output terminal for outputting an ηth drive signal; 0027] The ρ (ρ is an odd number greater than 1, and ρ is less than m) shift register units include: 099101706 Form number A0101 Page 5 / Total 40 pages 0992003304-0 201126499 [0028] A first life q>; Lv electric thousand input terminal for receiving the first level signal, [0029] - second level wheel human terminal for receiving the second level signal, [0030] a low thunder | '1000 input code for Receiving an external low-level signal, the first pulse signal input end is for receiving a clock pulse signal, and the just-second clock pulse signal input end is for receiving a reverse clock pulse signal, and the first start signal input end is turned Reference level node of the (pl) shift register unit, [0034] a wheel input end coupled to a reference level node of the (p + 1 )th shift register unit, [0035] a drive signal wheel output for outputting a first port drive signal; [0036] The m shift temporary storage units include: [0〇37] - a first level input terminal for receiving the first level credit, [0038] a second level input terminal for receiving the second level Signal, [0039] - a low level input for receiving an external low level signal, [0040] a first clock signal signal input 'for receiving a clock signal, [0041] a second clock signal The input end is configured to receive the reverse clock pulse signal, [0042] a first start signal is input to the input end, which is consumed by the reference level node of the (m-th) shift temporary storage unit, [0043] 099101706 A second start signal input terminal for receiving an external second start pulse form. No. A0101 Page 6 / Total 40 pages 0992003304-0 201126499 [0045] [0048] [0048] ❹ Signal, number output, for round-out - _ motion signal. Compared with the cutting technology, the closed-circuit driving circuit implemented by Cai (4) can construct the shifting signal output unit of the shifting meta-register unit from the first shift=storage circuit according to the :: storage unit to the mth external circuit, It is also possible to register a single person/out one or two levels from the „shift unit to the register unit _ _ end according to (10): a shifting element road, noisy a god recognizes π electric thousand to the external electric board The dynamic circuit is combined with different surfaces. [Embodiment] The following is a detailed description of the present invention. =, Figure 1 is a schematic diagram of the circuit board provided by the present invention. The circuit diagram of (4) is connected to the driving circuit. A schematic diagram of a circuit structure of the present invention. The _ drive circuit 1G provided by the embodiment of the present invention includes _ is greater than an integer number of shift register units S1 S S(4)' having the same circuit structure. The plurality of shift register units S1 s (m) Connected by money. Each shift register unit 1 to 1 m) includes a first level input terminal VCIN, a level input terminal VCINB, a low level round input terminal VGL, and a first clock. Pulse signal wheel terminal CL〇CK, - second clock pulse signal input terminal CL0CKB first - start signal input terminal S TVA, a second start signal input terminal STVB, and a ~drive signal output terminal VOUT, - reference level node N (i). 099101706 The shift-stage temporary single-level input-level VC IN is connected to the external Page 7 of 40 Form No. A0101 0992003304-0 [0049] 201126499 way to receive the first level signal generation 1; the second level input terminal VCINB of the shift register unit S1 is connected to an external circuit to receive The low level input terminal VGL of the second level signal VC2' remote shift register unit si is connected to the external circuit to receive the low level money; the first clock signal input terminal CLOCK of the money temporary storage unit S1 is used for The clock pulse signal cu is connected to the second clock signal signal input terminal CL〇CKB of the shift temporary storage unit ^cS1 for receiving the reverse clock pulse signal CLKB; the first start signal input terminal sm of the shift temporary storage unit (10) is used The receiving-external starting pulse ^TV1; the second starting signal input terminal STVB of the shift temporary storage list 7GS1 is connected to the subsequent stage shift temporary storage list AS2 to test the leveling node N2; the fresh bit temporarily storing the uSi driving signal The output terminal V0UT is used to rotate a level signal 〇ϋτ1 to an external circuit; The reference level junction of the shift temporary storage list (10) is connected to the first-start signal wheel of the post-stage shift temporary storage unit 7^2. [0050] The shift temporary storage unit η(η) (η is An even number greater than i, and the first level input terminal VCIN of the (four) is connected to the external circuit to receive the first level signal VC1 'the second level input of the shift register unit is connected to the external circuit to connect (4) The two-level signal VG2: the low-level input terminal VGL of the shift temporary storage unit S(n) is connected to an external circuit to receive the first clock pulse signal input of the low-level U-number shift register unit s(4) The terminal CLOCK is configured to receive the reverse clock signal CL〇; the second clock signal signal input terminal CL〇CKB of the shift register unit Μ is used to receive the clock signal CLK; the shift register unit s(n) The first start signal input terminal STVA is connected to the front 'stage shift register unit δ (n_υ reference level node NU-1); the second start signal wheel input terminal STVB of the shift register unit 8(4) is connected Reference level node of the first stage shift register unit 仏 +1) 099101706 Form number Α 0101 Page 8 / Total 4 pages 0992003304-0 201126 499 Ν(η + 1); the drive signal output terminal ν〇υτ of the shift register unit s(n) is used for outputting the level signal 〇UT(n) to the external circuit; the shift register unit S ( The reference level node N(n) of n) is connected to the first start signal input terminal STVA of the rear stage shift register unit S(n+1), and is connected to the previous stage shift register unit S(ni) The second start signal input terminal STVB. [0051] 第一 the shift register unit s(p) (p is an odd number greater than i, and p is less than m), the first level input terminal VCIN is connected to the external circuit to receive the first level signal vci; The second level input terminal vcinb of the bit buffer unit s(p) is connected to an external circuit to receive the second level signal VC2; the low level input terminal VGL of the shift register unit S(P) is connected to the external circuit Receiving a low level signal; the first clock pulse signal input end of the shift temporary storage unit (ρ) is used to receive the clock pulse signal ακ; the shift temporary storage unit is input by the first clock pulse signal of the port) The human terminal (10) (10) is configured to receive the clock signal CLKB; the first (s) signal input terminal STVA of the shifting (four) unit s (p) is connected to the reference level node of the pre-stage shift register unit ο Ν (ρ-ι The second enable signal rounding terminal STVB of the shift register unit s(p) is connected to the reference level node N(P+1) of the subsequent stage shift register unit s (p(1); The drive signal output end of the memory unit s(p) is used to output the -level signal 〇υτ(ρ) to the external circuit; the reference level node Ν(ρ) of the shift register unit S(p) is connected to Rear The first start signal input end sm of the stage shift register unit S(P+1) is connected to the second start signal input end milk of the previous stage temporary storage unit itS(pl). [0052] 099101706 «亥The shift temporary storage is connected to the circuit by the first _ level input terminal (10) of (4) to receive the first level of external music: 1:10 or VC1; the shift register unit 5 (-level input) The VCINB is connected to an external circuit to receive the second level signal form number A0101 « 0 page 9 / total 40 pages 0992003304h 201126499 VC2 ; the low level input terminal VGL of the shift register unit s (m) is connected to the external circuit Receiving a low level signal; the first start signal input terminal STVA of the shift register unit S(m) is connected to a reference level node N(ml) of the previous stage shift register unit S(mi); The driving signal output terminal VOUT of the shift register unit S(m) is used to rotate a level signal 〇UT(m) to an external circuit; the second start signal input terminal STVB of the shift register unit S(m) For receiving an external start pulse STV2. When m is an odd number, the first clock signal input terminal CLOCK of the shift register unit S(m) is used for receiving the clock signal CLK; The second clock signal input terminal CL0CKB of the shift register unit s(m) is configured to receive the reverse clock pulse balance signal CLKB. When m is an even number, the first clock pulse of the shift register unit S(m) The signal input terminal CLOCK is for receiving the reverse clock signal CLKB; the second clock signal input terminal cl〇ckb of the shift register unit S(m) is for receiving the clock signal CLK. [0054] Referring to FIG. 3, each of the shift register units S(i) of the gate driving circuit 1A includes a switching unit u, a pre-charging unit 12, a pulse signal output unit 13, and a low The level signal control unit 14 and a drive signal output terminal VOUT. The switching unit 11 includes a first transistor M1, a second transistor face, a third transistor M3, and a fourth transistor μ. The first level input terminal vci of the shift register unit is connected by the secret source of the second transistor M2, the secret source of the first transistor M1, and the first start signal input terminal stva. The second level input hop (10) of the shift register unit S(1) is connected to the third transistor via the fourth and fourth transistors, the third transistor, and the source to the enable signal (4). 099101706 Form No. A0101 Page 10 of 40 0992003304-0 201126499 The gate is connected to the first start signal input terminal STVA. The idle electrode of the third transistor M3 is connected to the first start signal input terminal STVB. The first transistor
Ml的汲極、第二電晶體M2的源極、第三電晶體M3的汲極 及第四電晶體M4的源極相互連接而形成—充電電平結點（ 圖未示）。 [0055]The drain of M1, the source of the second transistor M2, the drain of the third transistor M3, and the source of the fourth transistor M4 are connected to each other to form a charge level node (not shown). [0055]
[0056][0056]
該第二電晶體M2的閘極連接至後一級移位暫存單元的驅 動訊號輸出端VOUT(特例：第^!個移位暫存單元的第_ 晶體M2的閘極連接至第二啟動訊號輸入端STVB)，該第電 電晶體M4的開極連接至前―級移位暫存單元的驅動:B 輸出端VOUT(特例：第一個移位暫存單元的第 1 的閘極連接至第一啟動訊號輪入端STVA) » 當第二電平輸入端VCINB提供高電平時候，該第 M4的閘極用於接收該至少一外部啟動訊號， 晶體M4接收到的外部啟動訊號反轉為高電平時，該第 電晶體M4便可導通，從而該第四電晶體M4的汲極所接收 到的第一電平輸入端VCINB的高電平便可到達上述充 平結點，以用於向預充電單元12輸出高電平。 電 四電晶體M4 四電晶體 旦第四電 [0057]當第一電平輪入端VCIN提供高電平時候，該第二 一 ^晶體 M2的閘極用於接收該至少一外部啟動訊號，一日 —*系二電 晶體M2接收到的外部啟動訊號反轉為高電平時，哕第_ 電晶體M2便可導通，從而該第二電晶體M2的汲極所接收 到的第一電平輸入端VC IN的高電平便可到達上述充電 平結點，以用於向預充電單元丨2輸出高電平。 [0058]該預充電單元12包括第二電容C2、第六電晶體M6， 及第 099101706 表單編號A0101 第11頁/共40頁 0992003304-, 201126499 十電晶體Ml 0。該第二電容C2的一個電極與第六電晶體M6 的沒極相連接’以用於接收開關單元11輸出的高電平。 該第二電容C2的另一個電極與第六電晶體M6的源極相連 ’且該另一個電極還經由第十電晶體Ml 0的源極和汲極接 至低電平輸入端VGL以接收低電平。該第六電晶體M6的閘 極連接至第一時鐘脈衝訊號輸入端CLOCK，該第十電晶體 M10的閘極連接至第二時鐘脈衝訊號輸入端CL〇CKB。 [0059] [0060] [0061] 099101706 當第六電晶體M6的閘極接收到第一時鐘脈衝訊號輸入端 CLOCK的時鐘脈衝訊號為低電平、而第十電晶體M10的閘 極接收到第二時鐘脈衝訊號輸入端CL0CKB的反向時鐘脈 衝訊號為高電平時，該第六電晶體M6截止而第十電晶體 M10導通’該第二電容C2被開關單元丨丨提供的高電平充電 〇 當第六電晶體M6的閘極接收到第一時鐘舨衝訊號輸入端 CLOCK的時鐘脈衝訊號為高電平、而第十電晶體Ml 0的閘 極接收到第二時鐘脈衝訊辕輸入端；^CKB的反向時鐘脈 衝訊號為低電平時，該第六電晶體M6導通而第十電晶體 M10截止’該第二電容C2放電。 該脈衝訊號輸出單元13包括第八電晶體M8，該第八電晶 體M8的源極連接至第一時鐘脈衝訊號輸入端CLOCK，該第 八電晶體M8的没極連接至驅動訊號輸出端v〇UT，該第八 電晶體M8的閘極與預充電單元12相連以在預充電單元12 被預充電後被拉升至高電平而使得該第八電晶體M8導通 ’進而將該第一時鐘脈衝訊號輸入端CLOCK的訊號輸出至 驅動訊號輸出端V0UT。 表單編號A0101 第12頁/共40頁 0992003304-0 201126499 _2]該低％平訊號控制單元14包括第五電晶體奶、第七電晶 體M7、第九晶體㈣、第十一電晶體叫以及第一電容ci 〇 . 剛_位暫存單元的驅動訊號輸出端VGUT經由該第十一電 晶體Mil的源極和祕連接至低電平，該第十—電晶體 Mil的間極連接至第二時鐘脈衝訊號輪人端。該 第十一電晶體Mil在預充電單元12放電完畢後、且第二時 鐘脈衝訊號輸入端CL0CKB為高電平時導通並將驅動訊號 輸出端V0UT拉至一低電平。 〇 _] $第七電晶體M7的閘極與預充電單元12相連以在預充電 單兀12放電完畢前導通，該第五電晶體贴的閘極經由該 第七電晶體M7的汲極和源極連接至該第一時鐘脈衝訊號 - 輸入端CL0CKa在預充電單元12被放電惠畢前導通，該第 九電晶體M9的閘極經由第五電晶體心的汲極和源極連接 至低電平輸入端VGL以在預充電單元12被放電完畢前被拉 至低電平而截止。 0 [0065]該第七電晶體M7在預充電單元放電完畢後截止，進而第 五電晶趙M5截止，該驅動訊號輸出端ν〇υτ經由該第九電 晶體M9的源極和汲極連接至低電平輸入端VGL以接收低電 平’且該第九電晶體M9的閘極經由第一電容ci連接至該 第一時鐘脈衝訊號輸入端CLOCK，從而當預充電單元12放 電完畢後、且第一時鐘脈衝訊號輸入端CLOCK為高電平時 該第九電晶體M9的閘極被拉至高電平而導通，進而將驅 動訊號輸出端V0UT拉至一低電平。 099101706 表單編號A0101 第13頁/共40頁 0992003304-0 201126499 [0066]各移位暫存單元3⑴的第一至第十一電晶體、μ... 、MU均為N型薄膜電晶體。 [0067] [0068] [0069] [0070] ‘ ·二基於間化電路結構的考量，因為所述第十電晶體 M10與第十一電晶體Mil的電路連接關係相同，且二者的 · 功忐可藉由同一個電晶體實現，因此可省略圖2所示的第 十—電晶體Mil，從而藉由第十電晶體M1〇同時實現原第 十—電晶體Mil在低電平訊號控制單元14中的作用。 圖4所示即為利用省略第十一電晶體M1 j的移位暫存單元 構建的閘極驅動電路結構示意圖。請一併參見圖5，係閘 〇 極驅動電路10進行下掃操作（按Si、S2…S(m)的順序依 次向外部電路輸出一高電平）的工作時序示意圖。該種工 作狀態下，外部啟動脈衝STV2以及第一電平訊號νπ恒定 為低電平，第二電平訊號VC2恒定為高電年。 (a)在T0之前的時段’外部啟動脈衝STVi、時鐘脈衝訊 號CLK以及反向時鐘脈衝訊號(^〇均為低電平。該時段為 初始狀態’各移位暫存單元Si、S2…S(m)的驅動訊號輸 出端V0UT輸出的電平訊號ουτί ' 0UT2、〇UT3…此時段 均為低電平。 在το時段’外部啟動脈衝STV1為高電平，時鐘脈衝 訊號CLK為低電平，反向時鐘脈衝訊號CLKB為高電平。移 位暫存單元SI、S2…S(m)均輸出低電平。 對於移位暫存單元Si而言，由於反向時鐘脈衝訊號CLKB 為高電平’移位暫存單元S1的第十電晶體M1〇導通，移位 暫存單元S1的驅動訊號輸出端ν〇υτ直接與低電平輸入端 099101706 表單編號Α0101 第14頁/共40頁 0992003304-0 [0071] 201126499 [0072] Ο [0073] Ο [0074] VGL相連，因此移位暫存單元S1的驅動訊號輸出端叩耵 被拉至低電平，其輸出的電平訊號OUT1在T1時段為低電 平。 " 此外，由於T1時刻外部啟動脈衝以^為高電平，移位暫 存單凡S1的第一電晶體Ml、M4導通，從而第二電平訊號 VC2藉由第四電晶體“的汲極和源極對移位暫存單元w的 第一電容C2充電。同時，由於第二電容。被充電時第七 電晶體M7的閘極餘至高電平，該第七電晶體们導通， 此刻’時鐘脈衝訊號CLK藉由第七電晶·7的源極和沒極 把移位暫存單元S1的參考電平結點N1拉至低電平。 料移位暫存單谈p)(p為大於1的奇數，且卩小㈣而 吕，同樣由於反向時鐘脈衝訊號CLKB為高電平，移位暫 存單元s(p)的第十電晶體Ml〇導通，移位暫存單元8(“ 的驅動訊號輪出端_T直接與低電平輪人端VGL相連因 此移位暫存單^(P)的驅動訊號輸出端刪τ被拉至低電 平，移位暫存單its(p)輸出的電平訊號GUT⑻如時段 為低電平。此時刻’移位暫存單元s(p)的第二電容㈣ 均未被充電’且其參考電平結_(p)為低電平。 對於移位暫存單元S(n)(n為大於i的偶數，且ny)而 言，由於移位暫存單以（n)的前、後級移位暫存單元的 驅動訊號輸_剛1均輸出低電平，轉 S(n)的前、後級移位暫存單元的參考電平結點為低電平 ’因此移位暫存單元S(一第二電⑽均未被充電且移 位暫存單元s(n)的驅動訊號輸出端VOUT的電平訊號 OUT(n)為低電平。 ' 099101706 表單編號Α010Ι 第15頁/共40頁 0992003304-0 201126499 [0075] [0076] [0077] [0078] 對於移位暫存單元s⑷而言，m為大於〗的奇數或偶數， α此移位暫存單sS(m)的輸出情況與s(p)或者s(n)相同 ，其驅動訊號輪出端VOUT的電平訊號〇ϋτ(ω)為低電平。 (C)在Τ2時段，外部啟動脈衝STV1為低電平，時鐘脈衝 訊號CLK為高電平，反向時鐘脈衝訊號CLKB為低電平。移 位暫存單端輪丨高電平，其他移位暫存料均輸出低 電平。The gate of the second transistor M2 is connected to the driving signal output terminal VOUT of the rear stage shift register unit (special case: the gate of the first crystal M2 of the first shift register unit is connected to the second start signal Input terminal STVB), the open electrode of the first transistor M4 is connected to the drive of the pre-stage shift register unit: B output terminal VOUT (special case: the first gate of the first shift register unit is connected to the first When the second level input terminal VCINB is supplied with a high level, the gate of the M4 is used to receive the at least one external start signal, and the external start signal received by the crystal M4 is inverted to When the level is high, the first transistor M4 can be turned on, so that the high level of the first level input terminal VCINB received by the drain of the fourth transistor M4 can reach the above-mentioned leveling node for use in A high level is output to the precharge unit 12. The electric four-electrode M4 four-electrode is the fourth electric power [0057] when the first level-in terminal VCIN provides a high level, the gate of the second crystal M2 is used to receive the at least one external start signal, When the external start signal received by the second transistor M2 is inverted to a high level, the first transistor M2 can be turned on, so that the first level received by the drain of the second transistor M2 is received. The high level of the input terminal VC IN can reach the above-mentioned charging level node for outputting a high level to the pre-charging unit 丨2. The pre-charging unit 12 includes a second capacitor C2, a sixth transistor M6, and a 099101706 form number A0101 page 11/total 40 page 0992003304-, 201126499 ten transistor M10. One electrode of the second capacitor C2 is connected to the pole of the sixth transistor M6 for receiving a high level of the output of the switching unit 11. The other electrode of the second capacitor C2 is connected to the source of the sixth transistor M6 and the other electrode is also connected to the low level input terminal VGL via the source and the drain of the tenth transistor M10 to receive low Level. The gate of the sixth transistor M6 is connected to the first clock signal input terminal CLOCK, and the gate of the tenth transistor M10 is connected to the second clock signal signal input terminal CL〇CKB. [0060] [991] 099101706 When the gate of the sixth transistor M6 receives the clock pulse signal of the first clock signal signal input terminal CLOCK is low level, and the gate of the tenth transistor M10 receives the first When the reverse clock signal of the two clock signal input terminal CL0CKB is at a high level, the sixth transistor M6 is turned off and the tenth transistor M10 is turned on. 'The second capacitor C2 is charged by the switching unit 高电平. When the gate of the sixth transistor M6 receives the clock pulse signal of the first clock buffer signal input terminal CLOCK is high level, and the gate of the tenth transistor M10 receives the second clock pulse signal input terminal; When the reverse clock pulse signal of CKB is low level, the sixth transistor M6 is turned on and the tenth transistor M10 is turned off 'the second capacitor C2 is discharged. The pulse signal output unit 13 includes an eighth transistor M8. The source of the eighth transistor M8 is connected to the first clock signal input terminal CLOCK, and the electrode of the eighth transistor M8 is connected to the driving signal output terminal. UT, the gate of the eighth transistor M8 is connected to the pre-charging unit 12 to be pulled up to a high level after the pre-charging unit 12 is pre-charged, so that the eighth transistor M8 is turned on' and then the first clock pulse The signal of the signal input CLOCK is output to the drive signal output terminal VOUT. Form No. A0101 Page 12 / Total 40 Pages 0992003304-0 201126499 _2] The low % flat signal control unit 14 includes a fifth transistor milk, a seventh transistor M7, a ninth crystal (four), an eleventh transistor, and a a capacitor ci 〇. The drive signal output terminal VGUT of the just-bit temporary storage unit is connected to the low level via the source and the secret of the eleventh transistor Mil, and the inter-electrode of the tenth-transistor Mil is connected to the second Clock pulse signal wheel. The eleventh transistor Mil is turned on after the pre-charging unit 12 is discharged, and is turned on when the second clock signal input terminal CL0CKB is high level, and pulls the driving signal output terminal VOUT to a low level. 〇_] $The gate of the seventh transistor M7 is connected to the pre-charging unit 12 to be turned on before the pre-charging unit 12 is discharged, and the gate of the fifth transistor is past the drain of the seventh transistor M7. The source is connected to the first clock signal - the input terminal CL0CKa is turned on before the pre-charging unit 12 is discharged, and the gate of the ninth transistor M9 is connected to the low via the drain and the source of the fifth transistor core. The level input terminal VGL is turned off to be pulled low before the precharge unit 12 is discharged. [0065] The seventh transistor M7 is turned off after the pre-charging unit is discharged, and the fifth transistor M5 is turned off, and the driving signal output terminal ν〇υτ is connected through the source and the drain of the ninth transistor M9. The low level input terminal VGL receives the low level ' and the gate of the ninth transistor M9 is connected to the first clock signal input terminal CLOCK via the first capacitor ci, so that when the precharge unit 12 is discharged, When the first clock signal input terminal CLOCK is at a high level, the gate of the ninth transistor M9 is pulled to a high level to be turned on, thereby pulling the driving signal output terminal VOUT to a low level. 099101706 Form No. A0101 Page 13 of 40 0992003304-0 201126499 [0066] The first to eleventh transistors, μ..., and MU of each shift register unit 3(1) are N-type thin film transistors. [0070] [2] based on the consideration of the structure of the inter-layer circuit, because the tenth transistor M10 and the eleventh transistor Mil have the same circuit connection relationship, and the work of both忐 can be realized by the same transistor, so the tenth-transistor Mil shown in FIG. 2 can be omitted, so that the tenth transistor M1 〇 can simultaneously realize the original tenth-transistor Mil in the low-level signal control unit. The role of 14. Fig. 4 is a schematic view showing the structure of a gate driving circuit constructed by omitting a shift register unit omitting the eleventh transistor M1 j . Referring to Fig. 5 together, the operation timing diagram of the gate driving circuit 10 for performing the down scanning operation (outputting a high level to the external circuit in the order of Si, S2, ..., S(m)) is shown. In this working state, the external start pulse STV2 and the first level signal νπ are constantly at a low level, and the second level signal VC2 is constantly at a high power year. (a) The period before the T0 'external start pulse STVi, clock pulse signal CLK and reverse clock pulse signal (^〇 are all low level. This period is the initial state' each shift register unit Si, S2...S (m) The drive signal output terminal V0UT outputs the level signal ουτί ' 0UT2, 〇 UT3... This period is low level. In the το period 'the external start pulse STV1 is high level, the clock pulse signal CLK is low level The reverse clock signal CLKB is at a high level. The shift register units SI, S2, ..., S(m) both output a low level. For the shift register unit Si, since the reverse clock signal CLKB is high The tenth transistor M1 of the level shifting unit S1 is turned on, and the driving signal output terminal ν〇υτ of the shift register unit S1 is directly connected to the low level input terminal 099101706. Form number Α0101 Page 14 of 40 0992003304-0 [0071] 201126499 [0072] 007 [0074] VGL is connected, so the drive signal output terminal 移位 of the shift register unit S1 is pulled low, and the output level signal OUT1 is The T1 period is low. " In addition, due to the external start pulse at time T1 When ^ is at a high level, the first transistors M1, M4 of the shift register S1 are turned on, so that the second level signal VC2 is shifted by the drain and source pairs of the fourth transistor " The first capacitor C2 is charged. At the same time, due to the second capacitor, when the gate of the seventh transistor M7 is charged to the high level, the seventh transistor is turned on, and the clock pulse signal CLK is at the moment by the seventh transistor. · The source and the pole of 7 pull the reference level node N1 of the shift register unit S1 to a low level. The material shift temporary table talks p) (p is an odd number greater than 1, and is small (four) and Lu Similarly, since the reverse clock signal CLKB is at a high level, the tenth transistor M1 of the shift register unit s(p) is turned on, and the shift register unit 8 is shifted ("the drive signal wheel output terminal _T directly The low-level wheel terminal VGL is connected, so the drive signal output terminal of the shift temporary storage unit ^(P) is pulled to the low level, and the level signal GUT (8) of the shift temporary storage unit its (p) output is low. At this time, the second capacitor (4) of the shift register unit s(p) is not charged' and its reference level junction _(p) is low. For the shift register unit S(n) (n is an even number greater than i, and ny), because the shift temporary storage unit is driven by the (n) front and rear stage shift register unit drive signal output_just 1 output low level, turn S ( n) The front and rear stage shifting the reference level of the temporary storage unit is low level 'so the shift register unit S (a second power (10) is not charged and shifts the temporary storage unit s(n) The level signal OUT(n) of the drive signal output terminal VOUT is low level. ' 099101706 Form No. Α 010 Ι Page 15 / Total 40 Page 0992003304-0 201126499 [0075] [0078] For shifting In the case of the temporary storage unit s(4), m is an odd or even number greater than 〖, and the output of the shift temporary storage sS(m) is the same as s(p) or s(n), and the driving of the signal output terminal VOUT is driven. The flat signal 〇ϋτ(ω) is low. (C) During the Τ2 period, the external start pulse STV1 is at a low level, the clock pulse signal CLK is at a high level, and the reverse clock signal CLKB is at a low level. The shifting temporary storage single-ended rim is high, and the other shifting temporary storage materials are all output low.
對於移位暫存單元S1而言，由於反向時鐘脈衝訊號MB 為低電平，移位暫存單元幻的第十電晶體M1〇截止，移位 ❹ 暫存單元S1的驅動訊號輸出端_τ；ί；再被拉至低電平； 因為Τ1時段第二電容C26被充電，從而第七、第人電晶 體M7、M8導通，時鐘脈衝訊號CLK為高電平並藉由第八電 =體M8的源極和祕將驅動訊號輸出頌術拉升至高冑 平，驅動訊號輪出端VOl]T的電平訊號卯^在”時刻為高 電平。 。 此外，由於時鐘脈衝訊號CLK為高電平，移位暫存單元^For the shift register unit S1, since the reverse clock signal signal MB is at a low level, the tenth transistor M1 of the shift register unit is turned off, and the drive signal output terminal of the temporary storage unit S1 is shifted _ τ; ί; is pulled low again; because the second capacitor C26 is charged during the Τ1 period, so that the seventh and the first transistor M7, M8 are turned on, the clock signal CLK is high level and by the eighth power = The source and the secret of the body M8 pull the signal output to the high level, and the level signal of the driving signal wheel VO1]T is at the high level. In addition, since the clock signal CLK is High level, shift register unit ^
的第六電晶體Μ6導通’此時移位暫存單元S1的第二電容 U C2藉由第六電晶體的汲極和閘極放電。同時，時鐘脈 衝訊號cu藉由移位暫存單元S1第七電晶體们的源極和没 極直接將參考電平結隨拉升至高電平，進而致使移位 暫存單7LS1的第五電晶體M5導通，移位暫存單元Μ的第 九電晶體M9i|其閘極被連接至低電平輸人端VGL而戴止。 對於移位暫存單元82而言，由於移位暫存單的第十 電晶體M10閘極接收到的時鐘脈衝訊號cu為高電平從 099101706 表單編號A0101 第16頁/共40頁 0992003304-0 [0079] 201126499 :第十電晶魏0導通’移位暫存單元以的驅動訊號輪出 端VOUT輸出的電平訊綱T2被拉至低電平。另外，由於 匕時刻移位暫存單凡S1的驅動訊號輸出端爾丁輸出的電 平況號OUT1為③電平，因此移位暫存單的第四電晶 4導通第—電平訊號VC2藉由第四電晶體M4的沒極和 源極對移位暫存單元S2的第二電容G2充電。此外，由於 移位暫存單元S2的第：電⑽被充電時第七電晶體_ 閘極被拉至高電平，該第七電晶碰導通，此刻，時鐘 Ο [0080] G [0081] 099101706 衝訊號CLK藉由第七電晶體们的源極和汲極把參考電 結點N2拉至低電平。 祕移位暫存單元S(n)(n為大於^的偶數，且⑽於^而 "’同樣·時鐘脈衝訊號CLK為高電平，:移位暫存單元 SOO的第十電晶刪叫通，移位暫存單糾n)的驅動 訊號輸出端讀直接與低電平輸入端慨相連，因此移位 暫存單元S(n)的驅動訊號輸出端剛τ_至低電平而輸 出低電平，電平訊麵T(nm2時段為低電平。此外， 移位暫存單元s⑷的第二電容C2均未被充電，且其參考 電平結點N(n)為低電平。 狀移位暫存單元S(p)(p為大於丨的奇數，且㈣於心而 °由於其剛、後級移位暫存單元的驅動訊號輸出端 爾τ均輸出低電平，且移位暫存單元s(p)的前後級移 位暫存單元的參考電平結點為低電平，因此移位暫存單 Μ(ρ)的第二電容C2均未被充電且移位暫存單元3⑻的 驅動訊號輸出端VOUT輸出的電平訊號〇υτ(ρ)為低電平。 移位暫存單元S(m)的輸出情況與s(n)或者s(p)相同其 表單編號A0101 第17頁/共40頁 0992003304-0 [0082] 201126499 驅動訊號輪出端V0UT的電平訊號〇UT(m)為低電平。 [0083] [0084] [0085] [0086] (幻在1"3時段，外部啟動脈衝STV1為低電平，時鐘脈衝 Λ號CLK為低電平，反向時鐘脈衝訊號CLKB為高電平。移 位暫存單tlS2輸出高電平，其他移位暫存單元均輸出低 電平。 -The sixth transistor Μ6 is turned on. The second capacitor U C2 of the shift register unit S1 is discharged by the drain and gate of the sixth transistor. At the same time, the clock signal cu is directly pulled to the high level by the source and the immersion of the seventh transistor of the shift register unit S1, thereby causing the fifth transistor of the shift register 7LS1 to be shifted. M5 is turned on, and the ninth transistor M9i| of the shift register unit 其 is connected to the low level input terminal VGL to be worn. For the shift register unit 82, the clock signal cu received by the gate of the tenth transistor M10 of the shift register is high level from 099101706 Form No. A0101 Page 16 / Total 40 Page 0992003304-0 [ 0079] 201126499: The tenth electric crystal Wei 0 turns on the 'shift register unit' and the level signal T2 of the output of the drive signal output VOUT is pulled low. In addition, since the level condition OUT1 of the output of the driving signal output terminal of the S1 is temporarily shifted to 3, the fourth transistor 4 of the shift register is turned on by the first level signal VC2. The non-polar and source of the fourth transistor M4 charges the second capacitor G2 of the shift register unit S2. In addition, since the seventh transistor _ gate is pulled to a high level when the electric (10) of the shift register unit S2 is charged, the seventh transistor is turned on, and at this moment, the clock Ο [0080] G [0081] 099101706 The CLK CLK pulls the reference electrical junction N2 to a low level by the source and drain of the seventh transistor. The secret shift register unit S(n) (n is an even number greater than ^, and (10) is ^ and "the same" clock pulse signal CLK is high level: shifting the tenth power crystal of the temporary storage unit SOO The drive signal output terminal of the shift register, the shift register, and the low-level input terminal are directly connected, so that the drive signal output terminal of the shift register unit S(n) is just τ_ to the low level and is output. Low level, level signal plane T (nm2 period is low level. In addition, the second capacitor C2 of the shift register unit s(4) is not charged, and its reference level node N(n) is low level. Shifting the temporary storage unit S(p) (p is an odd number greater than 丨, and (4) is at the heart and is outputting a low level due to the driving signal output terminal τ of the initial stage and the rear stage shifting temporary storage unit, and The reference level node of the shift stage temporary storage unit s(p) is low level, so the second capacitor C2 of the shift temporary storage unit ρ(ρ) is not charged and is temporarily shifted. The level signal 〇υτ(ρ) outputted by the drive signal output terminal VOUT of the memory unit 3 (8) is at a low level. The output of the shift register unit S(m) is the same as s(n) or s(p). A0101 Page 17 / A total of 40 pages 0992003304-0 [0082] 201126499 The level signal UT(m) of the drive signal output terminal VOUT is low level. [0083] [0086] [Fantasy in 1" The external start pulse STV1 is low level, the clock pulse number CLK is low level, and the reverse clock pulse signal CLKB is high level. The shift temporary storage unit t1S2 outputs a high level, and the other shift temporary storage units output low power. Flat.
對於移位暫存單元S1而言，由於反向時鐘脈衝訊號CUB 反轉為间電平’移位暫存單元81的第十電晶體Μι〇再次導 通’移位暫存單端的驅動訊號輸出端VGUT直接與低電 平輪入端VGL相連’因此移位暫存單SS1的驅動訊號輸出 端VOUT被拉回低電平，其輸出的電平訊號〇uTi在時段 為低電平。 此外由於時鐘脈衝訊號CLK為低電平，且在Τ2時段移位 暫存單元S1的第二電容C2已被放電，從而移位暫存單元 S1的第六、第七、第八電晶體M6、M7、M8均截止，第九 電曰曰體M9的閘極經由第—電容ei被連接至_脈衝 pry T3時段移位暫存單元S1的第九電晶體㈣仍保持載 止。 、♦於移位暫存單元32而言，由於時鐘脈衝城為低電 、’移位暫存單元S2的第十電晶體μ 1〇截止，移位暫存單 的驅動訊號輸出端VGUT不再被拉至低電平；因為U 第電谷C2已被充電，從而第七、第八電晶體μ?、 導通，反向時鐘脈衝訊號CLKB為高電平並藉由第八電 =體Μ8的源極和汲極將驅動訊號輸出端ν〇υτ拉升至高電 平驅動矾號輪出端VOUT的電平訊號〇UT2在Τ3時刻為高 099101706 表單編號ΑΟίοι 第18頁/共40頁 0992003304- 201126499 電平。 [0087] 此外，由於反向時鐘脈衝訊號CLKB為高電平，移位暫存 早元S2的第六電晶體M6導通，此時移位暫存單元S2的第 電谷C2錯由第六電晶體的汲極和閘極放電。同時， 反向時鐘脈衝訊號Clkb藉由移位暫存單元S2第七電晶體 "的源極和汲極直接將參考電平結點N2拉升至高電平， 進而致使移位暫存單元52的第五電晶體M5導通，移位暫 Ο [0088] 存單元S2的第九電晶體M9因其閘極被連接至低電平輸入 k VGL而截止。 Ο 辦於移位暫存單元S3而言，由於移位暫存單元S3的第十 電晶體M10閘極接收到的反向時鐘脈衝訊號CLKB為高電平 ’從而第十電晶體M10導通，移位暫存單元S3的驅動訊號; 輪出端VOUT輸出的電平訊號0UT3被拉至抵電平。另外， 由於此時刻移位暫存單元S2的驅動訊號輸出端ν〇ϋΤ輸出 的電平訊號OUT2為高電平，因此移位暫存單元S3的第四 電晶體Μ4導通’第二電平訊號VC2藉由第四電晶體…的沒 極和源極對移位暫存單元S3的第二電容C2充電。此外， 由於移位暫存單元S3的第二電容C2被充電時第七電晶體 M7的閘極被拉至高電平，該第七電晶體)^7導通’此刻’ 時鐘脈衝訊號CLK藉由第七電晶體JJ7的源極和汲極把參考 電平結點N 3拉至低電平。 [0089] 對於移位暫存單元S(p)而言，當p大於3時，由於反向時 鐘脈衝訊號CLKB為高電平，移位暫存單元S(p)的第十電 晶體M10導通，移位暫存單元“口）的驅動訊號輸出端 νουτ直接與低電平輸入端VGL相連，因此移位暫存單元 099101706 表單編號A0101 第19頁/共40頁 0992003304-0 201126499 S(p)的驅動訊號輪出端VOUT被拉至低電平而輪出低電平 ，電平訊號0υτ(Ρ)在T3時段為低電平。此外，移位暫存 早元S(P)的第二電容C2均未被充電，且其參考電平結點 N(P)為低電平。 [0090] 對於移位暫存單元s(n)而言，當η大於2時，由於其前、 後級移位暫存單元的驅動號輸出端V0UT均輸出低電平 ’且移位暫存單元s(n)的前、後級移位暫存單元的參考 電平結點為低電平，因此移位暫存單元S(n)的第二電容 句未被充電且移位暫存單元s(n)的驅動訊號輸出端 …耵輪出的電平訊號0UTU)為低電平〇 [0091] 移位暫存單元S(m)的輸出情況與:s(p>或者s(n)相同其 驅動成號輸出端ν〇ϋΤ的電平訊號〇UT(m)為低電平。 [0092] |<1)在1'4時段，外部啟動脈衝STV1為低電平，時鐘脈衝 為高電平’反向時鐘脈衝訊號CLKB為低電平。移 暫存單tlS3輸出高電平，其他移位暫存單元均輸出低 電平。 ' [0093] 街於移位暫存單元S1 時段繼續為低電平， 而言，由於外部啟動脈衝STV1在T4 從而移位暫存單元S1的第二電容C2 被充電’因此第七電晶體M7不能導通，即使T4時段 夺鐘脈衝訊號CLK反轉為高電平，第五電晶體㈣也無法被 導通， ’故’此時第九電晶體!^的閘極無法連接至低電平 輪入端VGL而經由第—電容^連接至時鐘脈衝訊號cu， 從而第九電晶體M9的閘極被拉升至高電平，第九電晶體 M9導通’移位暫存單元S1的驅動訊號輸出端ν〇υτ經由第 099101706 表單編號Α0101 第20頁/共4〇頁 0992003304-0 201126499 [0094] ❹ [0095] [0096] 099101706 九電晶體M9的源極和汲極連接至低電平輸入端VGL，移位 暫存單元S1的驅動訊號輸出端νουτ被拉回低電平，其輪 出的電平矾號OUT1在Τ4時段仍為低電平。 對於移位暫存單元s2而言，由於時鐘脈衝減GLK為高電 平’移位暫存單元S2的第十電晶體Μ10導通，移位暫存單 TCS2的驅動訊號輸出端ν〇υτ直接與低電平輸入端vgl相 連，因此移位暫存單元S2的驅動訊號輸出端v〇UT被拉至 低電平，移位暫存單元S2輸出的電平訊號〇UT2在T4時段 為低電平。此時刻，移位暫存單元S2的第二電容C2未被 充電，且其參考電平結點N2為低電平。 對於移位暫存料S3W，由狀向時鐘_訊號clkb 為低電平，移位暫存單元幻的第十電晶體M1〇截止，移位 暫存單元以的驅動訊號輸出端VOUT不再彳皮拉至低電平； 因為T3時段第二電容C26被充電，從而第七、第八電晶 體M7、M8導通’時鐘脈衝訊號高電平並藉由第八電 晶體Μ 8的源極和汲極將驅動訊號輸出端ν〇υτ拉升至高電平，驅動訊號輸出端VOUT的電平訊號〇UT3在Τ4時刻為高 電平。 此外，由於時鐘脈衝訊號CLK為高電平，移位暫存單元幻 的第六電晶體M6導通，此時移位暫存單元S3的第二電容 C2藉由第六電晶體㈣的汲極和閘極放電。同時時鐘脈 衝訊號CLK藉由移位暫存單元S3第七電晶體M?的源極和淡 極直接將參考電平結細拉升至高電平，進較使移位 暫存單元S3的第五電晶體M5導通，移位暫存單元幻的第 九電晶體M9因其閘極被連接至低電平輸人端似而截止。 表單編號A0101 第21頁/共40頁 0992003304-0 201126499 [0097] [0098] [0099] 位暫存單元S4而言，由於移位暫存單元S4的第十 曰曰—M1G閘極接收到的時鐘脈衝訊號咖為高電平，從:電：1°導通，移位暫如^ 輪出的電平訊號顚被拉至低電平。另外，由於 工刻移位付W純號輪出職HIT輸出的電=::3第為高電平，因此移位暫存單卿 源極Γ 電平訊親2藉由第四電晶體_及極和 =極對移位暫存單元S4的第二電容Ο充電。此外，由於 =存單元S4的第二電容C2被充電時第七電晶體_ :破拉“電平，該第㈣晶體们導通，此刻，時鐘 二電LK藉由第七電晶顧的源極和没極把參考電平 、、-。點N 4拉至低電平。 ^移位暫存單元S(n)而言，針對於η大於4的情況，同 樣由於時鐘脈衝訊號ακ為高電平，移位暫存單元S(n)(n>4)的第十電晶體Μ1〇導缚移位暫存單元 = )U>4)的媒動訊號輸出糊υτ直接與低電平輸入端 :相連，因此移位暫存單從η)(η>4)的驅動訊號輸出 out被拉至低電平而輪出低電平， 在㈣段為低電平。此外/純暫存單元 (n)(n>4)的第二電容C2均未被充電，且其參考電平結 點N(n)(n>4)為低電平。 °^移位暫存單元S(P)^，針對％大於5的情心 二、前、後級移位暫存單元的驅動訊號輸出物齡 ===r·後一 由 均輸 因此移位暫存單元 099101706 表單編號A0101 第22頁/共40頁 201126499 Ο 〇 S(p)(p>5)的第二電容C2均未被充電且移位暫存單元 S(p)(p>5)的驅動訊號輪出端丫〇111>輸出的電平訊號 OUT(p)(p>5)為低電平》 [0100]移位暫存單元S(m)的輸出情況與s(n)(n>4)或者 S(p)(p>5)相同’其驅動訊號輸出端ν〇υτ的電平訊號 ΟϋΤ(πι)為低電平。 (e)依次類推，在T5~T(m)時段，移位暫存單元34 5(心 的驅動訊號輸出端V0UT依次輸出一高電平到外部電路。 請一併參見圖6，係閛極驅動電路1〇進行上掃操作（按 S(m)、S(m-l)…S(l)的順序依次向外部電路輸出—高電 平）的工作時序示意圖。該種工作狀態下，外部啟動脈衝 STV1以及第二電平訊號VC2恒定為低電平，第一電平訊號 VC1恒定為高電平。 ’ [_與前敘相同的原理，在Tb T2、T3...時段’如個移位暫 存單元S(m)〜S1的驅動訊號輸出端ν〇υτ依&輸出—高電 平到外部電路，在此不再贅述》 所述閘極驅動電路10可從移位暫存單元S1至移位暫存單 元s(m)的驅動訊號輸出端依次輸出—高電平到外部電路 ’也可從移位暫存單元su)至移位暫存單端的驅動: 號輸出端依次輸出一高電平到外部電路，該雙向傳輪力 能V使該閘極驅動電路10在搭配不同面板時有更多彈性 空間。 玎以理解，閘極驅動電路10兩端的移位暫存單元S1^ S(ro)可作為Dummy級不作輸出之用，而僅將移位暫存單 [0101] [0102] [0104] 099101706 表單编號A0101 第23頁/共_ 40頁 0992003304-0 [0105] 201126499 元S2、S3…S(m-l)用作脈衝訊號的輸出。 [0106] 綜上所述，本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本 案技藝之人士援依本發明之精神所作之等效修飾或變化 ，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0107] 圖1係本發明實施例提供的閘極驅動電路的電路框架示意 圖。 [0108] 圖2係圖1所示閘極驅動電路的電路結構示意圖。 [0109] 圖3係圖1所示閘極驅動電路的單個移位元寄存單元的電 路結構示意圖。 [0110] 圖4係本發明實施例提供的閘極驅動電路簡化後的電路結 構示意圖。 [0111] 圖5係圖4所示閘極驅動電路的第一工作時序示意圖。 [0112] 圖6係圖4所示閘極驅動電路的第二工作時序示意圖。 【主要元件符號說明】 [0113] 閘極驅動電路：10 [0114] 開關單元：11 [0115] 預充電單元：1 2 [0116] 脈衝訊號輸出單元：13 [0117] 低電平訊號控制單元：14 099101706 表單編號A0101 第24頁/共40頁 0992003304-0For the shift register unit S1, since the reverse clock signal CUB is inverted to the inter-level, the tenth transistor of the shift register unit 81 is turned on again, and the shift signal single-end drive signal output terminal VGUT is turned on again. Directly connected to the low-level wheel terminal VGL', so the drive signal output terminal VOUT of the shift temporary storage unit SS1 is pulled back to a low level, and the output level signal 〇uTi is at a low level during the period. In addition, since the clock pulse signal CLK is at a low level, and the second capacitor C2 of the shift register unit S1 has been discharged in the Τ2 period, the sixth, seventh, and eighth transistors M6 of the temporary storage unit S1 are shifted. M7 and M8 are both turned off, and the gate of the ninth electric body M9 is connected to the ninth transistor (4) of the _pulse pry T3 period shift register unit S1 via the first capacitor ei, and remains held. ♦ In the shift register unit 32, since the clock pulse city is low-power, the tenth transistor μ 1〇 of the shift register unit S2 is turned off, and the drive signal output terminal VGUT of the shift temporary storage table is no longer Pulled low; because U the first valley C2 has been charged, so that the seventh and eighth transistors μ?, turn on, the reverse clock signal CLKB is high and the source of the eighth power = body 8 The pole and the bungee pull the drive signal output terminal ν〇υτ to the high level to drive the level signal of the 轮 轮 wheel end VOUT 〇 UT2 is high at Τ3 time 099101706 Form No. ΑΟίοι Page 18 / Total 40 Page 0992003304- 201126499 level. [0087] In addition, since the reverse clock signal CLKB is at a high level, the sixth transistor M6 of the shift temporary element S2 is turned on, and at this time, the first valley C2 of the shift register unit S2 is wrong by the sixth power. The drain and gate of the crystal are discharged. At the same time, the reverse clock signal Clkb directly pulls the reference level node N2 to a high level by shifting the source and the drain of the seventh transistor " of the temporary storage unit S2, thereby causing the shift register unit 52 to be shifted. The fifth transistor M5 is turned on, shifting the temporary NMOS [0088] The ninth transistor M9 of the memory cell S2 is turned off because its gate is connected to the low level input k VGL .移位 In the shift register unit S3, since the reverse clock signal CLKB received by the gate of the tenth transistor M10 of the shift register unit S3 is at a high level, the tenth transistor M10 is turned on, and is shifted. The driving signal of the bit buffer unit S3; the level signal OUT3 outputted by the wheel terminal VOUT is pulled to the offset level. In addition, since the level signal OUT2 outputted from the driving signal output terminal ν of the temporary storage unit S2 is at a high level at this time, the fourth transistor Μ4 of the shift register unit S3 is turned on by the second level signal. The VC2 charges the second capacitor C2 of the shift register unit S3 by the inhomogeneous and source of the fourth transistor. In addition, since the gate of the seventh transistor M7 is pulled to a high level when the second capacitor C2 of the shift register unit S3 is charged, the seventh transistor) is turned on 'this moment' by the clock signal CLK by the first The source and drain of the seven transistor JJ7 pull the reference level node N 3 low. [0089] For the shift register unit S(p), when p is greater than 3, since the reverse clock signal CLKB is at a high level, the tenth transistor M10 of the shift register unit S(p) is turned on. The drive signal output terminal νουτ of the shift register unit "port" is directly connected to the low level input terminal VGL, so the shift register unit 099101706 form number A0101 page 19/total 40 page 0992003304-0 201126499 S(p) The drive signal output terminal VOUT is pulled low and turns low, and the level signal 0 υ τ (Ρ) is low during the T3 period. In addition, the shift is temporarily stored in the early S (P) Capacitor C2 is not charged, and its reference level node N(P) is low level. [0090] For shift register unit s(n), when η is greater than 2, due to its front and back The drive number output terminal V0UT of the stage shift register unit outputs a low level 'and the reference level node of the front and rear stage shift register unit of the shift register unit s(n) is low level, therefore The second capacitor sentence of the shift register unit S(n) is not charged and the drive signal output terminal of the shift register unit s(n) is turned off by the level signal 0UTU) [0091] shift The output of the temporary storage unit S(m) is the same as: s(p> or s(n), and the level signal 〇UT(m) driving the output terminal ν〇ϋΤ is low level. [0092] |< 1) In the 1'4 period, the external start pulse STV1 is low level, the clock pulse is high level 'the reverse clock pulse signal CLKB is low level. The shift temporary memory single t1S3 outputs high level, other shifts are temporarily stored. The unit outputs a low level. ' [0093] The street continues to be low during the shift register unit S1 period, and the second capacitor C2 of the temporary storage unit S1 is charged because the external start pulse STV1 is at T4. 'Therefore the seventh transistor M7 can not be turned on, even if the clock signal CLK is inverted to the high level in the T4 period, the fifth transistor (4) cannot be turned on, so the gate of the ninth transistor! Connected to the low-level wheel terminal VGL and connected to the clock signal cu via the first capacitor ^, so that the gate of the ninth transistor M9 is pulled high, and the ninth transistor M9 turns on the 'shift register unit The driving signal output terminal ν〇υτ of S1 is numbered through 099101706 Form number 1010101 Page 20/Total 4 page 0992003304-0 20112649 [0096] [0096] 099101706 The source and the drain of the nine-electrode M9 are connected to the low-level input terminal VGL, and the drive signal output terminal νουτ of the shift register unit S1 is pulled back to the low level. The turn-on level OUTOUT1 is still low during the Τ4 period. For the shift register unit s2, since the clock pulse minus GLK is high, the tenth transistor 移位10 of the shift register unit S2 is shifted. Turning on, the drive signal output terminal ν〇υτ of the shift temporary storage unit TCS2 is directly connected to the low-level input terminal vgl, so the drive signal output terminal v〇UT of the shift temporary storage unit S2 is pulled to a low level, and the shift is temporarily suspended. The level signal 〇UT2 outputted from the memory unit S2 is at a low level during the T4 period. At this moment, the second capacitor C2 of the shift register unit S2 is not charged, and its reference level node N2 is at a low level. For the shift temporary storage material S3W, the clock signal_signal clkb is low level, the tenth transistor M1 of the shift temporary storage unit is turned off, and the driving signal output terminal VOUT of the shift temporary storage unit is no longer defective. Pila is low; because the second capacitor C26 is charged during the T3 period, the seventh and eighth transistors M7, M8 turn on the 'clock pulse signal high level and pass the source and the 第八 of the eighth transistor Μ 8 The pole pulls the drive signal output terminal ν〇υτ to a high level, and the level signal 〇UT3 of the drive signal output terminal VOUT is at a high level at time Τ4. In addition, since the clock signal CLK is at a high level, the sixth transistor M6 of the shift register unit is turned on, and the second capacitor C2 of the shift register unit S3 is biased by the drain of the sixth transistor (4). The gate is discharged. At the same time, the clock pulse signal CLK directly pulls the reference level to a high level by shifting the source and the low pole of the seventh transistor M? of the temporary storage unit S3, and the fifth is shifted to the temporary storage unit S3. The transistor M5 is turned on, and the ninth transistor M9 of the shift register unit is turned off because its gate is connected to the low level input terminal. Form No. A0101 Page 21 / Total 40 Pages 0992003304-0 201126499 [0099] [0099] The bit buffer unit S4 is received by the tenth 曰曰-M1G gate of the shift register unit S4. The clock signal is high, from: electricity: 1° conduction, shifting temporarily ^ The level signal that is rotated is pulled low. In addition, due to the shift of the work, the power of the H-signal of the H-signal is equal to the high level of the HIT output, so the shift is temporarily stored in the source of the signal, and the level of the signal is 2, and the fourth transistor is used. The poles and the poles charge the second capacitor 移位 of the shift register unit S4. In addition, since the second transistor C2 of the memory cell S4 is charged, the seventh transistor _: breaks the "level, the fourth (4) crystals are turned on, at this moment, the clock two cells LK through the source of the seventh transistor And immersed the reference level, -. point N 4 to the low level. ^ Shift register unit S(n), for the case where η is greater than 4, also because the clock signal ακ is high Flat, the tenth transistor 移位1〇 of the shift register unit S(n)(n>(n>4) is shifted to the temporary storage unit = )U>4) The medium signal output paste τ directly and the low level input terminal : Connected, so the shift signal from the η) (η > 4) drive signal output out is pulled low and rounded low, in the (four) segment is low. In addition / pure temporary storage unit (n The second capacitor C2 of (n>4) is not charged, and its reference level node N(n)(n>4) is low level. °^Shift register unit S(P)^, For the love signal of % greater than 5, the drive signal output of the front and rear shift register unit is aged ===r·the latter is shifted by the shift register 099101706 Form No. A0101 Page 22 of 40 Page 201126499 Ο 〇S(p)(p>5) second The capacitor C2 is not charged and the drive signal output terminal 丫〇111 of the shift register unit S(p) (p>5) is outputted with the level signal OUT(p)(p>5) being low level. [0100] The output of the shift register unit S(m) is the same as s(n)(n>4) or S(p)(p>5) 'the level signal of the drive signal output terminal ν〇υτΟϋΤ (πι) is low level. (e) In turn, in the T5~T(m) period, the shift register unit 34 5 (the heart's drive signal output terminal V0UT sequentially outputs a high level to the external circuit. Referring to FIG. 6, the operation timing diagram of the bucker drive circuit 1〇 performing the up-scan operation (sequentially outputting the high-level to the external circuit in the order of S(m), S(ml)...S(l)). In the working state, the external start pulse STV1 and the second level signal VC2 are constantly at a low level, and the first level signal VC1 is constantly at a high level. '[_ The same principle as before, at Tb T2, T3. .. period ' as a shift register unit S (m) ~ S1 drive signal output ν 〇υ τ according to & output - high level to the external circuit, no longer repeat here, the gate drive circuit 10 Shift register unit S1 The drive signal output end of the shift register unit s(m) is sequentially outputted - the high level to the external circuit 'can also be shifted from the temporary storage unit su) to the shift temporary storage single end drive: the output end sequentially outputs a high power Flat to external circuit, the two-way transmission force V makes the gate drive circuit 10 have more flexible space when matched with different panels. 玎 To understand, the shift register unit S1^S at both ends of the gate drive circuit 10 ( Ro) can be used as Dummy level for output, but only shift temporary storage list [0101] [0102] [0104] 099101706 Form No. A0101 Page 23 / Total _ 40 Page 0992003304-0 [0105] 201126499 Yuan S2 S3...S(ml) is used as the output of the pulse signal. [0106] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0107] FIG. 1 is a schematic diagram of a circuit frame of a gate driving circuit according to an embodiment of the present invention. 2 is a schematic diagram showing the circuit structure of the gate driving circuit shown in FIG. 1. 3 is a circuit diagram showing the structure of a single shift element register unit of the gate driving circuit shown in FIG. 1. 4 is a schematic diagram showing a simplified circuit structure of a gate driving circuit according to an embodiment of the present invention. 5 is a first operational timing diagram of the gate driving circuit shown in FIG. 4. 6 is a second operational timing diagram of the gate driving circuit shown in FIG. 4. [Main component symbol description] [0113] Gate drive circuit: 10 [0114] Switch unit: 11 [0115] Precharge unit: 1 2 [0116] Pulse signal output unit: 13 [0117] Low level signal control unit: 14 099101706 Form No. A0101 Page 24 / Total 40 Pages 0992003304-0