TW201125375A - Wave noise eliminating circuit - Google Patents

Wave noise eliminating circuit Download PDF

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Publication number
TW201125375A
TW201125375A TW99100620A TW99100620A TW201125375A TW 201125375 A TW201125375 A TW 201125375A TW 99100620 A TW99100620 A TW 99100620A TW 99100620 A TW99100620 A TW 99100620A TW 201125375 A TW201125375 A TW 201125375A
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Taiwan
Prior art keywords
circuit
resistor
diode
amplifier
voltage
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TW99100620A
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Chinese (zh)
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TWI410144B (en
Inventor
Chun-Te Wu
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Hon Hai Prec Ind Co Ltd
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Priority to TW99100620A priority Critical patent/TWI410144B/en
Publication of TW201125375A publication Critical patent/TW201125375A/en
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Publication of TWI410144B publication Critical patent/TWI410144B/en

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Abstract

A wave noise eliminating circuit includes a signal acquire circuit, a peak voltage accumulation circuit, a time delay circuit, a Schmitt trigger, and an invert circuit which are connected in series, and a mute circuit connects with the Schmitt trigger and the invert circuit. The signal acquire circuit acquires the break signals of the left and right channel. The peak voltage accumulation circuit accumulates the voltage of the break signal. When the accumulation voltage greater than the threshold voltage of the time delay circuit, then a capacitance thereof is charged. The Schmitt trigger generates high level or low level signal according to the voltage of the capacitance. The invert circuit inverts the level signals generated by the Schmitt trigger. When the Schmitt trigger outputs high level signal and the invert circuit outputs low level signal, the mute circuit conducts the left and right channel.

Description

201125375 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種電路設計技術，尤其涉及一種爆音抑制 電路。 【先前技術】 [0002] 視聽類電子設備在開關機時，由於輸出之聲音信號受到 電源啟動時之突波之干擾，使得在聲音信號輸出前左右 聲道中可能存在正電壓突破或負電壓突破，從而導致在 ^ 聲音信號輸出前有“爆音”現象產生。傳統上為確決這 〇 種不良之聲音品質，也即解決“爆音”現象，會在聲音 輸出線路内加入一爆音抑制電路，用以消除電源之突波 〇 [0003] 然而，傳統之爆音抑制電路是在電源啟動之瞬間就產生 一靜音訊號，以消除視聽類電子設備在開關機之瞬間所 輸出之所有信號強制拉低。這就導致在電子設備中内設 一個定時模組對爆音抑制電路產生靜音訊號之時間進行 〇 控制，但是定時模組所設定之時間固定，無法在正負電 壓突破消除後立即讓左右聲道導通，從而讓正常之聲音 訊號通過。 【發明内容】 [0004] 有鑑於此，有必要提供一種在正負電壓突破消除後立即 讓左右聲道導通之爆音抑制電路。 [0005] —種爆音抑制電路，其包括依次串聯之信號採集電路、 電壓峰值累積電路、延時電路、正向施密特觸發電路、 反向電路及與正向施密特觸發電路和反向電路相連接之 099100620 表單編號A0101 第5頁/共18頁 0992001289-0 201125375 靜音電路；所述信號採集電路用於採集左右聲道中之正 負電壓突破；所述電壓峰值累積電路用於對信號採集電 路採集之正負電壓突破之電壓進行累積；當電壓峰值累 積電路所累積之電壓超過延時電路之導通電壓後，對延 時電路中之一充電電容進行充電；所述正向施密特觸發 電路根據充電電容之充電電壓對應產生高低電平；所述 反向電路對正向施密特觸發電路輸出之電平進行反向； 所述靜音電路與左右聲道連接，並在正向施密特觸發電 路輸出高電平，反向電路輸出低電平時，左右聲道導通 〇 [0006] 與先前技術相比，本發明提供之爆音抑制電路在偵測到 左右聲道中存在之正負電壓突破後，再經過一段時間之 延時後再控制左右聲道導通，從而不僅完成對左右聲道 中正負電壓突破之消除，還可及時之讓正常之聲音訊號 通過。 【實施方式】 [0007] 下面將結合附圖與實施例對本技術方案作進一步詳細說 明。 [0008] 請參閱圖1，為本發明實施方式提供之一種爆音抑制電路 100，其用於對視聽類電子設備在開關機時左右聲道LC、 RC中產生之正電壓突破或負電壓突破進行抑制。所述左 右聲道LC、RC連接於一音訊輸出端口 Vout及一喇叭Sp之 間。所述爆音抑制電路100包括信號採集電路10、電壓峰 值累積電路20、延時電路30、正向施密特觸發電路40、 反向電路50及靜音電路60。 099100620 表單編號A0101 第6頁/共18頁 0992001289-0 201125375 [0009] 所迷信號採集電路10包括第201125375 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a circuit design technique, and more particularly to a pop suppression circuit. [Prior Art] [0002] When the audio-visual electronic equipment is turned on and off, the output sound signal is interfered by the glitch when the power is turned on, so that there may be a positive voltage breakthrough or a negative voltage breakthrough in the left and right channels before the sound signal is output. , resulting in a "popping" phenomenon before the output of the sound signal. Traditionally, in order to determine the quality of this kind of bad sound, that is, to solve the "popping" phenomenon, a pop-up suppression circuit is added to the sound output line to eliminate the surge of the power supply. [0003] However, the traditional pop suppression The circuit generates a mute signal at the moment of power-on to eliminate all signals output by the audio-visual electronic device at the moment of switching on and off. This results in a timing module in the electronic device to control the time when the pop-up suppression circuit generates the mute signal, but the time set by the timing module is fixed, and the left and right channels cannot be turned on immediately after the positive and negative voltage breakthrough is eliminated. So that the normal voice signal passes. SUMMARY OF THE INVENTION [0004] In view of the above, it is necessary to provide a pop-up suppression circuit that turns the left and right channels on immediately after the positive and negative voltage breakthroughs are eliminated. [0005] A pop-up suppression circuit comprising a signal acquisition circuit, a voltage peak accumulation circuit, a delay circuit, a forward Schmitt trigger circuit, a reverse circuit, and a forward Schmitt trigger circuit and a reverse circuit in series Connected 099100620 Form No. A0101 Page 5 / Total 18 Page 0992001289-0 201125375 Silent circuit; the signal acquisition circuit is used to collect the positive and negative voltage breakthrough in the left and right channels; the voltage peak accumulation circuit is used for the signal acquisition circuit Collecting the voltage of the positive and negative voltages of the acquisition to accumulate; when the voltage accumulated by the voltage peak accumulation circuit exceeds the conduction voltage of the delay circuit, charging one of the charging capacitors in the delay circuit; the forward Schmitt trigger circuit is based on the charging capacitor The charging voltage correspondingly generates a high level; the reverse circuit reverses the level of the output of the forward Schmitt trigger circuit; the mute circuit is connected to the left and right channels, and is outputted in the forward Schmitt trigger circuit High level, when the reverse circuit outputs a low level, the left and right channels are turned on. [0006] Compared with the prior art, the present invention provides After detecting the positive and negative voltages in the left and right channels, the popping sound suppression circuit controls the left and right channels to turn on after a period of delay, thereby completing the elimination of positive and negative voltage breakthroughs in the left and right channels, and timely Let the normal voice signal pass. [Embodiment] The present technical solution will be further described in detail below with reference to the accompanying drawings and embodiments. Please refer to FIG. 1 , which is a pop-up suppression circuit 100 for performing a positive voltage breakthrough or a negative voltage breakthrough generated in an audio-visual electronic device when the power is turned on and off in the left and right channels LC and RC. inhibition. The left and right channels LC and RC are connected between an audio output port Vout and a speaker Sp. The pop suppression circuit 100 includes a signal acquisition circuit 10, a voltage peak accumulation circuit 20, a delay circuit 30, a forward Schmitt trigger circuit 40, a reverse circuit 50, and a mute circuit 60. 099100620 Form No. A0101 Page 6 of 18 0992001289-0 201125375 [0009] The signal acquisition circuit 10 includes

-—取大琴119 、第二放大器U3、第四放大器U4、第—電阻μ、第°_ 阻R2、第三電阻R3及第四電阻R4 ; 二電 k乐放大器U1之 正向輸入端與左聲itix相連接，負向輸人端與輪出端相 連接；所述第二放大器U2之正向輸入端接地，負向輸= 端通過所述第-電卩观與左聲道LG相連接並通過 二電阻R2與輸出端相連接；所述第三放大器们之正向、 入端與右聲道RC相連接’負向輪入端與輸出端相連接/ 所述第四放大器U4之正向輸入端接地，負向輸入端、雨、 所述第三電阻R3與右聲道RC相連接並通過所述第四電阻 R4與輸出端相連接。本實施方式令，所述第_、第三、第四放大器U1、U2、U3 'U4之型號為lM324，第 一電阻R1與第三電阻R3之阻值為20ΚΩ，所述第二 电阻 R2與第四電阻R5之阻值為40ΚΩ，所述第一、第二、 弟二- Take the big piano 119, the second amplifier U3, the fourth amplifier U4, the first-resistance μ, the first_resistance R2, the third resistor R3, and the fourth resistor R4; the positive input terminal of the second electric k-amplifier U1 The left sound is connected to the ground, the negative input terminal is connected to the wheel output end; the forward input end of the second amplifier U2 is grounded, and the negative input terminal is connected to the left channel LG through the first electrical view. Connected and connected to the output through a two-resistor R2; the forward and the inverting ends of the third amplifier are connected to the right channel RC. The negative wheel-in terminal is connected to the output terminal / the fourth amplifier U4 is connected The positive input terminal is grounded, the negative input terminal is rained, and the third resistor R3 is connected to the right channel RC and connected to the output terminal through the fourth resistor R4. In this embodiment, the first, third, and fourth amplifiers U1, U2, U3 'U4 are of the type LM324, and the resistances of the first resistor R1 and the third resistor R3 are 20 ΚΩ, and the second resistor R2 is The resistance of the fourth resistor R5 is 40 ΚΩ, the first, second, and second

[0010] 、第四放大器U1、ϋ2、ϋ3、ϋ4之正負電源端分別連接 + 12V和-12V之電壓。 . . ·+-- ；.. ':. ：；. > 所述電壓峰值累積電路20包括第一二極體D1、第二二極 體D2、第三二極體1)3、第四二極體D4、第五電阻1{5及累 積電容C1 ;所述第一一極體D1之陽極與第一放大器υ；[之 輸出端相連接，所述第二二極體D2之陽極與第二放大器 U2之輸出端相連接，所述第二二極體之陽極與第三放 大器U3之輸出端相連接，所述第四二極體D4之陽極與第 四放大器U4之輸出端相連接；所述第五電阻R5之一端與 第一至第四二極艘Dl、D2、D3、D4之陰極相連接，另— 端與累積電容C1相連接，所述累積電谷C1之另一端接地 099100620 表單編號A0101 第7頁/共18頁 0992001289-0 201125375 。本實施方式中，所述第五電阻以之阻值為，累積 電容C1之電容量為6. 8uF。 [0011] 所述延時電路30包括第—霞管M1、第六電阻R6及充 電電谷C2 ;所述第—^肋8管们之漏極(1連接—正電壓， 柵極g連接於第五電嶋與累積電容π之間，源極s與第 六電阻R6之一端相連接；所述第六電阻R6之另一端與充 電電容C2之一端相連接，充電電容C2之另—端接地。本 實施方式中，第六電阻R6之阻值為4 71(〇，充電電容Μ 之電容量為68uF。 [0012] 所述正向施密特觸發電路40包括第五放大器卯、第七電 阻R7、第八電阻R8、第九電eR9及策十電阻Rl〇 :所述 第五放大器U5之正向輸入端連接於第六電阻设6及充電電 容C2之間，且正向輸入端通過第九電阻的與輸出端相連 接，負向輸入端連接於第七電阻r7與第八電阻R8之間； 所述第七電阻R7另一端連捧·^正電壓；所述第八電阻R8 之另一端接地；所述第十電阻R10之一端與第五放大器仍 之輸出端相連接，另一端連接'至一:正電壓。本實施方弋 中所述第五放大器U5之正負電源端分別連接+ 3. 3^和_ 3.3V之電壓’第七電阻R7之阻值為1〇1(〇，第八電阻以 之阻值為510Ω ’第九電阻R9之阻值為20ΚΩ，第十電阻 R10之阻值為2· 2ΚΩ ’所述正電壓為+ 3. 3v。 [0013] 所述反向電路50包括第一 P-MOS管M2、第二N-MOS管M3 及第十一電阻R11 ;所述第一P-MOS管M2之栅極g與第二 N-MOS管M3之栅極g相連接並連接至第五放大器U5之輸出 端’所述第一P-MOS管M2之漏極d連接一正電壓，所述第 099100620 表單編號A0101 第8頁/共18頁 0992001289-0 201125375 二N-M0S管M3之源極s連接一負電壓，所述第一1>_河〇3管 M2之源極s與第二卜肋^管们之漏極d相連接並連接至第 十一電阻R11之一端；所述第十一電阻R11之另—端接地 。本實施方式中’所述第十一電阻R11之阻值為10ΚΩ， 所述負電壓為-3.3V。 ’ [0014]所述靜音電路60包括左聲道靜音電路61和右聲道靜音電 路62。所述左聲道靜音電路61包括第五二極體的、第六 二極體D6、第一三極管Q1、第二三極管Q2、第十二電阻 〇 R12及第十三電謂3 ;所述第五二極_之陰極連接於 第一 P-M0S管M2之源極S與第二N-M0S管M3之漏極d之間 ，陽極與第一三極管Q1之基举相連接；所述第一三極管 Q1之發射極接地，集電極與左聲道LC_連接；所述第= 2電M12之-端連接於第五二極體D5之陽極與第—三極 管Q1之基極之間，另一端連接一正電壓；所述第六二極 體D6之陽極連接於第五放大器U5之輸出端，陰極與第二 三極管Q2之基極減接；所述第二三_#Q2之發射極接 〇 地，集電極與左聲道LC相連接；所述第十三電阻R13之一 端連接於第六二極體D6之陽極與第二三極管的之基極之 間，另-端連接-負電壓。所述右聲道靜音電路Μ包括 第七二極體D7、第八二極體D8、第三三極管⑽、第四三 極管Q4、第十四電阻RH及第十五電阻…：所述第七二 極體D7之陰極連接於第-P-M0S_之源極s與第二I一 M0S管M3之漏極d之間，陽極與第三三極管⑽之基極相連 接；所述第三三極管(53之發射極接地，集電極盘右聲道 RC相連接；所述第十四電阻R14之—端料”七二㈣ 099100620 表單編號A0101 第9頁/共18頁 0992001289-0 201125375 1)7之％極與$三三極管⑽之基極 電壓；所述H極刪之陽極連接正 輸出端，㈣連接”五放大器卯之 三極⑽ 三極管Q4之基極相連接·，所述第四 述第二=::地端集電極與右聲道似目連接;所 四三極管二:：二^^ 艿鸲連接一負電壓。本實施 ，，述第十二至十五電mRl2、Ri3 阻值都&10ΚΩ。 Klb之 [0015] [0016] 之初始狀態下’所述第—關閉所述第 五放大器U5之正输入端之電壓為低電平，經過正向施 密特觸發祕40之仙後，«五放大现之輸出端輪 出低電平，使反向電路5Q中之第—卜咖㈣栅極g而第 二^_細戴止’從而第—P-MOS管M2之漏極d與源極 s相連通輪出高電平。由於第五：極體如及第七二極體^ 之陰極為高電平，第六二_D6及第八二極體⑽之陽極 為低電平，從而使第五至第八二極體D5、D6、D7、⑽截 止，則第一至第四三極管Ql、丨翁、即、Μ導通，從而將 左右聲道LC、RC之電壓拉低為〇。 當左右聲道LC、RC中存在正電壓突破或負電壓突破時， 經過第一至第四放大器Ul、U2、U3或U4整流放大後之電 壓分別通過第一至第四二極體以、112、1]3、1]4及第五電 阻R5後對累積電容C1進行充電。當累積電容(^所累積之 電壓高於第一 N-MOS管Ml之門檻電壓，使得第一 ^|^05管 Ml之源極s和漏極d導通。連接於第一^(^管駁之漏極d 之正電壓對充電電容C2進行充電。在充電電容C2之電壓 099100620 表單編號A0101 第10頁/共18頁 0992001289-0 201125375 =正向施密特觸發電路4〇之正向 述正向施密軸發 所 道靜音電加 輪出低電平；從而使得左右聲 。、62保持將左右聲道LC、RC拉低為〇 犬破訊號到達喇叭Sp，以產生“爆音，，現象， ♦左右聲道Lc、RC中之正負電壓突破實現消除 以 從而 [0017] Ο 田充電電之電壓超過正向施密特觸發電路μ之正向 閣值後所述正向施密特觸發電路40之輸出端輸出高電 平，使反向電路50中之第一 P-MOS管M2截止而第二N —M〇s 官们導通’從而第二N-MOS管M3之漏極d與源極s相連通 輸出低電平。由於第五二極體D5及第七二極體D7之陰極 為低電平，第六二極體D6及第八二極體卯之陽極為高電 平’從而使第五至第八二極體D5、D6、D7、D8導通則 第一至第四三極管Q1、Q2、q3、q4截止，從而使得左右 聲道LC、RC中在正負突破電壓之後之正轉音訊號通過 [0018] Ο 本發明提供之爆音抑制電路在偵測到左右聲道中存在之 正負電壓突破後，再經過一段時間之延時後再控制左右 聲道導通，從而不僅完成對左右聲道中正負電壓突破之 消除，還可及時之讓正常之聲音訊號通過。 [0019] 綜上所述，本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上該者僅為本發明之較佳實施方式 ，自不能以此限制本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化， 皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 099100620 表單編號A0101 第11頁/共18頁 0992001289-0 201125375 [0020] 圖1本發明實施方式提供之爆音抑制電路之電路圖。 【主要元件符號說明】 [0021] 爆音抑制電路1 0 0 [0022] 左聲道LC [0023] 右聲道RC [0024] 音訊輸出端口 Vout [0025] 制〇八S p [0026] 信號採集電路10 ' [0027] 第一、第二、第三、第四放大器U1、U2、U3、U4 [0028] 第一、第二、第三、第四電阻Rl、R2、R3、R4 [0029] 電壓峰值累積電路20 [0030] 第一、第二、第三、第四二極體Dl、D2、D3、D4 [0031] 第五電阻R5 [0032] ： ( 累積電容C1 [0033] 延時電路30 [0034] 第一 N-M0S 管 Ml [0035] 第六電阻R6 [0036] 充電電容C2 [0037] 正向施密特觸發電路40 [0038] 第七、第八、第九、第十電阻R7、R8、R9、R10 099100620 表單編號A0101 第12頁/共18頁 0992001289-0 201125375 [0039] 第五放大器U5 [0040] 反向電路5 0 [0041] 第一 P-MOS 管 M2 [0042] 第二 N-MOS 管 M3 [0043] 第十一電阻R11 [0044] 靜音電路60 [0045] 左聲道靜音電路61 〇 [0046] 第十二、第十三電阻R12、R13 [0047] 第五、第六二極體D5、D6 [0048] 第一、第二三極管Ql、Q2 [0049] 右聲道靜音電路62 [0050] 第十四、第十五電阻R14、R15 [0051] 第七、第八二極體D7、D8 ❹ [0052] 第三、第四三極管Q3、Q4 099100620 表單編號A0101 第13頁/共18頁 0992001289-0[0010] The positive and negative power terminals of the fourth amplifiers U1, ϋ2, ϋ3, and ϋ4 are respectively connected to voltages of +12V and -12V. The voltage peak accumulation circuit 20 includes a first diode D1, a second diode D2, a third diode 1) 3, and a fourth a diode D4, a fifth resistor 1{5 and a cumulative capacitor C1; an anode of the first body D1 is connected to an output terminal of the first amplifier; [the anode of the second diode D2 The output of the second amplifier U2 is connected, the anode of the second diode is connected to the output of the third amplifier U3, and the anode of the fourth diode D4 is connected to the output of the fourth amplifier U4. One end of the fifth resistor R5 is connected to the cathodes of the first to fourth poles D1, D2, D3, D4, the other end is connected to the cumulative capacitor C1, and the other end of the accumulated electric valley C1 is grounded. 099100620 Form No. A0101 Page 7 of 18 0992001289-0 201125375. In the present embodiment, the capacitance of the fifth capacitor is 6. 8 uF. [0011] The delay circuit 30 includes a first-light tube M1, a sixth resistor R6, and a charging electric valley C2; the drain of the first------------------------------------- Between the five electric 嶋 and the cumulative capacitance π, the source s is connected to one end of the sixth resistor R6; the other end of the sixth resistor R6 is connected to one end of the charging capacitor C2, and the other end of the charging capacitor C2 is grounded. In the present embodiment, the resistance of the sixth resistor R6 is 4 71 (〇, the capacitance of the charging capacitor Μ is 68 uF. [0012] The forward Schmitt trigger circuit 40 includes a fifth amplifier 卯 and a seventh resistor R7. The eighth resistor R8, the ninth electrical eR9, and the tenth resistor R1〇: the forward input end of the fifth amplifier U5 is connected between the sixth resistor set 6 and the charging capacitor C2, and the positive input end passes the ninth The resistor is connected to the output terminal, the negative input terminal is connected between the seventh resistor r7 and the eighth resistor R8; the other end of the seventh resistor R7 is connected to the positive voltage; the other end of the eighth resistor R8 Grounding; one end of the tenth resistor R10 is connected to the output end of the fifth amplifier, and the other end is connected to 'one to one: positive The positive and negative power terminals of the fifth amplifier U5 described in the embodiment are respectively connected with a voltage of + 3. 3^ and _ 3.3V. The resistance of the seventh resistor R7 is 1〇1 (〇, the eighth resistor is The resistance is 510 Ω. The resistance of the ninth resistor R9 is 20 ΚΩ, and the resistance of the tenth resistor R10 is 2.6 Ω. The positive voltage is +3.3v. [0013] The reverse circuit 50 includes the first P. a MOS transistor M2, a second N-MOS transistor M3, and an eleventh resistor R11; a gate g of the first P-MOS transistor M2 is connected to a gate g of the second N-MOS transistor M3 and connected to the The output terminal of the fifth amplifier U5 'the drain d of the first P-MOS transistor M2 is connected with a positive voltage, the 099100620 form number A0101 page 8 / total 18 page 0992001289-0 201125375 two N-M0S tube M3 The source s is connected to a negative voltage, and the source s of the first 1 > _ 3 管 3 tube M2 is connected to the drain d of the second rib tube and connected to one end of the eleventh resistor R11; The other end of the eleventh resistor R11 is grounded. In the present embodiment, the resistance of the eleventh resistor R11 is 10 Ω, and the negative voltage is -3.3 V. [0014] The mute circuit 60 includes the left Channel mute circuit 61 and a channel mute circuit 62. The left channel mute circuit 61 includes a fifth diode, a sixth diode D6, a first transistor Q1, a second transistor Q2, a twelfth resistor R12, and The thirteenth electric 3 is connected; the cathode of the fifth diode is connected between the source S of the first P-MOS tube M2 and the drain d of the second N-MOS tube M3, and the anode and the first three poles The base of the tube Q1 is connected; the emitter of the first transistor Q1 is grounded, the collector is connected to the left channel LC_; the end of the second power M12 is connected to the fifth diode D5 The anode is connected to the base of the third transistor Q1, and the other end is connected with a positive voltage; the anode of the sixth diode D6 is connected to the output end of the fifth amplifier U5, and the base of the cathode and the second transistor Q2 Subtracting; the emitter of the second three_#Q2 is connected to the ground, and the collector is connected to the left channel LC; one end of the thirteenth resistor R13 is connected to the anode and the second of the sixth diode D6 Between the bases of the triodes, the other end is connected - a negative voltage. The right channel mute circuit Μ includes a seventh diode D7, an eighth diode D8, a third transistor (10), a fourth transistor Q4, a fourteenth resistor RH, and a fifteenth resistor. The cathode of the seventh diode D7 is connected between the source s of the first-P-MOS_ and the drain d of the second I-MOS transistor M3, and the anode is connected to the base of the third transistor (10); The third triode (53 emitter is grounded, the collector disc right channel RC is connected; the fourteenth resistor R14 is - end material) seven two (four) 099100620 form number A0101 page 9 / total 18 pages 0992001289-0 201125375 1) The base voltage of 7% pole and $3 transistor (10); the anode of the H pole is connected to the positive output terminal, (4) is connected to the base of the five amplifiers (10) and the base of the transistor Q4 is connected. The fourth second=:: ground collector is connected to the right channel; the fourth transistor: two is connected to a negative voltage. In this embodiment, the twelfth to fifteenth electrical mRl2, Ri3 resistance values are & 10 Κ Ω. [0015] [0016] In the initial state of the first state, the voltage of the positive input terminal of the fifth amplifier U5 is low, and after the positive Schmitt triggers the secret of the secret 40, «five Amplifying the current output terminal to make a low level, so that the first circuit in the reverse circuit 5Q is the second gate, and the second gate is g-shaped, so that the drain d and the source of the first P-MOS transistor M2 The s phase is connected to a high level. Because the fifth: the cathode and the cathode of the seventh diode 2 are at a high level, the anodes of the sixth two _D6 and the eighth diode (10) are at a low level, thereby making the fifth to eighth diodes When D5, D6, D7, and (10) are turned off, the first to fourth transistors Q1, 丨, Μ, Μ are turned on, thereby pulling the voltages of the left and right channels LC and RC to 〇. When there is a positive voltage breakthrough or a negative voltage breakthrough in the left and right channels LC, RC, the voltages rectified and amplified by the first to fourth amplifiers U1, U2, U3 or U4 pass through the first to fourth diodes, respectively, 112 The accumulated capacitor C1 is charged after 1]3, 1]4 and the fifth resistor R5. When the accumulated capacitance (^ is higher than the threshold voltage of the first N-MOS transistor M1, the source s and the drain d of the first ^^05 tube M1 are turned on. Connected to the first ^ (^ tube The positive voltage of the drain d charges the charging capacitor C2. The voltage of the charging capacitor C2 is 099100620 Form No. A0101 Page 10/18 pages 0992001289-0 201125375 = Forward Schmitt trigger circuit 4〇正正正正Sending a low level to the Schmitt axis to make a low level; thus making the left and right sounds, 62 keep the left and right channels LC, RC low to the dog's broken signal to reach the speaker Sp, to produce a "popping, phenomenon, ♦ The positive and negative voltages in the left and right channels Lc and RC are broken to achieve the elimination. Thus, the forward Schmitt trigger circuit 40 is after the voltage of the charging current exceeds the positive value of the forward Schmitt trigger circuit μ. The output terminal outputs a high level, so that the first P-MOS transistor M2 in the reverse circuit 50 is turned off and the second N-M〇s is turned on, so that the drain d and the source of the second N-MOS transistor M3 The s phase is connected to the output low level. Since the cathodes of the fifth diode D5 and the seventh diode D7 are at a low level, the sixth diode D6 The anode of the eighth diode is at a high level, so that the fifth to eighth diodes D5, D6, D7, and D8 are turned on, and the first to fourth transistors Q1, Q2, q3, and q4 are turned off, thereby The positive sound signal after the positive and negative breakthrough voltages in the left and right channels LC and RC is passed through [0018] Ο The sound suppression circuit provided by the present invention detects the presence of positive and negative voltages in the left and right channels, and then after a period of time After the delay, the left and right channels are controlled to be turned on, thereby not only completing the elimination of the positive and negative voltage breakthroughs in the left and right channels, but also allowing the normal sound signals to pass in time. [0019] In summary, the present invention has indeed met the invention patent. The above is only a preferred embodiment of the present invention, and the above is not intended to limit the scope of the patent application of the present invention. Those who are familiar with the skill of the present invention are equivalent to the spirit of the present invention. Modifications or variations are to be included in the scope of the following patent application. [Simple Description of the Drawings] 099100620 Form No. A0101 Page 11 / Total 18 Pages 0992001289-0 201125375 [0020] FIG. 1 Circuit diagram of the pop-up suppression circuit. [Main component symbol description] [0021] Pop-up suppression circuit 1 0 0 [0022] Left channel LC [0023] Right channel RC [0024] Audio output port Vout [0025] S p [0026] signal acquisition circuit 10 ' [0027] first, second, third, fourth amplifier U1, U2, U3, U4 [0028] first, second, third, fourth resistance Rl, R2 R3, R4 [0029] Voltage peak accumulation circuit 20 [0030] First, second, third, and fourth diodes D1, D2, D3, D4 [0031] Fifth resistor R5 [0032] : (cumulative capacitance C1 [0033] Delay Circuit 30 [0034] First N-M0S Tube M1 [0035] Sixth Resistor R6 [0036] Charging Capacitor C2 [0037] Forward Schmitt Trigger Circuit 40 [0038] Seventh, Eighth, Ninth and Tenth Resistors R7, R8, R9, R10 099100620 Form No. A0101 Page 12/Total 18 Pages 0992001289-0 201125375 [0039] Fifth Amplifier U5 [0040] Inverting Circuit 5 0 [0041] First P- MOS transistor M2 [0042] Second N-MOS transistor M3 [0043] Eleventh resistor R11 [0044] Silent circuit 60 [0045] Left channel mute circuit 61 〇 [0046] Twelfth, thirteenth Resistor R12, R13 [0047] Fifth and sixth diodes D5, D6 [0048] First and second transistors Q1, Q2 [0049] Right channel mute circuit 62 [0050] Fourteenth, tenth Five resistors R14, R15 [0051] Seventh and eighth diodes D7, D8 ❹ [0052] Third and fourth transistors Q3, Q4 099100620 Form No. A0101 Page 13 of 18 0992001289-0

Claims (1)

201125375 七、申請專利範圍： 1 . 一種爆音抑制電路，其包括依次串聯之信號採集電路、電 壓峰值累積電路、延時電路、正向施密特觸發電路、反向 電路及與正向施密特觸發電路和反向電路相連接之靜音電 路；所述信號採集電路用於採集左右聲道中之正負電壓突 破；所述電壓峰值累積電路用於對信號採集電路採集之正 負電壓突破之電壓進行累積；當電壓峰值累積電路所累積 之電壓超過延時電路之導通電壓後，對延時電路中之一充 電電容進行充電；所述正向施密特觸發電路根據充電電容 之充電電壓對應產生高低電平；所述反向電路對正向施密 特觸發電路輸出之電平進行反向；所述靜音電路與左右聲 道連接，並在正向施密特觸發電路輸出高電平，反向電路 輸出低電平時，左右聲道導通。 2 .如申請專利範圍第1項所述之爆音抑制電路，其中，所述 信號採集電路包括第一放大器、第二放大器、第三放大器 及第四放大器；所述第一放大器之正向輸入端與左聲道相 連接，負向輸入端與輸出端相連接；所述第二放大器之正 向輸入端接地，負向輸入端通過一第一電阻與左聲道相連 接並通過一第二電阻與輸出端相連接；所述第三放大器之 正向輸入端與右聲道相連接，負向輸入端與輸出端相連接 ;所述第四放大器之正向輸入端接地，負向輸入端通過一 第三電阻與右聲道相連接並通過一第四電阻與輸出端相連 接。 3 .如申請專利範圍第2項所述之爆音抑制電路，其中，所述 電壓峰值累積電路包括第一二極體、第二二極體、第三二 099100620 表單編號A0101 第14頁/共18頁 0992001289-0 201125375 極體、第四二極體、第雷 辦”⑵ 累積電容；所述第一二極 ^ ^ °。輸出^相連接，所述第二二極體 &極與弟二放大器之輸出端相連拉 Β 铷出触相運接，所述第三二極體之 %極與第三放大器之輪ψ唑始、电拉 《輸出知相連接，所述第四二極體之陽 極與第四放大器之輪出端相連接； # ^地第五電阻之一端與 端與累積電容相連 弟一至第四二極體之陰極相連接，另 接；所述累積電容之另一端接地。 如申請專利_第3項所狀爆音抑㈣路，其中，所述 Ο 延時電路包括第略_管、第六電阻及充電電容；所述 第一Ν-_管之漏極連接一正電壓，_連接於第五電阻 與累積電容之間’源極與第六電阻之—端相連接；所述第 六電阻之另-端與充電電容之一端相連接，充電電容之另 一端接地。 5 ·如申請專利範圍第4項所述之爆音抑制電路，其中，所述 正向施密特觸發電路包括第五放大器、第七電阻、第八電 阻、第九電阻及第十電阻；_逃第五放九器之正向輸入端 》 祕於第六電阻及充電電容之間，且正向輸入端通過第九 電阻與輸出端相連接，負向輸八端連接於第七電阻與第八 電阻之間，所述第七電阻另一端連接一正電壓；所述第八 電阻之另一端接地；所述第十電阻之一端與第五放大器之 輸出端相連接’另一端連接至一正電壓。 6 ·如申請專利範圍第5項所述之爆音抑制電路，其中，所述 反向電路包括第一P-M0S管、第二N-M0S管及第十一電阻 ;所述第一P-M0S管之柵極與第二N-M0S管之栅極相連接 並連接至第五放大器之輸出端，所述第一P-M0S管之漏極 連接一正電壓’所述第二N-M0S管之源極連接一負電壓， 099100620 表單編號 Α0101 第 15 頁/共 α 頁 0992001289-0 201125375 所述第一 P-M0S管t源極與第二N-M0S管之漏極相連接並 連接至第十一電阻之一端；所述第十—電阻之另一端接地 〇 7.如申請專利範圍第6項所述之爆音抑制電路，其中，所述 靜音電路包括左聲道靜音電路和右聲道靜音電路，所述左 聲道靜音電路和右聲道靜音電路之一端都分別與第五放大 益之輸出端及第一 P - M0S管之源極相連接左聲道靜音電 路之另一端與左聲道相連接，右聲道靜音電路之另一端與 右聲道相連接。 8 ·如申請專利範圍第7項所述之爆音抑制電路其中，所述 左聲道靜音電路包栝第五二極體、第六二極體、第一三極 管、第二三極管、第十二電阻及第十三電阻；所述第五二 極體之陰極連接於第一 P-M0S管之源極與第二N_M〇s管之 漏極之間，陽極與第一三極管之基極相連接；所述第一三 極管之發射極接地，集電極與左聲道相連接；所述第十二 電阻之一端連接於第五二極體之陽極與第_三極管之基極 之間’另-端連接-正電壓:;所述第六二極體之陽極連接 於第五放大器之輸出端，陰極與絮二三極管之基極相連接 U ;所述第二三極管之發射極接地’集電極與左聲道相連接 •’所述第十三電阻之一端連接於第六二極體之陽極與第二 二極管之基極之間，另一端連接—負電壓。 9 .如申請專利範圍第7項所述之爆音抑制電路其中，所述 右聲道靜音電路包括第七二極體、第八二極體、第三三極 管、第四三極管、第十四電阻及第十五電阻；所述第七二 極體之陰極連接於第一P_M0S管之源極與第：n_m〇s管之 漏極之間，陽極與第三三極管之基極相連接；所述第三三 099100620 表單編號A0101 笛1ft百/ϋ 18百 0992001289-0 201125375 極管之發射極接地，集電極與右聲道相連接；所述第十四 電阻之一端連接於第七二極體之陽極與第三三極管之基極 之間，另一端連接一正電壓；所述第八二極體之陽極連接 於第五放大器之輸出端，陰極與第四三極管之基極相連接 :所述第四三極管之發射極接地，集電極與右聲道相連接 ;所述第十五電阻之一端連接於第八二極體之陽極與第四 三極管之基極之間，另一端連接一負電壓。 10 .如申請專利範圍第1項所述之爆音抑制電路，其中，所述 左右聲道連接於一音訊輸出端口及一喇叭之間。 Ο 〇 099100620 表單編號A0101 第17頁/共18頁 0992001289-0201125375 VII. Patent application scope: 1. A popping suppression circuit, which comprises a signal acquisition circuit, a voltage peak accumulation circuit, a delay circuit, a forward Schmitt trigger circuit, a reverse circuit and a forward Schmitt trigger in series. a circuit and a reverse circuit are connected to the mute circuit; the signal acquisition circuit is configured to collect a positive and negative voltage breakthrough in the left and right channels; and the voltage peak accumulation circuit is configured to accumulate a voltage generated by the positive and negative voltages collected by the signal acquisition circuit; After the voltage accumulated by the voltage peak accumulating circuit exceeds the turn-on voltage of the delay circuit, charging a charging capacitor in the delay circuit; the forward Schmitt trigger circuit generates a high level according to the charging voltage of the charging capacitor; The reverse circuit reverses the level of the output of the forward Schmitt trigger circuit; the mute circuit is connected to the left and right channels, and outputs a high level in the forward Schmitt trigger circuit, and the reverse circuit outputs a low power Normally, the left and right channels are turned on. 2. The pop suppression circuit of claim 1, wherein the signal acquisition circuit comprises a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier; a forward input of the first amplifier Connected to the left channel, the negative input terminal is connected to the output terminal; the forward input terminal of the second amplifier is grounded, and the negative input terminal is connected to the left channel through a first resistor and passes through a second resistor Connected to the output terminal; the positive input terminal of the third amplifier is connected to the right channel, the negative input terminal is connected to the output terminal; the forward input terminal of the fourth amplifier is grounded, and the negative input terminal is passed A third resistor is coupled to the right channel and coupled to the output through a fourth resistor. 3. The pop suppression circuit of claim 2, wherein the voltage peak accumulation circuit comprises a first diode, a second diode, a third two 099100620, a form number A0101, a page 14 of 18 Page 0992001289-0 201125375 polar body, fourth diode, thunder" (2) cumulative capacitance; the first two poles ^ ^ °. output ^ phase connection, the second diode & pole and brother two The output end of the amplifier is connected to pull and pull the phase contact, and the % pole of the third diode is connected with the rim of the third amplifier, and the output of the electric pull is connected, the fourth diode The anode is connected to the wheel end of the fourth amplifier; one end of the fifth resistor is connected to the cathode of the first to fourth diodes connected to the cumulative capacitor, and the other end of the cumulative capacitor is grounded. For example, the blast delay circuit includes a first _ tube, a sixth resistor, and a charging capacitor; and the drain of the first Ν-_ tube is connected to a positive voltage, _ connected between the fifth resistor and the cumulative capacitance 'source and The other end of the sixth resistor is connected to one end of the charging capacitor, and the other end of the charging capacitor is grounded. 5. The popping suppression circuit according to claim 4, wherein The forward Schmitt trigger circuit includes a fifth amplifier, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; a forward input terminal of the fifth escape device is secreted by the sixth resistor and charging Between the capacitors, and the positive input terminal is connected to the output terminal through the ninth resistor, the negative input terminal is connected between the seventh resistor and the eighth resistor, and the other end of the seventh resistor is connected to a positive voltage; The other end of the eighth resistor is grounded; one end of the tenth resistor is connected to the output end of the fifth amplifier, and the other end is connected to a positive voltage. 6. The pop-up suppression circuit according to claim 5, wherein The reverse circuit includes a first P-MOS tube, a second N-MOS tube, and an eleventh resistor; a gate of the first P-MOS tube is connected to a gate of the second N-MOS tube and Connected to the output of the fifth amplifier, the first P-MOS tube The drain is connected to a positive voltage 'the source of the second N-MOS tube is connected to a negative voltage, 099100620 Form No. 1010101 Page 15 / Total α Page 0992001289-0 201125375 The first P-M0S tube t source and The drain of the second N-MOS transistor is connected to and connected to one end of the eleventh resistor; the other end of the tenth-resistance is grounded. 7. The pop-up suppression circuit according to claim 6, wherein The mute circuit includes a left channel mute circuit and a right channel mute circuit, and the left channel mute circuit and the right channel mute circuit are respectively connected to the fifth amplification benefit output terminal and the first P-MOS tube The other end of the source phase connected left channel mute circuit is connected to the left channel, and the other end of the right channel mute circuit is connected to the right channel. 8. The pop-up suppression circuit according to claim 7, wherein the left channel mute circuit comprises a fifth diode, a sixth diode, a first transistor, a second transistor, a twelfth resistor and a thirteenth resistor; a cathode of the fifth diode is connected between a source of the first P-MOS tube and a drain of the second N_M〇s tube, and the anode and the first transistor The base of the first transistor is connected to the ground, and the collector is connected to the left channel; one end of the twelfth resistor is connected to the anode of the fifth diode and the base of the third transistor 'other-end connection-positive voltage between the poles; the anode of the sixth diode is connected to the output end of the fifth amplifier, and the cathode is connected to the base of the flocculation diode; the second triode The emitter grounding 'collector is connected to the left channel ・' one end of the thirteenth resistor is connected between the anode of the sixth diode and the base of the second diode, and the other end is connected - a negative voltage . 9. The pop suppression circuit of claim 7, wherein the right channel mute circuit comprises a seventh diode, an eighth diode, a third transistor, a fourth transistor, and a a fourteenth resistor and a fifteenth resistor; a cathode of the seventh diode is connected between a source of the first P_MOS tube and a drain of the n:m〇s tube, and a base of the anode and the third transistor Connected; the third three 099100620 form number A0101 flute 1ft hundred / ϋ 18 hundred 0992001289-0 201125375 The emitter of the pole tube is grounded, the collector is connected to the right channel; one end of the fourteenth resistor is connected to the Between the anode of the seven-diode body and the base of the third triode, the other end is connected with a positive voltage; the anode of the eighth diode is connected to the output end of the fifth amplifier, the cathode and the fourth triode The base is connected: the emitter of the fourth transistor is grounded, and the collector is connected to the right channel; one end of the fifteenth resistor is connected to the anode and the fourth transistor of the eighth diode Between the bases, the other end is connected to a negative voltage. 10. The pop suppression circuit of claim 1, wherein the left and right channels are connected between an audio output port and a speaker. Ο 〇 099100620 Form No. A0101 Page 17 of 18 0992001289-0
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CN107396243A (en) * 2017-08-10 2017-11-24 惠州Tcl移动通信有限公司 A kind of switching on and shutting down muting control circuit, control method and audio frequency apparatus

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CN106690361A (en) * 2015-07-20 2017-05-24 八琥桐事业有限公司 Baking machine

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TWI275312B (en) * 2005-05-02 2007-03-01 Asustek Comp Inc Anti-pop circuit
TWI351023B (en) * 2008-02-15 2011-10-21 Hon Hai Prec Ind Co Ltd Pop noise suppression apparatus and audio output system utilizing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107396243A (en) * 2017-08-10 2017-11-24 惠州Tcl移动通信有限公司 A kind of switching on and shutting down muting control circuit, control method and audio frequency apparatus
US10826455B2 (en) 2017-08-10 2020-11-03 JRD Communication (Shenzhen) Ltd. Mute control circuit used upon power-on or power-of, control method, and audio device

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