201123447 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體結構及其製造方法，特別 有關於崩潰電壓大於800V的雙擴散金氧半導體電晶體及 其製造方法。 【先前技術】 在當今的積體電路製程中，已於單一晶片中大量地整 合控制器、記憶體、低電壓操作元件與高電壓功率元件等 裝置’因而形成單一晶片系統。為了應付高電壓與電流之 需求’電源裝置中通常應用如雙擴散金氧半導體電晶體 (double-diffused metal oxide semiconductor, DMOS)之高電 壓裝置，其於高電壓下操作時具有較低之導通電阻 (on-resistance)。另外，於超大型積體電路邏輯電路(VLSI) 中則通常整合有其他高電壓裝置，例如具有簡單結構之橫 向擴散型金氧半導體電晶體（lateral double-diffused metal oxide semiconductor，LDMOS)，相較於慣用之垂直擴散型 金氧半導體電晶體（vertical double-diffused metal oxide semiconductor, VDMOS)，其具有較高之導通電阻。 一般在設計電晶體時，主要需考慮使元件具有高崩潰 電壓與低導通電阻(on-resistance)的特性，而近年來LDMOS 製程已見有採用降低表面電場（reduced surface electric field，RESURF)技術。第1圖即顯示美國專利案6,773,997 B2使用RESURF原理的N型LDMOS元件，包括自通道區 415延伸至N+型汲極區406的N型井413，以及在N变井 98009/0516-A42149-TW/fmal/ 4 201123447 413表面上以均一濃度摻雜的平板式（flapp型區4〇8，其中 N型井413作為元件受到電壓時的載子漂移區，p型區408 則作為RESUHF層。而美國專利案6,773,997 B2也進一步 揭露如第2圖所示具有多層以均一濃度摻雜之平板式p型 區408、402的元件。 由於N型井413位於平板式p型區408、402與P型基 底401之間而能在關閉狀態時輕易的空乏’因此能以較高 劑量的N型雜質形成，以降低元件的導通電阻。然而，已 • 發現類似上述結構的LDMOS在關閉狀態時，電場會集中 在N+型沒極區406附近，而擁擠的電場（或電荷的群聚效應 (current crowding effect))會導致元件的崩潰電壓下降，並同 時降低元件的切換速度(switching speed)。另一方面，雖然 可使用降低N型井413的摻雜濃度以增大空乏程度的方法 而達到提咼崩潰電壓的目的，然而元件的導通電阻會因此 跟著提高。根據上述’目前的技術仍難以同時達到高崩潰 電壓與低導通電阻的目的，因此難以應用在超高電壓(UHV) •元件中’故有需要提供一種半導體結構及其形成方法，以 克服先前技藝之不足。 【發明内容】 本發明提供一種半導體結構，包括：一第一導電型基 底，一第二導電型井區，位於該第一導電型基底上；一第 二導電型擴散源極與一第二導電型擴散汲極，位於該第一 導電型基底上；一閘極結構，位於該第二導電型擴散源極 與該第二導電型擴散沒極之間的該第二導電型井區上；以 98009/0516-A42149-TW/final/ 5 201123447 及以橫向排列的多數個第一導電型埋環，形成於該第二導 電型井區中，並將該第二導電型井區分為一上部漂移區血 一下部漂移區。 本發明也提供一種半導體結構的製造方法，包括.提 供一第-導電型基底；於該第一導電型基底上形成 導電型井區；於該第-導電型基底上形成一第二導電评 散源極與-第二導電型擴散沒極；於該第二導電型擴散^ =該第二導電型擴散錄之間的該第二導電型井區上形 結構；以及於該第二導電型井區+形成以横向拼 固第一導電型埋環，其將該第二導電型井區分為 上部漂移區與一下部漂移區。 ’·、、 【實施方式】 本發明之實_提供-⑽導體裝置及 =各力實施例之製造方式和使用方式係如下所詳述，並伴 隨圖不加以說明。其中，圖式和 卫佧 件編號係表示相同或類似之元件。而：圖式中之= =便說明起見’有關實施例之形狀和厚度 下所描述者係特別針對本發 = 件或其整合加以說明’然而 ㈣各項凡 不特別限定於所顯示或描述者，而”二::上述元件並 士所得知的各種形式白此技藝之人 料層或基底之上時，其可以是是位於另-材 入有其他中介層。 接位於其表面上或另外插 第3圖至第U圖顯示本發明N型通道LDM〇s的製程 98009/0516-A42 ] 49-TW/fmal/ 6 201123447 剖面圖。請參考第3圖，於型基底116中形成N型井區 117。；^型井區117的形成方法可包括進行一般的微影製程 以在P·型基底116上形成圖案化的罩幕層（未顯示），接著 對P—型基底116植入N型摻雜質，且然後移除罩幕層。上 述N型摻雜質可包括磷、砷、氮、銻或上述之組合，摻雜 劑量可介於約2xl012/cm2至約lxl013/cm2,摻雜能量可介 於約400keV至約600keV。在植入N型摻雜質後，可進行 退火步驟，其中溫度可介於約l〇〇〇°C至約1050°C，時間可 • 介於約8小時至約15小時，使N型井區117擴散至基底 116約5 μιη至約15 μπι的深度。 請參考第4圖，於Γ型基底116中形成Ρ型井區115。 Ρ型井區115藉由F型基底116而與Ν型井區117互相隔 開。Ρ型井區115的形成方法可包括進行一般的微影製程 以在F型基底116上形成圖案化的罩幕層（未顯示），接著 對Ρ—型基底116植入；Ρ型摻雜質，且然後移除罩幕層。上 述Ρ型摻雜質可包括硼、鎵、鋁、銦或上述之組合。摻雜 ® 劑量可介於約lxl〇14/cm2至約lxl015/cm2 ,摻雜能量可介 於約100 keV至約400 keV。接著可進行退火步驟，溫度介 於約1000°C至約1050°C，時間介於約3小時至約5小時， 使P型井區115擴散至基底116約5 μιη至約15 μπι的深 度。 請參考第5圖，於Ρ_型基底116上形成圖案化罩幕層 121。罩幕層121可包含任何適當的材料，例如二氧化矽、 碳化矽、氮化矽、或氮氧化矽，形成方法可包括物理氣相 沈積法、化學氣相沈積法、電漿增益化學氣相沈積法、高 98009/0516-Α42149-TW/fmal/ 7 201123447 密度電漿化學氣相沈積法、低壓化學氣相沈積法、或其他 任何適當的沈積技術或薄膜成長技術。於一實施例中，罩 幕層121是由矽烷與氧反應所沈積而成的二氧化矽。於其 他例子中，罩幕層121為由四乙氧基石夕淀(tetraethoxysilane; TE0S)與臭氧反應所沈積而成的二氧化矽。於某些實施例 中，罩幕層121為光阻材料。或者，於一實施例中，罩幕 層121也可為由二氧化矽層121A與光阻層121B構成的結 構，如第5圖所示。於一實施例中，係利用一光罩進行一 微影程序，以於罩幕層121中形成開口，其露出部分N型 井區117。微影程序依序為：上光阻、光阻曝光、顯影、 及去光阻等步驟，由於其為此技藝之人士所熟知的，因此 於此不再贅述。 請參考第6圖，接著可進行一或多個佈植製程以於圖 案化罩幕層121露出的N型井區117中形成多數個P型埋 環118，而之後還可進行退火步驟使P型埋環118擴散至 適當的輪廓(profile)。P型埋環Π8的寬度與間距主要可藉 由形成圖案化罩幕層121所使用的光罩予以定義。於實施 例中，每個P型埋環118藉由N型井區117而彼此分開，BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a double-diffused MOS transistor having a breakdown voltage greater than 800 V and a method of fabricating the same. [Prior Art] In today's integrated circuit process, devices such as controllers, memories, low voltage operating elements, and high voltage power components have been integrated in a single wafer, thus forming a single wafer system. In order to cope with the demand of high voltage and current, high voltage devices such as double-diffused metal oxide semiconductor (DMOS) are usually used in power supply devices, which have low on-resistance when operating at high voltage. (on-resistance). In addition, in the ultra-large integrated circuit logic circuit (VLSI), other high-voltage devices are usually integrated, such as a lateral double-diffused metal oxide semiconductor (LDMOS) with a simple structure. In a conventional vertical double-diffused metal oxide semiconductor (VDMOS), it has a high on-resistance. Generally, when designing a transistor, it is mainly necessary to consider the element to have a high breakdown voltage and a low on-resistance characteristic. In recent years, the LDMOS process has seen a reduced surface electric field (RESURF) technique. Figure 1 shows an N-type LDMOS device using the RESURF principle in U.S. Patent No. 6,773,997 B2, including an N-type well 413 extending from the channel region 415 to the N+ type drain region 406, and a N-well 98009/0516-A42149-TW /fmal/ 4 201123447 413 A flat type (flapp type region 4〇8) in which the surface is doped at a uniform concentration, wherein the N-type well 413 serves as a carrier drift region when the element is subjected to a voltage, and the p-type region 408 serves as a RESUHF layer. U.S. Patent No. 6,773,997 B2 further discloses an element having a plurality of planar p-type regions 408, 402 doped at a uniform concentration as shown in Figure 2. Since the N-well 413 is located in the flat p-type regions 408, 402 and P-type. The substrate 401 can be easily depleted in the off state, so it can be formed with a higher dose of N-type impurities to reduce the on-resistance of the device. However, it has been found that the LDMOS similar to the above structure is in the off state, the electric field will Concentrated near the N+ type non-polar region 406, the crowded electric field (or the current crowding effect of the charge) causes the breakdown voltage of the component to drop, and at the same time reduces the switching speed of the component. ,although The method of reducing the doping concentration of the N-type well 413 to increase the degree of depletion can be used to achieve the purpose of raising the breakdown voltage, but the on-resistance of the element is accordingly increased. It is still difficult to simultaneously achieve a high breakdown voltage according to the above-mentioned 'current technology. For the purpose of low on-resistance, it is therefore difficult to apply in ultra-high voltage (UHV) devices. It is therefore necessary to provide a semiconductor structure and a method of forming the same to overcome the deficiencies of the prior art. [Invention] The present invention provides a semiconductor structure. The method includes: a first conductive type substrate, a second conductive type well region on the first conductive type substrate; a second conductive type diffusion source and a second conductive type diffusion drain, located at the first conductive type a gate structure; the gate structure is located on the second conductivity type well region between the second conductivity type diffusion source and the second conductivity type diffusion electrode; 98009/0516-A42149-TW/final/ 5 201123447 and a plurality of first conductivity type buried rings arranged in a lateral direction are formed in the second conductivity type well region, and the second conductivity type well is divided into an upper drift region blood one The present invention also provides a method for fabricating a semiconductor structure, comprising: providing a first conductivity type substrate; forming a conductive well region on the first conductivity type substrate; forming a first layer on the first conductivity type substrate a second conductive type dispersion source and a second conductive type diffusion pole; a second conductive type diffusion ^= the second conductive type diffusion type between the second conductive type well region; and The two-conducting well region + is formed to laterally fix the first conductive type buried ring, and the second conductive type well is divided into an upper drift region and a lower drift region. EMBODIMENT OF THE INVENTION The present invention provides a method for manufacturing a conductor device and a method for using each of the force embodiments, as described below, and will not be described with reference to the drawings. Wherein, the drawings and the guard number are the same or similar components. And: = = in the drawings for the sake of explanation 'The shapes and thicknesses of the relevant embodiments are specifically described for the hair piece or its integration'. However, (4) are not particularly limited to the display or description. And "two:: When the various elements mentioned above are known to be in the form of a human layer or a substrate, it may be located in another material layer. Inserting FIG. 3 to FIG. U shows a process of the N-type channel LDM 〇s of the present invention 98009/0516-A42] 49-TW/fmal/ 6 201123447. Referring to FIG. 3, an N-type is formed in the type substrate 116. The method of forming the well region 117 may include performing a general lithography process to form a patterned mask layer (not shown) on the P·type substrate 116, followed by implanting the P-type substrate 116. N-type dopant, and then removing the mask layer. The above-mentioned N-type dopant may include phosphorus, arsenic, nitrogen, antimony or a combination thereof, and the doping amount may be from about 2×10 12 /cm 2 to about l×l013/cm 2 , The doping energy may be between about 400 keV and about 600 keV. After implanting the N-type dopant, an annealing step may be performed, The intermediate temperature may range from about 10 ° C to about 1050 ° C for a period of time ranging from about 8 hours to about 15 hours to allow the N-well region 117 to diffuse to a depth of the substrate 116 from about 5 μm to about 15 μm. Referring to FIG. 4, a 井-type well region 115 is formed in the Γ-type substrate 116. The 井-type well region 115 is separated from the Ν-type well region 117 by the F-type substrate 116. The formation method of the Ρ-type well region 115 A general lithography process can be performed to form a patterned mask layer (not shown) on the F-type substrate 116, followed by implantation of the Ρ-type substrate 116; Ρ-type dopant, and then removing the mask layer The above-mentioned erbium type dopant may include boron, gallium, aluminum, indium or a combination thereof. The doping amount may be from about lxl 〇 14/cm 2 to about l x l 015 / cm 2 , and the doping energy may be from about 100 keV to Approximately 400 keV. An annealing step can then be performed at a temperature of between about 1000 ° C and about 1050 ° C for a period of from about 3 hours to about 5 hours to diffuse the P-type well region 115 to the substrate 116 from about 5 μm to about 15 The depth of μπι. Referring to Figure 5, a patterned mask layer 121 is formed on the Ρ-type substrate 116. The mask layer 121 may comprise any suitable material, such as Cerium oxide, tantalum carbide, tantalum nitride, or niobium oxynitride may be formed by physical vapor deposition, chemical vapor deposition, plasma gain chemical vapor deposition, high 98009/0516-Α42149-TW/fmal / 7 201123447 Density plasma chemical vapor deposition, low pressure chemical vapor deposition, or any other suitable deposition technique or thin film growth technique. In one embodiment, the mask layer 121 is deposited by reacting decane with oxygen. As a cerium oxide. In other examples, the mask layer 121 is cerium oxide deposited by reacting tetraethoxysilane (TEOS) with ozone. In some embodiments, the mask layer 121 is a photoresist material. Alternatively, in an embodiment, the mask layer 121 may also be a structure composed of a ceria layer 121A and a photoresist layer 121B, as shown in Fig. 5. In one embodiment, a lithography process is performed using a mask to form an opening in the mask layer 121 that exposes a portion of the N-well region 117. The lithography procedure is followed by steps of: upper photoresist, photoresist exposure, development, and photoresist removal, which are well known to those skilled in the art and therefore will not be described again. Referring to FIG. 6, one or more implantation processes may be performed to form a plurality of P-type buried rings 118 in the N-type well region 117 exposed by the patterned mask layer 121, and then an annealing step may be performed to make P The buried ring 118 diffuses to the appropriate profile. The width and spacing of the P-type buried ring 8 can be primarily defined by the reticle used to form the patterned mask layer 121. In an embodiment, each P-type buried ring 118 is separated from each other by an N-type well region 117.
P型埋環118之間的間距則可相同或不同。此外，由於〆 型埋環118是以相同的佈植製程同步形成，因此具有相同 的深度及厚度，且每個P型埋環118的摻雜質總量是正比 於寬度。當從N型井區117的左端到右端，每個P型埋環 118的摻雜輪廓呈線性逐漸變小（或變窄）時，表示P型摻雜 質的量（或電荷量）呈線性逐漸變少，因此N型井區117的 表面摻雜濃度會從左端向右端逐漸變大。於實施例中，P 98009/0516-A42149-TW/final/ 8 201123447 μιη至 μιη至 型埋環118的寬度介於24卜瓜至65 μιη、深度為〇 ΙΟμιη，且相鄰近的Ρ型埋環U8之間的間距介於工 3 μιη 〇 、 ρ型埋環！㈣電荷量與深度（或厚度)可藉由 製程參數，例如摻雜劑量、摻雜能量㈣雜質，The spacing between the P-type buried rings 118 may be the same or different. In addition, since the 〆-type buried rings 118 are formed in synchronization with the same implantation process, they have the same depth and thickness, and the total amount of doping of each of the P-type buried rings 118 is proportional to the width. When the doping profile of each P-type buried ring 118 gradually becomes smaller (or narrower) from the left end to the right end of the N-type well region 117, the amount (or amount of charge) of the P-type dopant is linear. Gradually, the surface doping concentration of the N-type well region 117 gradually increases from the left end to the right end. In the embodiment, P 98009/0516-A42149-TW/final/ 8 201123447 μιη to μιη to the buried ring 118 has a width of 24 to 65 μm, a depth of 〇ΙΟμιη, and adjacent Ρ-type buried ring The spacing between U8 is between 3 μιη 〇, ρ-type buried ring! (4) The amount of charge and depth (or thickness) can be determined by process parameters such as doping amount, doping energy (IV) impurity,
退火製程參數，例如溫度與時間而予以控制。ρ型埋/= 使用的Ρ型捧雜質可包括棚、鎵，、銦或上述之组^ 掺雜劑量可介於約_^^至約3xlQ12/em2，接雜^ 可介於約1500 1cev至約2000kev。於實施例中’退火= 為約700°C至約90CTC，退火時間為約9〇分鐘至約12= 鐘。根據上述，本發明的P型埋環118僅需使用單一個= 罩進行微影及佈植製程即可控制輪廓分佈，方法簡單且不 會造成太大的額外負擔。 請參考第7圓’於P型埋環118上方形成介電層14〇。 如第7圖:斤示，介電層14〇可為局部場氧化結構。於一例 ^中，局部場氧化介電結構14〇的形成方式包括在N型井 品 上形成圖案化的罩幕層（未顯示），然後進行一姓刻 步驟，以將罩幕層所露出N型井區117表面的材料，例如 氧化妙或氮切材料移除，藉此露itU辣面，接著進行氧 化步驟使罩幕層露出白勺N型井區117石夕表面氧化而形 成抑介電層14G並不限定於局部場氧化結構，其亦可以利 技藝中料幕層所露出的N型井區117進行钮刻製 程以形成’冓槽，並以例如氧化物的介電材料填充溝槽的方 式开7成（未顯不）。接箸可移除罩幕層。介電層140的厚度 可介於5_)埃至8_埃，但不限於此。 98009/0516-A42l49-TW/fmal/ . 201123447 請參考第8圖，於P型井區115與N型井區117上形 成介電層120。介電層120的厚度小於介電層ι4〇,可介於 500埃至1〇〇〇埃。介電層12〇可包括利用熱氧化法，於^ 型井區115與N型井區117的表面所生成的氧化物。介電 層120亦可包括，例如：二氧化矽、氮氧化矽或氮化矽、 高介電常數介電質或上述之組合。介電層12〇亦可為下列 一或多個材料所組成，包括：氧化鋁（Al2〇3)、氧化給 (Hf〇2)、氮氧化铪(HfON)、矽酸铪(HfSi04)、氧化錯(Zr〇2)、 氮氧化錘(ZrON)、矽酸锆(ZrSiCXO、氧化釔(γ2〇3)、氧化鑭 (La203)、氧化鈽（Ce〇2)、氧化鈦（Ti〇2)或氧化鈕(Ta2〇5)。 介電層120的形成方法也可使用有化學氣相沉積法，如低 溫化學氣相沉積、低壓化學氣相沉積、快熱化學氣相沉積、 電聚化學氣相沉積法，或是使用例如濺鍍及物理氣相沉積 法進行。於一實施例中’介電層120與14〇皆為氧化石夕 (silicon dioxide)。 請參考第9圖’於介電層120上形成電極層U2。電 極層112可延伸至介電層140上，如第9圖所示。於一實 施例中，電極層112為多晶矽。而電極層U2也可包括其 他適當的材料，例如 Ti、TiN、Ta、TaN、cU、A1、Mo、' Co、W、WN、MoSi、WSi、CoSi 等金屬。 請參考第9圖’於P型井區115中形成型擴散區 114 ’並於N型井區117中形成N+型擴散區119。N+型擴 散區114與N+型擴散區119的形成方法可包括進行_般的 微影製程’以在P型井區115與N型井區〗17上形成圖案 化的罩幕層121，接著對P型井區115與n型井區117植 98009/0516-A42149-TW/fmal/ 10 201123447 入N型摻雜質，且然後移除罩幕層121。上述摻雜質 可包括磷、砷、氮、銻或上述之組合。由於罩幕層121相 似於第5圖至第6圖的罩幕層121，因此，為求簡潔’於 此不予贅述。 請參考第10圖，於P型并區115中形成p型擴散區 113°P+型擴散區113的形成方法可包括進行一般的微影製 程，以在P型井區115與N型井區117上形成圖案化的罩 幕層121 ’接著對p型井區115植入p型摻雜質，且然後 移除罩幕層121。上述p型摻雜質可包括硼、鎵、鋁、銦 或上述之組合。由於罩幕層121相似於第5圖至第6圖的 罩幕層121 ’因此’為求簡潔，於此不予贅述。於實施例 中，N+型擴散區119的寬度介於75 μπι至8〇 μιη，N+型擴 散區114的寬度介於1〇 μπι至18 μιη，p+型擴散區113的 寬度介於0 μιη至1 〇 μπι。 請參考第11圖，利用微影及蝕刻製程移除Ν+型擴散 區119、Ν+型擴散區114與γ型擴散區113上的介電層 120,然後於N+型汲極區119上形成導電層lu，於矿型 源極區114與P+型擴散區113上形成導電層11〇，並於電 極層112上形成導電層1〇9。於一實施例中，導電層1〇9、 110與111為同步形成。導電層109、11〇、m可包括金 屬或其合金，或其他合適的材料。舉例來說，導電層1〇9、 110、111可為鋁或鈦合金。 在第11圖所顯示的最終LDM0S結構中’N+型擴散區 114為源極，矿型擴散區119為汲極，通道區128則位於 N+型擴散源極114#N型井區117之間，而閘極位於通道 98009/0516-A42149-TW/fmay ,, 201123447 128上方，包括作為閘極絕緣層的介電層〗2〇與作為閘極 電極層的電極層112，用來控制電晶體電流，此外以介電 層140下方的N型井區117作為漂移區（drift region)123， 此傳導通道用來連接N+型擴散源極1H與型擴散汲極 119。在形成N+型擴散源極114與N型井區117時選擇適 當的摻雜劑量及能量能提供通道128恰當的臨界電壓。 導電層110可提供N+型擴散源極ι14電性連接而用作 源極電極，導電層1Π則可提供N+型擴散汲極119電性連 接而用作汲極電極。另外，使用P+型擴散區113緊鄰N+ 型擴散源極114能降低元件對寄生雙載子效應(parasitic bipolar effect)的感受性(susceptibility)並避免基底效應。 於一實施例中，厚介電層140可完全覆蓋漂移區123 (如第11圖所示）。於其他實施例中，介電層140則覆蓋 部分漂移區123，或者，漂移區123上方也可以沒有介電 層。使用厚介電層140能夠減少閘極邊緣所造成的垂直電 場效應，藉此提升元件的崩潰電壓。於一實施例中，汲極 電極111可延伸至介電層140上（未顯示）以作用為場板 (field plate)。此外，當閘極電極層112延伸至介電層140 上時(如第11圖所示），閘極電極層112也可用作場板(field plate)。使用上述場板結構能夠促進元件的電場分佈而減少 電場聚集，藉此增加電晶體的崩潰電壓。 請參考第11圖’由於P型埋環118的摻雜輪廓從左至 右逐漸變小，同時使N型漂移區123靠近通道區128的部 分其表面摻雜濃度會大於靠近N+型汲極區119的部分，因 此元件在關閉狀態時，N型漂移區123靠近通道區128的 98009/0516-A42149-TW/final/ 12 201123447 部分相較於靠近N+型擴散汲極Π9的部分會更容易被完全 空乏掉，使得元件在相同偏壓的環境下具有較低的飽和電 流。另外，輪廓呈線性變化的Ρ型埋環118其產生,的負電 荷會誘導出與内本電埸（intrinsic field)相反方向的額外電 場，其中在每個P型埋環118的邊緣產生新的尖峰電場 (peak electrical field)，因此能夠降低主要接面邊緣(main junction edge)的尖峰電場而有助於電荷的平衡，以重新分 配電晶體在關閉狀態時的電場分佈，使元件的崩潰電壓提 籲 升。崩潰電壓的提升可藉由調整每個埋環的寬度與間距達 到最佳化。提升崩潰電壓同時有助於提高元件的切換速度。 當LDMOS在導通狀態(on-state)時，來自N+型擴散源 極114的電子穿過通道區1_28 ’然後穿過由上部漂移區124 及下部漂移區125構成的雙平行導通通道，最後傳至N+型 擴散汲極119。上述雙平行導通通道能大幅提升元件的電 荷導通性。由於N型井區117下方為ρ·型基底116，且其 中具有P型埋環118’而具有環型摻雜輪廓的p型埋環118 ® 與N型井區117之間具有大接觸面積，因此當LDMOS在 關閉狀態時，N型.井區117能輕易空乏，故N型井區117 能以較高的摻雜濃度形成，此外，P型埋環118佔據N型 漂移區123的比例小，因此N型漂移區123的通道比例不 會縮小，故能藉此降低元件的導通電阻。Annealing process parameters such as temperature and time are controlled. Ρ-type buried /= used Ρ type holding impurities may include shed, gallium, indium or the above group ^ Doping dose may be from about _^^ to about 3xlQ12/em2, and the mixture may be between about 1500 1cev to About 2000kev. In the examples, the annealing = from about 700 ° C to about 90 CTC, and the annealing time is from about 9 Torr to about 12 = hr. According to the above, the P-type buried ring 118 of the present invention can control the contour distribution only by using a single mask = lithography and implantation process, and the method is simple and does not cause too much additional burden. Referring to the 7th circle, a dielectric layer 14 is formed over the P-type buried ring 118. As shown in Figure 7, the dielectric layer 14〇 can be a local field oxide structure. In one example, the formation of the local field oxide dielectric structure 14〇 includes forming a patterned mask layer (not shown) on the N-type well product, and then performing a surname step to expose the mask layer. The material on the surface of the well region 117, such as the oxidized or nitrogen-cut material, is removed, thereby exposing the itU spicy surface, followed by an oxidation step to oxidize the surface of the N-type well region 117 exposed to the mask layer to form a dielectric barrier. The layer 14G is not limited to the local field oxide structure, and the N-type well region 117 exposed by the material layer in the art can be subjected to a button engraving process to form a 'groove, and the trench is filled with a dielectric material such as oxide. The way to open 70% (not shown). The cover removes the mask layer. The thickness of the dielectric layer 140 may range from 5 Å Å to 8 Å, but is not limited thereto. 98009/0516-A42l49-TW/fmal/ . 201123447 Referring to FIG. 8, a dielectric layer 120 is formed on the P-type well region 115 and the N-type well region 117. The dielectric layer 120 has a thickness less than the dielectric layer ι4 〇 and may range from 500 angstroms to 1 angstrom. The dielectric layer 12A may include oxides formed on the surface of the well region 115 and the N-type well region 117 by thermal oxidation. Dielectric layer 120 can also include, for example, hafnium oxide, hafnium oxynitride or tantalum nitride, a high dielectric constant dielectric, or a combination thereof. The dielectric layer 12〇 may also be composed of one or more of the following materials, including: aluminum oxide (Al 2 〇 3), oxidized (Hf 〇 2), bismuth oxynitride (HfON), bismuth ruthenate (HfSi04), oxidation Malfunction (Zr〇2), nitrogen oxide hammer (ZrON), zirconium silicate (ZrSiCXO, yttrium oxide (γ2〇3), lanthanum oxide (La203), cerium oxide (Ce〇2), titanium oxide (Ti〇2) or Oxidation button (Ta2〇5). The dielectric layer 120 can also be formed by chemical vapor deposition, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, electropolymerization The deposition method is performed by, for example, sputtering and physical vapor deposition. In one embodiment, both dielectric layers 120 and 14 are silicon dioxide. Please refer to Fig. 9 for the dielectric layer. An electrode layer U2 is formed on 120. The electrode layer 112 may extend onto the dielectric layer 140 as shown in Fig. 9. In one embodiment, the electrode layer 112 is polycrystalline germanium, and the electrode layer U2 may also include other suitable materials. For example, Ti, TiN, Ta, TaN, cU, A1, Mo, 'Co, W, WN, MoSi, WSi, CoSi, etc. Please refer to Fig. 9 to form in the P-type well region 115. The diffusion region 114' forms an N+ type diffusion region 119 in the N-type well region 117. The formation method of the N+ type diffusion region 114 and the N+ type diffusion region 119 may include performing a general lithography process to be in the P-type well region 115. Forming a patterned mask layer 121 on the N-type well region 17, and then implanting N-type dopants into the P-type well region 115 and the n-type well region 117 98009/0516-A42149-TW/fmal/ 10 201123447, And then removing the mask layer 121. The above dopants may include phosphorus, arsenic, nitrogen, antimony or a combination thereof. Since the mask layer 121 is similar to the mask layer 121 of FIGS. 5 to 6, therefore, For the sake of brevity, the details are not described herein. Referring to FIG. 10, the formation of the p-type diffusion region 113°P+-type diffusion region 113 in the P-type pad 115 may include a general lithography process to be performed in the P-type. A patterned mask layer 121' is formed on the well region 115 and the N-type well region 117. Next, the p-type well region 115 is implanted with a p-type dopant, and then the mask layer 121 is removed. The p-type dopant can be used. Including boron, gallium, aluminum, indium or a combination thereof. Since the mask layer 121 is similar to the mask layer 121' of FIGS. 5 to 6 'so' for the sake of brevity, no further description is provided herein. In the embodiment, the N+ type diffusion region 119 has a width of 75 μm to 8 μm, the N+ type diffusion region 114 has a width of 1 μm to 18 μm, and the p+ type diffusion region 113 has a width of 0 μm to 1 〇μπι. Referring to Fig. 11, the Ν+-type diffusion region 119, the Ν+-type diffusion region 114 and the dielectric layer 120 on the γ-type diffusion region 113 are removed by a lithography and etching process, and then the N+-type drain electrode is used. A conductive layer lu is formed on the region 119, a conductive layer 11 is formed on the mineral source region 114 and the P+ diffusion region 113, and a conductive layer 1〇9 is formed on the electrode layer 112. In one embodiment, the conductive layers 1〇, 110, and 111 are formed in synchronization. Conductive layers 109, 11A, m may comprise metals or alloys thereof, or other suitable materials. For example, the conductive layer 1 〇 9, 110, 111 may be aluminum or a titanium alloy. In the final LDMOS structure shown in FIG. 11, the 'N+ type diffusion region 114 is the source, the mineral diffusion region 119 is the drain, and the channel region 128 is located between the N+ diffusion source 114#N type well region 117. The gate is located above the channel 98009/0516-A42149-TW/fmay, 201123447 128, and includes a dielectric layer as a gate insulating layer and an electrode layer 112 as a gate electrode layer for controlling the transistor current. In addition, an N-type well region 117 under the dielectric layer 140 is used as a drift region 123 for connecting the N+ type diffusion source 1H and the type diffusion drain 119. Selecting the appropriate dopant dose and energy during formation of the N+ diffusion source 114 and the N-well region 117 provides the proper threshold voltage for the channel 128. The conductive layer 110 can provide an N+ type diffusion source 145 electrically connected to serve as a source electrode, and the conductive layer 1 提供 can provide an N+ type diffusion 119 electrically connected to serve as a drain electrode. In addition, the use of the P+ type diffusion region 113 in close proximity to the N+ type diffusion source 114 can reduce the susceptibility of the element to the parasitic bipolar effect and avoid the substrate effect. In one embodiment, the thick dielectric layer 140 can completely cover the drift region 123 (as shown in FIG. 11). In other embodiments, the dielectric layer 140 covers a portion of the drift region 123, or there may be no dielectric layer above the drift region 123. The use of the thick dielectric layer 140 reduces the vertical electric field effects caused by the gate edges, thereby increasing the breakdown voltage of the components. In one embodiment, the drain electrode 111 can extend over the dielectric layer 140 (not shown) to act as a field plate. Further, when the gate electrode layer 112 extends over the dielectric layer 140 (as shown in FIG. 11), the gate electrode layer 112 can also function as a field plate. The use of the above field plate structure can promote the electric field distribution of the element to reduce electric field concentration, thereby increasing the breakdown voltage of the transistor. Please refer to FIG. 11 'Because the doping profile of the P-type buried ring 118 is gradually reduced from left to right, the surface doping concentration of the portion of the N-type drift region 123 near the channel region 128 is greater than that near the N+-type drain region. The portion of 119, so that when the component is in the off state, the portion of the N-type drift region 123 near the channel region 128 of 98009/0516-A42149-TW/final/ 12 201123447 is more likely to be compared to the portion near the N+-type diffusion gate Π9. Completely vacant, allowing the component to have a lower saturation current in the same biased environment. In addition, the Ρ-type buried ring 118, which has a linearly varying profile, produces a negative electric charge that induces an additional electric field in the opposite direction to the intrinsic field, where a new one is created at the edge of each P-type buried ring 118. The peak electrical field, thus reducing the peak electric field of the main junction edge and contributing to the charge balance, redistributing the electric field distribution of the transistor in the off state, and causing the breakdown voltage of the component Called up. The increase in breakdown voltage can be optimized by adjusting the width and spacing of each buried loop. Increasing the breakdown voltage also helps to increase the switching speed of components. When the LDMOS is in-state, electrons from the N+-type diffusion source 114 pass through the channel region 1_28' and then pass through the double parallel conduction channel formed by the upper drift region 124 and the lower drift region 125, and finally pass to The N+ type diffuses the drain 119. The above-described dual parallel conduction channel can greatly improve the charge conductivity of the component. Since the N-type well region 117 is below the p-type substrate 116, and has a P-type buried ring 118' therein, and has a large contact area between the p-type buried ring 118® having a ring-shaped doping profile and the N-type well region 117, Therefore, when the LDMOS is in the off state, the N-type well region 117 can be easily depleted, so the N-type well region 117 can be formed with a higher doping concentration, and in addition, the P-type buried ring 118 occupies a small proportion of the N-type drift region 123. Therefore, the channel ratio of the N-type drift region 123 is not reduced, so that the on-resistance of the device can be reduced.
於一實施例中’ N型漂移區的長度約為55μπι。於一實 施例中，上部漂移區124的電荷濃度約為2.8xl012 cm·2， 下部漂移區125的電荷濃度約為2,7xl〇12 cm·2，而p型埋 環118的電荷濃度約為2.4x1012 cm-2。於另一實施例中，N 98009/0516-A42149-TW/final/ 13 201123447 型上部漂移區124及N型下部漂移區125中的總淨電荷約 為 3xl012cnT2，其約為傳統單一（Singie) reSURF LDMOS 的三倍以上，傳統雙（double) RESURF LDMOS的兩倍以 上，也就是說，本發明LDMOS之漂移區的電阻縮減至傳 統裝置的三分之一左右，因而證實其具有較低的導通電 阻。於實施例中，崩潰電壓大於800V，例如介於800V至 900V ’而導通電阻小於11 〇 cm2，例如介於100 ιηΩ cm2 至 110 πιΩ cm2。 第13圖為本發明具有π個p型埋環的結構實施例的 分析圖。第14圖則為不具有p型埋環的典型結構的分析 圖。比較第13圖與第14圖可發現，第13圖N型漂移區 中的電場是均勻分佈的，因此元件會具有較高的崩潰電 壓’反觀第14圖中的電場會在N型漂移區的末端發生驟 起的現象’而使元件具有較低的崩潰電壓。 上述本發明的概念也可應用在具有指插狀結構的 LDMOS元件中。一般技術為了得到更大的驅動電流，需要 盡可能地延長元件的長度，而為了充分利用寸土寸金的晶 圓面積’因應而生的是部分區域元件被彎轉的指插狀結構 LDMOS。對於具有指插狀結構的LDM〇s元件來說，在元 件操作時’其具有彎曲表面的指末端（例如參考第12圖中 所示的以汲極為中心（drain center)的指末端150與以源極 為中心（source center)的指末端152)所產生的擁擠電場會導 致崩潰電壓下降，特別是當元件尺寸變小，亦即筆直的指 部（如第12圖中所示的指部154)寬度變窄，亦或是指末端 的弧半徑變小時，電場聚集會變嚴重而更加惡化崩潰電壓 98009/0516-A42149-TW/fmal/ 14 201123447 下降的問題°為了避免上述問題以增加元件的崩潰電壓， 習知技術是將指末端的寬度變寬以使其弧半徑變大，但此 會增加s件的佔據面積而降低佈局彈性題制微縮化的發 展。根據上述，本發明也提供一種應用多數個p型埋環佈 局以避免指末端電場擁擠的問題。 •第12圖為根據本發明概念之一實施例具有指插狀 (finger interdigitated)結構之LDM〇s的上示圖，其顯示例 如第11圖中的P型埋環118、n+型擴散源極n/、'通道區 128、N型井區117與N+型擴散汲極119的表面，其餘的 元件則省略須注意第12圖僅概念式的顯示本發明實施例 的精神，而未完整畫出P型埋環118的分佈，實際上卩型 埋環118也可具有連續延伸在整個元件中的跑道(繼⑽幻 結構，或者部分不同區域的p型埋環118會互相連接。 本發明實施例在以汲極為中心的指末端15〇、以源極 為中心的指末端152與筆直的指部丨“的^^型井區n7中 分別形成不同分佈的P型埋環，使不同區域N型井區ιΐ7 中的漂移區具有不同的表面摻雜濃度。為了適當調整整個 元件的崩=電壓’以祕為中心的指末端15G其漂移區的 表面摻雜濃度必須減少’以源極為中心的指末端152其漂 移區的表面掺雜濃度則必須增加，換句話說，指末端15〇 中P型埋％的總電荷量必須大於指末端152中的p型埋 環。於一實施例中’指末端15〇中的p型埋環的數量大於 指末端Μ2 ^ P型埋環。此外，為同時適當.的個別調整 不同區域元件部分的崩潰電壓’本發明也可同時在指末端 150使用上述摻雜輪廓從通道區到汲極方向呈線性逐 98009/0516-A42149-TW/fmai/ 啊、史 201123447In one embodiment, the length of the 'N-type drift region is about 55 μm. In one embodiment, the charge concentration of the upper drift region 124 is about 2.8×10 12 cm·2, and the charge concentration of the lower drift region 125 is about 2,7×1〇12 cm·2, and the charge concentration of the p-type buried ring 118 is about 2.4x1012 cm-2. In another embodiment, the total net charge in the upper drift region 124 and the N-type lower drift region 125 of the N 98009/0516-A42149-TW/final/ 13 201123447 type is about 3xl012cnT2, which is about the traditional single (Singie) reSURF. More than three times that of LDMOS, more than twice that of the conventional double RESURF LDMOS, that is, the resistance of the drift region of the LDMOS of the present invention is reduced to about one-third of that of the conventional device, thus confirming that it has a low on-resistance. . In an embodiment, the breakdown voltage is greater than 800V, such as between 800V and 900V' and the on-resistance is less than 11 〇 cm2, such as between 100 ηηΩ cm2 and 110 πιΩ cm2. Figure 13 is an analysis diagram of an embodiment of a structure having π p-type buried rings of the present invention. Figure 14 is an analysis of a typical structure without a p-type buried ring. Comparing Fig. 13 and Fig. 14 reveals that the electric field in the N-type drift region of Fig. 13 is uniformly distributed, so the component will have a higher breakdown voltage. In contrast, the electric field in Fig. 14 will be in the N-type drift region. The phenomenon of a sudden rise at the end' causes the component to have a lower breakdown voltage. The above concept of the present invention can also be applied to an LDMOS device having a finger-like structure. In order to obtain a larger driving current, it is necessary to extend the length of the element as much as possible, and in order to make full use of the crystal area of the inch of gold, a finger-inserted structure LDMOS in which a partial area element is bent is generated. For an LDM 〇 s element having a finger-like structure, the finger end having a curved surface when the element is in operation (for example, referring to the finger end 150 of the drain center shown in FIG. 12 and The crowded electric field generated by the source end of the source center 152) causes a collapse voltage drop, especially as the component size becomes smaller, i.e., a straight finger (such as the finger 154 shown in Figure 12). The width is narrowed, or the radius of the arc at the end is small, the electric field concentration becomes severe and the breakdown voltage is worse. 98009/0516-A42149-TW/fmal/ 14 201123447 The problem of falling °In order to avoid the above problems, the component collapse is increased. Voltage, the conventional technique is to widen the width of the end of the finger to make the radius of the arc larger, but this will increase the occupied area of the s piece and reduce the development of the layout elasticity miniaturization. In light of the above, the present invention also provides a problem of applying a plurality of p-type buried-ring layouts to avoid crowding of the end field electric field. • Fig. 12 is a top view of an LDM 〇s having a finger interdigitated structure according to an embodiment of the present invention, showing, for example, a P-type buried ring 118, an n+ type diffusion source in FIG. n /, 'channel area 128, N-type well area 117 and N + type diffusion dipole 119 surface, the rest of the components are omitted. Note that Figure 12 only conceptually shows the spirit of the embodiment of the present invention, but not completely drawn The distribution of the P-type buried ring 118, in fact, the 卩-type buried ring 118 may also have a runway extending continuously throughout the component (following the (10) phantom structure, or a portion of the different regions of the p-type buried ring 118 may be interconnected. Embodiments of the invention Differently distributed P-type buried rings are formed in the well-type finger end 152 with the center of the 汲, the finger end 152 with the source center, and the straight finger 丨" The drift region in the region ιΐ7 has different surface doping concentrations. In order to properly adjust the collapse/voltage of the entire component, the surface doping concentration of the drift region of the finger-end end 15G must be reduced by the source-centered finger end. 152 the surface doping concentration of the drift region is It must be increased, in other words, the total amount of charge in the P-type buried end of the terminal 15〇 must be greater than the p-type buried ring in the terminal end 152. In one embodiment, the number of p-type buried rings in the end 15〇 More than the end of the finger Μ 2 ^ P-type buried ring. In addition, the clamping voltage of the different regional component parts is adjusted individually for the same time. The present invention can also be linear at the finger end 150 using the above doping profile from the channel region to the drain. By 98009/0516-A42149-TW/fmai/ Ah, history 201123447
小的p型埋環；也能在指末端i52使用上述 = 及極方向呈線性逐漸變小的PS埋環C =使:，輪―及極方 漸變小的P型埋頊 ^ Dn _ 王深性逐 TT^mc 、 ^因此，本發明具有指插狀結播Μ 不需增加元件占據面積即可達到增雷 ㈣目的。此外，本發明在不同區域具有不同分 埋裱僅需利用一個光罩進行微影與佈植製裎即可形成，因 此方法簡單且不會造成太大的額外負擔。於實施例中，元 件的崩潰電壓大於800V，例如介於800V至900V，而導通 電阻小於 llOmficm2,例如介於 100inQcm2 至 ii〇mi2cm2。 本發明實施例具有以下優點：本發明在N型通道 LDMOS的N型漂移區中形成多數個互相分開且摻雜輪廓 從源極到汲極的方向遞減的P型埋環，能夠促進元件在關 閉狀態時的電場分佈，以避免電場群聚效應並提升崩潰電 壓。另一方面，本發明的N型井區能以高摻雜濃度形成， 且N型漂移區的通道比例不會因為？型埋環而縮小，因此 能夠藉此降低元件的導通電阻。此外，p型埋環僅需使用 光罩進行微影及佈植製程即可形成，方法簡單且不會造成 成本上的負擔。根據上述’本發明能以簡單的方法同時增 進LDMOS的崩潰電壓並降低導通電阻，因此能應用在超 高電壓技術中。 以上之實施例僅用以本發明之範例，舉例來說，當討 論N型通道LDMOS之實施例時，另一實施例可以是以相 反導電型摻雜質所形成的P型通道LDMOS。雖然本發明已 以較佳實施例揭露如上’然其並非用以限定本發明，任何 98009/0516-A42149-TW/final/ 16 201123447 熟悉此項技藝者，在不脫離本發明之精神和範圍内，當可 做些許更動與潤飾，因此本發明之保護範圍當視後附之申 請專利範圍所界定者為準。 【圖式簡單說明】 第1圖至第2圖為習知半導體結構的剖面圖。 第3圖至第11圖顯示本發明一實施例半導體結構的製 程剖面圖。 φ 第12圖顯示本發明另一實施例半導體結構的上示圖。 第13圖為本發明具有17個P型埋環的結構實施例的 分析圖。 第14圖則為不具有P型埋環的典型結構的分析圖。 【主要元件符號說明】 109〜導電層；110〜導電層；111〜導電層（或汲極電極）； 11.2〜電極層（或閘極電極層）；113〜P+型擴散區；114〜N+型 擴散區（或N+型擴散源極）；115-P型井區；116~?_型基底； ® 117〜N型井區；118〜P型埋環；119〜N+型擴散區（或N+型擴 散汲極）；120〜介電層；121〜罩幕層；121A〜二氧化矽層； 121B〜光阻層；123〜漂移區；124〜上部漂移區；125〜下部 漂移區；128〜通道區；140〜介電層（或局部場氧化介電結 構）；150〜指末端；152〜指末端；154〜指部；401〜P型基底； 402〜P型區；406〜N+型汲極區；408〜P型區；413〜N型井； 415〜通道區。 98009/0516-A42149-TW/fmal/ 17Small p-type buried ring; can also use the above-mentioned = and the direction of the pole gradually decreasing PS buried ring C = at the end of the finger i52:, the wheel - and the pole-gradient P-type buried 顼 ^ Dn _ Wang Shen TT^mc, ^ Therefore, the present invention has the function of inserting a knot and can increase the amount of components (4). In addition, the present invention has different buryings in different areas and can be formed by using only one photomask for lithography and implanting, so that the method is simple and does not impose too much additional burden. In an embodiment, the breakdown voltage of the component is greater than 800V, such as between 800V and 900V, and the on resistance is less than llOmficm2, such as between 100inQcm2 and ii〇mi2cm2. The embodiment of the present invention has the following advantages: the present invention forms a plurality of P-type buried rings which are separated from each other and whose doping profile decreases from the source to the drain in the N-type drift region of the N-channel LDMOS, which can promote the component to be turned off. The electric field distribution in the state to avoid the electric field clustering effect and increase the breakdown voltage. On the other hand, the N-type well region of the present invention can be formed with a high doping concentration, and the channel ratio of the N-type drift region is not caused by? The buried strap is reduced in size, so that the on-resistance of the device can be reduced. In addition, the p-type buried ring can be formed by using a photomask for the lithography and the implantation process, and the method is simple and does not impose a cost burden. According to the above, the present invention can simultaneously increase the breakdown voltage of the LDMOS and lower the on-resistance in a simple manner, and thus can be applied to ultra high voltage technology. The above embodiments are merely used in the examples of the present invention. For example, when discussing an embodiment of an N-channel LDMOS, another embodiment may be a P-channel LDMOS formed by a phase-conducting dopant. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of those skilled in the art, without departing from the spirit and scope of the invention, The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 2 are cross-sectional views showing a conventional semiconductor structure. 3 to 11 are process sectional views showing a semiconductor structure according to an embodiment of the present invention. φ Figure 12 shows a top view of a semiconductor structure in accordance with another embodiment of the present invention. Figure 13 is an analysis diagram of an embodiment of a structure having 17 P-type buried rings of the present invention. Figure 14 is an analysis of a typical structure without a P-type buried ring. [Main component symbol description] 109~ conductive layer; 110~ conductive layer; 111~ conductive layer (or drain electrode); 11.2~ electrode layer (or gate electrode layer); 113~P+ type diffusion region; 114~N+ type Diffusion zone (or N+ type diffusion source); 115-P type well zone; 116~?_ type substrate; ® 117~N type well zone; 118~P type buried ring; 119~N+ type diffusion zone (or N+ type Diffusion drain); 120~ dielectric layer; 121~ mask layer; 121A~ erbium oxide layer; 121B~ photoresist layer; 123~ drift region; 124~ upper drift region; 125~ lower drift region; Area; 140~ dielectric layer (or local field oxide dielectric structure); 150~fin end; 152~fin end; 154~fin; 401~P type substrate; 402~P type area; 406~N+ type bungee Zone; 408~P-zone; 413~N-well; 415~channel zone. 98009/0516-A42149-TW/fmal/ 17