TW201123426A - Buried bit line process and scheme - Google Patents

Abstract

The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a pair of insulating layers isolated with each other disposed in a bottom of the trench, wherein the pair of insulating layers is adjacent to a first side and a second side of the trench, respectively. A pair of conductive layers isolated with each other is formed in the trench with laminating on the pair of insulating layers, respectively. The pair of conductive layers is adjacent to a first side and a second side of the trench, respectively. A pair of diffusion regions is formed in a portion of the substrate, wherein the pair of diffusion regions is adjacent to the pair of conductive layers, respectively.

Description

201123426 VI. Description of the Invention: [Technical Field] The present invention relates to a dynamic random access memory cell and a method of fabricating the same, and more particularly to a buried bit line of a dynamic random access memory cell And its production method. [Prior Art] Dynamic Random Access Memory (Dynamic Randpm Access)

Memory, DRAM) is a kind of volatile memory (v〇latile memory). The main principle of operation is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 〇 to store data. To achieve high density requirements, the most effective method at present is to reduce the size of the wafer by reducing the manufacturing process and using cell design techniques. Another way to reduce the size of the second king is to achieve a more efficient array architecture. After a few consecutive years, the storage technology usually becomes a certain unit layout limitation. A lot of work is needed to reduce the most etched etch. Therefore, there is a need for a manufacturing method. BACKGROUND OF THE INVENTION In view of the above, an embodiment of the present invention provides a & & fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi fi a spacer layer is formed on the bottom surface of the trench, wherein the pair of edges and the insulating layer respectively adjoin a first sidewall of the trench and an opposite second galvanic knife, a pair of each other 9095-A34489TWF 4 201123426 a separate conductive layer formed in the trench and stacked on the pair of insulating layers, wherein the pair of conductive layers respectively abut the first sidewall and the second sidewall of the trench; a pair of diffusion regions And formed in a part of the substrate adjacent to the pair of conductive layers. Another embodiment of the present invention provides a method for fabricating a buried bit line, comprising: providing a substrate; forming a first trench in the substrate, having a first sidewall and an opposite second sidewall; Forming a first insulating layer in the first trench, covering a bottom surface of the trench and a portion of the first and second sidewalls; forming a pair of diffusion regions in a portion of the substrate adjacent to the first and second sidewalls; Forming a conductive layer in the first trench and covering the sidewall of the pair of diffusion regions; forming a pair of insulating spacers on the conductive layer, respectively covering the first and second sidewalls; The conductive layer covered by the insulating spacer and the first insulating layer therebelow until the substrate is exposed to form a second trench in the conductive layer and the first insulating layer therebelow; removing the pair of insulating layers 〇 〇 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施In the drawings or the description of the specification, the same drawing numbers are used for the similar or identical parts. Also, in the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and The examples are only intended to disclose the specific manner in which the present invention is used, and is not intended to limit the invention. Figure la is a perspective view showing a dynamic random access memory cell (hereinafter referred to as DRAM cell) 600 according to an embodiment of the present invention. Figure lb is an equivalent circuit diagram of the la diagram. In one embodiment of the invention, the DRAM 600 has a cell size of 4F2 (where F is the minimum lithography process size, or unit size) of a DRAM cell 600. A vertical transistor 300, a buried bit line (BL) 500, and a word line (WL) 308 of the above DRAM 6 〇 0 are disposed in a substrate 200 as shown in FIG. . As shown in FIGS. 1a and 1b, the DRAM 600 includes a substrate 200. A vertical transistor 300 is formed in the substrate 200. The vertical transistor 300 has a lower stacked drain region 314, an intermediate layer channel region 316, and an upper source region 318, respectively, stacked vertically. Additionally, the vertical electrical body 300 has at least one vertical sidewall 302. A word line 308 is formed in the substrate 200 along a first direction 322, wherein the word line 3〇8 is disposed on the vertical sidewall 302 of the vertical transistor 300 and serves as a gate of the vertical transistor 3〇〇. pole. An insulating layer 306 is disposed between the word line 308 and the vertical transistor 300 to serve as a gate insulating layer of the vertical transistor 300. As shown in the first & lb and lb diagrams, the DRAM 600 further includes a pair of buried bit lines 5A and 500B spaced apart from each other, and a second direction 32〇 different from the first direction 322 is formed on the substrate 200. A first trench 210 [and under the vertical transistor] buried bit 7G lines 5G0A and 50GB electrically contact the drain regions 3M of the pair of vertical transistors 300, respectively. In addition, the DRAM_ further includes a capacitor 3!2' electrically contacting the vertical transistor 3〇〇_(four) 318. The materials are respectively located in the adjacent first trenches 21〇 and the adjacent buried bit lines can be electrically connected by a single bit contact 330 (BL contact) in the case of n, (10)

9095-A34489TWF 6 201123426 The buried bit line 5〇〇B on the right side of the first trench 210 on the left side and the buried bit line 5〇〇A on the left side in the first trench 210 on the right side can be contacted by the bit 330 (BL contact) is electrically connected together. Fig. 1c is a cross-sectional view taken along the line A-A' of Fig. 1a, showing a cross-sectional view of the buried bit line 500 of the DRAM 600 according to an embodiment of the present invention. As shown in FIG. 1c, 'the buried bit line 500 includes a pair of insulating layers 238a and 238b spaced apart from each other, formed on the bottom surface 208 of the first trench 210, wherein the pair of insulating layers 238a and 238b respectively abut the above a first sidewall and a second sidewall 207 of the trench; and conductive layers 242a and 242b spaced apart from each other are formed in the first trench 210 and stacked on the pair of insulating layers 238a and 238b, wherein the pair of conductive layers 242a and 242b respectively abut the first sidewall 206 and the second sidewall 207 of the first trench 210; and a pair of diffusion regions 230a and 230b' are respectively formed adjacent to the pair of conductive layers Portions of 242a and 242b are in the above substrate 200. As shown in Fig. 1c, the insulating pad layer 236, the first insulating layer 238a, the barrier layer 240a, the conductive layer 242a, and the diffusion region 230a are structured to bury the bit line 500A. The insulating pad layer 236, the first insulating layer 238b, the barrier layer 240b, the conductive layer 242b, and the diffusion region 230b constitute a buried bit line 500B. As shown in Fig. 1c, the buried bit lines 500A and 500B are spaced apart from each other and are symmetrical to each other. 2 to 18 are schematic cross-sectional views showing a method of manufacturing the buried bit line 500 of the DRAM 600 according to an embodiment of the present invention. The buried bit line 500 of the embodiment of the present invention is formed by forming two buried bit lines of two different bits in one trench. For the sake of convenience of explanation, the manufacturing method of the buried bit line 5〇〇 displays two at the same time. As shown in Fig. 2, first, a substrate 2 is provided. 9095-A34489TWF 7 201123426 In an embodiment of the invention, the substrate 200 can be a germanium substrate. In other embodiments, germanium telluride (SiGe), bulk semiconductor, strained semiconductor, and combination may be utilized.

A semiconductor semiconductor, a silicon on insulator (SOI) or other conventional semiconductor substrate is used as the substrate 200. The substrate 200 can be implanted with a p-type or n-type dopant to change its conductivity type for design needs. In an embodiment of the invention, the substrate 2〇ρ can be implanted with a p-type dopant. Then, a first hard mask layer 2, a second hard mask layer 202, and a third hard mask layer are sequentially formed on the substrate 200 by a deposition process such as chemical vapor deposition (CVD). 2G3, as an etch hard mask for the subsequent formation of the trench. In one implementation of the present invention, the first hard mask layer 201 may be made of nitrogen cut (legs) having a thickness between the legs of HKhnn~2000. The material of the second hard mask layer may be carbon carbide, which may be between 5Gnm and nmm, and the third hard mask layer 203 may be formed by oxygen cutting and nitrogen cutting, between 50nm and 500nm. . After /; 丨孓 /A: The hard mask layer 203 sequentially forms an anti-reflective layer (ARC) 204 and a patterned first blocking ^ ^ 位置 position. Shield 205, and define the shape removal of the subsequent groove = the above can be said = ^ ": first & layer shift as a mask, (AR_ and the opening of the second layer 2 〇 3. Then 'available The above-mentioned hard mask having the mask layer tearing and engraving the second hard mask layer

9095-A34489TWF 201123426 The second hard mask layer 2〇2 exposed from the opening 250. During the etching process, the patterned photoresist layer 205, the underlying anti-reflective layer (ARC) 2〇4, and the third hard mask layer 203 are lost. Referring to Figure 4, after the anisotropic etching process described above, the opening 250 is passed through the second hard mask layer 202. Then, the second hard mask layer 202 having the opening 250 can be reused as a hard mask for etching the first hard mask layer 2〇1, and an anisotropic etching process is performed to remove the exposed from the opening 25〇. The first hard mask layer 201 is formed. After the etching process described above, the opening 250 is passed through the first hard mask layer 2〇1. After that, referring to FIG. 5, the first hard mask layer 201 having the opening 25 turns is used as a hard mask for etching the substrate 2, and an anisotropic etching process is performed to form a first layer in the substrate 200. A trench 21 is formed by a sidewall 206 and an opposite second sidewall 2〇7. In an embodiment of the invention, the depth d of the first trench 210 may be between 15 〇 nm and 5 〇〇 nm. The second hard mask 202 can then be removed by plasma ashing.曰 Next/Please refer to FIG. 6, which may utilize a thin film deposition process such as chemical vapor deposition (CVD). Compliance with the first sidewall 206, the second sidewall 2〇7 of the first trench 21() An insulating pad layer 21 is formed on the bottom surface 2〇8. In an embodiment of the invention, the insulating pad layer 211 may be made of yttrium oxide (Si〇2) having a thickness of between 5 nm and 2 nm. Then, a thin film deposition process such as low pressure chemical vapor deposition (LPCVD) can be used to comprehensively form a first-insulating material lift 212' and fill the first trench 21'. In a second embodiment of the invention, the first insulating material 212 may be nitrided. After that, please refer to Figure 7 for hydrogen training (legs) and hydrogen carbonization.

9095-A34489TWF 201123426 The object (CxHyFz, x=0~6, y=0~3, z=0~8) is used as a button engraving agent to carry out a process of engraving, removing the upper part of the substrate 200 and partially located in the first ditch. The first insulating material 212 in the trench 210 forms a first insulating layer 212a. In an embodiment of the invention, the height h of the first insulating layer 212a is less than one-half of the depth d of the first trench 210, and the value may be, for example, between 20 nm and 100 nm. In an embodiment of the invention, the height h! of the first insulating layer 212a determines the location at which the diffusion region is subsequently formed. Next, referring to Fig. 8, the insulating underlayer 211 which is not covered by the first insulating layer 212a can be removed by the wet etching method f to form the insulating pad layer 211a. As shown in Fig. 8, the insulating underlayer 211a formed after the wet etching has a top surface lower than the top surface of the first insulating layer 212a. Then, referring to Fig. 9, a diffusion source material 214 containing a dopant can be formed in a comprehensive manner by a thin film deposition process such as chemical vapor deposition (CVD), and filled in the first trench 210. As shown in Fig. 9, the diffusion source material 214 covers the top surface of the first insulating layer 212a. Thereafter, referring to FIG. 10, an etching process may be performed to remove the diffusion source material 214 above the substrate 200 and partially located in the first trench 210 to form a diffusion source layer 214a covering a portion of the first sidewall 206 and Part of the second side wall 207. In an embodiment of the invention, the diffusion source layer 214a may be a conductive layer doped with a polysilicon layer, such as an arsenic doped polysilicon layer (As_doped po) y), and the thickness T determines the height of the subsequently formed diffusion region. In an embodiment of the invention, the thickness T! of the diffusion source layer 214a may be between 5 nm and 100 nm. Next, referring to Fig. 11, an annealing process is performed to diffuse the doping f of the diffusion source layer 214a into the pad substrate 200 9095-A34489TWF 10 201123426 adjacent to the diffusion source layer 214a to form symmetric diffusion regions 230a and 230b. As shown in Fig. 11, the diffusion region 230a extends from the first sidewall 206 into the portion of the substrate 200, and the diffusion region 230b extends from the second sidewall 207 into the portion of the substrate 200. As shown in FIG. 11, the top surfaces 220 of the diffusion regions 230a and 230b may be aligned with or above the top surface 216 of the diffusion source layer 214a, respectively, while the bottom surfaces 222 of the diffusion regions 230a and 230b may be aligned with or below the diffusion source, respectively. The bottom surface 218 of layer 214a. Then, an etching process can be performed to remove the diffusion source layer 214a. In an embodiment of the invention, the diffusion regions 230a and 230b can be used as a diffusion junction of the bit line and the vertical transistor, and the subsequently formed conductive layer and the diffusion regions 230a and 230b are electrically connected. To the drain of the vertical transistor. In an embodiment in which the conductivity type of the substrate 200 is p-type, the conductivity types of the diffusion regions 230a and 230b may be n-type. The conductivity types of the diffusion regions 230a and 230b depend on the conductivity type of the dopant of the diffusion source layer 214a, but are not limited to this embodiment. Then, please refer to FIG. 12, a deposition method of atomic layer deposition (ALD) can be used to form a barrier layer 224 in the first trench 210 and cover the first insulating layer 212a and the diffusion regions 230a and 230b. Side wall. In an embodiment of the invention, barrier layer 224 may comprise titanium, titanium nitride, or a combination thereof. In the present embodiment, the barrier layer 224 may be a stacked structure of tantalum and titanium nitride, and its total thickness may be between 4 nm and 20 nm. Thereafter, a conductive material 226 can be formed in a comprehensive manner by, for example, a chemical vapor deposition (CVD) deposition method, and filled in the first trench 210. In the present embodiment, the electrically conductive material 226 may comprise a metal such as tungsten. Next, referring to FIG. 13, an etching process can be performed to remove the conductive material 226 above the substrate 200 and partially located in the first trench 21?

9095-A34489TWF 201123426 and barrier layer 224 to form a conductive layer 226 & and a barrier layer 224a in the first trench 210. As shown in Fig. 13, the conductive layer 2 covers the sidewalls of the diffusion regions 232 and 230b. In one embodiment of the invention, the thickness of the conductive layer 226a may be determined by the depth of the first trench 210 as shown in Fig. $, which may be, for example, between 30 nm and 200 nm. Alternatively, in another embodiment, the diffusion source layer 214a as shown in Fig. u can be directly used as the conductive layer, so that the process steps of the 12th to 13th steps are not required. The first to fourth embodiments show the manner in which two bit lines are formed in the first trench 210. Then, referring to FIG. 14, a thin film deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) may be utilized to form a second insulating material 232 in the first trench 210, and The top surface of the conductive layer 226a is covered. In an embodiment of the present invention, the second insulating material 232 may be made of yttria, and the thickness of the dicing material 3 may be between 5 nm and 3 〇 nm. Thereafter, referring to FIG. 15, an etching process may be performed to remove the second insulating material 232 above the substrate 200 and partially located in the first trench 21A until the conductive layer 226a is exposed to the conductive layer 226 & A pair of insulating spacers 232a and 232b are formed. As shown in Fig. 15, the insulating spacers 232a and 232b cover the first side wall 2〇6 and the second side wall 2〇7, respectively. In the embodiment of the present invention, the spacing S of the insulating spacers 232a and 232b from each other may be between one third and one quarter of the width of the first trench 210. Next, referring to FIG. 16, an anisotropic etching process may be performed using the insulating spacers 232a and 232b as an etched hard mask to remove the conductive layer 226a not covered by the insulating spacers 232a and 232b. The first insulating layer 212a' under it until the substrate 200 is exposed (or from the first trench 21)

9095-A34489TWF 201123426 Face 208 removes a portion of the substrate 200). As shown in FIG. 16, after the above-described anisotropic button etching process, a pair of spaced apart insulating pad layers 236a and 236b and a pair of spaced apart first insulating layers are formed self-aligned. 238a and 238b, a pair of spaced apart barrier layers 240a and 240b and a pair of spaced apart conductive layers 242a and 242b' and formed between conductive layers 242a and 242b and underlying first insulating layers 238a and 238b A second trench 234. As shown in FIG. 16, the first insulating layer 238a and the conductive layer 242a abut the first sidewall 206 of the first trench 210, and the first insulating layer 238b and the conductive # layer 242b abut the second sidewall of the first trench 210. 207. After the above process, the buried bit lines 5A and 5B are separated from each other in the first trench 21A on the left and right sides of FIG. 16, respectively, wherein the buried bit line 500A includes The insulating pad layer 236, the first insulating layer 238a, the barrier layer 240a, the conductive layer 242a and the diffusion region 230a, the buried bit line 5B includes an insulating pad layer 236, a first insulating layer 238b, and a barrier layer 24〇b , a conductive layer 24 沘 and a diffusion region 230b. As shown in FIG. 16, the buried bit line 5 located on the left first trench 2i and adjacent to the second sidewall 207 and the buried bit located in the first trench 210 on the right and adjacent to the first sidewall 2〇6 The line $(8)a can be electrically connected together via a bit contact 33〇 (BL c〇ntact) as shown in FIG. Then, the reference is made to the first sheet of the criminal film deposition process. The king-return third insulating material 244 is filled in the first first trench 2 second trench 234. In the f & 9 & month embodiment of the present invention, the third insulating material 244 can be used as a high-density electrical vapor deposition (HDP-CVD) method and a coated glass (0G) or a (four) sub-layer. The deposition method money ♦, the thickness of the third insulating material 244 can be

9095-A34489TWF 201123426 Between 10nm~lOOnm. Thereafter, referring to Fig. 18, an etching process may be performed to remove the third insulating material 244 above the substrate 200 and partially in the first trench 210 to form an insulating spacer layer 244a. The insulating spacer layer 244a is used to electrically insulate the buried bit lines 500A and 500B. The first hard mask layer 201 can be removed by a subsequent planarization process such as chemical mechanical polishing (CMP) to form the buried bit line 500 of an embodiment of the present invention as shown in FIG. After the above process, the method of manufacturing the buried bit line 500 of the DRAM 600 of the embodiment of the present invention is completed. An embodiment of the present invention provides a buried bit line 500, such as a DRAM, and a method of fabricating the same, wherein a pair of insulating spacers are used as an etched hard mask to self-align two symmetrical layers in a trench simultaneously The buried bit line' process is relatively simple. Also, the buried bit line on one side of a trench is electrically connected to the buried bit line on the adjacent side of the adjacent trench by a bit contact (BL contact). Further, the position of the diffusion region of the buried bit line 5 is determined by the height hi of the first insulating layer 212a located at the bottom of the first trench 210. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application. [Simple description of the map]

The third country shows a perspective view of a dynamic random cell unit in accordance with an embodiment of the present invention. Heart 11 9095-A34489TWF 14 201123426 The lb diagram is the equivalent circuit diagram of the first diagram. Figure lc is a cross-sectional view taken along line A-A' of the first drawing showing the buried bit line of the DRAM cell of an embodiment of the present invention. Figs. 2 to 18 are schematic cross-sectional views showing a method of manufacturing a buried bit line of a dynamic random access memory cell according to an embodiment of the present invention. [Main component symbol description] 200 to substrate; _ 201 to first hard mask layer; 202 to second hard mask layer; 203 to third hard mask layer; 204 to anti-reflection layer; 205 to ~ patterned light Resistor layer; 206~first sidewall; 207~second sidewall; 208, 218, 222, 229~ bottom surface; • 210~ first trench; 211, 211a, 236a, 236b~ insulating pad; 212~ first insulation Material; 212a, 238a, 238b~ first insulating layer; 214~ diffusion source material, 214a~ diffusion source layer; 230a, 230b~ diffusion region; 216, 220, 228~ top surface; 224, 224a, 240a, 240b~ resistance Barrier layer

9095-A34489TWF 201123426 226 ~ conductive material; 226a, 242a, 242b ~ conductive layer; 232 ~ second insulating material; 232a, 232b ~ insulating spacer; 234 ~ second trench; 244 ~ third insulating material; 244a ~ insulation Separation layer; 250~open; d~depth; h1~南度; T], τ2, τ3~thickness; W~width; S~pitch; 3 00~ vertical transistor, 302~vertical sidewall; 3 06~insulation Layer, 308 ~ word line; 312 ~ capacitor; 314 ~; "and pole area, 316 ~ channel area; 318 ~ source area, 320 ~ first - direction; 322 ~ second direction; 330 ~ bit contact; 500 Α, 500 Β ~ buried bit line; 9095-A34489TWF 16 201123426 600 ~ dynamic random access memory.

9095-A34489TWF 17

Claims (1)

201123426 VII. Patent application scope: 1. A buried bit line disposed in a trench of a substrate, comprising: a pair of insulating layers spaced apart from each other, formed on a bottom surface of the trench, wherein the pair of insulating layers Adjacent to a first sidewall and an opposite second sidewall of the trench; a pair of spaced apart conductive layers are formed in the trench and stacked on the pair of insulating layers respectively, wherein the pair of conductive layers respectively The first sidewall and the second sidewall adjacent to the trench; and a pair of diffusion regions ' are respectively formed in a portion of the substrate adjacent to the pair of conductive layers. 2. The buried bit line of claim 1 further comprising an insulating spacer layer between the pair of conductive layers and extending from the bottom of the trench to a portion of the substrate. 3. The buried bit line of claim 2, wherein the insulating spacer layer covers a top surface of the pair of conductive layers. 4. The buried texel of claim 2, wherein the insulating spacer layer comprises bismuth glass or cerium oxide. 5. The buried bit line of claim 1, further comprising a barrier layer disposed between the pair of insulating layers and the pair of guiding layers. 6. The buried bit line of claim 5, wherein the barrier layer covers a sidewall of the diffusion region. 7. The buried bit line of claim 5, wherein the barrier layer comprises titanium, titanium nitride or a combination thereof. 8. The buried bit line of claim 1, wherein the pair of diffusion regions are aligned with or above a top surface of the pair of conductive layers. 9. The buried bit line of claim 1, wherein the bottom surface of the pair of diffusion regions is aligned with or below the bottom surface of the pair of conductive layers. 10. The buried bit line of claim 1, further comprising a pair of insulating pads disposed between the pair of insulating layers and the trenches. 11. The buried bit line of claim 1, wherein the conductive layer comprises a metal or polycrystalline stone. 12. The buried bit line of claim 10, wherein the insulating layer or the insulating layer comprises an oxide, a nitride or a combination thereof. 13. The buried bit line of claim 1, wherein the insulating layer has a height less than one-half the depth of the trench. A method for manufacturing a buried bit line, comprising the steps of: providing a substrate; forming a first trench in the substrate, having a first sidewall and an opposite second sidewall; Forming a first insulating layer in the trench covering the bottom surface of the trench and a portion of the first and second sidewalls; • forming a pair of diffusion regions in the substrate adjacent to the first and second sidewalls; Forming a conductive layer in the first trench and covering sidewalls of the pair of diffusion regions; forming a pair of insulating spacers on the conductive layer, and covering the first and second sidewalls respectively; The conductive layer covered by the insulating spacer and the first insulating layer therebelow until the substrate is exposed to form a second trench in the conductive layer and the first insulating layer therebelow; and 9095-A34489TWF 19 201123426 Remove the pair of insulating spacers. 15. The method of manufacturing a buried bit line according to claim 14, wherein the step of forming the diffusion region further comprises: covering the first insulating layer with a diffusion source layer containing a dopant, which covers Part of the first and second sidewalls; = performing an annealing process 'diffusing the dopant of the diffusion source layer into a portion of the county plate adjacent to the diffusion source layer' to form the diffusion region; and privately removing the diffusion source layer. The method of forming a buried bit line as described in claim 14 wherein the step of forming the first insulating layer is more compliant with the ash. An insulating pad layer is formed on the first and second side walls and the bottom surface of the trench. The method for forming the first insulating layer in the green method of the buried bit line according to claim 16 further includes: forming a comprehensive-first insulating material and filling the trench; The ^"back (four) process 'removs the W-insulating material above the substrate and partially in the shallow trench to form the first insulating layer. After the step of forming the first insulating layer in the manufacturing method of the buried bit line described in Item 17 of the special silk fence, the method further comprises: an insulating (four) engraving process to remove the layer not covered by the first insulating layer Method ^7 Please refer to the side wall of the buried bit line described in Item 14 (4) and the step of conforming to the field bit line of the method described in item 19 of the method, and forming the conductive layer. The method includes: ^〇95-A34489TW 20 201123426 comprehensively forming a conductive material and filling the trench; and performing an etching process to remove the conductive material and the barrier above and partially in the trench a layer to form the conductive layer. 21. The method of fabricating a buried bit line of claim 19, wherein a top surface of the conductive layer is aligned with or below a plane of the pair of diffusion regions. 22. The method of manufacturing a patent range a π — π king wind position ' line, wherein the step of forming a pair of insulating spacers further comprises: compliant forming a second insulating material; and performing a process of removing the last name, removing The second insulating material is over the substrate and partially located in the thin trench until the conductive interlayer insulating spacer is exposed. ~ Take the screening method 'Where the pair is absolutely』:: The manufacturing of the wall-level bit line is three-to-four-points apart from each other by the width of the groove 24. As in the patent application, the 14th method, In addition to the step of forming the embossed bit line described above, the step of forming the H-gap wall further includes: a trench; and a rim material, and filling the first and second trenches for etching back The process of moving the second insulating material in the trench * is read over the substrate and partially at the 25th. as in the scope of the patent application to form an insulating spacer. The method wherein the fabrication of the buried bit line of the insulating spacers covers the top surface of the conductive layer. 9095-A34489TWF