TWI236139B - Dynamic random access memory cell and fabricating method thereof - Google Patents
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Abstract
Description
123611* 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種記憶體元件及其製造方法,且特 別是有關於一種動態隨機存取記憶胞(Dynamic Random Access Memory Cell ’ DRAM Cell)及其製造方法。 【先前技術】 隨著現今電腦微處理器(Microprocessor)的功能愈來愈 強,軟體所進行的程式與運算也愈來愈龐大。因此,記憶 體的製作技術已成為半導體產業重要的技術之一。 一般來說,記憶體可依其儲存資料的型態而分為揮發 性記憶體與非揮發性記憶體。而動態隨機存取記憶體 (Dynamic Random Access Memory,DRAM)即屬於一種揮 發性記憶體,且其係由多數個記憶胞構成。而每一個記憶 胞係由一主動元件與一電容器所構成,且每一個記憶胞係 藉由子元線(Word Line,WL)與位元線(Bit Line,BL)彼此 電性連接。 另一方面,動態隨機存取記憶體依其電容器的結構主 要可以分成1¾種形式,其—為具有堆4式電容器(stack Capacitor)之動態隨機存取記憶體,另一則為具有深溝渠式 電容器(Deep Trench Capacitor)之動態隨機存取記憶體。由 於具有料渠式電容器之動祕齡取記 式電容器是形成於基底之中,因此她於具有堆疊Γΐί 器之動態_魏記龍,在㈣上較不易產生平坦化的 問題’因而有利於小尺寸之記憶體元件的製作。不過,當 123611- 元件尺寸愈來愈小時,具有深溝渠式電容器之動態隨機存 取記憶體在製作上也同樣遭遇到愈來愈多的問題。 圖1A至圖1D是繪示習知的一種具有深溝渠式電容器 之動恶卩远機存取§己憶體的製造流程剖面示意圖。請參照圖 1Α ’此製造方法係先提供基底1〇〇,並於基底1〇〇表面依 序形成圖案化之墊層102與罩幕層1〇4。接著,利用圖案 化之墊層102與罩幕層1〇4作為蝕刻罩幕,於基底1〇()1; 形成深溝渠106。然後,於深溝渠1〇6底部之基底1〇〇中 形成下電極108,並且於深溝渠106底部依序形成電容介 電層110與多晶石夕層112。之後,於罩幕層1〇4與未被多 晶矽層112覆蓋之深溝渠1〇6表面形成領氧化層114。 繼之 睛麥照圖1Β,進行非等向蝕刻製程,移除位於 罩幕層1G4與多㈣層112頂部的領氧化層114,而僅 下位於深溝渠106側壁上之領氧化層114a。接著,於 渠106中填入多晶矽層116。 4 =’請參照圖1C ’移除深溝渠106财卜及位於深溝 :德,銘ίΓ分的多晶梦層116’而形成多晶石夕層u6a。 护成fit被多晶石夕層腕覆蓋之領氧化層114a,而 夕。繼之’於深溝渠106中填入多晶石夕声 墙:二曰曰矽層112、116續118係彼此電性連接,二 二,1D’進行一熱製程,以使多晶仰 中之摻負擴散至基底1〇〇中, 曰 —st,BS),且此埋入式穆雜》== 1236139 13504twf.doc 離結帶窗口⑽wind°w)122。錢,進行淺溝渠隔 溝渠隔離多㈣層118之基底⑽中形成淺 離結構12W μ亚且形成多晶石夕層隐,且淺溝渠隔 1〇2 μ ,、疋義出主動區(未繪示)。之後,在移除墊層 構126,並f 104後、、’於主動區之基底100上形成開極結 128 m、於淺溝渠隔離結構124上形成另一閘極結構 >成相對應之源極區13加與汲極區i3〇b,i 極區^3%係藉由埋入式摻雜帶12〇與上電極電性連接中。及 其埋^摻3=3^所得之動態隨機存取記憶體, 存取記1上的尺寸大小,係牽動著動態隨機 尺寸太Γ _丨轉效"b。舉例來說’紐人式摻雜帶窗口 入Μ件漏電流的問題。另一方面,若埋 之尺寸太小’則會因埋入式推雜帶與上電極 埋入m此’在製程中, 埋入式摻雜帶窗口的尺寸 人 =;】否具有良好之_能_=騎機存 有鑑於此,本發明的目的就是 取記憶胞的製造方法,以解決f 一=:=,存 寸過大或過小所產生的問題。 I、f ilj 口尺 本發明的再一目的是接供另— 的製造方法,以解決習知因埋入幾存取記憶胞 過小所產生的_。 #_窗口尺寸過大或 本發明的又-目的是提供一種動態隨機存取記憶胞, 12361說一 以解決習知因埋入式摻雜帶 問題。 口尺寸過大或過小所產生的 此 ,成於基底中之—_==== 成ΐ在此深溝渠底部之基底中係形 。,且在淥溝渠表面係形成有電容介電層。铁 2於深溝渠底部填人第—導電層。接著,: 導電層覆蓋之電容介電層。之後,於未被第—導電層【蓋 之洙溝渠側壁上形成領氧化層。繼之,於深溝渠中填入 二導電層’且覆蓋第-導電層。然後,於第二導電層之一 側的基底中形成溝渠,且此溝渠係暴露出部分基底二第二 導電層。接著,於溝渠中形成半導體條狀物,且半導體條 狀物係暴露出部分溝渠底部的基底,其中半導體條狀物的 一端係與第二導電層鄰接,而另一端係與基底鄰接。之後, 於基底上形成閘介電層,以覆蓋裸露之半導體條狀物與基 底表面。繼之,於閘介電層上形成閘極,其中閘極係與$ 導體條狀物相交,且閘極所覆蓋之部分半導體條狀物係作 為通道區之用。 本發明提出另一種動態隨機存取記憶胞的製造方法, 此方法係先提供基底,且此基底上已形成有圖案化之罩幕 層與形成於基底中之一深溝渠式電容器,且此深溝渠式電 容器係由下電極、上電極、電容介電層與領氧化層所構成 而且圖案化之罩幕層係暴露出上電極。然後,於深溝渠式 1236139 n^twf.doc 電容器一側的基底中形成溝渠,且此溝渠係暴露出部分基 底與上電極。接著,於溝渠中填入一半導體材料層之後, 圖案化此半導體材料層,以形成半導體條狀物,並形成暴 露出基底的二開口,其中半導體條狀物的一端係與上電極 鄰接’而另一端係與基底鄰接。之後,於基底上形成閘介 電層’以覆蓋裸露之半導體條狀物與基底表面。繼之,於 ,介電層上形成導電層,其中導電層係與半導體條狀物相 父’且導電層所覆蓋之部分半導體條狀物係作為通道區之 用。 本發明提出一種動態隨機存取記憶胞,此動態隨機存 取=憶胞係由深溝渠式電容器與主動元件所構成。其中深 ,朱式電容器係配置於基底之深溝渠中,且深溝渠式電容 =係由下電極、上電極、電容介電層與領氧化層所構成。 其中,下電極係配置在深溝渠底部之基底中。另外,上電 極,配置在、/讀渠巾。此外,電容介電層係配置在深溝渠 ^陳面與上電極之間。另外,領氧化層係配置在未有電 谷介電層的深溝渠側壁,且位於上電極與基底之間。此外, 置於基底之溝渠中’且主動元件係與深溝渠 電;、Ξ且此主動元件係由半導體條狀物、問介 與—摻雜區所構成。其中,半導體條狀物係配 的美^ ’且此_化之通道層係暴露出部分溝渠底部 半導體條狀物的—端係與基底鄰接,而另-此外,問介電層 閘極係配置在閘介電層上,且與半導體條123611 * IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a memory element and a method for manufacturing the same, and more particularly to a dynamic random access memory cell (DRAM cell). And its manufacturing method. [Previous Technology] With the increasingly powerful functions of today's computer microprocessors, the programs and calculations performed by software have become more and more huge. Therefore, the manufacturing technology of memory has become one of the important technologies in the semiconductor industry. Generally speaking, memory can be divided into volatile memory and non-volatile memory according to the type of data it stores. The dynamic random access memory (DRAM) is a kind of volatile memory, and it is composed of a plurality of memory cells. Each memory cell line is composed of an active element and a capacitor, and each memory cell line is electrically connected to each other through a word line (WL) and a bit line (BL). On the other hand, according to the structure of the capacitor, the dynamic random access memory can be mainly divided into 1¾ forms, which is a dynamic random access memory with a stack capacitor, and the other is a deep trench capacitor. (Deep Trench Capacitor). Since the moving secret type capacitor with the channel type capacitor is formed in the substrate, her dynamics with stacked Γΐί_Wei Jilong is less likely to produce a flattening problem on the cymbal ', which is conducive to small size Production of memory components. However, as 123611-components become smaller and smaller, the dynamic random access memory with deep trench capacitors also encounters more and more problems in the production. FIGS. 1A to 1D are schematic cross-sectional views illustrating a manufacturing process of a conventional memory device with a deep trench capacitor and a remote memory access device. Please refer to FIG. 1A. This manufacturing method first provides a substrate 100, and sequentially forms a patterned pad layer 102 and a cover layer 104 on the surface of the substrate 100. Then, the patterned pad layer 102 and the mask layer 104 are used as an etching mask to form a deep trench 106 on the substrate 10 () 1; Then, a lower electrode 108 is formed in the substrate 100 at the bottom of the deep trench 106, and a capacitive dielectric layer 110 and a polycrystalline silicon layer 112 are sequentially formed at the bottom of the deep trench 106. Thereafter, a collar oxide layer 114 is formed on the surface of the mask layer 104 and the deep trench 106 which is not covered by the polysilicon layer 112. Next, according to FIG. 1B, an anisotropic etching process is performed to remove the collar oxide layer 114 located on top of the mask layer 1G4 and the multi-layer layer 112, and only the collar oxide layer 114a located on the side wall of the deep trench 106 is removed. Next, a polycrystalline silicon layer 116 is filled in the trench 106. 4 = ’Please refer to FIG. 1C’ remove the deep trench 106 and the polycrystalline dream layer 116 ′ located in the deep trench: German, German, and German to form a polycrystalline evening layer u6a. The protective oxide layer 114a covered by the polycrystalline stone wrist is protected. Followed by 'filling polycrystalline stone sound wall in deep trench 106: the silicon layers 112, 116 and 118 are electrically connected to each other, 22, 1D' is subjected to a thermal process to make polycrystalline Negative diffusion diffuses into the substrate 100, ie, -st, BS), and this buried-type impurity is equal to 1236139 13504twf.doc. Qian, the shallow trench is separated from the base of the trench isolation layer 118 to form a shallow separation structure of 12W μ sub-layers and polycrystalline stones are hidden, and the shallow trench is separated by 102 μ, and the active area is defined (not shown) Show). After removing the pad structure 126 and f 104, 'an open junction 128 m is formed on the substrate 100 in the active area, and another gate structure is formed on the shallow trench isolation structure 124> corresponding The source region 13 plus the drain region i30b, and the i-pole region ^ 3% are electrically connected to the upper electrode through a buried doped band 120. And the dynamic random access memory obtained by mixing 3 = 3 ^, the size of the access record 1 is related to the dynamic random size too Γ _ 丨 transition effect " b. For example, the problem of the leakage current of the M-type doped band window with M-pieces. On the other hand, if the buried size is too small, the size of the window of the buried doped tape will be buried due to the buried doping band and the upper electrode. In the process, the size of the buried doped band window =; In view of this, the purpose of the present invention is to take a manufacturing method of memory cells to solve the problem that f a =: =, the deposit is too large or too small. I, f ilj Caliper A further object of the present invention is to provide another manufacturing method to solve the problem of _ which is caused by the small number of embedded memory cells. #_The window size is too large or another object of the present invention is to provide a dynamic random access memory cell, 12361 said to solve the conventional problem of embedded doped bands. This is caused by the oversize or undersize of the mouth, which is formed in the base — _ ==== Formed in the base of this deep trench. A capacitive dielectric layer is formed on the surface of the trench. Iron 2 fills the first-conductive layer at the bottom of the deep trench. Next: a capacitive dielectric layer covered by a conductive layer. After that, a collar oxide layer is formed on the side wall of the trench which is not the first conductive layer. Next, a deep conductive trench is filled with a second conductive layer 'and covers the first conductive layer. Then, a trench is formed in the substrate on one side of the second conductive layer, and the trench exposes part of the substrate and the second conductive layer. Then, a semiconductor strip is formed in the trench, and the semiconductor strip exposes a part of the substrate at the bottom of the trench. One end of the semiconductor strip is adjacent to the second conductive layer, and the other end is adjacent to the substrate. Then, a gate dielectric layer is formed on the substrate to cover the exposed semiconductor stripes and the surface of the substrate. Next, a gate is formed on the gate dielectric layer, where the gate intersects with the conductor strip, and a part of the semiconductor strip covered by the gate is used as a channel region. The present invention provides another method for manufacturing a dynamic random access memory cell. This method first provides a substrate, and a patterned mask layer and a deep trench capacitor formed in the substrate have been formed on the substrate. The trench capacitor is composed of a lower electrode, an upper electrode, a capacitor dielectric layer and a collar oxide layer, and the patterned mask layer exposes the upper electrode. Then, a trench is formed in the substrate on the side of the deep trench-type 1236139 n ^ twf.doc capacitor, and the trench exposes part of the substrate and the upper electrode. Then, after filling a semiconductor material layer in the trench, the semiconductor material layer is patterned to form a semiconductor strip, and two openings are formed to expose the substrate. One end of the semiconductor strip is adjacent to the upper electrode. The other end is adjacent to the base. After that, a gate dielectric layer is formed on the substrate to cover the exposed semiconductor stripes and the surface of the substrate. Next, a conductive layer is formed on the dielectric layer, wherein the conductive layer is a semiconductor stripe 'and a portion of the semiconductor stripe covered by the conductive layer is used as a channel region. The invention proposes a dynamic random access memory cell. The dynamic random access = memory cell system is composed of a deep trench capacitor and an active element. Among them, the deep capacitor is arranged in the deep trench of the base, and the deep trench capacitor is composed of the lower electrode, the upper electrode, the capacitor dielectric layer and the collar oxide layer. The lower electrode is arranged in a substrate at the bottom of the deep trench. In addition, the upper electrode is arranged at //. In addition, the capacitor dielectric layer is disposed between the deep trench and the upper electrode. In addition, the collar oxide layer is disposed on the side wall of the deep trench without the valley dielectric layer, and is located between the upper electrode and the substrate. In addition, the active device is placed in the trench of the substrate and the active device is electrically connected to the deep trench; and the active device is composed of a semiconductor strip, an interposer, and a doped region. Among them, the beauty of the semiconductor strip system ^ 'and the channel layer system exposed part of the semiconductor strip at the bottom of the trench-the end system is adjacent to the substrate, and the other-in addition, the dielectric layer gate system configuration On the gate dielectric layer
I2361H $物相父,且閘極所覆蓋之部分半導體條狀物係作為通道 區之用此外,摻雜區係配置在與基底鄰接之部分半導, 條狀物以及_鄰狀基底巾。 料體 由於本發明之主動元件的閘極所覆蓋之部分半 5物為通道區之用,而且此半導體條狀物係與深溝渠 工電谷為之導電層(或上電極頂部)鄰接,因此不需形成埋 入式摻雜帶,即可與主動元件電性連接,從而可以解決習 知因埋人式摻雜帶窗σ尺寸過大或過小所產生的問題。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說 明如下。 、 【實施方式】 圖2是繪示依照本發明一較佳實施例的一種動態隨機 存,記憶胞的上視示意圖。圖3是圖2由14,剖面所得之 動態隨機存取記憶胞的剖面示意圖。 明同日寸參照圖2與圖3 ’本發明之動態隨機存取記憶 胞係由深溝渠式電容器2〇1與主動元件203所構成。其中, 深溝渠式電容器201係配置於基底200之深溝渠2〇6中, 且深溝渠式電容器201係由下電極208、上電極205、電容 介電層210a與領氧化層214所構成。在一較佳實施例中, 上電極係由導電層212、216所構成。此外,主動元件203 係配置於基底200之溝渠218中,且與深溝渠式電容器201 鄰接,而且此主動元件203係由半導體條狀物228b、閘介 電層230、導電層232a與摻雜區236所構成。在一較佳實 12361諡· 細例中’半導體條狀物228b的兩端更包括分別配置之延伸 部228a與延伸部228c,以構成—「H」字形的半導體層 224。 其中,深溝渠式電容器201之下電極2〇8係配置在深 溝& 206底部之基底200中。此外,導電層212係配置在 沬溝渠206底部。另外,電容介電層21加係配置在深溝渠 206底部表面與導電層212之間。此外,導電層216配置 在導電層212上,且填滿深溝渠206。另外,領θ氧化層214 係配置在導電層216與基底200之間。 此外,主動元件203之半導體條狀物228b係配置在溝 渠218中,且此半導體條狀物228b係暴露出部分溝渠218 底部的基底200,而且其延伸部228a係與導電層216鄰 接’而另一延伸部228c係與基底200鄰接。當然,在一較 佳實施例中,亦可僅在溝渠218中配置半導體條狀物 228b,而使半導體條狀物228b的兩端分別與導電層216 及基底200鄰接。另外,半導體條狀物228b及其延伸部 228a、228c的材質例如是磊晶矽或是其他合適作為通道之 半導體材料。在一較佳實施例中,除了溝渠218底部之部 分基底200會裸露出來之外,溝渠218以外之部分基底2〇〇 亦會裸露出,其係如圖2之虛線區域226所示。土一 另外,閘介電層230係配置在半導體條狀物22讣及其 延伸部228a、228c的表面。在一較佳實施例中,閘介電層 230亦配置在導電層216的頂面。 曰 此外,導電層232a係配置在部分的閘介電層上, T2361^4twf.d〇c 且與半導體條狀物228b相交,且導電層232a所覆蓋之部 分半導體條狀物228b係作為通道區207之用。其中,上方 棱跨導電層232a的半導體條狀物228b之立體示意圖如圖 4所示(圖2之局部區域233)。特別是,對於主動元件2〇3 來說,導電層232a覆蓋了半導體條狀物228b的兩側壁 234a與頂部234b這三個區域,因此可以避免因短通道效 應(Short Channel Effect)所產生的相關問題。此外,對於單 一記憶胞來說,導電層232a係作為閘極之用,而對於整個 記憶胞陣列來說,導電層232a係作為串接多個記憶胞的字 元線之用。 另外’摻雜區236配置在半導體條狀物228b的部分之 延伸部228c,以及與延伸部228c鄰接之基底2〇〇中,以 作為源極區之用。 此外,在另一較佳實施例中,此動態隨機存取記憶胞 更包括摻雜帶220配置在基底2〇〇巾,且與下電極2〇8* 接。 ’ 另外,在X-較佳實_巾,聽紐機存取記憶胞 更匕括摻雜井區222配置在部分的導電層216與相鄰之基 底200中,且溝渠218係配置於摻雜井區222中。 除此之外’在再一較佳實施例中,此動 222Ht雜帶220配置在基底中,以及摻雜= 配置在°卩分的導電層216與相鄰之基底2〇〇中。 2帶,係與下電極應鄰接。此外,摻雜井區如係 」乡雜帶220鄰接,而且摻雜井區222與摻雜帶22〇的摻 12 I236I^,doc 質型態相反。 分半其導電層(閘極)所覆蓋之部 接,從而可以解決習知因娌 T电丨王逆 小所產生的問題。α里入式推雜帶窗口尺寸過大或過 接著,明參照圖5Α至圖5Ε所誇示之太私昍龢社杳Α 態隨機存取記憶胞的“流程剖‘圖二係二 盥=本么明之動態隨機存取記憶胞的製造方法。直中, ”上述圖式標號相同者係表示相同的構件。 全面if照圖5Α ’提供一基底200 ’於基底200上 盆中,熱=層202後,於塾層202上形成罩幕層204。 Ϊ進雜^=材_如是氧切,而其形成方法例如 石夕°此外,罩幕層204之材質例如是氮化I2361H $ The phase parent, and part of the semiconductor strip covered by the gate is used as the channel region. In addition, the doped region is arranged in the semiconductor, strip and adjacent substrate towel adjacent to the substrate. Since the material covered by the gate electrode of the active device of the present invention is used for the channel area, and the semiconductor strip is adjacent to the conductive layer (or the top of the upper electrode) of the deep trench industrial power valley, It is not necessary to form a buried doped band, and it can be electrically connected to the active element, so that the conventional problem caused by the too large or too small size of the buried doped band window σ can be solved. ▲ In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows. [Embodiment] FIG. 2 is a schematic top view of a dynamic random access memory cell according to a preferred embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of the dynamic random access memory cell obtained from the section 14 in Fig. 2. Refer to FIG. 2 and FIG. 3 tomorrow. The dynamic random access memory cell of the present invention is composed of a deep trench capacitor 201 and an active device 203. The deep trench capacitor 201 is arranged in the deep trench 206 of the substrate 200, and the deep trench capacitor 201 is composed of a lower electrode 208, an upper electrode 205, a capacitor dielectric layer 210a, and a collar oxide layer 214. In a preferred embodiment, the upper electrode is composed of conductive layers 212, 216. In addition, the active device 203 is disposed in the trench 218 of the substrate 200 and is adjacent to the deep trench capacitor 201, and the active device 203 is composed of a semiconductor strip 228b, a gate dielectric layer 230, a conductive layer 232a, and a doped region. 236. In a preferred embodiment 12361 谥 · ', the two ends of the' semiconductor stripe 228b 'further include extension portions 228a and 228c, respectively, to form an "H" shaped semiconductor layer 224. Among them, the lower electrode 208 of the deep trench capacitor 201 is arranged in the substrate 200 at the bottom of the deep trench & 206. In addition, the conductive layer 212 is disposed on the bottom of the trench 206. In addition, the capacitor dielectric layer 21 is disposed between the bottom surface of the deep trench 206 and the conductive layer 212. In addition, the conductive layer 216 is disposed on the conductive layer 212 and fills the deep trenches 206. The collar θ oxide layer 214 is disposed between the conductive layer 216 and the substrate 200. In addition, the semiconductor strip 228b of the active device 203 is disposed in the trench 218, and the semiconductor strip 228b exposes a portion of the base 200 at the bottom of the trench 218, and the extension portion 228a is adjacent to the conductive layer 216 and another An extension 228c is adjacent to the base 200. Of course, in a preferred embodiment, the semiconductor strip 228b may be disposed only in the trench 218, so that both ends of the semiconductor strip 228b are adjacent to the conductive layer 216 and the substrate 200, respectively. In addition, the material of the semiconductor strip 228b and its extensions 228a, 228c is, for example, epitaxial silicon or other semiconductor materials suitable as a channel. In a preferred embodiment, in addition to a portion of the substrate 200 at the bottom of the trench 218 being exposed, a portion of the substrate 200 other than the trench 218 is also exposed, as shown by the dotted area 226 in FIG. 2. First, the gate dielectric layer 230 is disposed on the surface of the semiconductor strip 22a and its extensions 228a and 228c. In a preferred embodiment, the gate dielectric layer 230 is also disposed on the top surface of the conductive layer 216. In addition, the conductive layer 232a is disposed on a part of the gate dielectric layer, T2361 ^ 4twf.d0c and intersects the semiconductor strip 228b, and a part of the semiconductor strip 228b covered by the conductive layer 232a is used as a channel region. 207 uses. The three-dimensional schematic diagram of the semiconductor strip 228b with the upper edge crossing the conductive layer 232a is shown in FIG. 4 (partial area 233 in FIG. 2). In particular, for the active device 203, the conductive layer 232a covers the three regions 234a and the top 234b of the semiconductor strip 228b, so the correlation caused by the Short Channel Effect can be avoided. problem. In addition, for a single memory cell, the conductive layer 232a is used as a gate, and for the entire memory cell array, the conductive layer 232a is used as a character line connected in series with a plurality of memory cells. In addition, the 'doped region 236 is disposed in the extension portion 228c of the portion of the semiconductor strip 228b and in the substrate 2000 adjacent to the extension portion 228c as a source region. In addition, in another preferred embodiment, the dynamic random access memory cell further includes a doped band 220 disposed on the substrate 200 and connected to the lower electrode 208 *. In addition, in X-preferably, the memory cell is further configured to doped well region 222 is disposed in part of conductive layer 216 and adjacent substrate 200, and trench 218 is disposed in doped Well area 222. In addition, in another preferred embodiment, the movable 222Ht doped band 220 is disposed in the substrate, and the doped = conducting layer 216 disposed in ° 卩 and the adjacent substrate 200 is disposed. 2 bands, the system and the lower electrode should be adjacent. In addition, if the doped well region 220 is adjacent to the impurity band 220, and the doped well region 222 and the doped band 2220 are doped with 12 I236I ^, doc, the quality is opposite. It divides half of its conductive layer (gate) to cover the parts, which can solve the problems caused by the conventional T power 丨 Wang Ni small. The size of the window of the α-type push-in miscellaneous tape is too large or too large. The “flow chart” of the random access memory cells exaggerated with reference to FIG. 5A to FIG. 5EA. Ming Zhi's manufacturing method of dynamic random access memory cells. In the middle, "The same reference numerals in the above drawings represent the same components. A full if view is shown in FIG. 5A ′, a substrate 200 ′ is provided on the substrate 200 in a pot. After the heat = layer 202, a mask layer 204 is formed on the base layer 202.杂 进 杂 ^ = Material_If it is oxygen cutting, and its forming method is, for example, Shi Xi ° In addition, the material of the cover layer 204 is, for example, nitride
Vapor D 如是進行化學氣相沉積(C—Vapor D is a chemical vapor deposition (C-
VaporDep咖。n,CVD)製程。接著,對罩幕層綱 ,二谈影製程以及蝕刻製程,以形成圖案化之墊声20曰2 層204。然後,以圖案化之罩幕層2〇4與墊層曰2〇2 為罩幕,進行蝕刻製程,以於基底2〇〇中形成深 其中所進行之餘刻製程例如是乾式钱刻製程。/木’ 二t,在深溝渠2〇6底部之基底2〇0中形成下電極 ’下電極2_如是一_區’而其形成方法例 如疋先於㈣渠施底部之側壁形成—層摻雜絕緣層,接 twf.doc 123613§〇4 著’=珠溝渠206中填入一光阻層,然後,移除未被光阻 層覆蓋之雜絕緣層,並將光阻層移除,之後,在形成一 共,的絕緣層後,進行熱製程,域摻雜絕緣層中的摻質 擴散至基底2GG巾,繼之將絕緣層及雜絕緣層移除。在 一較佳實施例中,下電極的摻㈣態例如是 於下電極208的詳細製作係為熟知此技術者所週知,於此 不再贅述。 、 然後’在罩幕層2〇4及此深溝渠施表 電容介電層21〇。其中,電容介電層別之材= =、氮财、氮氧切或技他合狀介電材料二豆 進行熱氧化製程、化學氣相沉積製程或是 八沾ΪΪ ’於深溝帛施底部填入導電層212,並覆蓋部 :的電谷介電層210。其中’導電層212之材 夕 =石夕、摻雜多晶梦或是其他合適之導電材料,而 = 法例如是以臨場(In-Situ)摻雜離子之方式, 二=成方 :於基底上形成-層摻雜多晶韻後 以外以及深溝渠2〇6頂部之部分的捧雜多曰二溝木 形成之。其中,摻雜多晶矽層的移除方法 曰9而 ,製程或渔式侧製程。另外,除了臨場摻 式之外,摻雜多晶韻的形成方法還可以4離子之方 相沈積製程日夺,同時通入含有摻質之反應進行化學氣 繼之,請參照圖5Β,移除未被導電而形成之。 介電層210,以形成電容介電層21〇a。^ 覆蓋之電容 ,、中,部分電容介 14 oc 1236敗fd 210的移除方法,例如是進行乾式蝕刻製程或溼式蝕 之後,於未被導電層212覆蓋之深溝渠2〇6側壁上形 成領氧化層214。其中,領氧化層214的材質例如是氧^ 矽,而其形成方法例如是先進行化學氣相沈積製程,以形 成=共形之領氧化材料層,之後再移除深溝渠2〇6以外^ 及V電層212頂部之領氧化材料層,而形成之。並中,移 除部分領氧化材料層的方法例如是進行一非等向性姓刻製 程。VaporDep coffee. n, CVD) process. Next, on the mask layer outline, the second discusses the shadowing process and the etching process to form a patterned pad sound 20 layer 204. Then, using the patterned mask layer 204 and the cushion layer 200 as masks, an etching process is performed to form a depth in the substrate 200. The remaining etching process performed is, for example, a dry money etching process. The lower electrode is formed in the substrate 2000 at the bottom of the deep trench 206. The lower electrode 2 is a region, and the formation method is, for example, formed before the sidewall of the bottom of the trench. The hybrid insulating layer is connected to twf.doc 123613 §〇4. '= Bead trench 206 is filled with a photoresist layer. Then, the hetero insulating layer not covered by the photoresist layer is removed, and the photoresist layer is removed. After forming a common insulating layer, a thermal process is performed, and the dopants in the domain-doped insulating layer diffuse to the substrate 2GG towel, and then the insulating layer and the hetero-insulating layer are removed. In a preferred embodiment, the erbium-doped state of the lower electrode is, for example, the detailed fabrication of the lower electrode 208 is well known to those skilled in the art, and will not be repeated here. Then, the capacitor dielectric layer 21 is applied on the mask layer 204 and the deep trench. Among them, the material of the capacitor dielectric layer = =, Nitrogen, Nitrogen, Oxygen, or other dielectric materials. The two beans are subjected to a thermal oxidation process, a chemical vapor deposition process, or a glutinous layer. Into the conductive layer 212 and cover a part of the valley dielectric layer 210. Wherein the material of the conductive layer 212 = Shi Xi, doped polycrystalline dream, or other suitable conductive materials, and the = method is, for example, in-situ doping ions, two = Cheng: on the substrate On top of the formation-layer doped polycrystalline rhyme and the top part of the deep trench 206 is more than two ditch wood. Among them, the method for removing the doped polycrystalline silicon layer is 9 Å, a manufacturing process or a fishing-side process. In addition, in addition to in-situ doping, the formation method of doped polycrystalline rhyme can also be used for the 4-ion square-phase deposition process. At the same time, a reaction containing a dopant is used for chemical gas followed by it. Please refer to FIG. 5B to remove It is formed without conduction. The dielectric layer 210 forms a capacitive dielectric layer 21a. ^ Covered capacitors, medium, and partial capacitors are removed by 14 oc 1236 and fd 210. For example, after performing a dry etching process or wet etching, they are formed on the side walls of deep trenches 206 that are not covered by the conductive layer 212.领 oxidation 层 214. The material of the collar oxide layer 214 is, for example, oxygen silicon, and its formation method is, for example, first performing a chemical vapor deposition process to form a conformal collar oxide material layer, and then removing the deep trenches other than 206 ^ And a collar oxide material layer on top of the V electrical layer 212 is formed. In the merging, a method of removing a part of the collared oxide material layer is, for example, performing an anisotropic last name engraving process.
然後,於深溝渠206中填入導電層216,其並覆蓋等 電層212,且此導電層216係與導電層212電性連接,雨 且二者係共同作為深溝渠式電容器之上電極205。關於導 電層216的材質及相關的形成方法係與導電層212類似, 且於前述内容中係已對導電層212作詳細地^明,故於’ 不再贅述。Then, a conductive layer 216 is filled in the deep trench 206 and covers the isoelectric layer 212. The conductive layer 216 is electrically connected to the conductive layer 212, and the two are used together as the upper electrode 205 of the deep trench capacitor. . The material of the conductive layer 216 and the related formation method are similar to those of the conductive layer 212, and the conductive layer 212 has been described in detail in the foregoing, so it will not be described in detail herein again.
“接著進行主動元件的相關製程。請參照圖5C,於導 電層^16之一側的基底200中形成溝渠218,且溝渠21丨 係暴露出部分基底200與導電層216。其中,溝渠218 ^ 形成方法例如是進行_製程。在—較佳實關中,在开 ΐί=18之前,更包括於基底2GG中形成摻雜帶, 220係與下電極施鄰接,其中此摻雜帶22〇 ^ 二準^如是^ °此外’在另—較佳實施例中,在开j ί ’更包括於預定形成溝渠218處之部^ 電層”相鄰的基底200巾形成摻雜井區222,而使之 15 twf.doc 123 613^04 =溝渠218形成於摻雜井區2 的摻雜型態例如是 -中此摻雜井區222 形成溝渠218之前,更包m—^圭實施例中,在 底200中形成摻雜井!^ 222 > A中^ ”相鄰的基 極208鄰接,且找中摻雜▼ 220係與下電 nl接且摻雜井區222係與摻 二者之摻質型態相反。 ▼ ~接’而且 丰莫冓渠218中填入半導體材料層223。其中,"Then proceed with the related process of the active device. Please refer to FIG. 5C, a trench 218 is formed in the substrate 200 on one side of the conductive layer ^ 16, and the trench 21 is exposed part of the substrate 200 and the conductive layer 216. Among them, the trench 218 ^ The forming method is, for example, a process. In the preferred practice, before the opening is 18, it further includes forming a doped band in the substrate 2GG. The 220 series is adjacent to the lower electrode, and the doped band is 22〇 ^ In addition, in another preferred embodiment, in a further preferred embodiment, a portion including the predetermined formation of the trench 218 is formed. The “electrical layer” adjacent to the substrate 200 forms a doped well region 222, so that 15 twf.doc 123 613 ^ 04 = the trench 218 is formed in the doped well region 2 and the doping pattern is, for example,-before this doped well region 222 forms the trench 218, in the embodiment described above, A doping well is formed in the bottom 200! ^ 222 > A medium ^ "adjacent base 208 is adjacent, and the middle doping ▼ 220 is connected to the power down nl and the doped well region 222 is doped with both The quality type is the opposite. ▼ ~ 接 'And the semiconductor material layer 223 is filled in the Feng Mo channel 218. Among them,
通材質例如是撕或是其他合適作為 l逼之材貞,料填人方法例如是進行沈積製程。 、之後,請參照圖5D ’圖案化半導體材料層奶,以於 溝渠218中形成半導體條狀物228b。而且,在一較佳實施 例中,更包括移除部分罩幕層2〇4、墊層2〇2與基底2⑻, 以形成暴硌出基底200的二開口(如圖2虛線區域226)。在 一較佳實施例中,在於溝渠218中形成半導體條狀物22肋 時’更包括分別於半導體條狀物228b的兩端分別形成延伸The common material is, for example, tearing or other suitable materials, and the filling method is, for example, a deposition process. After that, please refer to FIG. 5D ′ to pattern the semiconductor material layer milk to form a semiconductor strip 228 b in the trench 218. Moreover, in a preferred embodiment, it further includes removing a part of the cover layer 204, the cushion layer 200, and the substrate 2 to form two openings of the burst substrate 200 (see a dotted area 226 in FIG. 2). In a preferred embodiment, when the semiconductor bar 22 ribs are formed in the trench 218, the method further includes forming extensions at two ends of the semiconductor bar 228b, respectively.
部228a與228c’而形成「H」字形的半導體層224。其中, 延伸部228a係與導電層216鄰接,而另一延伸部228c係 與基底200鄰接。另外’半導體條狀物228b及其延伸告ρ 228a、228c的材質例如是蟲晶石夕或是其他合適作為通道之 半導體材料。 然後,於基底200上形成閘介電層230,以覆蓋裸露 之半導體條狀物228b及其延伸部228a、228c與基底200 表面。其中,閘介電層230的材質例如是氧化;5夕,而其形 16 123 61 成方法例如是熱氧化法。在一較佳實施例中,此閘介電層 230係一併形成於導電層216頂面。接著,於基底200上 形成導電層232,以覆蓋閘介電層230。 繼之,請參照圖5E,移除部分導電層232,以於部分 的閘介電層230上形成導電層232a,其中導電層232a係 與半導體條狀物228b相交,且被導電層232a所覆蓋之部 分半導體條狀物228b係作為通道區207之用(如圖2所 示)。此時,上方橫跨導電層232a的半導體條狀物228b之 立體示意圖係如圖4所示(圖2之局部區域233)。值得一提 的是,對於主動元件來說,導電層23杂覆蓋了半導體條狀 物228b的兩側壁234a與頂部234b魏三俯區域,因此可以 避免因短通道效應所產生的相關問‘。另外,對於單一記 憶胞來說,此處所形成之導電層232&係作為閘極之用,而 對於整個記憶胞陣列來說,導電層232a係作為串接多個記 憶胞的字元線之用。 之後,在一較佳實施例中,更可以於半導體條狀物 228b的部分之延伸部228c,以及與延伸部22%鄰接之基 底200中形成摻雜區236,以作為源極之用。 除此之外,在摻雜區236形成之後,更可以進行相關 製程,以藉由接觸窗,使摻雜區236及導電層232a 與外界電性連接。 由於本發明之主動元件, 分半導體條狀物係作為通道區之用,而且此半 係與深溝渠式電容器的導電層(上電極頂部體=The portions 228a and 228c 'form a semiconductor layer 224 having an "H" shape. Among them, the extension portion 228a is adjacent to the conductive layer 216, and the other extension portion 228c is adjacent to the substrate 200. In addition, the material of the semiconductor strip 228b and its extensions 228a and 228c is, for example, worm crystal or other semiconductor materials suitable as channels. Then, a gate dielectric layer 230 is formed on the substrate 200 to cover the exposed semiconductor strips 228b and their extensions 228a, 228c and the surface of the substrate 200. Among them, the material of the gate dielectric layer 230 is, for example, oxidation; and the method of forming 16 123 61 is, for example, a thermal oxidation method. In a preferred embodiment, the gate dielectric layer 230 is formed on the top surface of the conductive layer 216 together. Next, a conductive layer 232 is formed on the substrate 200 to cover the gate dielectric layer 230. Next, referring to FIG. 5E, a portion of the conductive layer 232 is removed to form a conductive layer 232a on a portion of the gate dielectric layer 230. The conductive layer 232a intersects with the semiconductor strip 228b and is covered by the conductive layer 232a. Part of the semiconductor strip 228b is used as the channel region 207 (as shown in FIG. 2). At this time, the three-dimensional schematic diagram of the semiconductor strip 228b across the conductive layer 232a is shown in Fig. 4 (partial area 233 in Fig. 2). It is worth mentioning that, for the active device, the conductive layer 23 covers the two sidewalls 234a and the top 234b of the semiconductor strip 228b, so that the related problems caused by the short channel effect can be avoided. In addition, for a single memory cell, the conductive layer 232 & formed here is used as a gate, and for the entire memory cell array, the conductive layer 232a is used as a character line connected in series with multiple memory cells. . After that, in a preferred embodiment, a doped region 236 may be formed in the extension portion 228c of the portion of the semiconductor strip 228b and the substrate 200 adjacent to the extension portion 228c for use as a source. In addition, after the doped region 236 is formed, a related process may be performed to electrically connect the doped region 236 and the conductive layer 232a to the outside through a contact window. Due to the active element of the present invention, the semiconductor strip is used as the channel region, and this half is connected to the conductive layer of the deep trench capacitor (top electrode top body =
I236H 需要進行埋入式摻雜帶的製程’即可鱼 接’從而可以解決習知因埋入式摻雜帶窗口 連 小所產生的問題。 尺寸過大或過 、;另外,上述所揭露之深溝渠式電容器的相 用以說明本發明’並非用以限林發明 、广仓 實施射,亦可先彻其他深絲式 ^ 渠式電容器之後,再進行本發明如圖5(:至=3= ==戈樣能夠解決習知因埋入式摻= 固口尺寸過大或過小所產生的問題。I236H requires the process of embedded doped bands, that is, ready-to-connect, so as to solve the problems caused by the small connection window of embedded doped bands. The dimensions are too large or too large; in addition, the phase of the deep trench capacitors disclosed above is used to illustrate the present invention 'is not intended to limit the invention of the forest, to implement the wide warehouse, but also to complete other deep wire ^ trench capacitors, The invention is then carried out as shown in FIG. 5 (: to = 3 === Ge sample can solve the conventional problem caused by the embedded type = solid size is too large or too small.
雖然本發明已以較佳實施例揭露如上,難並 :ίΐΓ丄任何熟習此技藝者’在不脫離本發明之· :槐圍内’當可作些許之更動與潤飾,因此本發明之偏 耗圍當視後附之申請專利範圍所界定者為準。 〜 【圖式簡單說明】 、、六圖1Α至圖1D是習知-種動態隨機存取記憶體之製益 >’IL程剖面示意圖。Although the present invention has been disclosed as above with a preferred embodiment, it is difficult to: ΐΐΓΐ Anyone skilled in the art can make some changes and retouching without departing from the invention: Huaiwei. Therefore, the present invention is biased. Wei Dang shall be determined by the scope of the attached patent application. ~ [Schematic description] Figures 1A to 1D are schematic diagrams of the benefits of a conventional type of dynamic random access memory > 'IL process.
圖2疋本發明一較佳實施例的一種動態隨機存取記憶 胞之上視不意圖。 ^圖3是圖2之動態隨機存取記憶胞,其由14,剖面所 传之剖面示意圖。 圖4是圖2之動態隨機存取記憶胞其局部區域的立體 剖面示意圖。 圖5A至圖5E是圖2之動態隨機存取記憶胞,其由14, 剖面所得之製造流程剖面示意圖。 18FIG. 2 is a top view of a dynamic random access memory cell according to a preferred embodiment of the present invention. ^ FIG. 3 is a schematic cross-sectional view of the dynamic random access memory cell of FIG. FIG. 4 is a schematic three-dimensional sectional view of a local area of the dynamic random access memory cell of FIG. 2. 5A to 5E are cross-sectional schematic diagrams of the manufacturing process of the dynamic random access memory cell of FIG. 2 obtained from the 14, cross-section. 18
I2361H 【主要元件符號說明】 100、200 ··基底 102、202 :墊層 104、204 :罩幕層 106、206 :深溝渠 108、208 :下電極 110、210、210a :電容介電層 112、116、116a、118、118a :多晶矽層 114、114a、114b、214 :領氧化層 120 :埋入式摻雜帶 122 :埋入式摻雜帶窗口 124 :淺溝渠隔離結構 126、128 ··閘極結構 130a :源極區 130b :沒極區 201 :深溝渠式電容器 203 :主動元件 205 :上電極 207 :通道區 212、216、232、232a :導電層 218 :溝渠 220 :摻雜帶 222 ·•摻雜井區 223 :半導體材料層 Ι23613§„ 224 :「Η」字形的半導體層 226、233 :區域 228a、228c ··延伸部 228b :半導體條狀物 230 :閘介電層 234a :側壁 234b :頂面 236 :摻雜區 •I2361H [Description of main component symbols] 100, 200 · · Substrates 102, 202: cushion layers 104, 204: cover layer 106, 206: deep trenches 108, 208: lower electrodes 110, 210, 210a: capacitor dielectric layer 112, 116, 116a, 118, 118a: polycrystalline silicon layers 114, 114a, 114b, 214: collar oxide layer 120: buried doped band 122: buried doped band window 124: shallow trench isolation structure 126, 128 Electrode structure 130a: source region 130b: non-electrode region 201: deep trench capacitor 203: active element 205: upper electrode 207: channel region 212, 216, 232, 232a: conductive layer 218: trench 220: doped band 222 • doped well region 223: semiconductor material layer I23613 § 224: "Η" shaped semiconductor layers 226, 233: regions 228a, 228c · extension 228b: semiconductor strip 230: gate dielectric layer 234a: sidewall 234b : Top surface 236: Doped region •
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