TWI236139B - Dynamic random access memory cell and fabricating method thereof - Google Patents

Abstract

A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided, and the patterned mask layer exposes the deep trench. Also, a deep trench capacitor is formed in the deep trench. A trench is formed in the substrate at one side of the deep trench capacitor, and the trench exposes the partial top electrode of the deep trench capacitor and the substrate. A semiconductor silicone stripe is formed in the trench. A gate dielectric layer is formed on the substrate to cover the exposed surfaces of the semiconductor silicone stripe and the substrate. A gate is formed on the gate dielectric layer and crossed with the semiconductor silicone stripe. Also, the semiconductor silicone stripe that is covered by the gate is used as a channel region.

Description

123611 * IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a memory element and a method for manufacturing the same, and more particularly to a dynamic random access memory cell (DRAM cell). And its manufacturing method. [Previous Technology] With the increasingly powerful functions of today's computer microprocessors, the programs and calculations performed by software have become more and more huge. Therefore, the manufacturing technology of memory has become one of the important technologies in the semiconductor industry. Generally speaking, memory can be divided into volatile memory and non-volatile memory according to the type of data it stores. The dynamic random access memory (DRAM) is a kind of volatile memory, and it is composed of a plurality of memory cells. Each memory cell line is composed of an active element and a capacitor, and each memory cell line is electrically connected to each other through a word line (WL) and a bit line (BL). On the other hand, according to the structure of the capacitor, the dynamic random access memory can be mainly divided into 1¾ forms, which is a dynamic random access memory with a stack capacitor, and the other is a deep trench capacitor. (Deep Trench Capacitor). Since the moving secret type capacitor with the channel type capacitor is formed in the substrate, her dynamics with stacked Γΐί_Wei Jilong is less likely to produce a flattening problem on the cymbal ', which is conducive to small size Production of memory components. However, as 123611-components become smaller and smaller, the dynamic random access memory with deep trench capacitors also encounters more and more problems in the production. FIGS. 1A to 1D are schematic cross-sectional views illustrating a manufacturing process of a conventional memory device with a deep trench capacitor and a remote memory access device. Please refer to FIG. 1A. This manufacturing method first provides a substrate 100, and sequentially forms a patterned pad layer 102 and a cover layer 104 on the surface of the substrate 100. Then, the patterned pad layer 102 and the mask layer 104 are used as an etching mask to form a deep trench 106 on the substrate 10 () 1; Then, a lower electrode 108 is formed in the substrate 100 at the bottom of the deep trench 106, and a capacitive dielectric layer 110 and a polycrystalline silicon layer 112 are sequentially formed at the bottom of the deep trench 106. Thereafter, a collar oxide layer 114 is formed on the surface of the mask layer 104 and the deep trench 106 which is not covered by the polysilicon layer 112. Next, according to FIG. 1B, an anisotropic etching process is performed to remove the collar oxide layer 114 located on top of the mask layer 1G4 and the multi-layer layer 112, and only the collar oxide layer 114a located on the side wall of the deep trench 106 is removed. Next, a polycrystalline silicon layer 116 is filled in the trench 106. 4 = ’Please refer to FIG. 1C’ remove the deep trench 106 and the polycrystalline dream layer 116 ′ located in the deep trench: German, German, and German to form a polycrystalline evening layer u6a. The protective oxide layer 114a covered by the polycrystalline stone wrist is protected. Followed by 'filling polycrystalline stone sound wall in deep trench 106: the silicon layers 112, 116 and 118 are electrically connected to each other, 22, 1D' is subjected to a thermal process to make polycrystalline Negative diffusion diffuses into the substrate 100, ie, -st, BS), and this buried-type impurity is equal to 1236139 13504twf.doc. Qian, the shallow trench is separated from the base of the trench isolation layer 118 to form a shallow separation structure of 12W μ sub-layers and polycrystalline stones are hidden, and the shallow trench is separated by 102 μ, and the active area is defined (not shown) Show). After removing the pad structure 126 and f 104, 'an open junction 128 m is formed on the substrate 100 in the active area, and another gate structure is formed on the shallow trench isolation structure 124> corresponding The source region 13 plus the drain region i30b, and the i-pole region ^ 3% are electrically connected to the upper electrode through a buried doped band 120. And the dynamic random access memory obtained by mixing 3 = 3 ^, the size of the access record 1 is related to the dynamic random size too Γ _ 丨 transition effect " b. For example, the problem of the leakage current of the M-type doped band window with M-pieces. On the other hand, if the buried size is too small, the size of the window of the buried doped tape will be buried due to the buried doping band and the upper electrode. In the process, the size of the buried doped band window =; In view of this, the purpose of the present invention is to take a manufacturing method of memory cells to solve the problem that f a =: =, the deposit is too large or too small. I, f ilj Caliper A further object of the present invention is to provide another manufacturing method to solve the problem of _ which is caused by the small number of embedded memory cells. #_The window size is too large or another object of the present invention is to provide a dynamic random access memory cell, 12361 said to solve the conventional problem of embedded doped bands. This is caused by the oversize or undersize of the mouth, which is formed in the base — _ ==== Formed in the base of this deep trench. A capacitive dielectric layer is formed on the surface of the trench. Iron 2 fills the first-conductive layer at the bottom of the deep trench. Next: a capacitive dielectric layer covered by a conductive layer. After that, a collar oxide layer is formed on the side wall of the trench which is not the first conductive layer. Next, a deep conductive trench is filled with a second conductive layer 'and covers the first conductive layer. Then, a trench is formed in the substrate on one side of the second conductive layer, and the trench exposes part of the substrate and the second conductive layer. Then, a semiconductor strip is formed in the trench, and the semiconductor strip exposes a part of the substrate at the bottom of the trench. One end of the semiconductor strip is adjacent to the second conductive layer, and the other end is adjacent to the substrate. Then, a gate dielectric layer is formed on the substrate to cover the exposed semiconductor stripes and the surface of the substrate. Next, a gate is formed on the gate dielectric layer, where the gate intersects with the conductor strip, and a part of the semiconductor strip covered by the gate is used as a channel region. The present invention provides another method for manufacturing a dynamic random access memory cell. This method first provides a substrate, and a patterned mask layer and a deep trench capacitor formed in the substrate have been formed on the substrate. The trench capacitor is composed of a lower electrode, an upper electrode, a capacitor dielectric layer and a collar oxide layer, and the patterned mask layer exposes the upper electrode. Then, a trench is formed in the substrate on the side of the deep trench-type 1236139 n ^ twf.doc capacitor, and the trench exposes part of the substrate and the upper electrode. Then, after filling a semiconductor material layer in the trench, the semiconductor material layer is patterned to form a semiconductor strip, and two openings are formed to expose the substrate. One end of the semiconductor strip is adjacent to the upper electrode. The other end is adjacent to the base. After that, a gate dielectric layer is formed on the substrate to cover the exposed semiconductor stripes and the surface of the substrate. Next, a conductive layer is formed on the dielectric layer, wherein the conductive layer is a semiconductor stripe 'and a portion of the semiconductor stripe covered by the conductive layer is used as a channel region. The invention proposes a dynamic random access memory cell. The dynamic random access = memory cell system is composed of a deep trench capacitor and an active element. Among them, the deep capacitor is arranged in the deep trench of the base, and the deep trench capacitor is composed of the lower electrode, the upper electrode, the capacitor dielectric layer and the collar oxide layer. The lower electrode is arranged in a substrate at the bottom of the deep trench. In addition, the upper electrode is arranged at //. In addition, the capacitor dielectric layer is disposed between the deep trench and the upper electrode. In addition, the collar oxide layer is disposed on the side wall of the deep trench without the valley dielectric layer, and is located between the upper electrode and the substrate. In addition, the active device is placed in the trench of the substrate and the active device is electrically connected to the deep trench; and the active device is composed of a semiconductor strip, an interposer, and a doped region. Among them, the beauty of the semiconductor strip system ^ 'and the channel layer system exposed part of the semiconductor strip at the bottom of the trench-the end system is adjacent to the substrate, and the other-in addition, the dielectric layer gate system configuration On the gate dielectric layer

I2361H $ The phase parent, and part of the semiconductor strip covered by the gate is used as the channel region. In addition, the doped region is arranged in the semiconductor, strip and adjacent substrate towel adjacent to the substrate. Since the material covered by the gate electrode of the active device of the present invention is used for the channel area, and the semiconductor strip is adjacent to the conductive layer (or the top of the upper electrode) of the deep trench industrial power valley, It is not necessary to form a buried doped band, and it can be electrically connected to the active element, so that the conventional problem caused by the too large or too small size of the buried doped band window σ can be solved. ▲ In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows. [Embodiment] FIG. 2 is a schematic top view of a dynamic random access memory cell according to a preferred embodiment of the present invention. Fig. 3 is a schematic cross-sectional view of the dynamic random access memory cell obtained from the section 14 in Fig. 2. Refer to FIG. 2 and FIG. 3 tomorrow. The dynamic random access memory cell of the present invention is composed of a deep trench capacitor 201 and an active device 203. The deep trench capacitor 201 is arranged in the deep trench 206 of the substrate 200, and the deep trench capacitor 201 is composed of a lower electrode 208, an upper electrode 205, a capacitor dielectric layer 210a, and a collar oxide layer 214. In a preferred embodiment, the upper electrode is composed of conductive layers 212, 216. In addition, the active device 203 is disposed in the trench 218 of the substrate 200 and is adjacent to the deep trench capacitor 201, and the active device 203 is composed of a semiconductor strip 228b, a gate dielectric layer 230, a conductive layer 232a, and a doped region. 236. In a preferred embodiment 12361 谥 · ', the two ends of the' semiconductor stripe 228b 'further include extension portions 228a and 228c, respectively, to form an "H" shaped semiconductor layer 224. Among them, the lower electrode 208 of the deep trench capacitor 201 is arranged in the substrate 200 at the bottom of the deep trench & 206. In addition, the conductive layer 212 is disposed on the bottom of the trench 206. In addition, the capacitor dielectric layer 21 is disposed between the bottom surface of the deep trench 206 and the conductive layer 212. In addition, the conductive layer 216 is disposed on the conductive layer 212 and fills the deep trenches 206. The collar θ oxide layer 214 is disposed between the conductive layer 216 and the substrate 200. In addition, the semiconductor strip 228b of the active device 203 is disposed in the trench 218, and the semiconductor strip 228b exposes a portion of the base 200 at the bottom of the trench 218, and the extension portion 228a is adjacent to the conductive layer 216 and another An extension 228c is adjacent to the base 200. Of course, in a preferred embodiment, the semiconductor strip 228b may be disposed only in the trench 218, so that both ends of the semiconductor strip 228b are adjacent to the conductive layer 216 and the substrate 200, respectively. In addition, the material of the semiconductor strip 228b and its extensions 228a, 228c is, for example, epitaxial silicon or other semiconductor materials suitable as a channel. In a preferred embodiment, in addition to a portion of the substrate 200 at the bottom of the trench 218 being exposed, a portion of the substrate 200 other than the trench 218 is also exposed, as shown by the dotted area 226 in FIG. 2. First, the gate dielectric layer 230 is disposed on the surface of the semiconductor strip 22a and its extensions 228a and 228c. In a preferred embodiment, the gate dielectric layer 230 is also disposed on the top surface of the conductive layer 216. In addition, the conductive layer 232a is disposed on a part of the gate dielectric layer, T2361 ^ 4twf.d0c and intersects the semiconductor strip 228b, and a part of the semiconductor strip 228b covered by the conductive layer 232a is used as a channel region. 207 uses. The three-dimensional schematic diagram of the semiconductor strip 228b with the upper edge crossing the conductive layer 232a is shown in FIG. 4 (partial area 233 in FIG. 2). In particular, for the active device 203, the conductive layer 232a covers the three regions 234a and the top 234b of the semiconductor strip 228b, so the correlation caused by the Short Channel Effect can be avoided. problem. In addition, for a single memory cell, the conductive layer 232a is used as a gate, and for the entire memory cell array, the conductive layer 232a is used as a character line connected in series with a plurality of memory cells. In addition, the 'doped region 236 is disposed in the extension portion 228c of the portion of the semiconductor strip 228b and in the substrate 2000 adjacent to the extension portion 228c as a source region. In addition, in another preferred embodiment, the dynamic random access memory cell further includes a doped band 220 disposed on the substrate 200 and connected to the lower electrode 208 *. In addition, in X-preferably, the memory cell is further configured to doped well region 222 is disposed in part of conductive layer 216 and adjacent substrate 200, and trench 218 is disposed in doped Well area 222. In addition, in another preferred embodiment, the movable 222Ht doped band 220 is disposed in the substrate, and the doped = conducting layer 216 disposed in ° 卩 and the adjacent substrate 200 is disposed. 2 bands, the system and the lower electrode should be adjacent. In addition, if the doped well region 220 is adjacent to the impurity band 220, and the doped well region 222 and the doped band 2220 are doped with 12 I236I ^, doc, the quality is opposite. It divides half of its conductive layer (gate) to cover the parts, which can solve the problems caused by the conventional T power 丨 Wang Ni small. The size of the window of the α-type push-in miscellaneous tape is too large or too large. The “flow chart” of the random access memory cells exaggerated with reference to FIG. 5A to FIG. 5EA. Ming Zhi's manufacturing method of dynamic random access memory cells. In the middle, "The same reference numerals in the above drawings represent the same components. A full if view is shown in FIG. 5A ′, a substrate 200 ′ is provided on the substrate 200 in a pot. After the heat = layer 202, a mask layer 204 is formed on the base layer 202.杂 进 杂 ^ = Material_If it is oxygen cutting, and its forming method is, for example, Shi Xi ° In addition, the material of the cover layer 204 is, for example, nitride

Vapor D is a chemical vapor deposition (C-

VaporDep coffee. n, CVD) process. Next, on the mask layer outline, the second discusses the shadowing process and the etching process to form a patterned pad sound 20 layer 204. Then, using the patterned mask layer 204 and the cushion layer 200 as masks, an etching process is performed to form a depth in the substrate 200. The remaining etching process performed is, for example, a dry money etching process. The lower electrode is formed in the substrate 2000 at the bottom of the deep trench 206. The lower electrode 2 is a region, and the formation method is, for example, formed before the sidewall of the bottom of the trench. The hybrid insulating layer is connected to twf.doc 123613 §〇4. '= Bead trench 206 is filled with a photoresist layer. Then, the hetero insulating layer not covered by the photoresist layer is removed, and the photoresist layer is removed. After forming a common insulating layer, a thermal process is performed, and the dopants in the domain-doped insulating layer diffuse to the substrate 2GG towel, and then the insulating layer and the hetero-insulating layer are removed. In a preferred embodiment, the erbium-doped state of the lower electrode is, for example, the detailed fabrication of the lower electrode 208 is well known to those skilled in the art, and will not be repeated here. Then, the capacitor dielectric layer 21 is applied on the mask layer 204 and the deep trench. Among them, the material of the capacitor dielectric layer = =, Nitrogen, Nitrogen, Oxygen, or other dielectric materials. The two beans are subjected to a thermal oxidation process, a chemical vapor deposition process, or a glutinous layer. Into the conductive layer 212 and cover a part of the valley dielectric layer 210. Wherein the material of the conductive layer 212 = Shi Xi, doped polycrystalline dream, or other suitable conductive materials, and the = method is, for example, in-situ doping ions, two = Cheng: on the substrate On top of the formation-layer doped polycrystalline rhyme and the top part of the deep trench 206 is more than two ditch wood. Among them, the method for removing the doped polycrystalline silicon layer is 9 Å, a manufacturing process or a fishing-side process. In addition, in addition to in-situ doping, the formation method of doped polycrystalline rhyme can also be used for the 4-ion square-phase deposition process. At the same time, a reaction containing a dopant is used for chemical gas followed by it. Please refer to FIG. 5B to remove It is formed without conduction. The dielectric layer 210 forms a capacitive dielectric layer 21a. ^ Covered capacitors, medium, and partial capacitors are removed by 14 oc 1236 and fd 210. For example, after performing a dry etching process or wet etching, they are formed on the side walls of deep trenches 206 that are not covered by the conductive layer 212.领 oxidation 层 214. The material of the collar oxide layer 214 is, for example, oxygen silicon, and its formation method is, for example, first performing a chemical vapor deposition process to form a conformal collar oxide material layer, and then removing the deep trenches other than 206 ^ And a collar oxide material layer on top of the V electrical layer 212 is formed. In the merging, a method of removing a part of the collared oxide material layer is, for example, performing an anisotropic last name engraving process.

Then, a conductive layer 216 is filled in the deep trench 206 and covers the isoelectric layer 212. The conductive layer 216 is electrically connected to the conductive layer 212, and the two are used together as the upper electrode 205 of the deep trench capacitor. . The material of the conductive layer 216 and the related formation method are similar to those of the conductive layer 212, and the conductive layer 212 has been described in detail in the foregoing, so it will not be described in detail herein again.

"Then proceed with the related process of the active device. Please refer to FIG. 5C, a trench 218 is formed in the substrate 200 on one side of the conductive layer ^ 16, and the trench 21 is exposed part of the substrate 200 and the conductive layer 216. Among them, the trench 218 ^ The forming method is, for example, a process. In the preferred practice, before the opening is 18, it further includes forming a doped band in the substrate 2GG. The 220 series is adjacent to the lower electrode, and the doped band is 22〇 ^ In addition, in another preferred embodiment, in a further preferred embodiment, a portion including the predetermined formation of the trench 218 is formed. The “electrical layer” adjacent to the substrate 200 forms a doped well region 222, so that 15 twf.doc 123 613 ^ 04 = the trench 218 is formed in the doped well region 2 and the doping pattern is, for example,-before this doped well region 222 forms the trench 218, in the embodiment described above, A doping well is formed in the bottom 200! ^ 222 > A medium ^ "adjacent base 208 is adjacent, and the middle doping ▼ 220 is connected to the power down nl and the doped well region 222 is doped with both The quality type is the opposite. ▼ ~ 接 'And the semiconductor material layer 223 is filled in the Feng Mo channel 218. Among them,

The common material is, for example, tearing or other suitable materials, and the filling method is, for example, a deposition process. After that, please refer to FIG. 5D ′ to pattern the semiconductor material layer milk to form a semiconductor strip 228 b in the trench 218. Moreover, in a preferred embodiment, it further includes removing a part of the cover layer 204, the cushion layer 200, and the substrate 2 to form two openings of the burst substrate 200 (see a dotted area 226 in FIG. 2). In a preferred embodiment, when the semiconductor bar 22 ribs are formed in the trench 218, the method further includes forming extensions at two ends of the semiconductor bar 228b, respectively.

The portions 228a and 228c 'form a semiconductor layer 224 having an "H" shape. Among them, the extension portion 228a is adjacent to the conductive layer 216, and the other extension portion 228c is adjacent to the substrate 200. In addition, the material of the semiconductor strip 228b and its extensions 228a and 228c is, for example, worm crystal or other semiconductor materials suitable as channels. Then, a gate dielectric layer 230 is formed on the substrate 200 to cover the exposed semiconductor strips 228b and their extensions 228a, 228c and the surface of the substrate 200. Among them, the material of the gate dielectric layer 230 is, for example, oxidation; and the method of forming 16 123 61 is, for example, a thermal oxidation method. In a preferred embodiment, the gate dielectric layer 230 is formed on the top surface of the conductive layer 216 together. Next, a conductive layer 232 is formed on the substrate 200 to cover the gate dielectric layer 230. Next, referring to FIG. 5E, a portion of the conductive layer 232 is removed to form a conductive layer 232a on a portion of the gate dielectric layer 230. The conductive layer 232a intersects with the semiconductor strip 228b and is covered by the conductive layer 232a. Part of the semiconductor strip 228b is used as the channel region 207 (as shown in FIG. 2). At this time, the three-dimensional schematic diagram of the semiconductor strip 228b across the conductive layer 232a is shown in Fig. 4 (partial area 233 in Fig. 2). It is worth mentioning that, for the active device, the conductive layer 23 covers the two sidewalls 234a and the top 234b of the semiconductor strip 228b, so that the related problems caused by the short channel effect can be avoided. In addition, for a single memory cell, the conductive layer 232 & formed here is used as a gate, and for the entire memory cell array, the conductive layer 232a is used as a character line connected in series with multiple memory cells. . After that, in a preferred embodiment, a doped region 236 may be formed in the extension portion 228c of the portion of the semiconductor strip 228b and the substrate 200 adjacent to the extension portion 228c for use as a source. In addition, after the doped region 236 is formed, a related process may be performed to electrically connect the doped region 236 and the conductive layer 232a to the outside through a contact window. Due to the active element of the present invention, the semiconductor strip is used as the channel region, and this half is connected to the conductive layer of the deep trench capacitor (top electrode top body =

I236H requires the process of embedded doped bands, that is, ready-to-connect, so as to solve the problems caused by the small connection window of embedded doped bands. The dimensions are too large or too large; in addition, the phase of the deep trench capacitors disclosed above is used to illustrate the present invention 'is not intended to limit the invention of the forest, to implement the wide warehouse, but also to complete other deep wire ^ trench capacitors, The invention is then carried out as shown in FIG. 5 (: to = 3 === Ge sample can solve the conventional problem caused by the embedded type = solid size is too large or too small.

Although the present invention has been disclosed as above with a preferred embodiment, it is difficult to: ΐΐΓΐ Anyone skilled in the art can make some changes and retouching without departing from the invention: Huaiwei. Therefore, the present invention is biased. Wei Dang shall be determined by the scope of the attached patent application. ~ [Schematic description] Figures 1A to 1D are schematic diagrams of the benefits of a conventional type of dynamic random access memory > 'IL process.

FIG. 2 is a top view of a dynamic random access memory cell according to a preferred embodiment of the present invention. ^ FIG. 3 is a schematic cross-sectional view of the dynamic random access memory cell of FIG. FIG. 4 is a schematic three-dimensional sectional view of a local area of the dynamic random access memory cell of FIG. 2. 5A to 5E are cross-sectional schematic diagrams of the manufacturing process of the dynamic random access memory cell of FIG. 2 obtained from the 14, cross-section. 18

I2361H [Description of main component symbols] 100, 200 · · Substrates 102, 202: cushion layers 104, 204: cover layer 106, 206: deep trenches 108, 208: lower electrodes 110, 210, 210a: capacitor dielectric layer 112, 116, 116a, 118, 118a: polycrystalline silicon layers 114, 114a, 114b, 214: collar oxide layer 120: buried doped band 122: buried doped band window 124: shallow trench isolation structure 126, 128 Electrode structure 130a: source region 130b: non-electrode region 201: deep trench capacitor 203: active element 205: upper electrode 207: channel region 212, 216, 232, 232a: conductive layer 218: trench 220: doped band 222 • doped well region 223: semiconductor material layer I23613 § 224: "Η" shaped semiconductor layers 226, 233: regions 228a, 228c · extension 228b: semiconductor strip 230: gate dielectric layer 234a: sidewall 234b : Top surface 236: Doped region •

20

Claims (1)

12361¾ 4twf.doc 10. Scope of patent application: 1. A method for manufacturing a dynamic random access memory cell, including: providing a substrate on which a patterned mask layer has been formed and a depth formed on the substrate; Trenches, and the patterned masking layer exposes the deep trenches, and a lower electrode is formed in the substrate at the bottom of the deep trenches, and a capacitive dielectric layer is formed on the surface of the deep trenches; A conductive layer is at the bottom of the deep trench; removing the capacitive dielectric layer not covered by the first conductive layer; a sidewall is formed into a weird layer on the deep trench layer not covered by the first conductive layer; Filling-a first conductive layer in the deep trench to cover the first conductive channel system exposing part of the base and the substrate, and the trench bottom body trench: and exposing part of the trench conductive layer is adjacent, and another ： == 1 series of semiconductor strips are adjacent to the second formation-opening C bottom :, strips and the base wire surface ^ & said semiconductor y of m, and two stripe phases On the electrical layer, where the gate system and the semiconductor system are used as channel regions The part of the semiconductor strip that is extremely difficult to cover with the phase 2. As in the manufacturing method in the scope of the patent application, wherein the dynamic random access memory cell of the two two, =, the material of the conductor strip is worm spar. 21 12361¾ 4twf.doc Scope of 12361¾ 4twf.doc The dynamic random access memory cell method described in item 1, the method of applying the semiconducting debris includes: inserting a semiconductor material layer into the trench ; And patterning the semiconductor material layer. To make a towel, please use the machine described in item 3 of the patent scope to access / remove the memory cell. In the step of patterning the semiconductor material layer, it further includes removing a part of the patterned mask layer and the substrate. 5. The method for manufacturing a random access memory cell as described in item 1 of ψ 4 patent, wherein the steps of forming the semiconductor strip in the trench: further include the two ends of the semiconductor strip respectively A first extension is formed. And a second extension portion to form a "H" shaped semiconductor layer. 6. The method for manufacturing a dynamic random access memory cell as described in item 1 of the scope of patent application, wherein after forming the gate, it further includes a portion of the semiconductor strip adjacent to the substrate and the substrate adjacent to the substrate. A doped region is formed. 7. The method for manufacturing a dynamic random access memory cell as described in item 1 of the scope of the patent application, wherein the method for forming the collar oxide layer includes: forming a collar oxide material layer on the side wall of the deep trench and on top of the first conductive layer Surface and the substrate surface; and removing the collar oxide material layer on the top surface of the first conductive layer and the substrate surface. 8. The method for manufacturing a dynamic random access memory cell according to item 1 of the scope of patent application, wherein before the step of forming the trench in the substrate on the side of the second conductive layer, it further comprises forming a doped band In the substrate, and 22 ^ twf.doc 12361, the doped band is adjacent to the lower electrode. 9 · The method for manufacturing a motion as described in item [Scope of the patent application], which makes the spike in the formation of the groove Γ ^ access memory cell substrate = conductive layer-side of the, medium / step of the rule It also includes forming a dowel well area on the conductive layer and the substrate /, so that the trench is formed in the __21-10 · — a method for manufacturing a dynamic random access memory cell, a spoon provided-a substrate, on the substrate One of the patterned I ·? Capacitors has been formed, and the deep trench container has a bottom electrode, an upper electrode, and a capacitor dielectric layer, and the mask layer is exposed. The upper electrode is formed; a trench is formed in the substrate on the side of the deep trench capacitor, and the trench exposes a part of the substrate and the upper electrode; a semiconductor material layer is filled in the trench; ... Patterning the semiconductor material layer to form a semiconductor strip and forming two openings exposing the substrate, wherein one end of the semiconductor strip is adjacent to the upper electrode and the other end is adjacent to the substrate; forming -A gate dielectric layer on the substrate to cover The bare stripe and the substrate surface are formed; and a conductive layer is formed on the gate dielectric layer, wherein the conductive layer intersects the semiconductor stripe and a portion of the semiconductor strip covered by the conductive layer The system serves as a channel area. L1. If you apply for the full-time secret of the tenth rhyme, a method of manufacturing a random access memory cell, in which the material of the semiconductor strip is stupid stone. 12. The manufacturing method of dynamic random access memory 23 12361¾¾ 04twf.doc as described in item 10 of the scope of patent application, wherein in the step of forming the semiconductor strip in the trench, it is further included in the semiconductor strip. Two ends of the object form two first extension portions and a second extension portion, respectively, to form an "H" shaped semiconductor layer. 13. The method for manufacturing a dynamic random access memory cell as described in item 10 of the scope of patent application, wherein after forming the conductive layer, the method further comprises: forming a doped region on a portion of the semiconductor strip adjacent to the substrate As well as in the substrate. 14. The method for manufacturing a random access cell as described in the patent application item No. 1G, wherein the step of patterning the semiconductor material layer further includes removing a part of the patterned mask layer and the substrate. . 15. The method for manufacturing a dynamic random access credit cell as described in item 1G of the scope of patent application, wherein the upper electrode is formed by a first: conductive and the semiconductor strip is adjacent to the second conductive layer. == dedicated dynamic random access on the two sides of the substrate; capacitor-the second conductive layer _ which includes the L-doped region in the section., &Quot; soil " in order to make the trench Formed in the doped well cell _City _ access to the memory side of the substrate in the deep trench capacitor one, and: the doped band system is adjacent; power down: .formed-doped band in the Substrate 18, a kind of dynamic random access memory cell-a deep trench capacitor n 'configured in _base red-deep trench capacitor 24 12361 ^., Doc deep trench capacitors include:-the lower electrode' is arranged at the bottom of the deep trench In the substrate; an upper electrode is disposed in the deep trench; between the electrodes is disposed on the bottom surface of the series channel and the upper, upper, and lower oxide layers are disposed on the surface where the capacitor dielectric layer is not disposed; Deep groove Zhu side wall 'is located between the upper electrode and the base; and the strain plate: : The piece is disposed in a trench of the substrate, and the active element is adjacent to the deep trench capacitor. The active element includes: = Lai Lu, which is disposed on the Lai Qu towel and the exposed portion of the substrate; and One end of the semiconductor strip is connected to the β-Hai substrate ball and the other end is adjacent to the upper electrode; a gate dielectric layer is disposed on the surface of the half-bar strip; a gate electrode is disposed on the And the semiconductor strips intersect, and a part of the deconducting strips covered by the gate is used as a channel region; and a doped region is disposed at a portion of the semiconductor strips adjacent to the substrate and Adjacent to the substrate. 19. The dynamic random access memory cell as described in item 18 of the scope of the patent application, wherein the material of the semiconductor stripe is wormworm stone. 20. The scope of the patent application is 18th. The dynamic random access memory cell according to the item, wherein the two ends of the semiconductor strip further include a first extension portion and a second extension portion, respectively, to form a “Η” -shaped semiconductor layer. 21. The dynamic random access memory 25 4twf.doc cell as described in item 18 of the scope of the patent application, wherein the upper electrode is composed of a first conductive layer and a second conductive layer, and the capacitor dielectric layer is It is arranged between the bottom surface of the deep trench and the first conductive layer, the collar oxide layer is arranged between the second conductive layer and the substrate, and the semiconductor strip is adjacent to the second conductive layer. 22. The dynamic random access memory cell described in item 18 of the scope of patent application, further comprising a doped band disposed in the substrate, and the doped band is adjacent to the lower electrode of the deep trench capacitor. 23. The dynamic random access memory cell described in item 18 of the scope of patent application, further comprising a doped well region, and the trench is arranged in the doped well region. 26