TW201123327A - Semiconductor device and method of forming an inductor on polymer matrix composite substrate - Google Patents

Abstract

A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Description

201123327 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to semiconductor devices and, more particularly, to semiconductor devices and methods of forming inductors on polymer matrix composite substrates. [Prior Art] A semiconductor device is often found in modern electronic products. Semiconductor devices have different numbers and densities of electrical components. Discrete semiconductor devices typically contain one type of electrical component, for example, a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor. And power metal oxide semiconductor field effect transistor (MeUl 〇xide

Semiconductor Field Effect Transistor, MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, Charged-Coupled Devices (CCDs), solar cells, and Digital Micro-mirror devices (DMDs). Semiconductor devices perform a wide variety of functions, such as high-speed computing, transmitting and receiving electromagnetic signals, controlling electronics, converting sunlight into electricity, and producing visual projections of television displays. Semiconductor devices are found in the entertainment, communications, power conversion, networking, computer, and consumer products sectors. Semiconductor devices are also found in military applications, aerospace, automated vehicles, industrial controllers, and office equipment. Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material 201123327 allows the conductivity to be manipulated by applying an electric field or a base current or via a doping process. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device. A semiconductor device will contain an active electrical structure and a passive electrical structure. The active structure, which contains bipolar transistors and field effect transistors, controls the flow of current. The transistor increases or limits the flow of current by varying the degree of doping and applying an electric or base current. Passive structures, which include electricity: capacitors, capacitors, and inductors, create the relationship between the voltage and current required to implement a wide variety of electrical functions. The passive structures and the =-state junctions are electrically connected to form a circuit that allows the semiconductor device to perform high-speed calculations and other useful functions. Semiconductor devices typically use 'front-end manufacturing and back-end manufacturing steps. Front end manufacturing involves half of the granules. Each die is usually the same and cuts into individual circuits in a circuit circle formed by passive components and is sealed and environmentally isolated. Two complex processes are used to make, that is, each of them may involve a plurality of crystals on the surface of hundreds of step wafers and contain active components by electrical connection. Back-end fabrication involves the fabrication of the die from the finished wafer to provide a structural support. One of the goals of semiconductor fabrication is to produce smaller semiconductor devices. Smaller devices typically consume less power, are more efficient, and can be produced efficiently. In addition, smaller semiconductor devices are also required for smaller end products that are smaller in area. A smaller grain size can be achieved by improving the end of the spearhead, resulting in a die with a smaller and higher density of active and passive components. Backend Process 201123327 A semiconductor device package with a small footprint can be produced by improving electrical interconnect materials and packaging materials. Another goal of semiconductor manufacturing is to produce higher performance semiconductor devices. In frequency-frequency applications, for example, radio frequency (Radi〇 FrequenCy, Rp>) wireless communication: integrated passive components (IPD) are often incorporated into semiconductor devices. Examples of integrated passive components include resistors, capacitors, and inductors. A typical RF system requires the use of multiple integrated passive components in one or more semiconductor packages to perform the necessary electrical functions. The inductor is typically formed over a sacrificial substrate for structural support purposes. The sacrificial substrate is removed by a grinding or etching process after the inductor is formed. The use of a sacrificial substrate increases processing steps, such as grinding and surnames, and increases the cost of the process. SUMMARY OF THE INVENTION In the case of liters into inductors, it is necessary to simplify the process and reduce the cost. Accordingly, in one embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: forming a polymer matrix composite substrate; forming a first insulation over the first surface of the polymer matrix composite substrate a first conductive layer is formed over the first insulating layer; a second insulating layer is formed over the first insulating layer and the first conductive layer; above the second insulating layer and the first conductive layer Forming a second conductor layer; forming a third insulating layer over the second insulating layer and the second conductor layer; removing a portion of the third insulating layer for exposing the second conductor layer; and A bump is formed above the two conductor layers. 6201123327 In another embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: forming a molded substrate; forming a first conductor layer over the molded substrate; and forming the substrate and the first conductor Forming a first insulating layer over the layer; forming a second conductive layer over the first insulating layer and the first conductive layer; forming a second insulating layer over the first insulating layer and the second conductive layer; And forming an interconnect structure over the second conductor layer. In another embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: forming a polymer matrix synthetic substrate; forming an inductor over the molecular matrix composite substrate; and forming an inductor at the inductor An interconnect structure is formed above. In another embodiment, the invention is a semiconductor device comprising a polymer matrix composite substrate and a first conductor layer formed over the polymer matrix synthesis substrate. A first insulating layer is formed over the polymer matrix composite substrate and the first conductor layer. A second conductor layer is formed over the first insulating layer and the first conductor layer. A second insulating layer is formed over the first insulating layer and the second conductor layer. An interconnect structure is formed over the second conductor layer. The present invention is described in the following description with reference to the drawings, in which the same symbols represent the same or identical elements. The present invention will be described in the best mode for achieving the object of the present invention; however, those skilled in the art will appreciate that the present invention is intended to cover the scope of the accompanying claims and their accompanying claims and the drawings. The equivalents of the invention are defined by the equivalents of the invention, and the alternatives, modifications, and equivalents that may be incorporated in the scope of the invention. Semiconductor devices are typically manufactured using two complex processes: front-end manufacturing and back-end manufacturing. Front end fabrication involves forming a plurality of grains on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components' that are electrically connected to form a functional circuit. Active electrical components (such as transistors and diodes) are capable of controlling the flow of current. Passive electrical components (such as capacitors, inductors, resistors, and transformers) create the relationship between the voltage and current required to implement the circuit's functions. The dynamic and active components are connected together. The process steps are mixed, deposited, and lighted: the process steps include: broadcast and flattening. Doping can be introduced into the semiconductor material by the following #', for example: ion implantation or thermal diffusion. The doping process modifies the active device 'electricity, converting the semiconductor material into an insulator, a conductor, ... = : field or base current to dynamically change the conductivity of the semiconductor material. The body contains a plurality of regions of two types and different degrees of substitution, which are arranged in two to be used to apply a current or a current that limits the current. The current causes the transistor to lift the two-piece and passive components. The multiple layers with different electrical characteristics can be shaped by a variety of deposition techniques depending on the type of material to be deposited. For example, 'thin 201123327 film deposition may include: chemical vapor deposition (Chemical Vapor Deposition CVD) process, physical vapor deposition (physic% (four)

Deposition PVD) Process, electrolyte ore process and electrodeless electric forging process. Each layer is typically patterned to form a portion of a passive component of the active component, or a portion of the electrical connection between the components. The layers b are sufficient to be patterned using photolithography, which involves depositing a photosensitive material, for example, a photoresist, over the layer to be patterned. A pattern is transferred from the reticle to the photoresist using light. The portion of the photoresist pattern that is exposed to light utilizes the solvent patterned portion. The remaining portion of the photoresist in the middle layer is removed, leaving a patterned layer. The latter, some types of materials will use the technology of electrodeless and electrolyte plating, such as electroless plating, by depositing the material directly first, month 1J, and/or The engraving process is # M d patterning. ... formed in the area or void (d) d) is deposited on top of an existing pattern - a thin pattern and produces a non-uniform hook qI 曰 expands the surface below & a go to ten. The production of smaller and more densely packed active components and passives can be used in the flattening of the flattening surface. Decimalization can be used to flatten the surface from the wafer. The flat removal material m produces a uniform surface. Abrasive action to grind the Japanese yen A Mg 8B , : 4 X and corrosive chemicals will be applied to the surface of the wafer during the flat grinding process, and the rhythmic effect of the combined machine u composed of the research function and Corrosion of the shape, resulting in uniformity, removes any irregular topology. 201123327 "Made" refers to cutting or cutting a completed wafer into individual dies' and then encapsulating the dies for structural support and environment The effect of isolation. To cut the die, the wafer is scored and broken along non-functional areas in the wafer known as saw streets or scribes. The wafer is cut using a laser cutting tool or saw blade. After dicing, the individual dies are embedded into a package substrate containing pins or contact pads for interconnection with other system components. A contact pad formed over the semiconductor die is then connected to the contact pads in the package. The electrical connection wires can be made using solder bumps, short stud bumps, conductive pastes or solder wires. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components. 1 illustrates an electronic device 50 having a printed circuit board (Printed Circuit Board) having a plurality of semiconductor packages. The electronic dream device has a wafer carrier substrate or

Device, memory, specific should, a _, - ping case I 詋 '罨 thousand device 5 〇 a little interface card or can be inserted into a computer. The semiconductor package may include an integrated circuit for micro processing (Application Specific 201123327)

Integrated Circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. In Fig. 1, printed circuit board 52 provides a general purpose substrate for structurally supporting and electrically interconnecting a semiconductor package that is mounted over the printed circuit board. A plurality of conductor signal lines 54 are formed over or over a surface of the printed circuit board 52 using an evaporation process, an electrolyte plating process, an electroless plating process, a screen printing process, or other suitable metal deposition process. Signal line 54 provides electrical communication between each of the semiconductor packages, the mounted components, and other external system components. Line 54 also provides power and ground connections to each of the semiconductor packages. In some embodiments, a semiconductor device will have two encapsulation layers. The first layer of packaging is a technique for mechanically and electrically attaching the semiconductor grain to an intermediate carrier. The second layer of packaging involves mechanically and electrically attaching the intermediate carrier to the printed circuit board. In other embodiments, a semiconductor device may only have the first layer package, wherein the die is mechanically and electrically mounted directly to the printed circuit board. For the purpose of explanation, a plurality of types of first layer packages are shown on the printed circuit board 52 in the figure, which include a wire bond package 56 and a flip chip 58. In addition, the figure also shows several types of second layer packages that are embedded on the printed circuit board 52, including: Ball Grid Array (BGA) 60; bump wafer carrier ( Bump Chip Carrier, BCC) 62; Dual In-line Package (DIP) 64; Platform Grid Array (Land Grid 201123327 y) 66, Muti-Chip Module (MCM) 68; Square Flat Quad Flat Non-leaded package (QFN) 7〇, and a quad flat package 72. Depending on the needs of the system, the (four) combination of various semiconductor packages configured to have any combination of the first layer package pattern and the second layer package pattern and other electronic components can be connected to the P brush circuit board 52. In some embodiments, the electronic device includes a single attached semiconductor package, while other embodiments require #multiple interconnect packages. By combining over a single-substrate—or multiple semiconductor packages—the manufacturer can incorporate previously fabricated components into electronic devices and systems. Because these semiconductor packages contain sophisticated functions, the electronic devices can be manufactured using cheaper components and efficient processes. The resulting device is less likely to fail and is less expensive to manufacture, thereby reducing the cost to the consumer. An exemplary semiconductor package shown in Figures 23 through 2C. The system shown by @2a is further detailed in the double in-line package 镶 above the printed circuit board 52. The semiconductor die 74 includes an active region containing an analog circuit or a digital circuit. The analog circuits or digital circuits are acted upon by active devices, passive devices, conductor layers, and dielectric layers formed within the die, and Electrical interconnections are made based on the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components formed within the active region of the semiconductor die 74. The contact pad 76 is made of - or a plurality of layers of conductor material (for example, aluminum (A1), copper (Cu), tin (Sn), _ 〇, gold (Au) or silver (a _, and will be electrically connected to form Circuit elements within the semiconductor die 74. During assembly of the dual in-line package 64, the semiconductor die 74 is adhered to a gold-plated or adhesive material (e.g., thermal epoxy gambling). & 78 H ^ body comprises - an insulating encapsulating material, such as or ceramic. The remote imprint (4) and the bonding wire 82 provide electrical interconnection between the semiconductor die 74 and the board 52. The encapsulant 84 will Sealing and smearing the ββ I rice " hoarding in this, by preventing moisture and particles from entering the seal and contaminating the granules or wire 82 to achieve environmental protection purposes. ^ Grain: 2b The details of the bumps of the crystal plate 62 on the printed circuit board 52. The semiconductor die 88 is encased in the carrier 9 by using an underfill material or epoxy dot material 92. Top., Solder: 94 will provide a first layer of package interconnect between contact % and %. The mold compound or encapsulant 100 will be deposited on The conductor dies and the soldering material above the 'to provide physical support and electrical isolation for the device. The contact pad 102 will be printed in a suitable metal deposition process (10) such as electrolyte plating or electrodeless plating). Above the surface of the circuit board 52

Used to prevent oxidation. The contact & 1 2 will be electrically connected to - or a plurality of conductor signal lines 54 in the printed circuit board W. A plurality of bumps 1〇4 are formed between the contact pads 98 of the bump wafer carrier 62 and the contact pads 102 of the printed circuit board 52. In Fig. 2c, the semiconductor die 58 is inlaid into the interposer carrier 1〇6 in a face down manner using a flip chip pattern of the first layer package. The active g(10) of the semiconductor die 58 contains an analog circuit or a digital circuit that is acted upon by an active device, a passive device, a conductor layer, and a dielectric layer formed according to the electrical design of the die. For example, the circuit may include - or a plurality of electro-crystals 13 201123327 bodies, diodes, inductors, capacitors, resistors, and other circuit components that are formed in the active positive 〇8 net. The semiconductor die 58 is electrically and mechanically coupled to the carrier 106 via a plurality of bumps 11 。. Ball grid array 60 utilizes a plurality of bumps 112 to be electrically and mechanically coupled to printed circuit board 52 in a second layer package of ball grid array style. The semiconductor die 58 is electrically connected to the conductor signal line 54 in the printed circuit board 52 via the bumps 11 讯, the signal wires 14 and the bumps 112. A molding compound or encapsulant 116 is deposited over the semiconductor die 58 and the carrier 1' to provide physical support and electrical isolation for the device. The flip-chip semiconductor device provides a short electrical conduction path from the active device on the semiconductor die 58 to the via on the printed circuit board 52 to reduce signal propagation distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 is mechanically and electrically connected directly to the printed circuit board 52 using a flip chip pattern of the first layer package without the intermediate carrier 106. 3a to 3!, together with Figures i and 2a to 2c, for forming a polymer matrix synthetic substrate (for example, an epoxy resin molding compound (Epoxy Molding Ccmpound)) Integration

The process of passive component structure. In Fig. 3, a mesh/u W Μ Μ 〒 'chase mold 120 has an upper plate 120a and a lower plate i20h. -roa a 〇b removable tape 122 will be applied

To the upper plate i2〇a of the mold 120. A non-essential metal carrier 124 will be embedded in the lower plate 120b. The carrier plate 124 can also be used as a visitor, a polymer, a polymer composition, a ceramic, a glass, a glass, a enamel, a cerium oxide, a tape, or other suitable low-cost rigid materials. , for the purpose of achieving structural support. 14 201123327 The carrier board 124 is reused during the manufacturing process. Alternatively, carrier plate 124 may be used only once, such as a support tape or a plastic liner. A removable tape 126 is applied to the carrier 124. Both tapes 122 and 126 can be removed by mechanical or thermal stress. A laminate film 128 is formed over the removable tape 126. The film 128 may be metal (e.g., Cu and A1) or may have an optional priming to achieve other conductive materials with a preferred adhesion to the encapsulant. An open area 13〇 is disposed between the upper plate 1 20a and the lower plate 120b for dispensing the encapsulant material. In Figure 3b, an encapsulant material or molding compound 132 may utilize a compressive molding applicator, a transfer molding applicator, a liquid encapsulant molding applicator, or other suitable The coater is dispensed into the region 13A between the upper plate 120a and the lower plate 120b. The encapsulating agent 13 2 may be in the form of a liquid, a granule, or a powder or a thin layer of a synthetic material, for example, an epoxy resin having a filler, an epoxy acrylate vinegar having a filler, or having a content of 4 〇% up to 9.5 % of the polymer of the appropriate filler. When cured and removed from the mold 12, the encapsulant 132 will form a polymeric matrix composite substrate wafer or panel having a laminate film 128, as shown in Figure 3c. Alternatively, the laminated film 128 may cover the entire surface of the substrate 134. The polymer matrix composite substrate 134 has a high resistivity, a low loss tangent, a low dielectric constant, a Coefficient of Thermal Expansion (CTE) matching the above integrated passive component structure, and a good Thermal Conductivity. In FIG. 3d, the film layer 128 is patterned and etched to provide a conductor layer 128a to 128c of 15201123327 and to form a recess or dimple having a surface 138 in the polymer matrix composite substrate 134. Hole 136. The recess 136 will have a layer 128 of the surface that completely covers the surface of the panel 134, as appropriate. Individual portions of conductor layers 128a through 128c may be either co-electrical or electrically isolated depending on how the individual semiconductor dies are connected. In FIG. 3e, an unnecessary planarization germany layer 142 is formed over the polymer matrix composite substrate 134 and the conductor layer 128 to form one or more layers made of cerium oxide (SiO 2 ); Cerium nitride (Si3N4); bismuth oxynitride (SiON); bismuth pentoxide (Ta2〇5); bismuth trioxide (A1203); polymethyleneamine; cyclobutene (BCB); polybenzoxazole Fiber (PBO); WPR; or other suitable dielectric materials, especially polymeric photosensitive dielectric materials. The insulating layer 142 is used to planarize the surface of the surface molecular matrix composite substrate 134 after partial removal of the laminated film stack 28 to improve the step coverage of the subsequent deposition and lithography processing steps. Alternatively, the insulating layer 142 can serve as a dielectric for the capacitor component incorporating the passive component, as described below. The remaining integrated passive component structures described in Figures 3f to 3i do not have an optional planarization layer 142. In Figure 3f, an optional resistive layer 146 is formed over conductor surface 128a and surface 138 of substrate 134 using a physical vapor deposition process, a chemical vapor deposition process, or other suitable deposition process. In one embodiment, the resistive layer 146 may be a bismuth button (TaxSiy) or other metal cerium compound; TaN; nickel chrome (NiCr); titanium (Ti); titanium nitride (TiN); TiW) ; or a polycrystalline spine with a resistivity between 5 and 1 〇〇〇/sq. 16 201123327 An insulating or dielectric layer 148 is patterned over the resistive layer 146 by physical vapor deposition, chemical vapor deposition, printing, sintering or thermal oxidation. The insulating layer 148 may be one or more layers made of: SiO 2 ; Si 3 N 4 ; SiON ; Ta 2 〇 5 ; A1203 ; polytheneamine; cyclobutene; polybenzoxazole fiber; or other suitable Dielectric material. Other embodiments may be present for overlap between conductor layer 128a, resistive layer 146, and insulating layer 148. For example, the resistive layer 146 may be entirely inside the conductor layer 128a. In FIG. 3g, an insulating layer or passivation layer 150 is formed over conductor layer 128, resistive layer 146, and insulating layer 148 in the following manner: spin coating; physical vapor deposition, chemical vapor deposition, printing , sintering, or thermal oxidation. The insulating layer 150 may be one or more layers made of the following: SiO 2 ; Si 3 N 4 ; SiON ; Ta 205 ; A 1203 ; polytheneamine; cyclopentane unloading, polybenzo σ bite fiber; WPR; Other materials suitable for insulating properties and structural properties, especially polymeric photosensitive dielectric materials. A portion of the insulating layer 150 is removed to expose the conductor layer 128, the resistive layer 146, and the insulating layer 148. In Figure 3h, a conductive layer 152 is patterned using a physical vapor deposition process, a chemical vapor deposition process, a sputtering process, an electrolyte plating process, an electrodeless plating process, or other suitable metal deposition process. Formed over conductor layer 128, insulating layers 148 and 150, and resistive layer 146 to form individual portions or sections 152a through 152j. Conductor layer 152 may be one or more layers made of: Al, Cu, Sn, Ni, Au, Ag, Ti, TiW, or other suitable electrically conductive material. The conductor layer portions 152a to 152j of the individual 17 201123327 can be considered to be either electrically connected or electrically isolated depending on the connection of the individual semiconductor dies. An insulating or purification layer 154 is formed over the insulating layer 150 and the conductive layer 152 by spin coating, physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation. The insulating layer 154 may be one or more of I: s; 〇2; torn; "ΟΝ; Ta205; A1203; poly-styrene; benzophenone; polybenzo-x-sand fiber; Other materials having suitable insulating properties and structural properties, especially polymeric photosensitive dielectric materials, a portion of the insulating layer 154 will be removed 'to expose the conductor layer 152.: In Figure 3i, an optional conductive layer 156 may be formed over the conductor layer 152c using a physical vapor deposition process, a chemical vapor deposition process, a tantalum process, an electrolyte electrical forging process, an electroless plating process, or other suitable metal deposition process. The conductor layer 156 may One or more layers made of Ti, TiW, NiV, Cr, CrCu, A1, Cu, Sn, guilt, Au,

Ag or a suitable conductive material. In one embodiment, the conductor layer 16 6 is an under bump metallization (UBM) having a multilayer metal stack having an adhesive layer, a barrier layer, and a seed layer. Or wet the layer. The adhesive layer may be formed over the conductor layer 152c and may be Ti, TiN, Ti; w, octa or chromium. The barrier layer may be formed over the adhesive layer and may be Ni, deuterated nickel (ΝιV), platinum (Pt), palladium (Pd), TiW, or chromium chromide (CrCu). The barrier layer prevents Cu from diffusing into the active region of the die. The seed layer may be Cu, Ni, NiV, Au' or a. The seed layer may be formed over the early layer of the screen 18 201123327 p and act as a conductor layer 152c and subsequent solder bumps or other interconnects, 'The middle conductor layer between the structures. The under bump metal 165 provides a low resistance interconnect to the conductor layer 152c and provides a barrier layer that prevents solder from spreading and a seed layer for solder wettability purposes. A conductive bump material is deposited over the under bump metal 156 by an evaporation process, an electrolyte plating process, an electroless plating process, a pellet process, or a screen printing process. The bump material may be A1, Sn, Ni, Au,

Ag, Pb, Bi, CU, solder, and combinations thereof have an optional fluxing solution. For example, the bump material may be a Sn/pb eutectic alloy, a lead-free solder, or a lead-free solder. The bump material is soldered to the under bump metal iridium 65 using a suitable attachment or soldering process. In its eleventh embodiment, the bump material is reflowed by heating the material above its melting point to form a spherical pellet or bump 158. In some applications, the bumps 158 will be re-welded to improve electrical contact with the under bump metal 156. The s- 4 bumps can also be compression-welded to the underlying metal of the bumps. Bumps 158 represent one of the types of interconnect structures that can be formed over the under bump metal 156. The interconnect structure can also use bond wires 'conductive paste, stud bumps, microbumps, or other electrical interconnects. For example, a bonding wire 16〇 is formed over the conductor layer 1 52j·. The structures described in Figures 3 through 3 i may constitute a plurality of passive circuit elements or integrated passive elements 162. In one embodiment, the conductor layer 128a, the resistive layer 146, the insulating layer 148, and the conductor layer 152a are Metal Insulator Metal (MIM) capacitors. A resistive layer 146 between conductor layers 152() and 152d is a resistor element in the passive circuit. The individual conductor layer segments 152d through 1521, such as 19 201123327, may be wound or coiled in plan view to create or present the characteristics of the inductor material. The entire piece (6) may have any of a capacitor, resistor, and/or inductor... The integrated passive element structure 162 provides high frequency applications (eg, resonators, high pass ferrites, low pass ferrites, band pass choppers, = required for symmetrical high q-spectrum spectral transformers, matching networks, and capacitors. These integrated passive components can be used as front-end radio components, which may be placed between the antenna and the transceiver. The inductor may be a high-Q balun converter, transformer or coil operating at up to 100 terahertz. In some applications, multiple balun converters are formed on the same substrate. To allow multi-band operation. For example, in a mobile phone or other global mobile communication system (Gl〇bal System

Two or more balun converters are used in the quad (qUad_band) of Mobile (G S M) communication, and each balun converter is dedicated to an operating band of the quad-band device. A typical RF system requires the use of multiple integrated passive components and other high frequency circuits in one or more semiconductor packages to perform the necessary electrical functions. Conductor layer 152 may be a ground plane for the integrated passive component structure. The integrated passive component structure 162 formed over the polymeric matrix composite substrate 134 simplifies the manufacturing process and reduces or otherwise. A non-essential, temporary and reusable metal carrier will be used to construct the sacrificial molded compound wafer or panel. The polymer matrix composite substrate 134 provides a high resistivity coefficient, a low loss tangent, a low dielectric constant, a coefficient of thermal expansion that matches the structure of the integrated passive component, and a good thermal conductivity teaching. 201123327 Figures 4a through 4e illustrate another process for forming an integrated passive component structure over a polymer matrix composite substrate or epoxy resin molding compound substrate. In Fig. 4a, a mold 170 has an upper plate 170a and a lower plate 170b. A removable tape 172 is applied to the upper plate 17〇a of the mold 17〇. A removable tape 1 74 having non-essential adhesive properties is applied to the lower plate 170b. Both tapes 172 and 174 can be removed by mechanical or hot pressing. An encapsulant or molding compound i 76 is applied to the upper plate 17〇a and the lower plate by a compression molding coating plate, a transfer molding applicator, a liquid encapsulant molding applicator or other suitable applicator. Among the open areas between 17〇b. The encapsulant 176 may be a liquid, granular, or powdered synthetic material, for example, an epoxy resin having a filler having a filler of propylene, or having a content & 40% up to 95% A suitable filler polymer. After curing and removal from the mold m, the encapsulant 176 will form a polymeric matrix composite substrate wafer or panel 178, as shown in Figure 4b. The polymer matrix composite substrate 178 has a south resistivity, a low loss tangent, a low dielectric constant, a coefficient of thermal expansion matching the above integrated passive component structure, and a good rail coefficient. A non-essential (4) material is formed just above the polymer matrix composite substrate , to form a planarization layer with good insulating properties. In Figure 4c, a conductive layer 182 is formed using a physical vapor deposition process, a chemical vapor deposition process, a germanium process, an electrolyte, or other suitable metal deposition process to perform the interface (4) above and above the interface and the insulating layer. Above 180, to identify # or section 182a^82c. The conductor layer 182 may be one or more layers made by 21 201123327 below.

Al, Cu, Sn, Ni, Au, Ag, Ti, di-iw,

TiN or other suitable conductive material, Ti, T:iN or w is used as an adhesive layer or a barrier layer. The individual portions of conductor layer 182 may be either electrically or electrically isolated, depending on how the individual semiconductor die are connected. An optional resistive layer 184 is formed over the conductor layer 182a and the interface layer _ of the substrate 178 using a physical vapor deposition process, a chemical vapor deposition process, or other suitable deposition process. In an embodiment A, the resistive layer 184 can be made of TaxSiy or other metal telluride; TaN; (10) '· Ti; TiN; TiW; or the resistance type is between 5 and 1〇〇a. Doped polycrystalline stone. An insulating or dielectric layer 186 is patterned over the resistors 184 by physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation. The insulating material 186 may be one or more layers made of SiO 2 , Si 3 N 4 , Si 〇 N , Ta 2 〇 5 , Ai 2 〇 3 , polyimide; cyclobutene; benzo (tetra) fiber; Other suitable dielectric materials. An insulating layer or passivation layer 188 is formed over the conductor layer 182, the resistive layer 184, and the insulating layer 186 by: a planar coating; physical vapor deposition, chemical vapor deposition, printing, sintering, or Thermal oxidation. The insulating layer 188 may be one or more layers made of the following: _2; S!〇N; Ta2Q5; A1203; polyamidamine; benzophenone; polybenzopyrene fiber; WPR; Other materials for insulating properties and structural properties, especially polymeric photosensitive dielectric materials. A portion of the insulating layer 188 is removed to expose the conductor layer 182, the resistive layer 18 22 201123327 1 8 6 〇 In Figure 4d, a conductive layer υ霄 uses a physical roll deposition process to dry the phase deposition process, splash Recording 裎, "鲅 胄 胄 胄 电镀 电镀 电镀 、 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 无 : : : : : : : : : : : : : : : : : : : : : : : : : : : The % disk 1 rim edges 186 and 188, and the upper portion of the resistive layer 184 are used to form individual portions or sections to i9〇j. The conductor layer (10) may be made of - or a plurality of layers: A, Cu, Sn, Nl, Au,

Ag, Ti, TiW, TiN, 4 杲 JL The conductive material of the dead-Gan--匕5, Ti, TiN, or TiW acts as an adhesive layer or a barrier layer. The individual conductor layer portions im9Gj may be either co-electrically or electrically isolated, depending on how the individual semiconductor dies are connected. An insulating layer or passivation layer 192 may be formed on the insulating layer 188 and the conductor layer 190 by using the following method: spin coating; physical vapor deposition chemical vapor deposition, printing, sintering Or thermal oxidation. The singularity (4) 192 may be one or more layers made of Si2; Si3N4; Si〇N; / AU03; polyamidamine; benzoin; polybenzoic. Wow fiber; wr丨 or 其它 other materials with suitable insulating properties and structural properties, especially polymeric photosensitive dielectric materials. - Part of the insulation 4 192 is removed to expose the conductor layer 190. In FIG. 4e, a conductive layer 194 is formed on the conductor using a physical vapor deposition process, a chemical vapor deposition process, a sputtering process, an electrolyte plating process, an electrodeless electrodeposition process, or other suitable metal deposition process. Above layer 190c. The conductor layer 19 may now be one or more layers made of Ti, TiW, NiV, Cr, CrCu, A1, and below:

Cu, Sn, Ni, Au, Ag, 23 201123327 or other suitable conductive materials. In one embodiment, the conductor layer i 94 is a bump metal comprising a plurality of metal stacks having an adhesive layer, a barrier layer, and a seed layer or a wetting layer. The adhesive layer may be formed over the conductor layer 190c and may be Ti, TiN, TiW, Al, or Cr. The barrier layer will be formed over the adhesive layer and may be Ni, NiV, Pt, Pd, TiW, or CrCu. The barrier layer prevents Cu from diffusing into the active region of the die. The seed layer may be Cu, Ni, NiV, yttrium or yttrium 1. The seed layer will be formed over the barrier layer and serve as an intermediate conductor layer between the conductor layer 190c and subsequent solder bumps or other interconnect structures. The under bump metal 194 provides a low resistance interconnect to the conductor layer 190c and provides a barrier layer to prevent solder diffusion and a seed layer for solder wettability purposes. A conductive bump material is deposited over the under bump metal 194 by an evaporation process, an electrolyte plating process, an electroless plating process, a pellet process, or a screen printing process. The bump material may be A, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, which may have an optional fluxing solution. For example, the bump material may be a Sn/Pb co-alloy, a high-salt solder, or a fault-free solder. The bump material is soldered to the under bump metal 194 using a suitable adhesion or soldering process. In one of the embodiments, the bump material is reflowed by heating the material above its glare to form a spherical pellet or bump 196. In some applications, the bumps 196 are re-welded to improve the electrical contact with the underlying metal iridium 94. The bumps can also be compression welded to the under bump metal 194. Bumps 196 represent 24 201123327 of the type interconnect structure that can be formed over the under bump metal 194. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects. For example, bond wire 198 will be formed over conductor layer 19〇j. The structure described in 3 4b to 4e may constitute a plurality of passive circuit elements or integrated passive elements 200. In one embodiment, the conductor layer ma, the resist layer 184, the insulating layer 186, and the conductor layer 19A are a metal insulator metal capacitor. The resistive layer 184 between the conductor layers (10) and 190d is a f-resistor element in the passive circuit. The individual conductor layer segments (10) d to 190i are wound or coiled in plan view to create or present the characteristics of an inductor. The integrated passive component 2 may have any combination of capacitors, resistors, and/or inductors. The integrated passive component structure 200 provides high frequency applications (eg, resonators, high pass data filters, low pass data filters, band pass filters, symmetric high, constant value resonant converters, matching networks, and tuning capacitors) Required electrical characteristics ▲ These integrated passive components can be used as front-end wireless RF components, which may be placed between the antenna and the transceiver. The inductor may be a "value balun converter, transformer two coils operating at up to 100 terahertz. In some applications, multiple balun converters are formed on the same substrate. 'To allow for multi-band operation. For example, two or more balun converters are used in the quad-band of a mobile phone or other global mobile communication system, and each balun converter is dedicated to; quad-band: In an operating frequency band, a typical RF, 耵 耵 糸 system requires the use of multiple integrated passive 卞 弁匕 阿 阿 在一 在一 在一 在一 , , , , , , 在一 在一 导体 在一 导体 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一 在一19〇j may be a ground plane for integrating the passive element 25 201123327. The integrated passive component structure 200 formed above the polymer matrix composite substrate 178 will simplify the manufacturing process and reduce the cost. i 7 8 will provide high resistivity, low loss tangent, low dielectric constant, thermal expansion coefficient matching the structure of the integrated passive component, and good thermal conductivity. The system shown in Figure 5 is formed. Another integrated passive tl structure above a polymer matrix composite substrate. Using a mold, a polymer matrix composite substrate wafer or panel 210 is formed in the same manner as in Figure 4 & 210 has a high resistivity, a low loss tangent, a low dielectric constant 'matching the thermal expansion coefficient of the integrated passive component structure, and a good thermal conductivity. The conductive layer 21 2 uses a physical vapor deposition process, chemical vapor deposition. A process, a sputtering process, an electrolyte plating process, an electrodeless plating process, or other suitable metal deposition process for patterning is formed over the substrate 2 1 , to form individual portions or sections 2 12a to 2 12c. The conductor layer 212 may be one or more layers made of the following: 八卜cu, sn, ... '八心八^丁丁丁丁丁~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TiW acts as an adhesive layer or a barrier layer. The individual portions of conductor layer 212 may be either electrically or electrically isolated, depending on how the individual semiconductor dies are connected. An insulating or passivation layer 218 is formed over the conductor layer 212 by spin coating; physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation. The insulating layer 218 can be one or more layers made of Si2N2; Si3N4; Si〇N; Ta2〇5; Ai2〇3' poly 26 201123327 melamine, cyclobutene; polyphenylene And oxazole fiber; WPR; or other materials having suitable insulating properties and structural properties, especially polymeric photosensitive dielectric materials. A portion of the insulation I 218 will be removed to expose the conductor layer 212. The conductive layer 220 is patterned on the insulating layer 218 by using a physical vapor deposition process, a chemical vapor deposition process, a sputtering process, an electrolyte plating process, an electrodeless plating process, or other suitable metal deposition process. Above. The conductor layer 22 is an adhesive layer or a barrier layer such as T!, TiW, TiN, TaxSiy, and TaN. The conductor layer 22 is operated as the resistive layer of the integrated passive component structure. A conductive layer 222 is formed on the conductor by using a physical vapor deposition process, a chemical vapor deposition process, a sputtering process, an electroplating process, an electroless plating process, or other suitable metal deposition process for patterning. Above layer 220 is used to form individual portions or sections 222a through 222j. The conductor layer 222 may be one or more layers made of: A &&, , Au, Ag or other suitable electrically conductive material. The individual conductor layer portions 222a through 222j are either electrically or electrically isolated, depending on how the individual semiconductor die are connected. An insulating or passivation layer 224 is formed over insulating layer 218 and conductor layer 220; above 222: spin coating; physical vapor deposition, chemical vapor deposition, printing, sintering, or thermal oxidation. The insulating layer 224 may be one or more layers made of: si〇2; Si3N4; si〇N;

Ta205 ; A1203 ; Polyimine; Cyclobutene; Polybenzopyrene fibers; WPR; or other materials with suitable insulating properties and structural properties. 27 201123327 It is especially suitable for molecular photosensitive dielectric materials. A portion of the insulating layer 224 is removed to expose the conductor layer 222. A conductive layer 226 is formed over the conductor layer 222c using a physical vapor deposition process, a chemical vapor deposition process, a sputtering process, an electrolyte plating process, an electrodeless plating process, or other suitable metal deposition process. Conductor layer 226 may be one or more layers made of: a &, ^, Ni, Αιι, Ag or other suitable electrically conductive material. In one embodiment, the conductor layer 226 is a bump underlayer metal comprising a plurality of metal stacks having an adhesive layer, a barrier layer, and a seed layer or a wetting layer. The adhesive layer may be formed over the conductor layer 222c and may be Ti, TiN, TiW, Al or Cr. The barrier layer will be formed over the adhesive layer and may be Ni, NiV, Pt, Pd, TiW or CrCu. The barrier layer prevents Cu from diffusing into the active region of the die. The seed layer may be Cu, Ni, Ni V, Au or A1. The seed layer will be formed over the barrier layer and serve as an intermediate conductor layer between conductor layer 222c and subsequent solder bumps or other interconnect structures. The under bump metal 226 provides a low resistance interconnect connected to the conductor layer 222c and provides a barrier layer that prevents solder from spreading and a seed layer for solder wettability purposes. A conductive bump material is deposited over the under bump metal 226 by an evaporation process, an electrolyte plating process, an electroless plating process, a pellet process, or a screen printing process. The bump material may be a Sn, Ni, Au, Ag 'Pb, Bi, Cu, solder, and combinations thereof, which may have an optional fluxing solution. For example, the bump material may be a Sn/pb eutectic alloy, a high lead solder or a lead-free solder. The bump material is soldered to the underlying metal of the crucible 2 2 6 using a suitable 28 201123327 or soldering process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a spherical nine-body or bump 228. In some applications, the bumps 228 will be re-welded to improve electrical contact with the under bump metal 226. The bumps can also be compression welded to the conductor layer 226. Bumps 228 represent one type of interconnect structure that can be formed over bump underlying metal 226. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other; electrical interconnects. For example, a bonding wire 2 3 〇 will be formed over the conductor layer 222j. The structure illustrated in Figure 5 may constitute a plurality of passive circuit elements or integrated passive elements 232. In one embodiment, the conductor layer 212a, the insulating layer 218, the conductor layer 220, and the conductor layer 222a are metal insulator metal capacitors. The individual conductor turns 222d through 222i are wound or coiled in plan view to create or exhibit the characteristics of an inductor. The integrated passive component 232 may have any combination of capacitors, resistors, and/or inductors. The integrated passive component structure 232 provides the high frequency applications (eg, resonators, high pass filters, low pass filters, band pass filters, symmetric high q resonant transformers, matching networks, and tuning capacitors) Electrical characteristics. These integrated passive components can be used as front-end radio frequency components, which may be placed between the antenna and the transceiver. The inductor may be a high-Q balun converter, transformer, or coil at up to 100 terahertz. For some applications, multiple balun converters are formed on the same substrate to allow for multi-band operation. For example, 29 201123327 A quad-frequency command in a mobile phone or other global mobile communication system would use two or more balun converters, each of which is dedicated to an operating band of the quad-band device. A typical RF system requires the use of multiple integrated passive components and other high frequency circuitry in one or more semiconductor packages to perform the necessary electrical functions. Conductor layer 222j may be a ground plane that integrates the passive element structure. The integrated passive component structure 232 formed over the polymeric matrix composite substrate 210 simplifies the manufacturing process and reduces cost. The polymer matrix composite substrate 210 provides high resistivity, low loss tangent, low dielectric constant, thermal expansion coefficient matching the integrated passive component structure, and good thermal conductivity. An exemplary inductor 242 formed by the conductor layer 222 shown in FIG. 6 is shown in FIGS. 7a to 7ri, together with FIGS. i and 2a to 2c, for use on a south molecular matrix composite substrate. A process for forming an inductor. In the figure & a mold 250 has an upper plate 25A and a lower plate 25A. An optional (4) 252 that can be removed is applied to the upper plate 2 of the mold 25 。. - An optional metal carrier 254 will be inlaid into the lower plate. The carrier board may also be a stone building polymer, a molecular composite, a ceramic, a glass 'glass epoxy tree yttrium oxide yttrium' tape or other suitable low-cost rigid materials for the purpose of a structural branch. The carrier plate 254 is reused during the manufacturing process. A removable adhesive tape 256 is applied to the carrier 254. Both tapes 252 and 256 can be removed by mechanical or thermal stress. In Figure 7b, the encapsulant material or molding compound 260 is applied dropwise onto the top by a press 30 201123327 shrink coater, transfer molding applicator, liquid encapsulant applicator or other suitable applicator. The enamel encapsulant 260 in the open region between the plate 250a and the lower plate 25〇b may be a liquid, granular or powder form of a molecular synthetic material, for example, an epoxy resin having a filler, and a filler. Epoxy propylene (an acid ester or a polymer having a suitable filler content of from 40% up to 95%. After curing and being removed from the mold 25, the encapsulant 260 constitutes a polymeric matrix A composite substrate wafer or panel 264, for example, an epoxy resin molded compound substrate, as shown in the drawings. Figure 7d shows another method for forming the polymer matrix composite substrate. The mold 266 has an upper plate 266a and Lower plate 266b. A non-essential removable tape 268 having an adhesive layer is applied to the upper plate 266a of the mold. The optional removable tape 27 having an adhesive layer is applied to the lower portion. Plate 266b. Both tapes 268 and 27G can be mechanically Pressure or hot pressure to remove. - Encapsulant material or molded compound 16272 will utilize compressed if & soil coating, transfer molding applicator, liquid encapsulant molding machine or other suitable coating machine The method of being applied to the open area between the upper plate 266a and the lower plate 266b. The sputum sputum and the encapsulant 272 may be liquid, granular or powder.

The form of the surface molecule is synthesized as a crude material. For example, an epoxy resin with a filler, an epoxy resin with a filler, a p oxy acrylate, or a suitable filler having a content of from 40% up to 95%. polymer. After the field has solidified and is removed from the mold 266, the encapsulant 2 7 9 a.9?4, 2 will form a polymer matrix composite substrate wafer or panel 274.

The latex resin molding compound substrate is shown in the figure. The polymer matrix is incorporated into & I β T . The substrates 264 and 274 each have a high resistivity, 31 201123327 low loss tangent, a lower dielectric constant, a thermal expansion coefficient of the integrated passive component structure above, and a good thermal conductivity. In FIG. 7f, a blanket insulating layer or passivation layer 276 is formed over the top surface of the polymer matrix composite substrate 274 (or polymer matrix composite substrate 264) in the following manner: spin coating; physical vapor deposition, chemistry Vapor deposition, printing, sintering, or thermal oxidation. The insulating layer 276 may be one or more layers made of: SiO 2 ; Si 3 N 4 ; SiON ; Ta 2 〇 5 ; Ai 2 〇 3 ; linoleamide, cyclobutene; polybenzoxazole fibers; wpR; It is another material that has suitable insulating properties and structural properties. Alternatively, the insulating layer 276 can be formed in the mold 250 or 266 during the molding process using the interaction between the encapsulant and the release tape. An alternative embodiment of the blanket insulating layer 276 is formed over the top surface of the polymeric matrix composite substrate 274 as shown in Figure 7g. In addition, a blanket insulating layer (Si) 278 is formed on the bottom surface of the molecular matrix composite substrate 274 opposite to the top surface by the following method: spin coating; lamination; physical vapor deposition, chemical vapor phase Deposition, printing, sintering or heat. The insulating layer 278 may be one or more layers made of: (10);

Si3N4, SiON, Ta2〇5; A1203; polyamidamine; cycline; polybenzo (tetra) fiber; WPR; or other material having suitable insulating properties and structural properties. Alternatively, the insulating layer 276 can be formed into the mold 250 or 266 during the molding process using the interaction between the encapsulant and the release tape. The insulating layers and μ may be the same material having the same or different thicknesses. The pattern shown in the figure is formed by forming the blanket insulating layer 276 over the top surface of the polymer matrix composite substrate 32 201123327 274 and forming a blanket insulating layer or passivation layer 28 over the insulating layer a%. Examples: spin coating; lamination, physical vapor deposition, chemical vapor deposition, printing, sintering or thermal oxidation. The insulating layer 280 may be one or more layers made of:

Si02; Si3N4; SiON; Ta205; A1203; polymethyleneamine; cyclobutene-polyphenylene oxazole fiber; or other material having suitable insulating properties and structural properties. Insulation layers 276 and 278 are formed in mold 250 or 266 during the molding process. Fig. 7I shows an embodiment in which there is no insulating layer on either of the top surface and the bottom surface of the polymer matrix composite substrate 274. Following the embodiment of Figure 7f, a conductive layer 282 is patterned using a physical vapor deposition process, a chemical vapor deposition ploughing process, a sputtering process, an electrolyte plating process, an electroless plating process, or other suitable metal deposition process. Rain is formed over the insulating layer 276 to form individual portions or sections 282a through 282c, as shown in Figure 7j. The conductor layer 282 may be one or more layers made of the following: Al, Cu, Sn, Ni, Au, Ag, Ti, TiN, TiW or other suitable conductive materials, Ti, TiN or Tiw as a glue Sticky layer or barrier layer. The individual conductor layer portions 282a through 282c are either electrically or electrically isolated depending on how the individual semiconductor dies are connected. The conductor layer 282 shown in FIG. 7j is above the insulating layer 276; however, the conductor layer is also formed in the insulating layer and/or the polymer matrix composite substrate 274 in the embodiment of FIGS. 7 to 71. Above. In FIG. 7k, an insulating layer or passivation layer 284 is formed over the insulating layer 276 and the conductor layer 282 by the following method: spin coating; physical gas phase 33 201123327 deposition, chemical vapor deposition, printing, sintering Thermal oxidation. The insulating layer 284 may be one or more layers made of: si〇2; Si3N4; Si〇N; Ta205; A1203; polyamidamine; cyclobutene; polybenzoxazole fiber; WPR 'or其它 Other materials with suitable insulating properties and structural properties, especially polymeric photosensitive dielectric materials. The insulating layer 284 portion is used to planarize the surface of the polymer matrix composite substrate 274 to partially improve the step coverage of the subsequent deposition and lithography processing steps. In FIG. 71, a conductive layer 286 is formed by patterning using a physical vapor deposition process, a chemical vapor deposition process, a sputtering process, an electrolyte plating process, an electrodeless plating process, or other suitable metal deposition process. Above the conductor layers 282a to 282c and the insulating layer 284. Conductor layer 286 may be one or more layers made of: a, Cu, sn'Ni, Au'Ag, Ti, TiW or other suitable electrically conductive material. Conductor layer 286 is an adhesive or barrier layer. The adhesive layer may be Ti, TiN, Tiw, A1 or Cr. The barrier layer may be Ni, NiV, Pt, Pd, TiW or CrCu. The barrier layer prevents Cu from diffusing into the k-movement region of the die. The beta conductive layer 288 may use a physical vapor deposition process, a chemical vapor deposition process, a sputtering process, an electrolyte battery process, an electrodeless plating process, or Other suitable metal deposition processes are formed over conductor layer 286 to form individual portions or sections 288a through 288j. Conductor layer 288 may be one or more layers made of: A1, CU, Sn, sin, Au, Ag or other suitable electrically conductive material. The individual conductor layer portions 288a through 288j are either electrically or electrically isolated, depending on how the individual semiconductor die are connected. 34 201123327 In Figure 7m, an insulating or purification layer 292 is formed over insulating layer 284 and v conductor layer 288 by spin coating, physical vapor deposition, chemical vapor deposition, printing 'sintering, or Thermal oxidation. The insulating layer 292 may be one or more layers made of: Si〇2; Si3N4; SiON; Ta205; A1203; polymethyleneamine; cyclobutene; polybenzofluorene. Spherical fiber, WPR; or bismuth material with suitable insulating properties and structural properties, especially polymeric photosensitive dielectric materials. A portion of the insulating layer 292 will be removed to expose the conductor layers 288c and 288j. In FIG. 7n, a conductive layer 294 is formed over the conductor layers 288c and 28 8j to form a bump underlayer metal having a multilayer metal stack, and the metal stack has an adhesive layer, a barrier layer, And a seed layer or a wetting layer. The adhesive layer may be Ti, TiN, Tiw, A1 or Cr. The barrier layer may be Ni, NiV, Pt, Pd, TiW or CrCu. The barrier layer prevents Cu from diffusing into the active region of the die. The seed layer may be Cu Ni NiV, AU or a. The seed layer will be formed over the barrier layer and act as intermediate between the conductor layers 288c and 288 and subsequent solder bumps or other interconnect structures. Guide layer. Bump under layer gold > 1 294 will provide a

The electrical bump material utilizes low resistance interconnects of evaporation processes 288c and 28 8j and provides a barrier layer and seed for solder wettability. Layer 294 overlaps the edges of the vias in insulating layer 292.

The electrolyte plating process, the pill drop process, or the screen printing process is deposited under the bumps. The bump material may be A, Sn, Ni, Au, solder: and combinations thereof, which may have a non-essential 35 201123327 flux solution. For example, the bump material may be a Sn/Pb eutectic alloy, a high lead solder, or a lead-free solder. The bump material is soldered to the under bump metal 2 94 using a suitable attachment or soldering process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a spherical pellet or bump 296. In some applications, the bumps 296 are re-welded to improve electrical contact with the under bump metal 294. The special bumps can also be compression welded to the under bump metal 294» bumps 296 representing one of the types of interconnect structures that can be formed over the under bump metal 294. The interconnect structure can also use bond wires 'conductive paste, stud bumps, microbumps, or other electrical interconnects. The structures described in Figs. 7a to 7n, more specifically, the conductor layers 288e to 288i constitute an inductor formed over the polymer substrate. The individual conductor layer segments 288e through 288i will be used to create or present an inductor in a plan view. . The sensor structure 2886 to 288 will provide high frequency applications (eg, vibrators, high pass filters, low pass filters, bandpass filters, symmetric ground-valued spectral transformers, matching networks, and tonalization capacitors). The electricity required: levy. The inductor can be used as a front-end radio frequency component that can be placed between the antenna and the transceiver. The inductor $ may be an operation: a high-Q balun converter at 100 billion Hz, a transformer or - in some applications, multiple balun converters are formed on the same A, so that Multi-band operation is allowed. For example, in the mobile power system is the other, the four-frequency of the ball mobile communication system will be: two or more two-bar converters are used. Each of the balun converters is dedicated to the operation of the four-frequency device: 36 201123327 in the band. A typical RF system requires the use of multiple inductors and other south frequency circuits in one or more semiconductor packages to implement the necessary electrical functions. The inductor structures 288e to 288i formed over the molecular matrix composite substrate 274 simplifies the manufacturing process and reduces cost. A non-essential, temporary and reusable metal carrier will be used to construct the sacrificial molded compound wafer or panel. The polymeric matrix composite substrate 274 provides a high resistivity, low loss tangent, low dielectric constant, thermal expansion coefficient matching the integrated passive component structure, and good thermal conductivity. Although one or more embodiments of the present invention have been explained in detail herein, the skilled artisan will be able to make modifications and changes to the embodiments, which will not be removed from the scope of the patent application. The proposed scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a printed circuit board having different types of packages embedded in its surface; Figures 2a to 2c are further embedded in a representative semiconductor package of the printed circuit board. Details; Figures 3a to 3i are used to form a process for integrating a passive component over a polymer matrix composite substrate; Figures 4e are for a flat surface of a polymer matrix composite substrate. Another process for forming a passive component is formed above; Figure 5 is formed above the flat surface - integrated passive 37 201123327 component and square polymer matrix synthetic substrate; Figure 6 is The conductors for forming an inductor are wound; the processes shown in Figures 7a to 7n are used to form an inductor on a polymer matrix composite substrate. [Main component symbol description] 50 Electronic device 52 Printed circuit board (PCB) 54 Line 56 Wire bond package 58 Semiconductor die 60 Ball grid array (BGA) 62 Bump wafer carrier (BCC) 64 Dual in-line package (DIP) 66 Platform Grid Array (LGA) 68 Multi-Chip Module (MCM) 70 Square Flat Conductorless Package (QFN) 72 Square Flat Package 74 Semiconductor Die 76 Contact Pad 78 Intermediate Carrier 80 Conductor Conductor ' 82 Bond Wire 38 201123327 84 Encapsulant 88 Semiconductor die 90 Carrier 92 Adhesive material 94 Bond wire 96 Contact pad 98 Contact pad 100 Molding compound or encapsulant 102 Contact pad 104 Bump 106 Intermediate carrier ^ 108 Active area 110 Bump 112 bump 114 signal line 116 molding compound or encapsulant 120 mold 120a upper plate 120b lower plate 122 tape 124 metal carrier plate 126 tape 128 laminated film 128a-c first conductor layer 39 201123327 130 open region 132 encapsulant 134 high Molecular matrix synthesis substrate wafer or panel 136 cavity 13 8 surface 142 insulation layer 146 resistance layer 148 insulation layer or dielectric layer 15 0 insulation layer or purification layer 152 Electrical layer 152a-j Conductor layer 15 4 Insulating layer or purification layer 156 Conductor layer 158 Spherical pellet or bump 160 Bond wire 162 Integrated passive component structure 170 Mold 170a Upper plate 170b Lower plate! 172 Removable tape 174 Removable Tape 176 Encapsulant or Molding Compound. 178 Polymer Matrix Composite Substrate Wafer or Panel 180 Insulation Layer 201123327 182 Conductive Layer 182a-c Individual Portions or Sections 184 Resistive Layer 186 Insulation or Dielectric Layer 188 Insulation or Purification Layer 190 Conductive Layer 190a-j Individual Portions or Sections 192 Insulation or Purification Layer 194 Conductive Layer 196 Bumps 198 Bonding Wire 200 Passive Circuit Components or Integrated Passive Components 210 Polymer Matrix Composite Substrate Wafers or Panel 212 Conductive Layers 212a-c Individual Portions or Sections 218 Insulation or Passivation Layer 220 Conductor Layer 222 Conductive Layers 222a-j Individual Portions or Sections 224 Insulation or Purification Layers 226 Conductive Layers 228 Bumps 230 Bond Wires 232 Passive circuit component or integrated passive component 41 201123327 242 Exemplary Inductor 250 Mold 250a Upper Plate 250b Lower Plate 252 Removable Tape 254 carrier 256 removable tape 260 encapsulant material or molding compound 264 polymer matrix synthetic substrate wafer or panel 266 mold 266a upper plate 266b lower plate 268 removable tape 270 removable tape 272 encapsulation Agent 274 polymer matrix composite substrate wafer or panel 276 blanket insulation or passivation layer 278 insulation layer 280 blanket insulation or passivation layer 282 conductive layer 282a-c individual portion or section 284 insulation layer or passivation layer 286 conductive Layer 288 Conductive Layer 42 201123327 288a-j Individual Portions or Sections 292 Insulation or Passivation Layer 294 Bump Lower Metal or Conductor Layer 296 Spherical Pellets or Bumps 43

Claims (1)

201123327 VII. Patent application scope: 'It includes: ·* forming a first ι_ on the surface of a surface to form a polymer matrix composite substrate; forming a gastric insulating layer on the polymer matrix composite substrate; a second insulating layer is formed on the first insulating layer and the first conductive layer and the first conductive layer; and a second conductive layer is formed on the second insulating layer and the first conductive layer or the like Forming a third insulation on the second insulating layer and the first layer of the first layer of the second insulating layer to remove the second insulating layer of the second insulating layer to expose the second conductor and A bump is formed above the two conductor layers. 2. The method of claim i, wherein the forming the polymer matrix synthetic substrate comprises: providing a mold having a first plate and a second plate; and depositing a first layer over the first plate a removal layer; a metal carrier plate formed over the second plate; a second releasable layer disposed over the metal carrier; and between the first plate and the second plate of the mold An encapsulant material is deposited. 3. The method of claim 1, further comprising forming a third conductor layer between the conductor layer and the second conductor layer of the 201123327. 4. The method of claim 1, further comprising forming a fourth insulating layer over the second surface of the polymer matrix composite substrate, the second surface and the polymer substrate A surface is reversed. 5. The method of claim 1, further comprising forming a fourth insulating layer over the first insulating layer prior to forming the first conductor layer. 6. The method of claim 1, wherein the second conductor layer is wound to exhibit inductive characteristics. 7. A method of fabricating a semiconductor device, comprising: forming a molded substrate; 'forming a first conductive layer over the molded substrate; forming a first insulating layer over the molded substrate and the first conductive layer; Forming a second conductor layer over the first insulating layer and the first conductor layer; forming a second insulating layer over the first insulating layer and the second conductor layer; and forming a second conductive layer An interconnect structure. 8. The method of claim 7, wherein the forming the molded substrate comprises: providing a mold having a first flat plate and a second flat plate; and depositing a first removable layer above the first flat plate 45 i 201123327 右 夕 笛 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — The method of clause 7, further comprising forming a third conductor layer between the first body layer and the second conductor layer. 10. The method of claim 7, further comprising: forming a third insulating layer over a first surface of the molded substrate prior to forming the first conductive layer; A fourth insulating layer is formed over a second surface of the embossed substrate. The second surface is opposite to the first surface of the molded substrate. The method of claim 7, further comprising: forming a third insulating layer over a first surface of the molded substrate before forming the first conductive layer; and the third insulating layer A fourth insulating layer is formed over the layer. 12. The method of claim 7, wherein the second conductor layer is wound 'for presenting inductive characteristics. 13. The method of claim 7, wherein the interconnect structure comprises a bump or wire bond. 14. A method of fabricating a semiconductor device, comprising: forming a polymer matrix composite substrate; forming an inductor over the polymer matrix composite substrate; and forming an interconnect structure over the inductor. 15. The method of claim 14, wherein the forming of the polymer matrix synthetic substrate comprises: 46 201123327 providing a mold having a first plate and a second plate; and laying a layer above the first plate a first releasable layer; a second releasable layer disposed over the first plate; and an encapsulant material deposited between the first and second plates of the mold. 16. The method of claim 14, further comprising: forming a first conductor layer over the polymer matrix composite substrate; forming a first layer over the polymer matrix composite substrate and the first conductor layer An insulating layer; a second conductor layer is formed over the first insulating layer and the first conductor layer; a second insulating layer is formed over the first insulating layer and the second conductor layer; and ii is in the second conductor The interconnect structure is formed over the layer. The method of claim 16, further comprising forming a third conductor layer between the first conductor layer and the second conductor layer. 18. The method of claim 16, further comprising: forming a third insulating layer over the first surface of the polymer matrix composite substrate prior to forming the first conductor layer; A fourth insulating layer is formed over a second surface of the polymer matrix composite substrate, and the second surface is opposite to the first surface of the polymer matrix composite substrate. 19. The method of claim 16, further comprising: forming a third insulating layer over a first surface of the polymer matrix composite substrate 47 201123327 prior to forming the first conductor layer; A fourth insulating layer is formed over the third insulating layer. 20. A semiconductor device comprising: a polymer matrix synthetic substrate; :: a first conductor layer 'which will be formed over the polymer matrix composite substrate; a first insulating layer that will be formed Above the polymer matrix composite substrate and the first conductor layer; a second conductor layer formed over the first insulating layer and the first conductor layer; a second insulating layer, which is formed in Above the first insulating layer and the second conductor layer; and an interconnect structure 'which will be formed over the second conductor layer. 21. The semiconductor device of claim 2, further comprising a third conductor layer formed between the first conductor layer and the second conductor layer. 22. The semiconductor device of claim 20, further comprising: a third insulating layer 'which is formed over a first surface of the polymer matrix composite substrate; and a fourth insulating layer It is formed above a first surface of the polymer matrix composite substrate, and the second surface is opposite to the first surface of the polymer matrix composite substrate. 23. The semiconductor device of claim 2, further comprising: 48 201123327' comprising: a third insulating layer formed over a first surface of the polymer matrix composite substrate; and a first A fourth insulating layer that is formed over the third insulating layer. 24. The semiconductor device of claim 20, wherein the second conductor layer is wound to exhibit inductive characteristics. 25. The semiconductor device of claim 20, wherein the interconnect structure comprises a bump or a bonding wire. Eight, the pattern: (such as the next page) 49