SG171520A1 - Semiconductor device and method of forming an inductor on polymer matrix composite substrate - Google Patents

Semiconductor device and method of forming an inductor on polymer matrix composite substrate

Info

Publication number
SG171520A1
SG171520A1 SG201007560-4A SG2010075604A SG171520A1 SG 171520 A1 SG171520 A1 SG 171520A1 SG 2010075604 A SG2010075604 A SG 2010075604A SG 171520 A1 SG171520 A1 SG 171520A1
Authority
SG
Singapore
Prior art keywords
conductive layer
insulating layer
formed over
polymer matrix
matrix composite
Prior art date
Application number
SG201007560-4A
Inventor
Yaojian Lin
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/621,738 external-priority patent/US8158510B2/en
Priority claimed from US12/726,880 external-priority patent/US8791006B2/en
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of SG171520A1 publication Critical patent/SG171520A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. (Fig 3i)
SG201007560-4A 2009-11-19 2010-10-14 Semiconductor device and method of forming an inductor on polymer matrix composite substrate SG171520A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/621,738 US8158510B2 (en) 2009-11-19 2009-11-19 Semiconductor device and method of forming IPD on molded substrate
US12/726,880 US8791006B2 (en) 2005-10-29 2010-03-18 Semiconductor device and method of forming an inductor on polymer matrix composite substrate

Publications (1)

Publication Number Publication Date
SG171520A1 true SG171520A1 (en) 2011-06-29

Family

ID=44130330

Family Applications (3)

Application Number Title Priority Date Filing Date
SG2013027552A SG189780A1 (en) 2009-11-19 2010-10-14 Semiconductor device and method of forming an inductor on polymer matrix composite substrate
SG10201503210QA SG10201503210QA (en) 2009-11-19 2010-10-14 Semiconductor device and method of forming an inductor on polymermatrix composite substrate
SG201007560-4A SG171520A1 (en) 2009-11-19 2010-10-14 Semiconductor device and method of forming an inductor on polymer matrix composite substrate

Family Applications Before (2)

Application Number Title Priority Date Filing Date
SG2013027552A SG189780A1 (en) 2009-11-19 2010-10-14 Semiconductor device and method of forming an inductor on polymer matrix composite substrate
SG10201503210QA SG10201503210QA (en) 2009-11-19 2010-10-14 Semiconductor device and method of forming an inductor on polymermatrix composite substrate

Country Status (3)

Country Link
CN (1) CN102097301B (en)
SG (3) SG189780A1 (en)
TW (1) TWI498983B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
CN103876432B (en) * 2012-12-12 2016-09-14 深圳市神达实业有限公司 Solar mobile phone charging sheath
JP7148300B2 (en) * 2018-07-12 2022-10-05 上村工業株式会社 Conductive Bump and Electroless Pt Plating Bath
US10971446B2 (en) * 2018-11-30 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2749489B2 (en) * 1992-10-29 1998-05-13 京セラ株式会社 Circuit board
US6362012B1 (en) * 2001-03-05 2002-03-26 Taiwan Semiconductor Manufacturing Company Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications
JP2003101222A (en) * 2001-09-21 2003-04-04 Sony Corp Thin film circuit substrate unit and its manufacturing method
US8409970B2 (en) * 2005-10-29 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of making integrated passive devices

Also Published As

Publication number Publication date
TWI498983B (en) 2015-09-01
CN102097301B (en) 2016-06-15
CN102097301A (en) 2011-06-15
SG10201503210QA (en) 2015-06-29
TW201123327A (en) 2011-07-01
SG189780A1 (en) 2013-05-31

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