201121232 六、發明說明： 【發明所屬之技術領域】 本發明係制-種糊數財式的舰器截止辭校正電路，特別有 關-種·n鼓鮮校正電路，其根據觀半導_卫程變化㈣㈣ 而計算出被扭曲的時間常數變化率，且根據時間常數變化率棚數位方式 對截止頻率(cut-off frequency)進行校正。 【先前技術】201121232 VI. Description of the invention: [Technical field to which the invention pertains] The present invention is a system for correcting a ship's cut-off word for a variety of pastes, especially for a kind of n-drum fresh correction circuit, which is based on a semi-conductor The variation (4) and (4) are used to calculate the rate of change of the time constant that is distorted, and the cut-off frequency is corrected according to the time constant rate of change. [Prior Art]
電子工學大體上是-種對信號進行傳送、接收或處理的領域。從而， 在信號舰的難幅人其他不需⑽錢時，僅紐猶波騎據出需 要傳送的原先信號，尤其是類輯波器，其制在於：在信號傳送到數位 信號處理料之前’將錢成只有所需資_鮮的信號。 由於安裝於積體電路内的滤波器的截止頻率會隨著溫度變化或製程工 藝而發生變化’耻需賊其進行校正_止鮮校正電路。濾波器的截 止頻率是_分11的時間常數(time咖麵)決定的^於時間常數會隨著 溫度變化或餘工藝_化而_發生變化，喊止鮮校正電 時間常數維持一定值的功能^ ^吏Electronic engineering is generally an area where signals are transmitted, received, or processed. Therefore, when the signal ship's difficult person does not need (10) money, only the New York wave rides out the original signal that needs to be transmitted, especially the class filter, which is based on: before the signal is transmitted to the digital signal processing material. Put the money into a signal that only needs the resources. Since the cutoff frequency of the filter installed in the integrated circuit changes with the temperature change or the process process, it is necessary to calibrate the _ 止 校正 correction circuit. The cutoff frequency of the filter is determined by the time constant of _minute 11 (time coffee surface). The time constant will change with temperature change or residual process, and the function of keeping the fresh time constant constant will be maintained. ^ ^吏
在類比渡波器中截止頻率的準確度是決定信號品質的重要因素。但 是，以半導體來體現濾、波器時，工程變化使得辭相對於設計時所需的截 止頻率最多會有±25%的扭曲。Gm_c濾波器使賴比鎖相環㈣ 一ked —電路來對截止頻率進行調節。但是，有源電阻電」 ㈣讀：）遽波器為了能對電阻值、電容值、或電阻及電容值兩者進^ 節在有源電阻電谷;慮波器進行設計時，係利用電阻列及電容列L 201121232 止頻率進行調節β 第1圖疋用於調節類比滤波器截止頻率的電阻列的-般架構圖，第2 圖疋用於調節類比遽波器截止頻率的電容列的一般架翻。 s μ為了實驗目的而製作濾波料’有時會從晶片的外部手動輸入代碼來 調即截止鮮’但為了㈣目的啼際使贿波糾，需要增加可在晶片 勺將扭曲的截止頻率調節至原來的截止頻率的截止頻率校正電路。 根據祕的需求，至今對截止鮮校正電路翻了多種技術方案。 第如圖是採用數位铺鏈接庫（DLL)技術的截止鮮校正電路圖， 第3b圖為其時序圖。 請參照第3a圖及第％圖，由電阻和電容構成的無源據波器上施加時 鐘時，比較!!(0>)根據·器的特性而輸出的時鐘(D)與施加於紐器的時 鐘_)的鮮相同’但會有-定時__。當沒紅程變化而電阻 和電容轉正f辦，從_發__%職㈣私___ 脈波(LATCH CLK)的上升邊(rising edge)與比較卿雨㈣鐘⑼的上 升邊一致。但是，當由於工程變化而使得電阻和電容的值敎或變小時， 會使得比較器(CP)的輸出時鐘(D)的上升邊比延遲發生器所輸出的脈波 (LATCH OUT)的上升邊更晚錢早，檢測_咖㈣的上升邊位 置的結果傳制雜__ ，並_:__基本電阻 列代碼進行增加或減少-個位元㈣_程，從而找出能使延遲發生器的輸 tfjMdOi 與&較則CP)輸ά時鐘剛上升邊一致的 代碼後傳送至濾波器，從而調節截止頻率。 但是，由於該技術需要將上述—㈣触重複至達職止頻率為止， 201121232 因此存在濾波器充分過濾出信號的狀態所需時間過長的問題。 【發明内容】 本發明的主要目的在於提供一種濾波器截止頻率校正電路，其能利用 數位方式對起因於工程變化而被扭曲的濾波器截止頻率進行校正。 根據上述目的，本發明提供一種濾波器截止頻率校正電路，其輪入有 從第-電壓增加到第二電壓的階梯函數(卿―出時該濾波器截止頻率校 正電路包括：—次無源滤波器，其包括電阻和電容，所述-次無源據波器 對所述階梯函數進行積分而得到第三電壓；第一比較器，用以比較所述第 二電壓與已設定的第-基準電壓，當所述第三電壓高於已設定的第—基準 電壓時，所述第-比較ϋ輸出高頻信號；第二比較器，用以從施加所述第 二輕的時刻起到所述第—比較器輸出高頻信號的時刻為止的第—期間内 輸出高頻信號；計數器，其第—輸人端連接於所述第二比較器的輸出端， 第二輸入端連接於基準時鐘，所述計數器對所述第—綱崎輸入的基準 時鐘的數量進行計數；數錄塊，用關贿料妓魏的基準時鐘的 數量來計算dj舰__常㈣化率，並產生能校正所述時間常數變化 率的校正碼；以及毅^，用以根據職數健塊的校正碼⑽截止頻率 進行校正。 本發明的實施例中，—次就能計算出由紅程變化而改變的時間常數 變化率，數位區塊能夠根據時間常數變化率產生渡波器的校正碼，因此加 快了截止頻率補速度，從而可以縮短包域波器的系統的動作準備時間 (warming-up time) ° 另外，本發明的實施例中，可以由數位區塊計算出截止頻率校正碼， 201121232 因此還能夠提升數位區塊所占面積與截止頻率準確度之比。 【實施方式】 以下參照關紐本發_魏例進行雜，以使本發明所屬技 術領域具有通常知識的技術人員輯以實施。但是，本發明可以各種不同 的形態實施，而不限於本書提及的實施例。而且，為了明確地對本發 明進行’省略了與本發贿_部分，並且整個·書巾魏或結構 類似的元件使用相同的元件標號。 在整個說明書中，當提到某-元件與另一元件相“連接，，時，不僅包 括“直接連接”的情況’還包括在其中間隔著其他元件而“電連接，，的情 況。另外，當提到某個元件“包括”某些構成要素時，只要沒有特別說明， 則不等於繼其他_成要素，而是意味著還可吨祕他構成要素。 說明書中所記載的“…部”、“…器，，及“…模組，，等用語意味著能 處理至少-個功能或動作的單位’其可由硬體、軟體或硬體與軟體的結合 來實現。 以下，參照附圖對根據本發明實施的濾波器截止頻率校正電路進行詳 細說明。 第4圖是根據本發明實施的利用數位方式的濾波器截止頻率校正電路 的架翻’第5圖是根據本發明實施的利用數位方式的渡波器截止頻率校 正電路的時序圖。 如第4圖所示’根據本發明實施的利用數位方式的滤波器截止頻率校 正電路包括一次無源濾波器(1〇〇)、第一比較器(2〇〇)、第二比較器(3〇〇)、第 三比較器(400)、計數器(5〇〇)、數位區塊(6〇〇)及濾波器(7〇〇)。 201121232 此時，渡波器(700)包括多個電阻⑻和多個電容⑹，這些電阻⑻可以 由線性(linear array)架構及R-2R梯型(ladder)架構等架構構成，但本發明以 这些電阻(I⑽R_2R梯型架構來妨咖。這些電阻⑻及這些冑容⑹分別 連接有開關’ ®此可以透蝴關的接通及靖來調節雜印⑻)的電阻⑻ 值和電容(C)值》 -次無源濾波器(1〇〇)包括電阻(Rref )及電容(Cref)。電阻知）連接於 重置(RESET)端子，電容((¾的第—端連接於餘(Rref)和第二比較器(細) 的連接點’電容(Cref)的第二端接地。 -次無源濾;^⑽)為由電胁電容構成的紐^…次無源遽波器 (100)的輸出電壓(VRC)如以下公式卜The accuracy of the cutoff frequency in an analog waver is an important factor in determining signal quality. However, when semiconductors are used to represent filters and filters, engineering changes can cause distortions of up to ±25% relative to the cutoff frequency required for design. The Gm_c filter allows the Laby phase-locked loop (4) a ked-circuit to adjust the cutoff frequency. However, the active resistance is electrically charged. (4) Reading:) The chopper is used to measure the resistance value, capacitance value, or resistance and capacitance value in the active resistance electric valley. When designing the filter, the resistor is used. Column and capacitor column L 201121232 Stop frequency adjustment β Figure 1 is a general structure diagram of the resistor column used to adjust the cutoff frequency of the analog filter, and Figure 2 is used to adjust the capacitance column of the analog chopper cutoff frequency. Overturned. s μ for the purpose of the experimental production of the filter material 'sometimes manually input code from the outside of the wafer to adjust the cutoff fresh' but for the purpose of (four) to make the bribe wave correction, need to increase the cutoff frequency of the wafer scoop to adjust to The cutoff frequency correction circuit of the original cutoff frequency. According to the secret needs, a variety of technical solutions have been turned over for the cut-off fresh-correction circuit. The figure is a cut-off fresh-correction circuit diagram using the digital-paged link library (DLL) technology, and the third diagram is its timing diagram. Referring to Fig. 3a and Fig. %, when a clock is applied to a passive damper consisting of a resistor and a capacitor, the clock (D) outputted according to the characteristics of the device is compared with that applied to the device. The clock _) is the same as 'but there will be - timing __. When there is no red-cycle change and the resistance and capacitance are turned positive, the rising edge of the pulse_wave (LATCH CLK) from the ____% job (4) private ___ pulse is consistent with the rising edge of the comparative (4) clock (9). However, when the value of the resistor and capacitor is reduced or decreased due to engineering changes, the rising edge of the output clock (D) of the comparator (CP) is higher than the rising edge of the pulse (LATCH OUT) output by the delay generator. Later, the money is early, the result of detecting the rising edge position of _Caf (four) is transmitted __, and the _:__ basic resistance column code is increased or decreased by one bit (four) _ the process, thereby finding the delay generator The input tfjMdOi is transmitted to the filter after the code corresponding to the & CP is the same as the rising edge of the clock, thereby adjusting the cutoff frequency. However, since this technique requires repeating the above-mentioned (4) touch to the duty frequency, 201121232, therefore, there is a problem that the filter takes a long time to sufficiently filter out the state of the signal. SUMMARY OF THE INVENTION A main object of the present invention is to provide a filter cutoff frequency correction circuit capable of correcting a filter cutoff frequency which is distorted due to an engineering change by a digital method. According to the above object, the present invention provides a filter cutoff frequency correction circuit having a step function of increasing from a first voltage to a second voltage (the filter cutoff frequency correction circuit includes: - a passive filter And comprising: a resistor and a capacitor, wherein the step-by-pass data unit integrates the step function to obtain a third voltage; and the first comparator compares the second voltage with the set first reference a voltage, when the third voltage is higher than a first reference voltage that is set, the first comparison buffer outputs a high frequency signal; and a second comparator is configured to apply the second light timing to a first high frequency signal is outputted during a first period from the time when the comparator outputs the high frequency signal; a counter having a first input terminal connected to the output end of the second comparator and a second input terminal connected to the reference clock The counter counts the number of reference clocks input by the first-stage; the number-recording block calculates the dj ship __normal (four) rate by using the number of reference clocks of the bribes, and generates a correction Time constant a correction code of the rate; and a correction code for correcting according to the cutoff frequency of the correction code (10) of the job number block. In the embodiment of the present invention, the rate constant of the time constant changed by the change of the red range can be calculated. The digital block can generate the correction code of the wave filter according to the rate constant of the time constant, thereby speeding up the cutoff frequency compensation speed, thereby shortening the operation-up time of the system of the packet domain wave. Further, the implementation of the present invention In the example, the cutoff frequency correction code can be calculated from the digital block, and 201121232 can also improve the ratio of the area occupied by the digital block to the accuracy of the cutoff frequency. [Embodiment] The following is a reference to the key issue. The present invention may be implemented in various different forms, but is not limited to the embodiments mentioned herein. Moreover, in order to clearly omit the present invention, This is a bribe _ part, and the entire kerchief or structurally similar components use the same component numbering. Throughout the specification, when Mention that a certain element is "connected" to another element, and includes not only the "direct connection" but also the case where the other elements are "electrically connected". In addition, when referring to a certain element When "including" certain constituent elements, unless otherwise specified, it is not equal to the other _ into elements, but means that it can also be used as a constituent element. "...", "...", And "...module," and the like means a unit capable of handling at least one function or action' which may be implemented by hardware, software or a combination of hardware and software. Hereinafter, filtering according to the present invention will be described with reference to the accompanying drawings. The cutoff frequency correction circuit is described in detail. Fig. 4 is a flip chart of the filter cutoff frequency correction circuit using the digital method according to the present invention. FIG. 5 is a waveform cutoff frequency correction using a digital method according to the present invention. Timing diagram of the circuit. As shown in FIG. 4, the filter cutoff frequency correction circuit using the digital method according to the present invention includes a primary passive filter (1〇〇), a first comparator (2〇〇), and a second comparator (3). 〇〇), third comparator (400), counter (5〇〇), digital block (6〇〇) and filter (7〇〇). 201121232 At this time, the wave transformer (700) includes a plurality of resistors (8) and a plurality of capacitors (6), and the resistors (8) may be constituted by a linear array structure and an R-2R ladder structure, but the present invention uses these Resistor (I(10)R_2R ladder type architecture. These resistors (8) and these capacitors (6) are connected with a switch 'TM which can be turned on and the tuned (8) is adjusted for the resistance (8) value and capacitance (C) value. The secondary passive filter (1〇〇) includes a resistor (Rref) and a capacitor (Cref). The resistor is connected to the reset (RESET) terminal, and the capacitor ((the third end of the 3⁄4 is connected to the junction of the remaining (Rref) and the second comparator (thin), the second end of the capacitor (Cref) is grounded. Passive filter; ^(10)) is the output voltage (VRC) of the secondary passive chopper (100) composed of the electric shock capacitor, as shown in the following formula
VDD為透過重置端子輸人的電M，如第5騎示，Vdd電壓為從〇增加 到VDD的階梯函數(卿加ction)。由於透過重置端子輸入的階梯函數，一 次無源遽波器(100)的輸出電壓(Vrc)呈現如第5圖所示逐漸增加的波形。 第-比較器⑽)為運算放大器(〇perati〇namplifier)，其(+)端子連 次無源驗ϋ(·)的輸出端，㈠端子連接於基準電卿咖）。 第-比較器_對—次無源濾波器_的輸出電壓㈤和基準電產 OW進行比較後’輪出如第5圖的波形。當―次無麟波器_的輸出電 壓(vRC)低於基準龍(Vref)時，第一比較器⑽)輸出低頻㈣)信號卜 次無源濾卿00)的輸出峨Vrc)大於基準電M(v脏)的時刻起第一比較 器(200)輸出高頻(high)信號。 利用下面的公式2， 可計算出第一比較器⑽)輸出錄變成高頻信號 201121232 的時刻。 t = -RREFC· 111(1-¥卿 f vDD)[公式 2] 當基準電壓(Vref)固定於-定值的狀態下，將一次無源滤波器_的電 阻(Rref)和電容(¾)的值設為特定值，即可知道第一比較器阐的輸出信 號變成高頻信號的時刻。 因此，在本發日月的第三比較器(400)中，對重置端子上施加有I電壓 的時刻起到第-比較器_輸出高頻信號的時刻為止的期間㈣與透過公 式2而計算出來的時間⑴進行比較，從而可以預測出電哪赃)和電邮一 由於工程變化而改變了多少。 首先’第二比較器(3〇0)為運算放大器，其⑴端子連接於重置端子且(_) 端子連接於基準電壓(Vref)。此時，基準電壓(Vr£f)被設成低於V如電壓的 電壓。從而，當重置端子被施加〇 v的電壓時，第二比倾勘)輸出低頻 信號’當由於階梯函數而被施加Vdd電壓的時刻起，第二比較器⑼酬輸 出高頻信號。 第三比較器_為互斥（X0R)閘，其第一輸入端連接於第一比較器 (200)，第二輸入端連接於第二比較器(3〇〇)。 在第-比較器_的輸出信號和第二比較器⑽)的輸出信號的電位不 同的情況下’第三比較器(400)輸出高頻信號。如第5圖所示，第三比較器 (4〇〇)的馬頻信號在期間(tw)内被輸出，並可以期間(tw)作為脈波幅度的脈波 表現出來。 在本發明的實施例中’在重置端子與第三比較器(400)之間並連接有與 第-比健(20__比較H ’即第二比鮮(綱’因此可靖止比較器 201121232 本身的延遲（delay)對第三比較器(400)的脈波幅度(tw)造成的影響。 計數器(500)中’啟用端子(EN)連接於第三比較器(400)的輸出端，基準 時鐘(reference clock)被輸入至時鐘端子(CLK) 〇 如第5圖所示’具有脈波幅度(tw)的脈波從第三比較器(4〇〇)輸入的期間 内’計數器(5〇0)對所輸入的基準時鐘的數量進行計數。此時，根據計數器 (500)是增序計數器(up_counter)還是減序計數器(D〇WN c〇unter)，計數器 (500)的輸出數量(p)會不同。 在計數器(500)為增序計數器的情況下，增序計數器對在脈波幅度 内所輸入的基準時鐘的數量⑺進行計數並輸出至數位區塊(_)。 在計數器(5〇0)為減序計數器的情況下，減序計數器考慮好電阻供咖) 和電谷(CreF)後’對脈波幅度(tw)期間内所施加的基準時鐘的基準數量(Prc) 進订计算並提前蚊。够，纽過fja(RREF)和電容(c㈣)的值來計算出 來的脈波幅度(tw)為1〇 us ’且基準時鐘為4〇MHz時，減序計數器計算出來 的基準時鐘的基準數量會是彻。由於工程變化而使得依據電阻^)和電 今（REF)的純常數變小時，脈波幅度⑹會減小，從而會使減序計數器的 輸出數量(P)成為不能聊『，的正數值。相聽，由於工程幅使得依據 電_一和電容(CW)的時間常數變大時，脈波幅度⑹會增加，從而使減 序计數H的輸岐量⑺成為小於"G"的負數值。 數位&塊_)連接於計數器(5⑽)的輸出端且根據計數郎⑽)的輸出 數量(P)來計算出齡器㈣間常數變化率，並產生能對時間常數變化率進 行校正的校正碼。 數位&塊(600)可以按功能分為兩大部分。數位區塊⑼〇)其中一個功能 201121232 是，為了校域妓⑽)賴止___正躺核方向，判斷校正 碼應該是向降低遽波器⑽)的電阻⑻值和電容(c)值的方向生成，還是應該 向增加的方向生成。另—個功能是，決定應該按照指定的方向改變多少， 以生成校正碼。 數位區塊(6GG则找郎⑻)的輸出數量(p)來崎濾波即G〇)電阻 ⑻和電容(C)的時間常數(timecons㈣是隨著工程變化而增加還是減少。 當計數器(500)為增序計數器時，數位區塊_對輸出數量_數位區 _)0)中已設定的時鐘的基準數量㈣進行比較。數位區塊轉)在輸出數 量⑺大於基雜量(P·)時欺鱗，朗加，並卿降财阻⑻值和 電容⑹值的方向’當輸出數量(P)小於基準數量I)時判定為時間常數減 少，並選擇增加電阻⑻值和電容(C)值的方向。數㈣塊(6〇〇)產生用於校正 輸出數量(P)與基準數量(Pref)之差的校正碼。 當計數器(5〇〇)為減序計數器時，輸出數量(p)為正數時數位區塊⑽〇)判 定為時間常數減少，並選擇增加電阻(R)值和電容(c)值的方向，而輸出數量 (p)為負數時則判定為時間常數增加’並選擇減少電阻(R)值和電容⑹值的方 向。 數位區塊(6GG)可以透過如下的公式3計算崎紅程變化而變化的時 間常數變化率(a%)。 念100川公式3] 其中’ Prc為減序計數器中提前設定好的基準時鐘的基準數量。 接下來，數位區塊(600)利用時間常數變化率(a%)，透過如下公式4計 201121232 算出濾波器(700)的電阻(R)值和電容(〇值的校正值(m%)，以使濾波器(700) 的時間常數逹到所需的時間常數。 [公式 4] 另外’數位區塊(600)產生能使電阻(R)和電容(〇增加校正值(m%)大小 的校正碼，並輸出至濾波器(700)。此時，濾波器(7〇〇)根據由數位區塊(6〇〇) 輸入的校正碼’對電阻(R)和電容(C)的值進行校正，由此可以對濾波器(7〇〇) 的截止頻率進行校正。 第6圖是根據本發明實施的濾波器(700)的電阻架構示意圖。 如第6圖所示，當多個電阻取)為R_2R梯型架構的情況下，根據校正 碼(code)的電阻(R)的校正值(Reff)如公式5。VDD is the electric power input through the reset terminal. As shown in the fifth riding, the Vdd voltage is a step function (clearing ction) that increases from 〇 to VDD. Due to the step function input through the reset terminal, the output voltage (Vrc) of the primary passive chopper (100) exhibits a gradually increasing waveform as shown in Fig. 5. The first comparator (10) is an operational amplifier (〇perati〇namplifier), the (+) terminal is connected to the output of the passive test (·), and the (1) terminal is connected to the reference battery. The output voltage (f) of the first-comparator_parallel-passive filter_ is compared with the reference power OW, and the waveform as shown in Fig. 5 is rotated. When the output voltage (vRC) of the sub-no-waver_ is lower than the reference dragon (Vref), the first comparator (10) outputs the low-frequency (four)) signal, and the output 峨Vrc) of the passive filter 00) is greater than the reference power. The first comparator (200) outputs a high frequency signal from the moment M (v dirty). Using Equation 2 below, the time at which the first comparator (10) outputs the high frequency signal 201121232 can be calculated. t = -RREFC· 111(1-¥卿f vDD) [Formula 2] When the reference voltage (Vref) is fixed at a constant value, the resistance (Rref) and capacitance (3⁄4) of the passive filter _ will be used once. The value of the value is set to a specific value, and the time at which the output signal of the first comparator becomes a high frequency signal can be known. Therefore, in the third comparator (400) of the present day and the month, the period when the I voltage is applied to the reset terminal is the period (four) from the time when the first comparator outputs the high frequency signal, and the equation 2 is transmitted. The calculated time (1) is compared so that it can predict how much electricity and how much the email has changed due to engineering changes. First, the 'second comparator (3〇0) is an operational amplifier whose (1) terminal is connected to the reset terminal and the (_) terminal is connected to the reference voltage (Vref). At this time, the reference voltage (Vr£f) is set to a voltage lower than V such as voltage. Thus, when the reset terminal is applied with the voltage of 〇 v, the second ratio is outputted as the low frequency signal '. When the Vdd voltage is applied due to the step function, the second comparator (9) outputs the high frequency signal. The third comparator_ is a mutually exclusive (X0R) gate having a first input coupled to the first comparator (200) and a second input coupled to the second comparator (3〇〇). The third comparator (400) outputs a high frequency signal in the case where the potential of the output signal of the first comparator_ and the output signal of the second comparator (10) are different. As shown in Fig. 5, the horse frequency signal of the third comparator (4 〇〇) is outputted during the period (tw), and can be expressed as a pulse wave of the pulse wave amplitude during the period (tw). In the embodiment of the present invention, 'between the reset terminal and the third comparator (400) and connected with the first-birth (20__ compares H', that is, the second ratio is fresh (the program 'so can be compared to the comparator The effect of the delay of the 201121232 itself on the pulse amplitude (tw) of the third comparator (400). The enable terminal (EN) in the counter (500) is connected to the output of the third comparator (400), The reference clock is input to the clock terminal (CLK). As shown in Fig. 5, the pulse with the pulse amplitude (tw) is input from the third comparator (4〇〇). 〇0) Count the number of input reference clocks. At this time, according to whether the counter (500) is an up-counter (up_counter) or a down-sequence counter (D〇WN c〇unter), the number of counters (500) is output ( p) will be different. In the case where the counter (500) is an up-sequence counter, the up-sequence counter counts the number of reference clocks (7) input within the pulse amplitude and outputs it to the digital block (_). 5〇0) In the case of a down-sequence counter, the down-sequence counter considers the good resistance for the coffee) and the electric valley (CreF) The reference number (Prc) of the reference clock applied during the amplitude (tw) period is calculated and pre-set by the mosquito. The pulse amplitude (tw) calculated by the values of fja (RREF) and capacitance (c (4)) is When 1〇us ' and the reference clock is 4〇MHz, the reference number of the reference clock calculated by the down-sequence counter will be completely. Due to the engineering change, the pure constant according to the resistance ^) and the current (REF) becomes small. The wave amplitude (6) is reduced, so that the output quantity (P) of the down-sequence counter becomes a positive value that cannot be chatted. In contrast, since the time constant of the electric__and capacitance (CW) becomes larger due to the engineering width, the pulse amplitude (6) increases, so that the output quantity (7) of the descending count H becomes less than the negative of "G" Value. The digit & block_) is connected to the output of the counter (5(10)) and calculates the constant rate of change between the ages (4) based on the number of outputs (P) of the count lang (10), and produces a correction that corrects the rate constant of the time constant. code. The Digit & Block (600) can be divided into two major parts by function. Digital block (9) 〇) One of the functions 201121232 is that, in order to correct the ___ lie in the nucleus direction, the correction code should be the resistance (8) value and the capacitance (c) value of the chopper (10). The direction of the generation, or should be generated in the direction of increase. Another function is to decide how much to change in the specified direction to generate a correction code. The number of outputs of the digital block (6GG is lang (8)) (p) is the filter (ie G 〇) the time constant of the resistor (8) and the capacitor (C) (timecons (four) is increasing or decreasing with engineering changes. When counter (500) In order to increase the counter, the digital block _ compares the reference number (four) of the clock set in the output quantity_digit area _)0). The digital block turns) when the output quantity (7) is greater than the base amount (P·), the bully scale, the Langa, and the wealth reduction (8) value and the capacitance (6) value direction 'when the output quantity (P) is less than the reference quantity I) It is determined that the time constant is decreased, and the direction in which the resistance (8) value and the capacitance (C) value are increased is selected. The number (four) block (6 〇〇) generates a correction code for correcting the difference between the number of outputs (P) and the number of references (Pref). When the counter (5〇〇) is the down-sequence counter, when the number of outputs (p) is a positive number, the digit block (10) 〇) is determined to be a time constant reduction, and the direction of increasing the resistance (R) value and the capacitance (c) value is selected. When the output quantity (p) is a negative number, it is determined that the time constant is increased 'and the direction of decreasing the resistance (R) value and the capacitance (6) value is selected. The digital block (6GG) can calculate the rate constant change rate (a%) of the change in the saturation of the redness by Equation 3 below. Read 100 River Formula 3] where ' Prc is the reference number of the reference clock set in advance in the down-sequence counter. Next, the digital block (600) calculates the resistance (R) value and the capacitance (corrected value of the 〇 value (m%) of the filter (700) by using the time constant change rate (a%), by the following formula 4, 201121232, In order to make the time constant of the filter (700) to the required time constant. [Equation 4] In addition, the 'digital block (600) can generate the resistance (R) and the capacitance (〇 increase the correction value (m%) size The correction code is output to the filter (700). At this time, the filter (7〇〇) performs the values of the resistance (R) and the capacitance (C) according to the correction code 'entered by the digital block (6〇〇). Correction, thereby correcting the cutoff frequency of the filter (7〇〇). Fig. 6 is a schematic diagram showing the resistance structure of the filter (700) according to the implementation of the present invention. As shown in Fig. 6, when multiple resistors are taken In the case of the R_2R ladder type architecture, the correction value (Reff) according to the resistance (R) of the correction code is as Equation 5.
Reff =Reff =
1.2R 1 + 0.25χ code +1 [公式5：| 從而’在預設代碼(defaultcode)的狀態下用於對電阻⑻進行m%的變化 的校正碼(code)如下公式6。1.2R 1 + 0.25 χ code +1 [Formula 5: | Thus] The correction code for m% change of the resistance (8) in the state of the default code (default code) is as follows.
__n m \2R l7〇.25x-(defiultC^±I( +I〇Q =r+〇25xgggII [公式 6] 25 · 公式6中的“code”為濾波器(700)的電阻(幻的校正碼，數位區塊(6〇〇) 内安裝有根據校正值(m%)來計算出電阻(R)的校正碼表。 第7圖是根據本發明實施的遽波器(7〇〇)的電容架構示意圖第8圖是 根據本發明實施的電容的校正碼表的示意圖。 如第7圖所示’多個電容(〇被並列連接且每個電容(c)上連接有開關 時數位區塊(600)内安裝有如第8圖的表，從而可以根據校正值扣％)來計 算出電容(C)的校正代碼。 201121232 更具體地講’第8圖中開關的數字表示第7圖的開關符號，第8圖中 的開關符號意味著接通(on)相應開關的意思。即，數位區塊(6〇〇)產生能夠根 據校正值(m%)而從多個開關中選出需要接通及切斷的開關的校正碼，由此 可以調節濾波器(700)的電容(C)值。 本發明的實施例中，根據構成濾波器(700)的電阻(R)和電容(c)的特性， 可以選擇性地降低或增加電阻⑻和電容(c)的值。例如，可以只降低或增加 電阻(R)值’可以只降低或增加電容(c)值，可以一起降低或增加電阻⑻值 和電容(C)值。 综上所述，本發明實施例中對截止頻率進行校正，以使遽波器⑺騎 設計的時間常數能夠維持在一定值。 综上所述’雖然本發明已用較佳實施例揭露如上，然其並非用以限定 本發明’本發日月所屬技術領域中具有通常知識者，在不脫離本發日月之精神 〃圍内_可作各種之更動細飾，因此本發明之保護細當視後附之 申請專利細所狀者為準。 【圖式簡單說明】 第1圖是用於調節類比遽波器截止頻率的電阻列的-般架構圖； 第2圖疋用於調節類比滤波器截止頻率的電容列的一般架構圖； 第如圖是細触絲鏈麟技術喊賴輪正電路圖； 第3b圖是第3a圖巾的截止鮮校正電路的時序圖； ^岐根縣㈣實蘭數字赋㈣妓餘鮮校正電路 構 , 第5圖是根據本發明實施的利用數字模式的濾波器截止頻率校正電路 12 201121232 的時序圖； 第6圖是根據本發明實施的濾波器(700)的電阻架構示意圖； 第7圖是根據本發明實施的濾波器(700)的電容架構示意圖； 第8圖是根據本發明實施的電容的校正碼表的示意圖。 【主要元件符號說明】__n m \2R l7〇.25x-(defiultC^±I( +I〇Q =r+〇25xgggII [Equation 6] 25 · The "code" in Equation 6 is the resistance of the filter (700) (phantom correction code, A correction code table for calculating the resistance (R) based on the correction value (m%) is mounted in the digital block (6〇〇). Fig. 7 is a capacitance structure of the chopper (7〇〇) according to the present invention. Figure 8 is a schematic diagram of a calibration code table of a capacitor according to an embodiment of the present invention. As shown in Fig. 7, a plurality of capacitors (〇 are connected in parallel and a digital block (600) is connected to each capacitor (c). The table as shown in Fig. 8 is installed so that the correction code of the capacitance (C) can be calculated based on the correction value.) 201121232 More specifically, the number of the switch in Fig. 8 indicates the switch symbol of Fig. 7, The switch symbol in Fig. 8 means that the corresponding switch is turned on. That is, the digital block (6〇〇) is generated from the plurality of switches according to the correction value (m%), which needs to be turned on and cut. The correction code of the broken switch, whereby the capacitance (C) value of the filter (700) can be adjusted. In the embodiment of the present invention, according to the resistance (R) constituting the filter (700) and The characteristic of the capacitor (c) can selectively reduce or increase the values of the resistor (8) and the capacitor (c). For example, the resistance (R) value can be reduced or increased only by reducing or increasing the value of the capacitor (c). The resistance (8) value and the capacitance (C) value are reduced or increased. In summary, the cutoff frequency is corrected in the embodiment of the present invention so that the time constant of the chopper (7) riding design can be maintained at a certain value. 'Also, the present invention has been disclosed in the above preferred embodiments, and it is not intended to limit the invention to the general knowledge of the technical field of the present invention, and may be used without departing from the spirit of the present invention. All kinds of movements and fines, so the protection of the present invention is subject to the details of the patent application attached. [Simplified description of the drawing] Figure 1 is a resistor column for adjusting the cutoff frequency of the analog chopper - General architecture diagram; Figure 2 is a general architecture diagram of the capacitor column used to adjust the cutoff frequency of the analog filter; the first figure is the schematic diagram of the thin-touch chain technology, and the third diagram is the cut-off of the 3a towel. Timing diagram of fresh correction circuit; ^岐根县The Fig. 5 is a timing chart of the filter cutoff frequency correction circuit 12 201121232 using the digital mode according to the present invention; and Fig. 6 is a filter (700) implemented according to the present invention. FIG. 7 is a schematic diagram of a capacitor structure of a filter (700) according to an embodiment of the present invention; and FIG. 8 is a schematic diagram of a calibration code table of a capacitor according to an embodiment of the present invention.
100 一次無源遽波器 200 第一比較器 300 第二比較器 400 第三比較器 500 計數器 600 數位區塊 700 遽波器 13100 primary passive chopper 200 first comparator 300 second comparator 400 third comparator 500 counter 600 digital block 700 chopper 13