201121029 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-種半導體封 是有關於一種具貫穿孔之堆疊式封及^造方』 【先前技術】 在半導體製程中，爲了保護自晶圓上切割下來的晶 片’現今已提出各種關於晶片的封裝結構與封裝方法。封 裝結構能保護晶片不受外界環境的熱量、濕氣、電荷或其 •他非預期因素的影響，以提升晶片的穩定性與工作性能。 隨著半導體元件朝向積集化及輕量化的趨勢，晶片之 封裝技術亦朝向微型化及高密度化發展。因此，球格陣列 封裝（Ball Grid Array，BGA)、晶片尺寸封裝（Chip—Scale Package，CSP)、覆晶式封裝(Flip Chip Package, F/C Package) 與多晶片模組(Multi - Chip Module，MCM)等，各種高密度 的封裝技術隨之應運而生。 在封裝過程中，一般會利用封膠來覆蓋各種元件，例 • 如晶片、基板、銲線等，以保護各個元件免於受損及受潮。 然而’基於封膠的絕緣特性，當欲將數個封裝體堆疊在一 起時’封膠會導致各個封裝體之間難以電性連接，因而增 加其互相堆疊的困難度。 有鑑於此’需要一種具創新性與進步性的封裴結構及 其製造方法，以解決上述之問題。 【發明内容】 本發明之目的，係提供一種具貫穿孔之堆疊式封裝結 201121029 貫穿封膠與基板的貫穿孔及導電材 繼之間紐連= -第士::提:之堆叠式封裝結構，其包含 笫土板 第一封膠、數個貫穿孔、數個導雷 s -封裝體。第1膠至少覆蓋第—基板。此些=枓與 工封膠。此些導電材料分別位於此4; 孔：並錢連接第一基板與封裝體。封裝體堆聂穿 封膠之上，並電性連接此些導電材料。 -於第- 含步封;結:之製造方法 與第-基板，以形成數個貫穿孔。形成數=封膠 些貫穿孔中，並電性連接此些 4於此 -封裝體於第-封心卜，二*板。堆疊 材料。 封膠之上’並電性連接封裝體與此些導電 含至種具貫穿孔之堆疊式封裝結構，盆包 =二每-_具有-基板二 些貫穿孔中，並電以：此些導電材料分別位於此 含至孔之，封裝結構，其包 料。每一封裝體具且有二:貫穿孔和數個導電材 此些貫穿孔均貫穿每。封膠至少覆蓋基板。 發月更提出一種堆叠式封穿社 χ 含步驟有:提供數個封裝體方法，其包 展遛具有一基板與一 201121029 封膠，且封膠至少覆蓋基板。堆疊此些封裝體。貫穿〜 - _裝體之基板與封膠’以形成數個貫穿孔。形成數個 材料於此些貫穿孔中，以電性連接此些導電材料與封裝體。 綜上所述，利用數個貫穿孔及數個位於此些貫穿孔 的導電材料，作為各個封裝體之間電性連接的管道。藉此 可增加堆疊式封裝結構中電性連接管道的密度。 ， 【實施方式】 請參考第1圖，其繪示本發明具貫穿孔之堆疊式封 0 結構之第一實施例的剖面圖。堆疊式封裝結構100包含二 第一封裝體102與一第二封裝體104。第一封裝體1(^具 有一第一基板no、一第一封膠130、數個貫穿孔14〇與ς 個導電材料150。第一封膠130至少覆蓋第一基板11〇:此 些貫穿孔140均貫穿第一基板11〇與第一封膠13〇。此此 導電材料150分別位於此些貫穿孔14〇中。 ‘ 第二封裝體104堆疊於第一封膠13〇之上。此些導電 材料150電性連接第一基板11 〇與第二封裝體丨〇4，使得 第一封裝體102與第二封襄體1〇4電性連接。 • 由此可知，利用貫穿第一封膠130與第一基板11〇的 貫穿孔140及導電材料150，可作為第一封裝體1〇2的第 一基板110與第二封裝體104之間電性連接的管道。 第一封裝體102可具有一第一晶片120(或電子元件）， 第一晶片120位於第一基板11 〇上，並電性連接第一基板 110。具體來說，第一晶片120可透過數個銲球160或數個 . 銲線(未繒'示）電性連接第一基板11 〇。第一封膠130覆蓋第 一晶片120，以保護第一晶片120不受外界環境的影響。 上述之貫穿孔140貫穿第一基板11〇及其上的第一封 5 201121029 膠130，並分別在第一基板110與第一封膠130上形成數 個開口。具體來說，第一基板110具有相對的第一面114 和第二面116,第二面116面對第一晶片120。第一封膠130 具有一表面134。此些貫穿孔140具有數個第一開口 142 與數個第二開口 144,此些第一開口 142位於第一基板110 的第一面114，此些第二開口 144位於第一封膠130的表 面134。此些導電材料150分別位於此些貫穿孔140中， 並自第一開口 142延伸至第二開口 144。 為了使此些導電材料150電性連接第一基板110，第 ^ 一基板110上可設置數個銲墊170(或導線），以接觸此些導 電材料150。此些銲墊170分別位於第一面114的第一開 口 142處，並電性連接此些導電材料150，且此些銲墊170 被此些貫穿孔140所貫穿。 為了使此些導電材料150電性連接第二封裝體104, 第一封裝體102可具有數個導電元件172。此些導電元件 172分別位於此些貫穿孔140的第二開口 144處，並遮覆 或圍繞此些第二開口 144，且電性連接此些導電材料150。 第二封裝體104可透過數個凸塊176連接此些導電元件 • 172，進而電性連接到此些導電材料150。另選地，第二封 裝體104亦可直接接觸此些導電材料150,而不需透過此 些導電元件172或此些凸塊176。 為了穩固此些導電材料150、第一基板110與第二封 裝體104之間的電性連接管道，第一封裝體102可具有數 個導電層152。此些導電層152分別位於此些貫穿孔140 的内壁，並用以電性連接第一基板110與第二封裝體104。 此外，封裝結構100亦可包含數個凸塊174，此些凸 塊174分別位於此些第一開口 142處，並設置於此些銲墊 6 201121029 170上’ W電性連 請參考第2A圖至：1 電路(未繪不)。 堆疊式封裝結構的製程^圖圖，狀示第1圖具貫穿孔之 如第2A圖所干 首先為設置一第一’曰、。隹疊式封裝結構之製造方法， 上，並透過數個^曰片120(f，子元件）於一第一基板110 第一基板110。^ (或知線)電性連接第一晶片120與 和第一晶M 以一第一封膠13〇覆蓋第一基板110 弟日曰片U0’以保護第一基板11〇及第一晶片12〇。 以妒魏彳所7F。貫穿第—娜13G與第-基板110 ’ 之‘一 & η貝穿孔、140。此些貫穿孔14。會在第一基板110 4形成數個第一開口 142，並在第一封膠130 之面134形成數個第二開口 144。在第-實施例中，可 ，先形成數個銲塾17G於第-基板11G的第-開口 142 地。在形成此些貫穿孔14〇日寺’可使此些孔14〇分別 貫穿此些銲墊170。 如第2C圖所示。完成此些貫穿孔140後，可形成數個 導電層I52於此些貫穿孔⑽的内壁，並使此些導電層⑸ 接觸第一基板110上的銲塾17〇。 如第2D圖所示。形成數個導電材料150於此些貫穿 孔140中。可將此些導電材料ι5〇連接此些導電層ι52與 此些銲塾17G ’以電性連接此些導電材料15()與第一基板 110。進一步地，可形成數個導電元件172於第一封膠130 上的第二開口 144處，並電性連接此些導電元件172與此 些導電材料150。 最後，如第1圖所示。再堆疊一第二封裝體1〇4於第 =封膠130上’並電性連接第二封裝體1(M與此些導電材 料150。第二封裝體1〇4的種類與結構可依據實務設計所 201121029 需而變動。舉例來說’第二封裝體104可具有一第二基板 • 112、一第二晶片122與一第二封膠132。第二基板112位 於第一封膠130之上’並可透過數個凸塊176與此些導電 元件172電性連接此些導電材料150。第二晶片122位於 第二基板112上’並可透過數個銲線162(或銲球）電性連接 第二基板112。第二封膠132覆蓋第二基板in、第二晶片 122與此些銲線162。 請參考第3圖，其繪示本發明具貫穿孔之堆疊式封裝 結構之第二實施例的剖面圖，第3圖與第1圖之堆疊式封 φ 裝結構100相似。在第3圖中’第一封裝體1〇2可不需形 成此些導電材料150於此些貫穿孔140中，只需形成此乂 導電層150於此些貫穿孔140之内壁，即可透過此些導^ 層150電性連接第一封裝體102之第一基板110與第二 裝體104。換句話說’導電層150與導電材料15〇之 雷同’可視實務設計形成兩者或其中一者於貫穿孔14〇 第二封裝體1〇4具有一導線架180、一第二晶片122 與一第二封膠132。導線架180具有一晶片座182及數 引腳184 ’此些引腳184透過此些導電元件丨72電性 鲁 此些導電層152。第二晶片122位於晶片座m2上，並、 過數個銲線162電性連接此些引腳184。第二封膠132' 蓋第二晶片122、此些銲線162、晶片座182及每一引覆 182之一部分或全部。 腳 請參考第4圖’其繪示本發明具貫穿孔之堆疊式 結構之第三實施例的剖面圖。堆疊式封農結構2〇〇包人裝 少二個封裝體202，且此些封裝體202互相堆疊。每二至 裝體202具有一基板210、一封膠230、數個貫^孔24^封 數個導電材料2 5 0。封膠23 0至少覆蓋基板2丨〇。此此| ^ 8 201121029 孔240均貫穿基板210與封膠230。此些導電材料250分 別位於此些貫穿孔240中，並電性連接基板210。 每一封裝體202可具有一晶片220(或電子元件）。晶片 220位於基板210上，並可透過數個銲線260(或銲球）電性 連接基板210 ’且晶片220被封膠230所覆蓋。201121029 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package which is related to a stacked package having a through hole. [Prior Art] In the semiconductor process, in order to protect Wafers cut on wafers' various packaging structures and packaging methods for wafers have been proposed. The package structure protects the wafer from the heat, moisture, charge or other unintended factors of the external environment to enhance wafer stability and performance. As semiconductor components are becoming more integrated and lighter, wafer packaging technology is also moving toward miniaturization and higher density. Therefore, Ball Grid Array (BGA), Chip-Scale Package (CSP), Flip Chip Package (F/C Package) and Multi-Chip Module (Multi-Chip Module) , MCM), etc., a variety of high-density packaging technology came into being. In the packaging process, the sealing material is generally used to cover various components, such as wafers, substrates, bonding wires, etc., to protect the components from damage and moisture. However, based on the insulating properties of the encapsulant, when a plurality of packages are to be stacked together, the encapsulation may cause difficulty in electrical connection between the respective packages, thereby increasing the difficulty of stacking them on each other. In view of this, there is a need for an innovative and progressive sealing structure and a manufacturing method thereof to solve the above problems. SUMMARY OF THE INVENTION The object of the present invention is to provide a stacked package with a through hole 201121029 through the through hole of the sealant and the substrate and the conductive material followed by a new connection = -Taxis:: mention: stacked package structure The utility model comprises the first sealant of the alumina board, a plurality of through holes, and a plurality of guide s-packages. The first glue covers at least the first substrate. These = 枓 and Gong sealant. The conductive materials are respectively located at the 4; the holes: and the first substrate and the package are connected. The package body is mounted on the sealant and electrically connected to the conductive materials. - in the first - including step seal; junction: the manufacturing method and the first substrate to form a plurality of through holes. The number of formation = sealant in some through holes, and electrically connected to this 4 - the package in the first - seal heart, two * plate. Stacking materials. On the top of the encapsulant, and electrically connected to the package and the stacked package structure of the conductive to the through-holes, the basin package=two--the substrate has two through holes, and the electricity is: The materials are respectively located in the hole, the package structure, and the material thereof. Each package has two: a through hole and a plurality of conductive materials. These through holes run through each. The sealant covers at least the substrate. The company also proposes a stacked sealing mechanism. The steps include: providing a plurality of package methods, the package having a substrate and a 201121029 sealant, and the sealant covering at least the substrate. Stack these packages. A plurality of through holes are formed through the substrate of the mounting body and the encapsulant. A plurality of materials are formed in the through holes to electrically connect the conductive materials and the package. In summary, a plurality of through holes and a plurality of conductive materials located in the through holes are used as conduits for electrical connection between the packages. Thereby, the density of the electrical connecting pipes in the stacked package structure can be increased. [Embodiment] Please refer to Fig. 1, which is a cross-sectional view showing a first embodiment of a stacked package structure having a through hole according to the present invention. The stacked package structure 100 includes two first packages 102 and a second package 104. The first package body 1 has a first substrate no, a first sealant 130, a plurality of through holes 14 and a plurality of conductive materials 150. The first sealant 130 covers at least the first substrate 11: The holes 140 are respectively penetrated through the first substrate 11 〇 and the first sealant 13 此. The conductive material 150 is respectively located in the through holes 14 。. The second package 104 is stacked on the first seal 13 。. The conductive material 150 is electrically connected to the first substrate 11 〇 and the second package 丨〇 4 such that the first package 102 is electrically connected to the second package 〇 4 . The through hole 140 and the conductive material 150 of the first substrate 11 可 can be used as a conduit for electrically connecting the first substrate 110 and the second package 104 of the first package 1 〇 2 . The first wafer 120 can be disposed on the first substrate 11 and electrically connected to the first substrate 110. Specifically, the first wafer 120 can pass through the plurality of solder balls 160 or a plurality of soldering wires (not shown) are electrically connected to the first substrate 11 . The first sealing paste 130 covers the first wafer 120 to The first wafer 120 is protected from the external environment. The through hole 140 penetrates through the first substrate 11 and the first seal 5 201121029, and is formed on the first substrate 110 and the first seal 130, respectively. Specifically, the first substrate 110 has an opposite first surface 114 and a second surface 116, and the second surface 116 faces the first wafer 120. The first sealing material 130 has a surface 134. The through holes The first opening 142 has a plurality of first openings 142 and a plurality of second openings 144 . The first openings 142 are located on the first surface 114 of the first substrate 110 . The second openings 144 are located on the surface 134 of the first sealing material 130 . The conductive materials 150 are respectively disposed in the through holes 140 and extend from the first opening 142 to the second opening 144. In order to electrically connect the conductive materials 150 to the first substrate 110, the number of the first substrate 110 can be set. The pads 170 (or wires) are in contact with the conductive materials 150. The pads 170 are respectively located at the first openings 142 of the first surface 114, and are electrically connected to the conductive materials 150, and the pads are electrically connected. 170 is penetrated by the through holes 140. In order to make such conductive materials 15 The first package body 102 can have a plurality of conductive elements 172. The conductive elements 172 are respectively located at the second openings 144 of the through holes 140 and cover or surround the first package body 172. The second opening 144 is electrically connected to the conductive material 150. The second package 104 is connected to the conductive elements 172 through a plurality of bumps 176, and is electrically connected to the conductive materials 150. Alternatively, the second package body 104 can also directly contact the conductive materials 150 without passing through the conductive members 172 or the bumps 176. In order to stabilize the electrically conductive material 150, the electrical connection between the first substrate 110 and the second package 104, the first package 102 may have a plurality of conductive layers 152. The conductive layers 152 are respectively located on the inner walls of the through holes 140 and electrically connected to the first substrate 110 and the second package 104. In addition, the package structure 100 may also include a plurality of bumps 174 respectively located at the first openings 142 and disposed on the pads 6 201121029 170. Please refer to FIG. 2A. To: 1 circuit (not shown). The process of the stacked package structure is shown in Fig. 2, and the through hole is as shown in Fig. 2A. First, a first '曰' is set. The manufacturing method of the stacked package structure is performed on a first substrate 110 of the first substrate 110 through a plurality of dies 120 (f, sub-elements). ^ (or a known line) electrically connecting the first wafer 120 and the first crystal M to cover the first substrate 110 with a first seal 13 〇 to protect the first substrate 11 and the first wafer 12 Hey. Take the Wei Wei Institute 7F. Through the first and the first substrate 110', the 'one & η shell perforation, 140. Such through holes 14. A plurality of first openings 142 are formed in the first substrate 110 4 , and a plurality of second openings 144 are formed in the face 134 of the first sealant 130 . In the first embodiment, a plurality of solder bumps 17G may be formed first on the first opening 142 of the first substrate 11G. These holes 14 are formed in the through holes 14 to form the holes 14 through the pads 170, respectively. As shown in Figure 2C. After the through holes 140 are completed, a plurality of conductive layers I52 may be formed on the inner walls of the through holes (10), and the conductive layers (5) may be in contact with the pads 17 on the first substrate 110. As shown in Figure 2D. A plurality of conductive materials 150 are formed in the through holes 140. The conductive material ι5 is connected to the conductive layer ι52 and the solder pads 17G' to electrically connect the conductive materials 15() with the first substrate 110. Further, a plurality of conductive elements 172 are formed on the second opening 144 of the first sealant 130, and the conductive elements 172 and the conductive materials 150 are electrically connected. Finally, as shown in Figure 1. Then, a second package body 1〇4 is stacked on the first package sealant 130 and electrically connected to the second package body 1 (M and the conductive materials 150. The type and structure of the second package body 1〇4 can be implemented according to the practice. For example, the second package body 112 may have a second substrate 112, a second wafer 122 and a second sealant 132. The second substrate 112 is located above the first sealant 130. 'The conductive material 150 can be electrically connected to the conductive elements 172 through a plurality of bumps 176. The second wafer 122 is located on the second substrate 112' and can be electrically connected through a plurality of bonding wires 162 (or solder balls). The second substrate 112 is connected to the second substrate in, the second wafer 122 and the bonding wires 162. Referring to FIG. 3, the second package of the present invention has a through-hole stacked package structure. The cross-sectional view of the embodiment is similar to the stacked package φ package structure 100 of FIG. 1. In FIG. 3, the first package body 1〇2 does not need to form the conductive material 150 for the through holes 140. The only conductive layer 150 is formed on the inner walls of the through holes 140, and the conductive layer 150 can be electrically transmitted through the conductive layers 150. The first substrate 110 and the second package 104 of the first package body 102 are connected. In other words, the conductive layer 150 is similar to the conductive material 15'. The visual design is designed to form either or both of the through holes 14 and second. The package body 〇4 has a lead frame 180, a second wafer 122 and a second sealant 132. The lead frame 180 has a wafer holder 182 and a plurality of pins 184' through which the pins 184 pass through the conductive members 丨72. The conductive layer 152 is electrically connected to the wafer holder m2, and the plurality of bonding wires 162 are electrically connected to the pins 184. The second sealing material 132' covers the second wafer 122, and the soldering A portion or all of the line 162, the wafer holder 182, and each of the lead plates 182. Please refer to FIG. 4 for a cross-sectional view showing a third embodiment of the stacked structure with through holes of the present invention. 2, the package packs two less packages 202, and the package bodies 202 are stacked on each other. Each of the two packages 202 has a substrate 210, a glue 230, and a plurality of holes 24 and a plurality of conductive materials. 2 5 0. The sealant 23 0 covers at least the substrate 2丨〇. This is | ^ 8 201121029 The holes 240 are all penetrated through the substrate 210 The sealing material 230 is disposed in the through holes 240 and electrically connected to the substrate 210. Each of the packages 202 may have a wafer 220 (or an electronic component). The wafer 220 is located on the substrate 210, and The substrate 210' is electrically connected through a plurality of bonding wires 260 (or solder balls) and the wafer 220 is covered by the sealing material 230.
此些貫穿孔240會在基板210和封膠230上形成數個 開口。詳細來說，基板210具有相對的第一面212和第二 面214’第二面214面對晶片220。封膠23〇具有一表面 232。此些貫穿孔240具有數個第一開口 242及數個第二開 口 244,此些第一開口 242位於基板21〇的第一面212，此 些第二開口 244位於封膠230的表面232。 基板210具有數個銲墊270，此些銲墊27〇分別位於 基板210的第-開口 242處，且被此些貫穿孔2 4 〇所、。 此些鲜墊27〇分別電性連接此些導電 ％ 210與此些導電材料250電性連接。 侍暴板 每-封裝體搬可具有數個導電元件272。此 兀件272分別位於封膠230上的第二 或圍繞此些貫穿孔240,且電性連接此此導電‘=遮3 此些封裝體202互相堆疊時，各個封 虽 電元件272與凸塊274互相電性連接2〇2可透過其導 每一封裝體202可具有數個導電 252分別位於此些貫穿孔施之内】層252，此；導電層 材料250更易形成於貫穿孔24”，、藉此，使各個導電 272 "X! 270 至少兩個互罐的封裝體3二==包含 201121029 基板310與一封膠33〇，封膝33〇至少覆蓋基板31〇。 為了使此些封裝體302互相電性連接，堆疊式封装钟 構300包含數個貫穿孔34〇與數個導電材料35〇。此些； 穿孔340均貫穿每一封裝體302之基板310與封膠33〇。 此些導電材料350分別位於此些貫穿孔34〇中，且電性連 接各個封裝體302。堆疊式封裝結構3〇〇可包含數個導電 層352,此些導電層352分別位於此些貫穿孔340的内壁。 每一封裝體302可具有一晶片320(或電子元件）。晶片 320位於基板310上，並可透過數個銲球36〇或數個銲線 φ 362電性連接基板310，且晶片320可被封膠330所覆蓋。 為了使各個封裝體302可穩固地互相堆疊，兩相鄰的 封裝體302可藉由黏合層370互相黏合。詳細來說，黏人 層370介於兩封裝體302之間，用以黏合兩封裝體3〇2， 此些貫穿孔340可貫穿各封裝體302之間的黏合層37〇。 請參考第6A圖至第6C圖’其繪示第5圖具貫穿孔之 堆疊式封裝結構的製程剖面圖。 如第6A圖所示。堆疊式封裝結構3〇〇之製造方法， 首先為提供數個封裝體302。每一封裝體302具有一基板 • 310與一封膠330，且封膠330至少覆蓋基板310。每一封 裝體302更具有一晶片320，晶片320位於基板310上， 並電性連接基板310，且晶片320可被封膠330所覆蓋。 接著’堆疊此些封裝體302。在第四實施例中，可藉由黏 合層370黏合相鄰的封裝體302。 如第6B圖所示。貫穿每一封裝體302之基板310與封 膠330 ’以形成數個貫穿孔340。此些貫穿孔340可貫穿各 個封裝體302之間的黏合層370。 如第6C圖所示。完成此些貫穿孔340後，可形成數個 201121029 導電層,352於此些貫穿孔340的内壁。 fJti二第5圖所示。形成數個導電材料350於此此 體3〇2之基板μΓ電性連接此些導電材料350 *各個封襄 属方Ϊ封裝結構3〇0 f，此些封裝體302的堆 二二變化，其可依據實務設計而有所變動 舉而°，如第5圖、第7圖及第8圖所示。在第5圖中 兩封裝體逝互相堆疊，上方封裝體搬的基板31〇圖面中對 下方封裝體302的封夥33〇,並藉由黏合層370相貼合。、 考i7圖’其繪示本發明具貫穿孔之堆疊物 例的剖面圖，第7圖與第5圖之堆疊“ 1'^ 相似。在第7圖中，兩相鄰的封裝體302互相 其方封裝體3〇2的基板310面對下方封裝體3〇2的 土板310 ’並藉由黏合層370相貼合。 社構圖，其繪示本發明具貫穿孔之堆疊式封裂 在第8圖中，兩相鄰的封裝體3〇^目 ‘2 ί體302 #封膠330面對下方封裳體3〇2的 封膠330 ’並藉由黏合層370相貼合。 應瞭解到’本發明各實施例所述之基板可為 ，、-陶€基板、一玻璃基板、—印刷電路板、—積屏 板二載板或-承載件等。各個晶片可為心種類 、曰曰片。各個封膠之材質可為一環氧樹脂、一一 固性塑膠、—聚醯藝或—聚苯二f基類等 孔、-導電孔或-電嫂通孔。各個導電= ^導電柱、一導電條、一導線、一導電層、一金屬線、 一金屬針、一金屬材料、一金屬層或一銲料，其材質可為 201121029 金、銀、銅、鋁、鎳或其合金。各個導電層之材質可為金、 銀、銅、鋁、鎳或其合金等導電材料或金屬材料。各個導 電元件可為一導電體、一導電膠、一連接體、一凸塊、一 銲墊、一鲜球、一錫球或一金屬球等。各個銲墊可為一金 屬墊、一鋁墊、一接墊、一接點、一接腳、一引指或一引 腳等。各個銲線可為一金屬線、一金線、一銅線、一連接 線或一導線等。各個凸塊可為一金球、一錫球、一銲球、 一金屬球、一導電體、一金屬塊、一接點、一導電元件或 一連接元件等。各個黏合層之材質可為一黏膠、一單面膠、 一雙面膠、一彈性膠、一果凍膠、一散熱膠、一固定膠、 一接合膠、一黏著材料或一絕緣材料等。 綜上所述，利用貫穿封膠與基板的貫穿孔及導電材 料，作為互相堆疊的封裝體之間電性連接的管道。藉此， 可增加堆疊式封裝體中電性連接管道的密度。 雖然本發明已以實施方式揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖繪示本發明具貫穿孔之堆疊式封裝結構之第 一實施例的剖面圖。 第2A圖至第2D圖繪示本發明第1圖具貫穿孔之堆 疊式封裝結構的製程剖面圖。 第3圖繪示本發明具貫穿孔之堆疊式封裝結構之第 二實施例的剖面圖。 第4圖繪示本發明具貫穿孔之堆疊式封裝結構之第 12 201121029 三實施例的剖面圖。 第5圖繪示本發明具貫穿孔之堆疊式封裝結構之第 四實施例的剖面圖。 第6A圖至第6C圖繪示本發明第5圖具貫穿孔之堆 疊式封裝結構的製程剖面圖。 第7圖繪示本發明具貫穿孔之堆疊式封裝結構之第 五實施例的剖面圖。 第8圖繪示本發明具貫穿孔之堆疊式封裝結構之第 六實施例的剖面圖。 【主要元件符號說明】 100、200、300 :堆疊式封裝結構 102 :第一封裝體 104 :第二封裝體 110 :第一基板 112 :第二基板 114、212 :第一面 116、214 :第二面 120 :第一晶片 122 :第二晶片 130 :第一封膠 132 :第二封膠 134、232 :表面 140、240、340 :貫穿孔 142、242 :第一開口 144、244 :第二開口 150、250、350 :導電材料 152、252、352 :導電層 160、360 :銲球 162、260、362 :銲線 170、270 :銲墊 172、272 :導電元件 174、176、274 :凸塊 180 :導線架 182 :晶片座 184 :引腳 202、302 :封裝體 210、310 :基板 220、320 :晶片 230、330 ·•封膠 370 :黏合層 13The through holes 240 form a plurality of openings in the substrate 210 and the encapsulant 230. In detail, substrate 210 has opposing first side 212 and second side 214' second side 214 facing wafer 220. The sealant 23 has a surface 232. The through holes 240 have a plurality of first openings 242 and a plurality of second openings 244. The first openings 242 are located on the first surface 212 of the substrate 21, and the second openings 244 are located on the surface 232 of the sealant 230. The substrate 210 has a plurality of pads 270 which are respectively located at the first opening 242 of the substrate 210 and are surrounded by the through holes 24 . The fresh pads 27 are electrically connected to the conductive materials 210 and electrically connected to the conductive materials 250. The violent board can have a plurality of conductive elements 272 per package. The second member 272 is located on the encapsulant 230 or surrounds the through holes 240, and is electrically connected to the conductive portion =3. When the packages 202 are stacked on each other, the electrical components 272 and the bumps are respectively sealed. 274 electrically connected to each other 2 〇 2 through which each package 202 can have a plurality of conductive 252 respectively located within the through holes 252, wherein the conductive layer material 250 is more easily formed in the through holes 24 ” Therefore, each of the conductive 272 "X! 270 at least two inter-tank packages 3==includes 201121029 substrate 310 and a piece of glue 33〇, and the knee cover 33〇 covers at least the substrate 31〇. To make this The package body 302 is electrically connected to each other. The stacked package structure 300 includes a plurality of through holes 34 and a plurality of conductive materials 35. These holes 340 extend through the substrate 310 and the seal 33 of each package 302. The conductive materials 350 are respectively located in the through holes 34 , and are electrically connected to the respective packages 302. The stacked package structure 3 〇〇 may include a plurality of conductive layers 352 , and the conductive layers 352 are respectively located in the through holes The inner wall of 340. Each package 302 can have a wafer 320 (or The sub-element is disposed on the substrate 310, and is electrically connected to the substrate 310 through a plurality of solder balls 36 or a plurality of bonding wires φ 362, and the wafer 320 can be covered by the sealing 330. The two adjacent packages 302 can be bonded to each other by the adhesive layer 370. In detail, the adhesive layer 370 is interposed between the two packages 302 for bonding the two packages 3〇2, The through holes 340 can extend through the adhesive layer 37 各 between the packages 302. Please refer to FIGS. 6A to 6C for a cross-sectional view of the stacked package structure of the through hole. The method of manufacturing the stacked package structure is first to provide a plurality of packages 302. Each package 302 has a substrate 310 and a glue 330, and the seal 330 covers at least the substrate 310. A package 302 further has a wafer 320, the wafer 320 is located on the substrate 310, and electrically connected to the substrate 310, and the wafer 320 can be covered by the sealant 330. Then, the packages 302 are stacked. In the fourth embodiment The adjacent package 302 can be bonded by the adhesive layer 370. As shown in FIG. 6B, the substrate 310 and the encapsulant 330' of each package 302 are formed to form a plurality of through holes 340. The through holes 340 may penetrate the adhesive layer 370 between the respective packages 302. As shown in Fig. 6C After completing the through holes 340, a plurality of 201121029 conductive layers 352 may be formed on the inner walls of the through holes 340. The fJti 2 is shown in Fig. 5. A plurality of conductive materials 350 are formed in the body 3〇2 The substrate is electrically connected to the conductive materials 350. Each of the packages is a package structure 3〇0 f, and the stacks of the packages 302 are changed according to the practical design. 5, 7 and 8 are shown. In Fig. 5, the two packages are stacked on each other, and the substrate 31 on the upper package is placed on the lower surface of the package 302, and is bonded by the adhesive layer 370. , FIG. 7 is a cross-sectional view showing a stack of the present invention having a through hole, and FIG. 7 is similar to the stack “1′^ of FIG. 5. In FIG. 7, two adjacent packages 302 are mutually The substrate 310 of the package 3 〇 2 faces the earth plate 310 ′ of the lower package 3 〇 2 and is bonded by the adhesive layer 370. The composition diagram shows the stacked crack of the through hole in the present invention. In Fig. 8, the two adjacent packages 3 are in the same direction as the sealant 330' of the lower cover body 3〇2 and are bonded by the adhesive layer 370. The substrate described in the embodiments of the present invention may be: - a substrate, a glass substrate, a printed circuit board, a two-plate or a carrier, etc. Each wafer may be a heart type, 曰The material of each sealant can be an epoxy resin, a solid plastic, a polysilicon or a polyphenylene f-based hole, a conductive hole or an electric via. Each conductive = ^ a conductive pillar, a conductive strip, a wire, a conductive layer, a metal wire, a metal needle, a metal material, a metal layer or a solder, which may be made of 201121029 gold , silver, copper, aluminum, nickel or alloys thereof. The material of each conductive layer may be a conductive material or a metal material such as gold, silver, copper, aluminum, nickel or alloy thereof. Each conductive element may be an electric conductor or a conductive adhesive. a connecting body, a bump, a solder pad, a fresh ball, a solder ball or a metal ball, etc. Each of the pads may be a metal pad, an aluminum pad, a pad, a contact, a pin a lead wire or a pin, etc. Each wire can be a metal wire, a gold wire, a copper wire, a connecting wire or a wire, etc. Each bump can be a gold ball, a solder ball, a solder a ball, a metal ball, a conductor, a metal block, a contact, a conductive component or a connecting component, etc. The material of each adhesive layer can be a glue, a single-sided adhesive, a double-sided adhesive, an elastic a glue, a jelly gel, a heat-dissipating glue, a fixing glue, a bonding glue, an adhesive material or an insulating material, etc. In summary, the through-holes and the conductive material penetrating the sealing material and the substrate are used as a package stacked on each other. a pipe that is electrically connected between the bodies. Thereby, the electrical connection in the stacked package can be increased </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Therefore, the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a first embodiment of a stacked package structure having a through hole according to the present invention. 2A to 2D are cross-sectional views showing a process of a stacked package structure having a through hole according to a first embodiment of the present invention. Fig. 3 is a cross-sectional view showing a second embodiment of the stacked package structure having a through hole according to the present invention. Figure 4 is a cross-sectional view showing a third embodiment of the stacked package structure of the present invention having a through-hole structure. Figure 5 is a cross-sectional view showing a fourth embodiment of the stacked package structure having a through-hole according to the present invention. . 6A to 6C are cross-sectional views showing the process of the stacked package structure of the through-hole according to the fifth embodiment of the present invention. Figure 7 is a cross-sectional view showing a fifth embodiment of the stacked package structure having a through hole according to the present invention. Figure 8 is a cross-sectional view showing a sixth embodiment of the stacked package structure having a through hole according to the present invention. [Main component symbol description] 100, 200, 300: stacked package structure 102: first package body 104: second package body 110: first substrate 112: second substrate 114, 212: first surface 116, 214: Two sides 120: first wafer 122: second wafer 130: first sealant 132: second sealant 134, 232: surface 140, 240, 340: through holes 142, 242: first opening 144, 244: second Openings 150, 250, 350: conductive material 152, 252, 352: conductive layers 160, 360: solder balls 162, 260, 362: bonding wires 170, 270: pads 172, 272: conductive elements 174, 176, 274: convex Block 180: lead frame 182: wafer holder 184: pins 202, 302: package 210, 310: substrate 220, 320: wafer 230, 330 · • sealant 370: adhesive layer 13