TW201119512A - Lamp driving apparatus and level shift driving circuit - Google Patents
Lamp driving apparatus and level shift driving circuit Download PDFInfo
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- TW201119512A TW201119512A TW98138752A TW98138752A TW201119512A TW 201119512 A TW201119512 A TW 201119512A TW 98138752 A TW98138752 A TW 98138752A TW 98138752 A TW98138752 A TW 98138752A TW 201119512 A TW201119512 A TW 201119512A
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201119512 、發明說明: 【發明所屬之技術領域】 本發明係關於一種燈管驅動裝置及位移驅動電路。 【先前技術】 請參見第一圖,為習知之螢光燈管驅動電路之電路示意 圖。電子式安定控制器10包含了一高端驅動電路HSD及一低 端驅動電路LSD,分別透過一高端驅動腳位〇UMl及一低端 驅動腳位OUM2驅動開關模組40中對應的一高端P型金氧半 場效電晶體Ml及一低端N型金氧半場效電晶體M2。高端p 型金氣半場效電晶體Ml及低端N型金氧半場效電晶體M2彼 此串聯於一輸入電源VIN及接地之間,根據電子式安定器1〇 的控制將輸入電源VIN的電力傳遞至一諧振模組3〇。譜^模 組30包含一電感L1以及一電容C2,將輸入電源VIN的電力 轉換成一交流訊號以驅動一燈管20。 ^電子式安定控制器10為了能確實控制高端P型金氧半場 效電晶,Ml及低端N型金氧半場效電晶體M2之導通與戴 止,故向端驅動電路HSD及一低端驅動電路LSD必須同時耦 接輸入電源VIN及接地。然而,燈管2〇的驅動電壓在數 特,故輸入電源VIN的電壓也在數百伏特,使得電子式安 '物了電子式安定控制器 【發明内容】 I»,先則技射的電子式安定控㈣的製程難度及成本 t二,明的位移驅動電路除了提供控制訊號的準位之位 ‘縣端的電晶體可同時使$ n型金氧半場效電晶體外, 移·^電路㈣合至輸人電_部分元件採⑽高壓元 Ιϋΐΐ隔t輸人電源的高壓施加於其他元件,使控制器 器的糊猶用控制 為達上述目的,本發明提供了一種燈管驅動裝置,包含一 201119512 開關模組、一控制器、一諧振模 ,組包含㈣於—輸人電壓源及-共同電位之= 晶體開關及一低端電晶體開關。控二上同舳電 開關及低端電晶體開關之切換^^端^晶體 訊號以驅動-燈管。位準 制益、開關模組以及一位移參考電 控201119512, invention description: TECHNICAL FIELD The present invention relates to a lamp driving device and a displacement driving circuit. [Prior Art] Please refer to the first figure, which is a circuit diagram of a conventional fluorescent lamp driving circuit. The electronic stability controller 10 includes a high-end driving circuit HSD and a low-end driving circuit LSD, respectively driving a corresponding high-end P-type in the switching module 40 through a high-side driving pin 〇UM1 and a low-end driving pin OUM2. The gold-oxygen half-field effect transistor M1 and a low-end N-type gold-oxygen half-field effect transistor M2. The high-end p-type gold gas half-field effect transistor M1 and the low-end N-type gold-oxygen half-field effect transistor M2 are connected in series between an input power source VIN and a ground, and the power of the input power source VIN is transmitted according to the control of the electronic ballast 1〇. To a resonant module 3〇. The spectrum module 30 includes an inductor L1 and a capacitor C2 for converting the power of the input power source VIN into an alternating current signal to drive a lamp tube 20. ^ Electronic stability controller 10 in order to be able to accurately control the high-end P-type MOS half-field effect transistor, Ml and low-end N-type MOS half-effect transistor M2 conduction and wear, so the end drive circuit HSD and a low end The drive circuit LSD must be coupled to both the input power supply VIN and ground. However, the driving voltage of the lamp 2 在 is a few special, so the voltage of the input power supply VIN is also several hundred volts, so that the electronic safety controller is electronically stable. [Inventive content] I», first electrons The stability and cost of the stability control (4) t, the displacement drive circuit of the Ming not only provides the position of the control signal. The transistor at the county end can simultaneously make the $n-type gold-oxygen half-field effect transistor, and the circuit (4) Combined with the input power to the human part _ part of the component (10) high voltage element t t input power supply high voltage is applied to other components, so that the controller of the controller is used to achieve the above purpose, the present invention provides a lamp driving device, including A 201119512 switch module, a controller, a resonant mode, the group includes (four) - input voltage source and - common potential = crystal switch and a low-end transistor switch. Control two on the same switch and low-end transistor switch switch ^ ^ end ^ crystal signal to drive - lamp. Level control, switch module and displacement reference electronic control
制高:電晶體開關:行::以號以產生-高端控制訊號以控 響ii:同?ί提供了 一種位移驅動電路,用以位移-控制 以及一苐二釋能路徑。儲能路徑之路後 送位移參考電位魏之電力。魏元件 電位,用以儲存位移參考參考 -第第一端,第-釋能以二 晶,關。第二釋能路徑之一第一端==== 制ΐ Li第二釋能路徑之—第二端耗接參考電位,用j!釋放ί J晶體間㈣生電容觸存之術㈣-電= -步說:範性質,是為了進 優點’將在後續的以而閣ί本發明的其他目的與 【實施方式】 圖。Γ電路方塊 模組130以及-‘:丨40,用以 控制态100包含一驅動電路1〇5減一驅動電屢vcc及一共 201119512 同電位(即接地)’以根據驅動電壓VCC之電位透過腳位ουτ 輸出一控制訊號Si2。位移驅動電路110包含一相位調整電路 150以及一位準移位電路16〇。相位調整電路150耦接於位準 移位電路160 ’並接收控制訊號Si2以調整控制訊號Si2之相 ,關模組140耦接一輸入電壓源VIN及共同電位,其包 電晶體開關T1及—低端電晶體開關T2,而高端ΐ晶 體開關Τ1與低端電晶體開關Τ2串聯。在本實施例中 2體開關Τ1與低端電晶體開關Τ2均為Ν型金氧半場^ 晶體。 % ㊉曰^準移位電路160耦接控制器100、開關模組〗4〇中高端 电曰日體開關及低端電晶體開關之連接點VS以及一位移參考雷 源,在本實施例係以驅動電屢vcc作為此位移參i電位 位ί路160接收經相位調整電路150調整相位之 ^端電:體1Sl2的準位依據高端電晶體開關及 i接觀電位進行難並輸出為一高端 控制5ίΙ#〇&1。由於當高端電晶體開關耵 VIN ^ 驅動電>1 Gr達數ί伏特之而,而遠高於幾伏特到數十伏特的 Ϊ控f,Sil的準位高於連接點VS -個驅動電 保高端電晶體開關T1可以順利導通另外,值? 碭的疋本發明的位移驅動電路110具有 了 覆源·_,因此控制器! 厂堅T外之=柯,此部分由後續的實=來以 控制低端電晶體之=器出控制訊㈣以 位準務位她⑽m換透過相位調整電路15〇及 η 產生向端控制訊號Sil來控制古滅恭日神 =τι之切換。為了避免高端電晶體開關 開關T2 w㈣錢㈣此梅 201119512 及低端電晶體開關T2之導通時間彼此錯開。透過相位調整電 路150可以調整控制訊號si2之相位,使根據織相位^吏‘ 制訊號SC而產生的高端控制訊號Sil,其相位可以和控= 號之相位維持在一預定的相位差,在本實施例為⑽度。 在某些應用場合’例如:控制器輸出兩個相位 移位電路⑽同於具有反相功能,可以省略相 路 150 〇 接著清參見第三圖,為根據本發明之―第—實施例之Height: Transistor Switch: Line:: Use the number to generate - high-end control signal to control ii: same? ί provides a displacement drive circuit for displacement-control and a second-discharge path. After the path of the energy storage path, the displacement reference potential Wei Zhi power is sent. Wei component potential, used to store the displacement reference - the first end, the first release can be dicrystal, off. The first end of the second release path ==== ΐ Li The second release path - the second end consumes the reference potential, and uses j! to release ί J between the crystals (4) the capacitive contact (4) - electricity = - Step: The nature of the paradigm is for the sake of the advantages of the other objects and embodiments of the present invention. Γ circuit block module 130 and - ': 丨 40, for control state 100 includes a drive circuit 1 〇 5 minus a drive power repeatedly vcc and a total of 201119512 the same potential (ie ground) 'to penetrate the foot according to the potential of the drive voltage VCC Bit ουτ outputs a control signal Si2. The displacement drive circuit 110 includes a phase adjustment circuit 150 and a one-bit shift circuit 16A. The phase adjustment circuit 150 is coupled to the level shifting circuit 160' and receives the control signal Si2 to adjust the phase of the control signal Si2. The off module 140 is coupled to an input voltage source VIN and a common potential, and includes a transistor switch T1 and The low-end transistor switch T2, and the high-end ΐ crystal switch Τ1 are connected in series with the low-side transistor switch Τ2. In the present embodiment, the 2-body switch Τ1 and the low-end transistor switch Τ2 are both Ν-type gold oxide half-field crystals. The tenth 准^ quasi-shift circuit 160 is coupled to the controller 100, the switch module, the connection point VS of the middle and high-end electric cesium switch and the low-end transistor switch, and a displacement reference ray source. The driving power frequency vcc is taken as the displacement parameter i potential bit ί path 160 receives the phase adjustment circuit 150 to adjust the phase of the terminal end: the level of the body 1Sl2 is difficult according to the high-end transistor switch and the i-connected potential, and the output is a high-end Control 5ίΙ#〇&1. Since the high-end transistor switch 耵 VIN ^ drives electricity > 1 Gr volts, and is much higher than a few volts to tens of volts, the level of Sil is higher than the connection point VS - a drive The high-end transistor switch T1 can be smoothly turned on. In addition, the displacement drive circuit 110 of the present invention has the source _, so the controller! The factory is outside the T = ke, this part is controlled by the subsequent real = to control the low-end transistor = device control (4) with the level operator she (10) m through the phase adjustment circuit 15 〇 and η to generate the end control signal Sil to control the switch of the ancient annihilation god god = τι. In order to avoid the high-end transistor switch T2 w (four) money (four) this May 201119512 and low-end transistor switch T2 conduction time are staggered from each other. The phase adjustment circuit 150 can adjust the phase of the control signal si2 so that the phase of the high-end control signal Sil generated according to the woven phase signal SC can be maintained at a predetermined phase difference with the phase of the control signal. The example is (10) degrees. In some applications, for example, the controller outputs two phase shifting circuits (10) having the same inverting function, and the phase 150 can be omitted. Referring now to the third figure, it is a "first embodiment" according to the present invention.
示賴^移鶴魏包含了她調整電路 150以及位準移位電路16〇。相位調整電路15〇包含了 R4、R5以及一 ΝΡΝ雙載子接面電晶體S2。電阻R4、R5之 8^2端收域端轉驗LG所輸㈣控制訊號 ί山、電 另一端連接至低端電晶體開關T2的閘極(控 制知)’使低端電晶體開關Τ2受控制訊號Si2之控制進^ ,。電阻R4之另-端連接至则雙載子 t NPN雙載子接面電晶體S2之基極連接至驅動二vc= 集極連接至位準移位電路16〇。 位準移位電路160包含電阻R〇、幻、们、R3、Shi Lai ^ Shihe Wei contains her adjustment circuit 150 and the level shift circuit 16〇. The phase adjustment circuit 15A includes R4, R5 and a ΝΡΝ bipolar junction transistor S2. The 8^2 end of the resistors R4 and R5 is returned to the LG. (4) The control signal ί山, the other end of the electric is connected to the gate of the low-end transistor switch T2 (control know) 'Low the low-end transistor switch Τ2 The control signal Si2 is controlled by ^. The other end of the resistor R4 is connected to the double carrier t. The base of the NPN bipolar junction transistor S2 is connected to the driving two vc= collector connected to the level shifting circuit 16A. The level shift circuit 160 includes resistors R 〇, 幻, 、, R3,
載子接面電晶體S1以及二極體m、D3。三極 連接驅動電壓vcc,負端連接電阻R卜PNP雙 载子接面f MSI之雜及電容C3 ^。電 子ίϊ電晶體S1之集極及二雙二= ^ _ 土參毛今03之另一端連接高端電晶體開關T1 =關τ2喊接點vs。pnp雙鮮接面電晶體 接點;而電?=另5遠一:,電二且Μ之另-端連接連 m Α 之另一端連接二極體D3之正端。二極矽 雷阳連接高端電晶體關T1之酿及電阻R3之一端, 電阻R3之另一端連接連接點¥8。 傳送驅D2作為-儲能路徑’用以 电登VLC之電力至作為儲能元件之電容c3儲存, 201119512 關i可以提供訊號準位位移之電位及驅動高端電曰咖 1 τι :刀換之電力。PNP雙载子接面電晶體S1、電曰:,開 -極體D3作為-第―釋能職’用以將 : =高端電晶體開關T1之閘極,使高端電 之 Ϊ生广第二釋_㈣以使高端電晶二 寄生電谷所儲存之電荷能透過電阻R3釋放而戴止。 巧說明相位調整電路15〇以及位準移位電路16 =。备控制訊號Si2為高準位(等於驅動電壓VCc '、The carrier is connected to the transistor S1 and the diodes m and D3. The three-pole connection drive voltage vcc, the negative-end connection resistance R, the PNP double-carrier junction f MSI, and the capacitance C3 ^. Electron ϊ ϊ ϊ ϊ ϊ 及 及 及 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 今 今Pnp double fresh junction transistor contact; and electricity? = another 5 far one:, the other end of the electric two and the other end of the connection m Α connected to the positive end of the diode D3. The two poles of Leiyang are connected to the high-end transistor to close the T1 and one end of the resistor R3, and the other end of the resistor R3 is connected to the connection point of ¥8. The transmission drive D2 is used as the - energy storage path to store the power of the VLC to the capacitor c3 as the energy storage component. 201119512 can provide the potential of the signal displacement displacement and drive the high-end electric coffee 1 τι: . PNP double-carrier junction transistor S1, electric 曰:, open-pole body D3 as - the first - release energy job's will: = the gate of the high-end transistor switch T1, so that the high-end electricity is the second Release _ (four) so that the charge stored in the high-end electro-crystal two parasitic electric valley can be released through the resistor R3. The phase adjustment circuit 15A and the level shift circuit 16 = are described. The standby control signal Si2 is at a high level (equal to the driving voltage VCc ',
電晶體開關T2導通使連接點vs之電位為零。由於 ί ί ΐ VS之電位為零,低於驅動電壓VCC,使驅動電壓VCC 儲存於電容C3直至電容C3㈣麗等於 ,動電壓VCC減去二極體D2之順向導通偏壓為止。另外, N雙载子接自t M S2之絲及射極之紐均為驅動電壓 cc之電位,故處於截止狀態而無法導通電流流經電阻。 因^ ’電阻R1之兩鱗餘,也就是pNp雙載子接面電晶體 極及射極等電位,PNP雙载子接面電晶體S1也處於截止 丄無法導通電流流經電阻R3,電阻R3兩端等電位。也就 疋說尚端電晶體開關T1的閘極與源極等電位,高端電晶體開 關T1為截止狀態。此時由於PNP雙載子接面電晶體S1及NPN 雙載子接面電晶體S2均為截止,故驅動電壓vcc之電力不至 於流經PNP雙載子接面電晶體S1 &NpN雙載子接面電晶體 S2而損耗。 當控制訊號Si2轉為低準位(即零電位)時,低端電晶體 開關T2截止。此時,電阻R4連接至零電位使雙載子接面電 晶體S2之射極電位往下降而使雙載子接面電晶體S2導通。由 於雙載子接面電晶體S2的導通,使電流流經電阻R1而形成 電壓差並進而使PNP雙載子接面電晶體si也為導通。此時, 電容C3的電壓透過PNP雙載子接面電晶體S1、電阻R〇及二 極體D3形成高端控制訊號Sil施加於高端電晶體開關T1,使 高端電晶體開關T1導通。當高端電晶體開關T1導通時,連 201119512 接點vs之電位上升至輸入電壓源VIN之電壓。因此,二極體 D2與電谷C3之連接點電位會上升至(vin+vcc_vth),使二極 體D2處於逆偏而截止。其中Vin為輸入電壓源VIN之電壓, Vcc為驅動電壓VCC之電壓,Vth為二極體D2之順向導通偏 壓。 當控制訊號Si2再度轉為高準位時,PNP雙載子接面電晶 體S1及NPN雙載子接面電晶體S2再度截止。高端電晶體開 ,T1的寄生電容之電荷透過電阻R3釋放使其閘極電位降至 等於連接點VS之電位而使高端電晶體開關T1截止。電容C3 再度透過二極體D2儲能,使電容C3之電壓再度回升至 W Vcc-Vth。 如同上述說明,當低端電晶體開關T2導通時,高端電晶 體開關T1為截止,反則反之,故不會造成高端電晶體開關Ή 與低端電晶體開關T2同時導通而毀損之問題。 另外’當端電晶體開關T1導通而使二極體D2與電容C3 之連接點電位會上升至(Vin+Vcc-Vth),此時只要選用耐壓能力 足夠的二極體D2及NPN雙載子接面電晶體§2,其他元件, 包括控制器100之耐壓能力僅要求高於驅動電壓VCc即可。 故可以大幅降低控制器及大部分元件的耐壓要求,因而降低電 φ 路之成本。 請芩見第四圖,為根據本發明之一第二實施例之位移驅動 電路之電路示意圖。相較於第三圖所示之實施例,本實施例的 相位調整電路150,增加一齊納二極體Z1耦接於低端電晶體開 ^ T2及電阻R5之間,當控制訊號Si2由低準位轉為高準位 時[將因齊納二極體zi的雪崩電壓而使低端電晶體開關T2 的導通時點往後延遲,可更確保高端電晶體開關T1與低端電 晶體開關T2不會同時導通。另外,本實施例的位準移位電路 160’中作為第二釋能路徑的電阻R3改以pNp雙載子接面電晶 體S3取代,以加速高端電晶體開關Ή由導通轉為截止及= 截止轉為導通之速度。PNP雙載子接面電晶體S3的射極連接 201119512 的閘極,基極連接電阻112與pNp雙載子 ί之連接點,而集極連接連接點VS。 卷啼二.ί第五圖,為第四圖所示實施例之訊號波形圖。 為低準位時’低端電晶體開關η之閘極電位 載子^電位下降。ΡΝΡ雙載?接φ電晶體S1及ΝΡΝ雙 接點vs二體幻導通,使高端電晶體開關T1導通,使連 二ί^3快速上升至接近輸入電壓源vin之電位 並於後因釋開關T1之間極電位上升至接近(Vin+Vcc), 此時,高端電晶體開關T1導通而略微下降。 截止。相較電晶體S3 極電位高於射極電位而 流,故太麻圖所不貫施例中的電阻113此時仍會流過電 抓故^貫施例可以減少功率損耗。 T2 踹雷曰稱驅動電壓VCC之電位Vcc上升。此時,低 愛雷T2導通使連接點VS之電位V3快速下降至接近 S'2截止,雷子接面電晶體S1及雙載子接面電晶體 於ί接!占U^將PNP雙載子接面電晶體S3的射極拉至等 ‘曰^ *PNP雙載子接面電晶體S3導通。此時, 卿雙荷賴速的透過 止。Μ 曰曰體S3釋放使局端電晶體開關TU夬速截 點VS夕带虽尚端電晶體開關T1之閘極電位V1降至與連接 幻合截止順向導通電壓時,PNP雙載子接面電晶體 維持I略順3體開關T1之’電位V1與連接點vs 較ίί ϊ ίϊί壓之電壓差vth (與vth與νώ尺度相差 開關τι由进二中未緣出此差異),如此也可加速高端電晶體 開關Τ1由截止轉為導通之速度。 用。ίίΓίίΓ 電路可以積體化成單—W來搭配使 驅動電:燈ϊ驅動裝置包含一控制器100、一位移 咱振模組130以及一開關模組14〇,用以驅 201119512 動一燈管120。位移驅動電路1丨〇,包含了驅動電路LSD、相位 調整電路150以及位準移位電路160,以根據控制器1〇〇之控 制訊號來產生兩控制訊號以控制開關模組14〇的高端電晶體 開關T1及低端電晶體開關T2。其中,驅動電路LSD係用以 加強控制為由低端驅動腳位LO所發出的控制訊號之驅動能 力。因此,對於不同應用環境使用不同的低端電晶體開關T2 時以透過,位移驅動電路110,之驅動電路LSD來配合驅動。The transistor switch T2 is turned on to make the potential of the connection point vs zero. Since the potential of ί ΐ VS is zero, lower than the driving voltage VCC, the driving voltage VCC is stored in the capacitor C3 until the capacitor C3 (four) is equal to, and the dynamic voltage VCC is subtracted from the forward bias of the diode D2. In addition, since the N double carrier is connected to the potential of the driving voltage cc from the wire of the t M S2 and the emitter of the emitter, the current is not turned off and the current flows through the resistor. Because of the two scales of the resistor R1, that is, the pNp bipolar junction transistor pole and the emitter equipotential, the PNP bipolar junction transistor S1 is also at the cutoff 丄 unable to conduct current through the resistor R3, the resistor R3 Equipotential at both ends. That is to say, the gate and source of the transistor switch T1 are equipotential, and the high-end transistor switch T1 is turned off. At this time, since the PNP bipolar junction transistor S1 and the NPN bipolar junction transistor S2 are both turned off, the power of the driving voltage vcc does not flow through the PNP bipolar junction transistor S1 & NpN dual load. The sub-surface transistor S2 is lost. When the control signal Si2 is turned to the low level (i.e., zero potential), the low side transistor switch T2 is turned off. At this time, the resistor R4 is connected to the zero potential so that the emitter potential of the bipolar junction transistor S2 is lowered to turn on the bipolar junction transistor S2. Due to the conduction of the bipolar junction transistor S2, a current flows through the resistor R1 to form a voltage difference and thereby the PNP bipolar junction transistor si is also turned on. At this time, the voltage of the capacitor C3 is applied to the high-side transistor switch T1 through the PNP bipolar contact transistor S1, the resistor R 〇 and the diode D3 to form a high-side control signal Sil, so that the high-end transistor switch T1 is turned on. When the high-end transistor switch T1 is turned on, even the potential of the 201119512 contact vs rises to the voltage of the input voltage source VIN. Therefore, the potential at the junction of the diode D2 and the electric valley C3 rises to (vin + vcc_vth), causing the diode D2 to be reverse biased and turned off. Vin is the voltage of the input voltage source VIN, Vcc is the voltage of the driving voltage VCC, and Vth is the forward bias voltage of the diode D2. When the control signal Si2 is again turned to the high level, the PNP bipolar contact junction transistor S1 and the NPN dual carrier junction transistor S2 are again turned off. The high-end transistor is turned on, and the charge of the parasitic capacitance of T1 is released through the resistor R3, so that the gate potential drops to be equal to the potential of the connection point VS, and the high-end transistor switch T1 is turned off. Capacitor C3 again stores energy through diode D2, causing the voltage of capacitor C3 to rise again to W Vcc-Vth. As described above, when the low-side transistor switch T2 is turned on, the high-side transistor switch T1 is turned off, and vice versa, so that the high-side transistor switch Ή and the low-end transistor switch T2 are not turned on at the same time and are damaged. In addition, when the transistor switch T1 is turned on, the potential of the connection point between the diode D2 and the capacitor C3 will rise to (Vin+Vcc-Vth). At this time, the diode D2 and the NPN double load with sufficient withstand voltage capability are selected. The sub-junction transistor §2, other components, including the voltage resistance of the controller 100, is only required to be higher than the driving voltage VCc. Therefore, the voltage withstand requirements of the controller and most of the components can be greatly reduced, thereby reducing the cost of the electrical circuit. Please refer to the fourth figure, which is a circuit diagram of a displacement driving circuit according to a second embodiment of the present invention. Compared with the embodiment shown in FIG. 3, the phase adjustment circuit 150 of the present embodiment adds a Zener diode Z1 coupled between the low-end transistor opening T2 and the resistor R5 when the control signal Si2 is low. When the level is changed to the high level [the delay time of the low-end transistor switch T2 is delayed by the avalanche voltage of the Zener diode zi, the high-end transistor switch T1 and the low-end transistor switch T2 can be ensured. It will not be turned on at the same time. In addition, the resistor R3 as the second release path in the level shifting circuit 160' of the present embodiment is replaced by the pNp bipolar junction transistor S3 to accelerate the turn-on of the high-side transistor switch to be turned off and = The cut-off is the speed of conduction. The emitter of the PNP bipolar junction transistor S3 is connected to the gate of 201119512, the base connection resistor 112 is connected to the pNp bipolar ί, and the collector is connected to the connection point VS. The fifth figure is the signal waveform diagram of the embodiment shown in the fourth figure. When the level is low, the gate potential of the low-side transistor switch η is lowered. ΡΝΡ double load? Connect the φ transistor S1 and the ΝΡΝ double contact vs the two-body phantom conduction, so that the high-end transistor switch T1 is turned on, so that the lian ί ^ 3 rises rapidly to the potential close to the input voltage source vin and then the transition between the switch T1 The potential rises to near (Vin+Vcc), and at this time, the high-end transistor switch T1 is turned on and slightly lowered. cutoff. Compared with the potential of the transistor S3, the potential is higher than the emitter potential, so the resistor 113 in the case of the smear is still flowing through the current. The potential Vcc of the driving voltage VCC rises at T2. At this time, the low love T2 conduction causes the potential V3 of the connection point VS to rapidly drop to near S'2 cutoff, and the lightning junction transistor S1 and the double carrier junction transistor are connected to each other! The emitter of the sub-junction transistor S3 is pulled to the same level as the 'PNP bipolar junction junction transistor S3. At this time, the speed of Qing Shuanghe Lai speed.曰曰 曰曰 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S The surface transistor maintains the I potential of the 3-body switch T1's potential V1 and the connection point vs. the voltage difference vth of the voltage (the difference between the vth and the νώ scale switch τι is in the second place), so It accelerates the speed at which the high-end transistor switch Τ1 turns from off to on. use. The circuit can be integrated into a single-W to match the driving power: the driving device comprises a controller 100, a displacement oscillating module 130 and a switch module 14A for driving the 201119512 to a lamp 120. The displacement driving circuit 1A includes a driving circuit LSD, a phase adjusting circuit 150 and a level shifting circuit 160 for generating two control signals according to the control signal of the controller 1 to control the high-end power of the switch module 14〇 Crystal switch T1 and low-end transistor switch T2. The driving circuit LSD is used to strengthen the driving ability of the control signal issued by the low-side driving pin LO. Therefore, when different low-end transistor switches T2 are used for different application environments, the driving circuit LSD of the displacement driving circuit 110 is driven to cooperate.
请參見第七圖,為根據本發明之一第三實施例之位移驅動 電路之電路不意圖。相較於第三圖所示之實施例,本實施例的 相位調整電路150”接收控制器的高端驅動腳位H〇之輸出訊 號jH,並透過位準移位電路16〇,,產生高端驅動訊號su 以驅 動兩端電晶體開Μ τι,而低端電晶體開關T2則由控制器的低 端驅動腳位LO之輸出訊號SL直接控制。其中,高端驅動腳 位HO之輸出訊號SH與低端驅動腳位L〇之輸出訊號SL相 差180度。相位調整電路15〇”包含了電阻R6、R7及一 wn 雙載子接面電晶體S4。電阻R6-端連接高端驅動腳位恥, 另一端連接NPN雙載子接面電晶體S4之基極。電阻R7 端連接NPN雙載子接面電晶體Μ之射極,另一端接地。卿 雙載子接面電晶體S4之集極連接至位準移位電路16 PNP雙載子接面電晶體S1之基極。 、 當低端驅動腳位LO之輸出訊號SL為低準位時,高 位HO =出訊號SH為高準位。此時,低端電晶體開關 曰is4的 雙載子接面電晶體S1及麵雙載子接面電 )’高,晶體開關T1導通。當低端驅動腳ί 輸出峨SL為高準位時,高端驅動腳位Η〇之 為t準位。此時,低端電晶體開關Τ2導通,而PNP錐 電晶體S1及㈣雙載子接面電晶體S4 , ,,驅動訊號Sil為低準位(相對於連接點V 二 端電晶體開關T!戴止。因此,軸低端電晶 )1 201119512 極接收的訊號SL與位移驅動電路接收的訊號SH相位相反, 但透過相位調整電路15〇”進行相位調整後,然確保高端電晶 體,關T1接收的訊號Sil與低端電晶體開關T2之閘極接收的 訊號SL反相,即相位差18〇度,使高端電晶體開關Ή1盘 端電晶體開關T2的導通時間彼此錯開。 一另外,在本實施例的位準移位電路160”,將第一釋能路 控中的電阻R0及二極體D3改以雙載子接面電晶體^ ,代,而第二釋能路徑的電阻R3改以pNp雙載子接面電晶體 3取代。當低端驅動腳位L〇之輸出訊號SL為低準位 鳊驅動腳位HO之輸出訊號sh為高準位。此時,pNp雙载子 J面電晶體S1及NPN雙載子接面電日日日體S4均為導通,聊 又载子接面電晶體S1的集極電位被拉高而使雙載子 ,晶體S5導通而PNP雙載子接面電晶體%截止。因此,位 準移位電路160”輸出高準位的高端驅動訊號Sil。反之, =鷄腳位HO之輸出訊號SH為低準位時,pNp雙載子接面 |晶體S1及NPN雙載子接面電晶體%截止。此時,聰雙 雷5接的集極電位被電阻M拉至與連接點VS等 子接面電日體雙it接面電晶體s5截止而pnp雙載 的高端驅i日訊號^此’位準移位電路勝,輸出高準位 和吝本發明完全符合專利三要件:新穎性、進步性 孰習。本發明在上文中已以較佳實施例揭露,然 n之鑤二5 圍。應注意的是,舉凡與該實施例 1 ^ 、’均應设為涵蓋於本發明之範噚内。因此, 本發明之賴朗當以下文之申請專機騎界定者^此 【圖式簡單說明】 知之螢光燈管驅動電路之電路示意圖。 第-圖為根縣發明之燈管驅練置之電路方塊圖。 201119512 苐二圖為根據本發明之一第一實施例之位移驅動電路之 電路示意圖。 第四圖為根據本發明之一第二實施例之位移驅動電路之 電路示意圖。 第五圖為第四圖所示實施例之訊號波形圖。 二第六圖為使用本發明之位移驅動電路之燈管驅動襄置之 電路方塊圖。 第七圖為根據本發明之一第三實施例之位移驅動電 電路示意圖。 < 【主要元件符號說明】 響 先前技術: 電子式安定控制器10 燈管20 譜振模組30 開關模組40 高端驅動電路HSD 低端驅動電路LSD 高端驅動腳位OUT 1 低端驅動腳位OUT2 鲁 向端P型金氧半場效電晶體Ml 低端N型金氧半場效電晶體M2 輸入電源VTN 電感L1 電容C2 本發明: 控制器100 驅動電路105 位移驅動電路110、11〇, 燈管120 13 201119512 諧振模組130 開關模組140 相位調整電路150、150’、150” 位準移位電路160、160’、160”Referring to the seventh drawing, a circuit of a displacement driving circuit according to a third embodiment of the present invention is not intended. Compared with the embodiment shown in FIG. 3, the phase adjustment circuit 150" of the embodiment receives the output signal jH of the high-side driving pin H〇 of the controller, and generates a high-end driver through the level shifting circuit 16〇. The signal su drives the transistor at both ends to open τι, and the low-end transistor switch T2 is directly controlled by the output signal SL of the low-side driving pin LO of the controller. Among them, the output signal SH of the high-end driving pin HO is low. The output signal SL of the terminal driving pin L is 180 degrees out of phase. The phase adjusting circuit 15A" includes resistors R6, R7 and a wn bi-carrier junction transistor S4. The resistor R6-end is connected to the high-end driver pin shame, and the other end is connected to the base of the NPN bipolar junction transistor S4. The end of the resistor R7 is connected to the emitter of the NPN bipolar junction transistor, and the other end is grounded. The collector of the bipolar junction transistor S4 is coupled to the base of the PNP bipolar junction transistor S1. When the output signal SL of the low-side driving pin LO is at a low level, the high bit HO = the outgoing signal SH is at a high level. At this time, the low-side transistor switch 曰is4 has a high bipolar junction transistor S1 and a surface bipolar junction junction, and the crystal switch T1 is turned on. When the low-side driver pin ί is at the high level, the high-side driver pin is at the t level. At this time, the low-end transistor switch Τ2 is turned on, and the PNP cone transistor S1 and the (four) double-carrier junction transistor S4, , the driving signal Sil is at a low level (relative to the connection point V two-terminal transistor switch T! Therefore, the low-end transistor of the axis 1 201119512 The signal received by the pole is opposite to the phase of the signal SH received by the displacement drive circuit, but after the phase adjustment by the phase adjustment circuit 15〇, the high-end transistor is turned off, and the T1 is turned off. The received signal Sil is inverted from the signal SL received by the gate of the low-end transistor switch T2, that is, the phase difference is 18 degrees, so that the on-times of the high-end transistor switch Ή1 disk-end transistor switch T2 are staggered from each other. In the level shift circuit 160" of the embodiment, the resistor R0 and the diode D3 in the first release path are changed to the double carrier junction transistor, and the resistor R3 of the second release path is replaced. Replace with pNp double carrier junction transistor 3. When the output signal SL of the low-side driving pin L is low, the output signal sh of the driving pin HO is high. At this time, the pNp double-carrier J-plane transistor S1 and the NPN double-carrier junction surface are both turned on, and the collector potential of the carrier-side transistor S1 is pulled high to make the double carrier. The crystal S5 is turned on and the PNP bipolar junction transistor % is turned off. Therefore, the level shifting circuit 160" outputs the high-level driving signal Sil of the high level. Conversely, when the output signal SH of the chicken foot position HO is at the low level, the pNp double-carrier interface | the crystal S1 and the NPN double carrier The junction transistor % is cut off. At this time, the collector potential of Congshuanglei 5 is pulled by the resistor M to the sub-junction of the connection point VS, and the high-frequency drive of the pnp dual-loaded transistor s5 is turned off. i day signal ^ this 'level shift circuit wins, output high level and 吝 the invention fully meets the patent three elements: novelty, progressive habits. The present invention has been disclosed above in the preferred embodiment, It should be noted that the same as the embodiment 1 ^, ' should be included in the scope of the present invention. Therefore, the Lai Lang of the present invention is defined as the following application plane rider ^ This is a schematic diagram of the circuit of the fluorescent tube driving circuit. The first figure is a circuit block diagram of the lamp tube driving device invented by the county. 201119512 The second figure is a first embodiment according to the present invention. Schematic diagram of the displacement drive circuit. The fourth figure is a second according to the present invention. The circuit diagram of the displacement driving circuit of the embodiment is shown in Fig. 5. The fifth figure is the signal waveform diagram of the embodiment shown in Fig. 4. The sixth figure is the circuit block diagram of the lamp driving device using the displacement driving circuit of the invention. Figure 7 is a schematic diagram of a displacement drive circuit according to a third embodiment of the present invention. < [Description of main component symbols] Previous technology: Electronic stability controller 10 Lamp 20 Spectrum module 30 Switch module 40 High-end Driver circuit HSD Low-side driver circuit LSD High-side driver pin OUT 1 Low-side driver pin OUT2 Luster-side P-type gold-oxide half-field transistor Ml Low-side N-type gold-oxygen half-field transistor M2 Input power VTN Inductor L1 Capacitor C2 The present invention: controller 100 drive circuit 105 displacement drive circuit 110, 11 〇, lamp 120 13 201119512 resonant module 130 switch module 140 phase adjustment circuit 150, 150', 150" level shift circuit 160, 160', 160”
腳位OUT 電阻 R0、RJ、R2、R3、R4、R5、R6、R7 高端控制訊號Sil 控制訊號Si2 高端電晶體開關T1 低端電晶體開關T2 連接點VS 驅動電壓VCC 輸入電壓源VIN 電感L1 電容C2、C3 NPN雙載子接面電晶體S2、S4、S5 控制訊號Si2Pin OUT resistor R0, RJ, R2, R3, R4, R5, R6, R7 High-end control signal Sil Control signal Si2 High-end transistor switch T1 Low-side transistor switch T2 Connection point VS Drive voltage VCC Input voltage source VIN Inductance L1 Capacitor C2, C3 NPN double carrier junction transistor S2, S4, S5 control signal Si2
PNP雙載子接面電晶體S1、S3 二極體D2、D3 連接點VS 高端電晶體開關之閘極電位V1 低端電晶體開關之閘極電位V2 連接點電位V3 驅動電路LSD 高端驅動腳位HO 低端驅動腳位LO 輸出訊號SL、SH 齊納二極體Z1 14PNP bipolar junction transistor S1, S3 diode D2, D3 connection point VS high-end transistor switch gate potential V1 low-end transistor switch gate potential V2 connection point potential V3 driver circuit LSD high-end driver pin HO low-end driver pin LO output signal SL, SH Zener diode Z1 14
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TW98138752A TW201119512A (en) | 2009-11-16 | 2009-11-16 | Lamp driving apparatus and level shift driving circuit |
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