WO2010082480A1 - Rectification circuit, control circuit for said rectification circuit, and integrated circuit element containing said circuits - Google Patents

Rectification circuit, control circuit for said rectification circuit, and integrated circuit element containing said circuits Download PDF

Info

Publication number
WO2010082480A1
WO2010082480A1 PCT/JP2010/000138 JP2010000138W WO2010082480A1 WO 2010082480 A1 WO2010082480 A1 WO 2010082480A1 JP 2010000138 W JP2010000138 W JP 2010000138W WO 2010082480 A1 WO2010082480 A1 WO 2010082480A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor element
potential
current path
bipolar transistor
control
Prior art date
Application number
PCT/JP2010/000138
Other languages
French (fr)
Japanese (ja)
Inventor
羽田正二
高草英博
岡田實
和田晴樹
Original Assignee
エヌ・ティ・ティ・データ先端技術株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エヌ・ティ・ティ・データ先端技術株式会社 filed Critical エヌ・ティ・ティ・データ先端技術株式会社
Publication of WO2010082480A1 publication Critical patent/WO2010082480A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6877Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the control circuit comprising active elements different from those used in the output circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06Modifications for ensuring a fully conducting state
    • H03K17/063Modifications for ensuring a fully conducting state in field-effect transistor switches
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30Modifications for providing a predetermined threshold before switching
    • H03K17/302Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the present invention relates to a diode circuit, an ORingFET diode application circuit, and the like realized by a low-loss rectifier circuit in which an FET is highly controlled, and to a diode circuit suitable for a rectifier circuit such as a switching power source to which this is applied.
  • a normal PN-junction silicon diode has a forward voltage drop of about 0.6 V to 1 V.
  • the power loss is great.
  • the forward voltage drop is about 0.2 V to 0.4 V, and the magnitude of power loss is not significantly different from that of a silicon diode.
  • this diode has a small reverse withstand voltage, it is not suitable for high voltage rectification.
  • a DC power source for example, a DC / DC converter
  • a DC power supply outputs are connected in parallel through diodes.
  • these devices are driven at a low voltage. Therefore, since a DC power supply having a low output voltage (12 V is becoming standard) is used, when a normal PN junction silicon diode or Schottky barrier diode is used for the OR diode circuit, the order of the DC power supply voltage is reduced.
  • the rate of directional voltage drop is large, and power loss and waste of voltage are large. Therefore, a low-loss rectifier circuit using a FET with a low conduction resistance can be considered. Further, when a FET (a field-effect transistor) used in a synchronous rectifier circuit having a rectifying action is controlled, a complicated circuit is obtained. A switching power supply diode used for the same purpose is required to have a high frequency response.
  • Patent Document 1 The operation of Patent Document 1 is as follows. (1) When the source potential of the FET 1 is lower than the drain potential or when the terminal 12 is open, the emitter potential of the bipolar transistor 3 is lower than the base potential, so that the bipolar transistor 3 is non-conductive. The collector potential of the transistor 3 is high and the FET 1 becomes conductive. (2) When the emitter potential of the bipolar transistor 3 is higher than the base potential, the bipolar transistor 3 becomes conductive. Therefore, the collector potential of the bipolar transistor 3 is lowered and the FET 1 becomes non-conductive.
  • the present invention is a rectifier circuit that reliably prevents backflow, and realizes an ORingFET diode application circuit, a diode circuit suitable for a switching power supply circuit, and the like.
  • a rectifier circuit is: A first semiconductor element having a first control end and having one end and the other end of a current path; A second semiconductor element having a second control end and having one end and the other end of a current path; A third semiconductor element having a third control end and having one end and the other end of a current path; A first resistance element, a second resistance element, and an inductive element; An external bias potential is applied to the second control end and the third control end by the second resistance element, A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow, The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element.
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted.
  • a rectifier circuit is: A first semiconductor element having a first control end and having one end and the other end of a current path; A second semiconductor element having a second control end and having one end and the other end of a current path; A third semiconductor element having a third control end and having one end and the other end of a current path; A first resistance element and a second resistance element; An external bias potential is applied to the second control end and the third control end by the second resistance element, A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow, A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted.
  • a rectifier circuit is: A first semiconductor element having a first control end and having one end and the other end of a current path; A second semiconductor element having a second control end and having one end and the other end of a current path; A third semiconductor element having a third control end and having one end and the other end of a current path; A first resistance element, a second resistance element, and an inductive element; An external bias potential is applied to the second control end and the third control end by the second resistance element, A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and One end of the third semiconductor element is opened, The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the in
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted.
  • a rectifier circuit is: A first semiconductor element having a first control end and having one end and the other end of a current path; A second semiconductor element having a second control end and having one end and the other end of a current path; A third semiconductor element having a third control end and having one end and the other end of a current path; A first resistance element and a second resistance element; An external bias potential is applied to the second control end and the third control end by the second resistance element, A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and One end of the third semiconductor element is opened, A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element.
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted.
  • a control circuit is: A first semiconductor element having a first control end and having one end and the other end of a current path; A second semiconductor element having a second control end and having one end and the other end of a current path; A third semiconductor element having a third control end and having one end and the other end of a current path; A first resistance element, a second resistance element, and an inductive element; An external bias potential is applied to the second control end and the third control end by the second resistance element, A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow, The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted.
  • a control circuit comprising: The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and between the one end and the other end of the current path of the second semiconductor element.
  • a current supplied by an external DC power source flows between the one end and the other end of the current path of the third semiconductor element via the first resistance element. 2 is configured to be transmitted to one end of the first semiconductor element, and is configured to be transmitted to the other end of the third semiconductor element.
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conducted, and the potential at one end of the second semiconductor element is output as a low potential.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is increased. It is output as a potential.
  • a control circuit is: A first semiconductor element having a first control end and having one end and the other end of a current path; A second semiconductor element having a second control end and having one end and the other end of a current path; A third semiconductor element having a third control end and having one end and the other end of a current path; A first resistance element and a second resistance element; An external bias potential is applied to the second control end and the third control end by the second resistance element, A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow, A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element.
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted.
  • the potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and one of the rectifier circuits having a current path between one end of the first semiconductor element and the other end of the first semiconductor element.
  • a control circuit constituting a unit The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of the current path of the second semiconductor element.
  • a current supplied by an external DC power source flows through one end of the current path of the third semiconductor element via the second resistance element via the element, and the potential at the other end of the second semiconductor element is
  • the first semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is configured to be transmitted to the other end of the third semiconductor element.
  • a control circuit is: A first semiconductor element having a first control end and having one end and the other end of a current path; A second semiconductor element having a second control end and having one end and the other end of a current path; A third semiconductor element having a third control end and having one end and the other end of a current path; A first resistance element, a second resistance element, and an inductive element; An external bias potential is applied to the second control end and the third control end by the second resistance element, A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and One end of the third semiconductor element is opened, The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element.
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted.
  • a control circuit comprising: The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of the current path of the second semiconductor element.
  • a current supplied from an external DC power source is configured to flow through the element, one end of the third semiconductor element is opened, and the potential at the other end of the second semiconductor element is transmitted to one end of the first semiconductor element.
  • a control circuit is: A first semiconductor element having a first control end and having one end and the other end of a current path; A second semiconductor element having a second control end and having one end and the other end of a current path; A third semiconductor element having a third control end and having one end and the other end of a current path; A first resistance element and a second resistance element; An external bias potential is applied to the second control end and the third control end by the second resistance element, A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and One end of the third semiconductor element is opened, A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element.
  • the potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element.
  • the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive.
  • the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted.
  • the potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and one of the rectifier circuits having a current path between one end of the first semiconductor element and the other end of the first semiconductor element.
  • a control circuit constituting a unit The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of the current path of the second semiconductor element.
  • a current supplied from an external DC power source is configured to flow through the element, one end of the third semiconductor element is opened, and the potential at the other end of the second semiconductor element is transmitted to one end of the first semiconductor element.
  • the potential of the other end of the first semiconductor element is configured to be transmitted to the other end of the third semiconductor element.
  • the rectifier circuit according to claim 9 is the rectifier circuit according to any one of claims 1 to 4, wherein one end of the second semiconductor element is a collector of a bipolar transistor, and the other end of the second semiconductor element. Is an emitter of a bipolar transistor, and one end of the third semiconductor element is an emitter of the bipolar transistor, and the other end of the third semiconductor element is a collector of the bipolar transistor.
  • the rectifier circuit according to claim 10 is the rectifier circuit according to any one of claims 1 to 4, wherein one end of the second semiconductor element is an emitter of a bipolar transistor, and the other end of the second semiconductor element.
  • the control circuit according to claim 11 is the control circuit according to any one of claims 5 to 8, wherein one end of the second semiconductor element is a collector of a bipolar transistor, and the other end of the second semiconductor element Is an emitter of a bipolar transistor, and one end of the third semiconductor element is an emitter of the bipolar transistor, and the other end of the third semiconductor element is a collector of the bipolar transistor.
  • a control circuit according to claim 12 is the control circuit according to any one of claims 5 to 8, wherein one end of the second semiconductor element is an emitter of a bipolar transistor, and the other end of the second semiconductor element. Is a collector of the bipolar transistor, wherein one end of the third semiconductor element is an emitter of the bipolar transistor, and the other end of the third semiconductor element is a collector of the bipolar transistor.
  • An integrated circuit device according to a thirteenth aspect is characterized in that the rectifier circuit according to any one of the first to fourth aspects, the ninth aspect, and the tenth aspect is incorporated.
  • An integrated circuit device according to a fourteenth aspect is characterized in that the control circuit according to any one of the fifth to eighth, eleventh and twelfth aspects is incorporated.
  • a rectifier circuit according to the present invention uses an FET for the rectification current path, the forward voltage drop due to rectification is extremely small, and the power loss is extremely low.
  • B A rectifier circuit according to the present invention uses an FET as a rectifier current path, and a control circuit in which two bipolar transistors constitute a potential of a portion corresponding to the anode of the rectifier circuit and a potential of a portion corresponding to the cathode of the rectifier circuit
  • the FET is controlled to be conductive / non-conductive, current does not flow backward from the cathode to the anode.
  • circuit block diagrams which show 1st Embodiment of the rectifier circuit by this invention, and a control circuit.
  • These are the circuit block diagrams which show 2nd Embodiment of the rectifier circuit by this invention, and a control circuit.
  • These are the circuit block diagrams which show 3rd Embodiment of the rectifier circuit by this invention, and a control circuit.
  • These are the circuit block diagrams which show 4th Embodiment of the rectifier circuit by this invention, and a control circuit.
  • circuit block diagrams which show 5th Embodiment of the rectifier circuit by this invention, and a control circuit.
  • These are the circuit block diagrams which show 6th Embodiment of the rectifier circuit by this invention, and a control circuit.
  • circuit block diagrams which show 7th Embodiment of the rectifier circuit by this invention, and a control circuit.
  • circuit block diagrams which show 8th Embodiment of the rectifier circuit by this invention, and a control circuit These are the circuit block diagrams which show 9th Embodiment of the rectifier circuit by this invention, and a control circuit.
  • FIG. 1 shows a rectifier circuit according to a first embodiment of the present invention and a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel FETQ1. In FIG. 1, a portion surrounded by a broken line is the control circuit.
  • the control circuit includes an NPN bipolar transistor Q2 that is a second semiconductor element, an NPN bipolar transistor Q3 that is a third semiconductor element, a resistance element R1 that is a first resistance element, and a resistance element R2 that is a second resistance element. .
  • terminal T1 (corresponding to an anode referred to as a diode) for inputting the positive potential of the DC power supply
  • terminal T2 (corresponding to a cathode referred to as a diode) for outputting the positive potential of the DC power supply.
  • the terminal S1 is connected to the source S of the FET Q1
  • the drain D of the FET Q1 is connected to one end of an inductor L, which is an inductive element
  • the other end of the inductor L is connected to the terminal T2.
  • the current flows from the terminal T1 to the terminal T2, that is, from the source S to the drain D of the FET Q1.
  • the current from the drain D to the source S is controlled to be cut off.
  • a collector C of an NPN bipolar transistor Q2 which is a second semiconductor element is connected to the terminal T1
  • a collector C of an NPN bipolar transistor Q3 which is a third semiconductor element is connected to the terminal T2.
  • the base B of the bipolar transistor Q2 and the base B of the bipolar transistor Q3 are connected, and one end of a resistance element R2 that is a second resistance element is connected to this connection portion, and the other end of the resistance element R2 is connected to both bipolar transistors Q2, Q3. Is connected to a terminal T3 to which a DC power supply for supplying a bias potential is applied to the base B.
  • the emitter E of the bipolar transistor Q3 is connected to one end of the resistance element R2. That is, the base and emitter of the bipolar transistor Q3 are short-circuited.
  • the emitter E of the bipolar transistor Q2 is connected to one end of a resistance element R1 which is a first resistance element, and the other end of the resistance element R1 is applied with a DC power supply for supplying the emitter E potential of the bipolar transistor Q2 and the gate potential of the FET Q1.
  • the bipolar transistor Q3 is used as a collector C ground, but since an external DC power supply potential is applied to the terminal T2, a collector whose breakdown voltage is higher than that of the emitter is connected to the terminal T2.
  • the bipolar transistor Q2 is also used as the collector C ground so that the operating characteristics of both bipolar transistors Q2 and Q3 are made uniform.
  • the emitter E of the bipolar transistor Q2 is connected to the gate G of the FET Q1, and the collector C of the bipolar transistor Q2 is connected to the source of the FET Q1.
  • a circuit surrounded by a broken line composed of the bipolar transistor Q2, the bipolar transistor Q3, the resistor element R1, and the resistor element R2 is the control circuit of the present invention which is a part of the rectifier circuit of the present invention.
  • the rectifier circuit in the circuit of FIG. 1 of the present invention comprises a diode having the terminal T1 as an anode and the terminal T2 as a cathode, and the control circuit discriminates the voltage polarity applied between the terminals T1 and T2, and the gate of the FET Q1.
  • the potential applied to G is controlled to control the conduction / non-conduction of the FET Q1.
  • One end of a DC power source for load operation is connected to the terminal T1, and one end of the load is connected to the terminal T2.
  • the other end of the DC power supply and the other end of the load are connected by another current path to form a current path of the DC power supply and the load.
  • one end of the DC power source has a positive potential and the other end of the DC power source has a negative potential.
  • the FET Q1 when the FET Q1 is non-conductive, the current from the drain D to the source S of the FET Q1 does not flow, but the current from the source to the drain flows by the body diode of the FET Q1. Is possible. However, since there is a precondition that the FET Q1 is non-conductive when V1 ⁇ V2, there is no current from the source toward the drain.
  • the FET Q1 when the FET Q1 is conductive, a current flowing from the source S to the drain D of the FET Q1 flows, but a current flowing from the drain D to the source S of the FET Q1 can also flow. However, since there is a precondition that the FET Q1 becomes conductive when V1> V2, there is no current from the drain of the FET Q1 toward the source. When the FET Q1 is conductive, a current flowing from the source to the drain direction can be flowed by the extremely low conductive resistance of the FET Q1 regardless of the body diode of the FET Q1, which is far more advantageous than the rectification by the PN junction diode.
  • hfe2 is a current amplification factor when the collector C of the bipolar transistor Q2 is grounded
  • hfe3 is a current amplification factor when the collector C of the bipolar transistor Q3 is grounded.
  • I BC2 is the base current of the bipolar transistor Q2, and I BC3 is the base current of the bipolar transistor Q3.
  • IEC2 is the emitter current of the bipolar transistor Q2, and IEC3 is the emitter current of the bipolar transistor Q3.
  • r1 is the resistance value of the resistance element R1, and r2 is the resistance value of the resistance element R2.
  • V BC2 is the base potential with respect to the collector potential of the bipolar transistor Q2
  • V BC3 is a base potential with respect to the collector potential of the bipolar transistor Q3.
  • the base forward voltage VBC2 is a voltage at which the emitter E and the collector C of the bipolar transistor Q2 are conducted.
  • the base forward voltage VBC3 is a voltage that conducts between the emitter E and the collector C of the bipolar transistor Q3.
  • hfe2 I EC2 / I BC2
  • hfe3 I EC3 / I BC3
  • I EC2 is represented by a reciprocal function of r1
  • I EC3 is represented by a reciprocal function of r2
  • Formula (1-1) In the case of hfe2> hfe3, r1 ⁇ r2...
  • I EC3 ⁇ V3 / r2 and I EC2 V3 / r1.
  • V3 is a DC power supply potential applied to the terminal T3.
  • the bipolar transistor Q2 Since the bipolar transistor Q2 is reliably turned on, the collector C potential of the bipolar transistor Q2 is reduced to about 0 V, and the FET Q1 is non-conductive at the gate G of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
  • Vc2 ⁇ Vc3 ′ (the state where V1 ⁇ V2; the collector potential of the bipolar transistor Q2 ⁇ the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 is non-conductive and the bipolar transistor Q2 is reliably conductive. If Vc2 ⁇ Vc3 ′ is expressed in another way, Vc2 ⁇ Vc3 ′ can be expressed as Vc2 ⁇ Vc3 + V ⁇ .
  • the potential of the collector C of the bipolar transistor Q2 decreases to approximately 0 V, and the FET Q1 is non-conductive at the gate G of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
  • bipolar transistor Q3 becomes non-conductive is that, for the base B of the bipolar transistor Q3, the reverse bias voltage is applied from the collector side, and the base current does not flow.
  • Vc2> Vc3 ′′ (the state of V1> V2, the collector potential of the bipolar transistor Q2> the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 is turned on and the bipolar transistor Q2 is turned off.
  • Vc2> Vc3 ′′ can be expressed as Vc2> Vc3-V ⁇ .
  • the emitter E potential of the bipolar transistor Q2 rises and becomes the DC power supply potential applied to the terminal T3, and the FET Q1 becomes conductive at the gate potential of the FET Q1 to which this potential is applied. Therefore, a current flows from the source S of the FET Q1 to the drain D, the source S of the FET Q1 has a function of an anode of the diode, and the drain D of the FET Q1 has a function of a cathode of the diode.
  • the reason why the bipolar transistor Q3 becomes conductive is that the forward bias voltage is applied from the collector C side to the base B of the bipolar transistor Q3, and the base current flows sufficiently.
  • the reason why the inductor L, which is an inductive element, is inserted between the drain D of the FET Q1 and the terminal T2 is to improve the frequency characteristics related to current path interruption that makes the FET Q1 of the circuit non-conductive. . That is, rectification can be performed without backflow in rectification of high-frequency current. That is, it corresponds to a high frequency.
  • This operating principle is that when the potential applied between the terminals T1 and T2 transitions from V1> V2 to V1 ⁇ V2, the collector potential of the bipolar transistor Q3 immediately becomes V2, but the inductor L causes the drain of the FET Q1 to This is because a delay occurs in the applied potential V2, and time is taken until the FET Q1 becomes non-conductive.
  • the inductor L is not inserted in the drain D-side current path of the FET Q1 in the current path in which the FET Q1 is disposed, the potential transfer due to the charge discharge time of each element, particularly the bipolar transistors Q2 and Q3 and the gate of the FET Q1. This causes a time delay for the FET Q1 to transition from conduction to non-conduction. Therefore, the current flows backward from the drain D to the source S of the FET Q1 while the FET Q1 is in the conductive state.
  • the inductor L has a function of delaying transmission of the potential V2 applied to the terminal T2 to the drain D of the FET Q1.
  • This inductor L can be adapted to a rectifier circuit such as a switching power supply to which a harmonic pulse potential is applied.
  • FIG. 2 shows a rectifier circuit according to a second embodiment of the present invention and a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel FETQ1.
  • the control circuit includes an NPN bipolar transistor Q2 as a second semiconductor element, an NPN bipolar transistor Q3 as a third semiconductor element, a resistance element R1 as a first resistance element, and a resistance element R2 as a second resistance element. .
  • terminal T1 (corresponding to an anode referred to as a diode) for inputting the positive potential of the DC power supply
  • terminal T2 (corresponding to a cathode referred to as a diode) for outputting the positive potential of the DC power supply
  • terminal T1 ′ for inputting the negative potential of the DC power supply
  • terminal T2 ′ for outputting the negative potential of the DC power supply.
  • the terminal T2 ′ is not essential and may not be present.
  • a DC power supply to be supplied to the load is input between the terminals T1 and T1 ′, and this power supply is diverted to the power supply for operating the control circuit.
  • the terminal T1 ′ may be omitted in the present invention.
  • the terminal T1 includes a collector of an NPN bipolar transistor Q2 as a second semiconductor element, one end of a capacitor C as a capacitive element, and a PDn cathode of a series circuit of photodiodes PD1 to PDn as light receiving elements constituting a DC power supply for a control circuit. And an anode of a light emitting diode LED which is a light emitting element for exciting the photodiode.
  • the terminal T1 ′ and the terminal T2 ′ are connected, and a cathode of a constant current diode RD that is a constant current element is connected to the connection portion, and an anode of the constant current diode RD is connected to a cathode of the light emitting element LED.
  • the anode of the photodiode PD1, the other end of the capacitor C, the other end of the resistance element R1 that is a resistance element, and the other end of the resistance element R2 that is a resistance element are connected.
  • the inductor L which is the inductive element shown in FIG. 1 of the first embodiment does not exist, and the drain D of the FET Q1 which is the first semiconductor element Terminal T2 is directly connected.
  • the control circuit configured by the resistance element R2 that is a resistance element and the N-channel FET Q1 that is the first semiconductor element constitute a rectification current path and the rectification circuit as a whole.
  • the difference from FIG. 1 is a light receiving element that emits light from a light emitting diode LED that is a light emitting element by using a DC power source applied between the terminal T1 and the terminal T1 ′, and receives this light emission.
  • the control circuit operation power supply voltage is generated by the photodiodes PD1 to PDn.
  • the inductor L does not exist in FIG. Therefore, in FIG. 1, the potential V2 of the terminal T2 is directly applied to the collector C of the bipolar transistor Q3, whereas it is applied to the drain D of the FET Q1 through the inductor L. In FIG. The potential V2 of the terminal T2 is applied directly to the collector C of the bipolar transistor Q3 and to the drain D of the FET Q1.
  • the description of the circuit operation of FIG. 2 according to the second embodiment can be applied to the description of the circuit operation of FIG. 1 according to the first embodiment. Therefore, the description of the circuit operation in FIG. 1 is used for the description of the circuit operation in FIG. 2, and the overlapping description is omitted.
  • FIG. 3 shows a rectifier circuit according to a third embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
  • the inductor L which is an inductive element
  • the inductor L is removed from the circuit of FIG. 1 in the first embodiment, and the terminal T2 and the drain D of the FET Q1 are directly connected.
  • the connection between the base B and the emitter E of the transistor Q3 is opened. That is, the emitter of the bipolar transistor Q3 is open. Therefore, the reference numerals of the elements in the circuit of FIG. 3 are the same as the reference numerals of the elements of the circuit in FIG. 1, and the description of the circuit configuration in FIG.
  • the inductor L which is an inductive element, is removed from the circuit of FIG. 1 in the first embodiment, and the terminal T2 and the drain D of the FET Q1 are directly connected. In this circuit, the connection between the base B and the emitter E of the transistor Q3 is opened.
  • the circuit of FIG. 3 which is the third embodiment of the present invention is a circuit in which the base B and the emitter E of the bipolar transistor Q3 are not connected, that is, the circuit of FIG. 3 in the third embodiment of the present invention. This is the reason why the control circuit surrounded by the broken line is different from the circuit operation of the control circuit surrounded by the broken line in FIG. 1 according to the first embodiment of the present invention. Also in the description of the third embodiment of the present invention, the same symbols are used for symbols such as potential value, current value, current amplification factor, and resistance value used in the description of the first embodiment. The significance is the same.
  • the bipolar transistor Q3 functions as a PN junction diode with the base B being P-type and the collector C being N-type.
  • I BC3 + I BC2 V3 / r2 and V3 / r2 is constant, I BC3 is larger when the emitter current of bipolar transistor Q3 does not flow than when the emitter current of bipolar transistor Q3 flows. .
  • the potential of the emitter E of the bipolar transistor Q2 is reduced to approximately 0 V due to a voltage drop caused by the resistance element R1 (operation of the control circuit).
  • the FET Q1 is non-conductive due to the gate potential of the FET Q1 to which this potential is transmitted (operation of the rectifier circuit in addition to the operation of the control circuit). That is, no current flows from the drain D to the source S of the FET Q1. Therefore, the circuit of FIG. 3 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.
  • I ′ BC3 is the base current of the bipolar transistor Q3 when the emitter E of the bipolar transistor Q3 is opened.
  • V ′′ BC3 is a base potential with respect to the collector potential of the bipolar transistor Q3 when the emitter E of the bipolar transistor Q3 is opened.
  • Source potential of FETQ1 drain potential.
  • Collector potential of bipolar transistor Q2 collector potential of bipolar transistor Q3.) Since the base forward voltage V ′′ BC3 of the bipolar transistor Q3 is about 0.6V (the forward voltage of a standard PN junction diode), the bipolar transistor Q3 has a base forward voltage V BC2 of the bipolar transistor Q2 lower than this voltage. The bipolar transistor Q2 is reliably turned on by the base potential of the bipolar transistor Q2 having the common base potential.
  • the bipolar transistor Q2 since the bipolar transistor Q2 is surely turned on, the emitter potential of the bipolar transistor Q2 is reduced to about 0 V, and the FET Q1 is non-conductive at the gate of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
  • Vc2 ⁇ Vc3 ′ V1 ⁇ V2 state.
  • Collector potential of bipolar transistor Q2 ⁇ collector potential of bipolar transistor Q3.
  • Source potential of FET Q1 ⁇ drain potential bipolar transistor Q2 is surely turned on.
  • Vc2 ⁇ Vc3 ′ is expressed in another way, Vc2 ⁇ Vc3 ′ can be expressed as Vc2 ⁇ Vc3 + V ⁇ .
  • the bipolar transistor Q3 maintains the potential difference between its own collector C and base B, so the base potential rises by V ⁇ . Will do. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 further increases, and the bipolar transistor Q2 is surely turned on.
  • the potential of the emitter E of the bipolar transistor Q2 decreases to about 0 V, and the FET Q1 is non-conductive at the gate of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
  • Vc2> Vc3 This is V1> V2 (the collector potential of the bipolar transistor Q2> the collector potential of the bipolar transistor Q3.
  • Vc2> Vc3 ′′ can be expressed as Vc2> Vc3-V ⁇ .
  • the base potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 decreases, and the bipolar transistor Q2 becomes non-conductive.
  • the emitter E potential of the bipolar transistor Q2 rises and becomes the DC power supply potential applied to the terminal T3, and the FET Q1 becomes conductive at the gate potential of the FET Q1 to which this potential is applied.
  • FIG. 4 shows a rectifier circuit according to a fourth embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
  • the control circuit is a circuit surrounded by a broken line in FIG.
  • the circuit of FIG. 4 in the fourth embodiment is similar to the circuit of FIG. 2 in the second embodiment in that the emitter follower current is generated by an NPN bipolar transistor Q4 as a fourth semiconductor element and a PNP bipolar transistor Q5 as a fifth semiconductor element.
  • An amplifier circuit is added. This is the only difference between the circuits of FIG. 4 and FIG. Therefore, in the circuit of FIG. 4, each element of the circuit common to the circuit of FIG. 2 that is the second embodiment is denoted by the same reference numeral as that of FIG. 2, and the description of the circuit configuration of FIG. And omit duplicate explanations.
  • the bases of the bipolar transistors Q4 and Q5 are connected to the collector C of the bipolar transistor Q2, the emitters of the bipolar transistors Q4 and Q5 are connected to the gate G of the FET Q1, and the collector of the bipolar transistor Q4 is The collector of the bipolar transistor Q5 is connected to the terminal T3 and the terminal T1.
  • FIG. 4 An emitter follower current amplifier circuit is added to FIG. 2 which is the second embodiment, and a current sufficient to charge the gate capacitance of the FET Q1 can be supplied.
  • the bipolar transistor Q4 When the emitter potential of the bipolar transistor Q2 is high (the potential at the terminal T3), the bipolar transistor Q4 is turned on, the bipolar transistor Q5 is turned off, the FET Q1 is turned on, and the emitter potential of the bipolar transistor Q2 is low (the potential at the terminal T1). At this time, bipolar transistor Q4 is non-conductive, bipolar transistor Q5 is conductive, and FET Q1 is non-conductive.
  • circuit operation of the second embodiment is as described in FIG. 2, and the circuit operation description of the second embodiment uses the circuit operation description of the first embodiment. . Therefore, the circuit operation description of FIG. 4 which is the fourth embodiment uses the circuit operation descriptions of FIG. 1 and FIG. 2 which are the first and second embodiments, and omits the overlapping description.
  • FIG. 5 shows a rectifier circuit according to a fifth embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
  • the control circuit is a circuit surrounded by a broken line in FIG.
  • the PNP bipolar transistor Q5 which is a fifth semiconductor element constituting a part of the emitter follower circuit in the circuit of FIG. 4 in the fourth embodiment, is replaced with a diode that is a rectifier. D is replaced.
  • This diode D corresponds to a PN junction diode formed by the emitter E and base B of the bipolar transistor Q5.
  • the anode of the diode D is connected to the emitter E of the bipolar transistor Q4, and the cathode of the diode D is connected to the emitter E of the bipolar transistor Q2.
  • the circuit operation of the rectifier circuit and the control circuit according to the fifth embodiment of the present invention will be described with reference to FIG.
  • the diode D in FIG. 5 plays a role of discharging the charge accumulated in the gate G of the FET Q1 and making the FET Q1 non-conductive when the FET Q1 is made conductive. This is possible because the bipolar transistor Q2 is conducting when the FET Q1 is non-conducting, so that the cathode of the diode D is conducting with the collector C of the bipolar transistor Q2.
  • circuit operation of FIG. 4 is the description of the fourth embodiment.
  • the circuit operation description of the fourth embodiment is based on the circuit operation description of the second embodiment.
  • the circuit operation description of the second embodiment uses the circuit operation description of the first embodiment. Therefore, the description of the circuit operation of FIG. 5 which is the fifth embodiment overlaps with the description of the circuit operation of FIG. 1, FIG. 2 and FIG. 4 which is the first, second and fourth embodiments. I will omit the explanation.
  • FIG. 6 shows a rectifier circuit according to a sixth embodiment of the present invention and a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel FETQ1. In FIG. 6, the portion surrounded by a broken line is the control circuit.
  • the control circuit includes an NPN bipolar transistor Q2 that is a second semiconductor element, an NPN bipolar transistor Q3 that is a third semiconductor element, a resistance element R1 that is a first resistance element, and a resistance element R2 that is a second resistance element. .
  • terminal T1 (corresponding to an anode referred to as a diode) for inputting the positive potential of the DC power supply
  • terminal T2 (corresponding to a cathode referred to as a diode) for outputting the positive potential of the DC power supply.
  • the terminal S1 is connected to the source S of the FET Q1
  • the drain D of the FET Q1 is connected to one end of an inductor L, which is an inductive element
  • the other end of the inductor L is connected to the terminal T2.
  • the current flows from the terminal T1 to the terminal T2, that is, from the source S to the drain D of the FET Q1.
  • the current from the drain D to the source S is controlled to be cut off.
  • an emitter E of an NPN bipolar transistor Q2 that is a second semiconductor element is connected to the terminal T1
  • a collector C of an NPN bipolar transistor Q3 that is a third semiconductor element is connected to the terminal T2.
  • the base B of the bipolar transistor Q2 and the base B of the bipolar transistor Q3 are connected, and one end of a resistance element R2 that is a second resistance element is connected to this connection portion, and the other end of the resistance element R2 is connected to both bipolar transistors Q2, Q3. Is connected to a terminal T3 to which a DC power supply for supplying a bias potential is applied to the base B.
  • the emitter E of the bipolar transistor Q3 is connected to one end of the resistance element R2. That is, the base and emitter of the bipolar transistor Q3 are short-circuited.
  • the collector C of the bipolar transistor Q2 is connected to one end of a resistance element R1 that is a first resistance element, and the other end of the resistance element R1 is applied with a DC power supply that supplies the collector C potential of the bipolar transistor Q2 and the gate potential of the FET Q1. Connected to terminal T3.
  • the collector C of the bipolar transistor Q2 is connected to the gate G of the FET Q1, and the emitter E of the bipolar transistor Q2 is connected to the source of the FET Q1.
  • a circuit surrounded by a broken line composed of the bipolar transistor Q2, the bipolar transistor Q3, the resistor element R1, and the resistor element R2 is the control circuit of the present invention which is a part of the rectifier circuit of the present invention.
  • the rectifier circuit in the circuit of FIG. 1 of the present invention comprises a diode having the terminal T1 as an anode and the terminal T2 as a cathode, and the control circuit discriminates the voltage polarity applied between the terminals T1 and T2, and the gate of the FET Q1.
  • the potential applied to G is controlled to control the conduction / non-conduction of the FET Q1.
  • One end of a DC power source for load operation is connected to the terminal T1, and one end of the load is connected to the terminal T2.
  • the other end of the DC power supply and the other end of the load are connected by another current path to form a current path of the DC power supply and the load.
  • one end of the DC power source has a positive potential and the other end of the DC power source has a negative potential.
  • the FET Q1 when the FET Q1 is non-conductive, the current from the drain D to the source S of the FET Q1 does not flow, but the current from the source to the drain flows by the body diode of the FET Q1. Is possible. However, since there is a precondition that the FET Q1 is non-conductive when V1 ⁇ V2, there is no current from the source toward the drain.
  • the FET Q1 when the FET Q1 is conductive, a current flowing from the source S to the drain D of the FET Q1 flows, but a current flowing from the drain D to the source S of the FET Q1 can also flow. However, since there is a precondition that the FET Q1 becomes conductive when V1> V2, there is no current from the drain of the FET Q1 toward the source. When the FET Q1 is conductive, a current flowing from the source to the drain direction can be flowed by the extremely low conductive resistance of the FET Q1 regardless of the body diode of the FET Q1, which is far more advantageous than the rectification by the PN junction diode.
  • hfe2 is the current amplification factor when the emitter E of the bipolar transistor Q2 is grounded
  • hfe3 is the current amplification factor when the collector C of the bipolar transistor Q3 is grounded.
  • I BE2 is the base current of the bipolar transistor Q2
  • I BC3 is the base current of the bipolar transistor Q3.
  • I CE2 is the collector current of the bipolar transistor Q2, and IEC3 is the emitter current of the bipolar transistor Q3.
  • r1 is the resistance value of the resistance element R1, and r2 is the resistance value of the resistance element R2.
  • the emitter potential of the bipolar transistor Q2 is Ve2
  • V BE2 is a base potential with respect to the emitter potential of the bipolar transistor Q2
  • V BC3 is a base potential with respect to the collector potential of the bipolar transistor Q3.
  • the base forward voltage V BE2 is a voltage at which the collector C and the emitter E of the bipolar transistor Q2 are conducted.
  • the base forward voltage VBC3 is a voltage that conducts between the emitter E and the collector C of the bipolar transistor Q3.
  • hfe3 I EC3 / I BC3
  • I CE2 is expressed as a function of the reciprocal of r1
  • I EC3 is expressed as a function of the reciprocal of r2.
  • I EC3 ⁇ V3 / r2 and I CE2 V3 / r1.
  • V3 is a DC power supply potential applied to the terminal T3.
  • the bipolar transistor Q2 Since the bipolar transistor Q2 is reliably turned on, the collector C potential of the bipolar transistor Q2 is reduced to about 0 V, and the FET Q1 is non-conductive at the gate G of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
  • Ve2 ⁇ Vc3 ′ (the state of V1 ⁇ V2, the emitter potential of the bipolar transistor Q2 ⁇ the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 is non-conductive, and the bipolar transistor Q2 is reliably conductive. If Ve2 ⁇ Vc3 ′ is expressed in another way, Vc2 ⁇ Vc3 ′ can be expressed as Ve2 ⁇ Vc3 + V ⁇ .
  • the potential of the collector C of the bipolar transistor Q2 decreases to approximately 0 V, and the FET Q1 is non-conductive at the gate G of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
  • bipolar transistor Q3 becomes non-conductive is that, for the base B of the bipolar transistor Q3, the reverse bias voltage is applied from the collector side, and the base current does not flow.
  • Ve2> Vc3 ′′ (the state of V1> V2, the emitter potential of the bipolar transistor Q2> the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 becomes conductive and the bipolar transistor Q2 becomes nonconductive. If Ve2> Vc3 ′′ is expressed in another way, Ve2> Vc3 ′′ can be expressed as Ve2> Vc3-V ⁇ .
  • the collector C potential of the bipolar transistor Q2 rises and becomes the DC power supply potential applied to the terminal T3, and the FET Q1 becomes conductive at the gate G of the FET Q1 to which this potential is applied. Therefore, a current flows from the source S of the FET Q1 to the drain D, the source S of the FET Q1 has a function of an anode of the diode, and the drain D of the FET Q1 has a function of a cathode of the diode.
  • the reason why the bipolar transistor Q3 becomes conductive is that the forward bias voltage is applied from the collector C side to the base B of the bipolar transistor Q3, and the base current flows sufficiently.
  • the reason why the inductor L, which is an inductive element, is inserted between the drain D of the FET Q1 and the terminal T2 is to improve the frequency characteristics related to the current path interruption that makes the FET Q1 of the circuit non-conductive. .
  • This operating principle is that when the potential applied between the terminal T1 and the terminal T2 transitions from V1> V2 to V1 ⁇ V2, the collector potential of the bipolar transistor Q3 immediately becomes V2, but the inductor L causes the drain of the FET Q1 to be drained. This is because a delay occurs in the applied potential V2, and time is taken until the FET Q1 becomes non-conductive.
  • the inductor L is not inserted in the drain D-side current path of the FET Q1 in the current path in which the FET Q1 is disposed, the potential due to the charge discharge time of each element, in particular, the gates of the bipolar transistors Q2, Q3 and FET Q1 Due to the transmission delay, a time delay occurs for the FET Q1 to transition from conduction to non-conduction. Therefore, the current flows backward from the drain D to the source S of the FET Q1 while the FET Q1 is in the conductive state.
  • the inductor L has a function of delaying transmission of the potential V2 applied to the terminal T2 to the drain D of the FET Q1.
  • This inductor L can be adapted to a rectifier circuit such as a switching power supply to which a harmonic pulse potential is applied.
  • FIG. 7 shows a rectifier circuit according to a seventh embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
  • FIG. 7 in the seventh embodiment is a circuit in which the inductor L, which is an inductive element, is removed from FIG. 6 in the sixth embodiment, and the terminal T2 and the drain D of the FET Q1 are directly connected. Therefore, in the circuit of FIG. 7, the reference numerals of the elements other than the inductor L are the same as those of the elements of the circuit of FIG. 6, and the description of the circuit configuration of FIG. Omit.
  • Seventh Embodiment (7-2) Circuit Operation The circuit of FIG. 7 in the seventh embodiment removes the inductor L that is an inductive element from the circuit of FIG. 6 in the sixth embodiment. , A circuit in which the terminal T2 and the drain D of the FET Q1 are directly connected. Therefore, the description of the circuit operation in FIG. 7 is the same as that in which the operation description of the inductor L, which is an inductive element, is deleted from the description of the circuit operation in FIG. 6, and the same overlapping description is omitted.
  • FIG. 8 shows a rectifier circuit according to an eighth embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
  • the circuit of FIG. 8 in the eighth embodiment removes the inductor L, which is an inductive element, from the circuit of FIG. 6 in the sixth embodiment, directly connects the terminal T2 and the drain D of the FET Q1, and is further bipolar.
  • the connection between the base B and the emitter E of the transistor Q3 is opened. That is, the emitter of the bipolar transistor Q3 is open. Therefore, the reference numerals of the elements of the circuit of FIG. 8 are the same as the reference numerals of the elements of the circuit of FIG. 6, the description of the circuit configuration of FIG. 6 is used, and the overlapping description is omitted.
  • the circuit of FIG. 8 in the eighth embodiment removes the inductor L that is an inductive element from the circuit of FIG. 6 in the sixth embodiment, directly connects the output terminal T2 and the drain D of the FET Q1, In this circuit, the connection between the base B and the emitter E of the bipolar transistor Q3 is opened.
  • the circuit of FIG. 8 which is the eighth embodiment of the present invention is a circuit in which the base B and the emitter E of the bipolar transistor Q3 are not connected, that is, surrounded by a broken line in the eighth embodiment of the present invention. This is the reason why the control circuit is different from the circuit operation of the control circuit surrounded by the broken line in FIG. 6 which is the sixth embodiment of the present invention.
  • the same symbols are used for symbols such as potential value, current value, current amplification factor, resistance value, etc. used in the sixth embodiment, and Identical.
  • the inductor L does not exist in the circuit of FIG. 8, a high frequency cutoff characteristic that does not need to improve the frequency characteristic related to the current path cutoff (the FET Q1 is made non-conductive) in the operation of the circuit of FIG. 6 is required.
  • This is suitable for a rectifier circuit that is not connected, an ORingFET diode circuit for connecting DC power supplies in parallel, and the like.
  • the bipolar transistor Q3 functions as a PN junction diode with the base B being P-type and the collector C being N-type.
  • the potential of the collector C of the bipolar transistor Q2 is reduced to approximately 0 V due to a voltage drop caused by the resistance element R1 (operation of the control circuit).
  • the FET Q1 is non-conductive due to the gate potential of the FET Q1 to which this potential is transmitted (operation of the rectifier circuit in addition to the operation of the control circuit). That is, no current flows from the drain D to the source S of the FET Q1. Therefore, the circuit of FIG. 4 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.
  • Formula (5) means Formula (6). That is, the base current I BE2 of the bipolar transistor Q2 is set smaller than the base current I ′ BC3 of the bipolar transistor Q3.
  • I ′ BC3 is the base current of the bipolar transistor Q3 when the emitter E of the bipolar transistor Q3 is opened.
  • V ′′ BC3 is a base potential with respect to the collector potential of the bipolar transistor Q3 when the emitter E of the bipolar transistor Q3 is opened.
  • Emitter potential of bipolar transistor Q2 collector potential of bipolar transistor Q3.
  • Source potential of FETQ1 drain potential) Since the base forward voltage V ′′ BC3 of the bipolar transistor Q3 is about 0.6V (standard PN junction diode forward voltage), the bipolar transistor Q3 has a base forward voltage V BE2 of the bipolar transistor Q2 lower than this voltage.
  • the bipolar transistor Q2 is reliably turned on by the base potential of the bipolar transistor Q2 having a common base potential.
  • V ′′ BC3 > V ′′ ′ BC3 V ′′ BE2 > VBE2 .
  • the bipolar transistor Q2 since the bipolar transistor Q2 is surely turned on, the collector C potential of the bipolar transistor Q2 is reduced to about 0 V, and the FET Q1 is non-conductive at the gate of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
  • Vc2 ⁇ Vc3 ′ the state of V1 ⁇ V2, the emitter potential of the bipolar transistor Q2 ⁇ the collector potential of the bipolar transistor Q3. The source potential of the FET Q1 ⁇ the drain potential), the bipolar transistor Q2 is surely turned on. If Ve2 ⁇ Vc3 ′ is expressed in another way, Vc2 ⁇ Vc3 ′ can be expressed as Ve2 ⁇ Vc3 + V ⁇ .
  • the bipolar transistor Q3 maintains the determined potential difference between its own collector C and base B. V ⁇ will rise. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 further increases, and the bipolar transistor Q2 is surely turned on.
  • the potential of the collector C of the bipolar transistor Q2 decreases to approximately 0 V, and the FET Q1 is non-conductive at the gate of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
  • Ve2> Vc3 This is the state of V1> V2, where the emitter potential of the bipolar transistor Q2> the collector potential of the bipolar transistor Q3 and the source potential of the FET Q1> the drain potential. At this time, bipolar transistor Q2 becomes non-conductive. If Ve2> Vc3 ′′ is expressed in another way, Ve2> Vc3 ′′ can be expressed as Ve2> Vc3-V ⁇ . In addition to the description of the above condition A8, when the potential of the collector C of the bipolar transistor Q3 is lowered by V ⁇ from Vc3, the base potential is lowered by V ⁇ in order to maintain the predetermined potential between the collector C and base B. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 decreases, and the bipolar transistor Q2 becomes non-conductive.
  • the collector C potential of the bipolar transistor Q2 rises and becomes the DC power supply potential applied to the terminal T3, and the FET Q1 becomes conductive at the gate of the FET Q1 to which this potential is applied.
  • FIG. 9 shows a rectifier circuit according to a ninth embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
  • the control circuit is a circuit surrounded by a broken line in FIG.
  • the circuit of FIG. 9 in the ninth embodiment is different from the circuit of FIG. 6 in the sixth embodiment in that an emitter follower current is generated by an NPN bipolar transistor Q4 as a fourth semiconductor element and a PNP bipolar transistor Q5 as a fifth semiconductor element.
  • An amplifier circuit is added. Therefore, in FIG. 9, the same reference numerals as those in FIG. 6 are given to the elements of the circuit common to the circuit in FIG. 6 as the sixth embodiment, and the description of the circuit configuration in FIG. Omit duplicate explanations.
  • the bases of the bipolar transistors Q4 and Q5 are connected to the collector C of the bipolar transistor Q2, the emitters of the bipolar transistors Q4 and Q5 are connected to the gate G of the FET Q1, and the collector of the bipolar transistor Q4 is connected to the terminal T3. In addition, the collector of the bipolar transistor Q5 is connected to the terminal T1.
  • FIG. 9 An emitter follower current amplifier circuit is added to FIG. 6 which is the sixth embodiment, and a current sufficient to charge the gate capacitance of the FET Q1 can be supplied.
  • the collector potential of the bipolar transistor Q2 is high (the potential at the terminal T3)
  • the bipolar transistor Q4 is turned on
  • the bipolar transistor Q5 is turned off
  • the FET Q1 is turned on
  • the collector potential of the bipolar transistor Q2 is low (the potential at the terminal T1).
  • bipolar transistor Q4 is non-conductive
  • bipolar transistor Q5 is conductive
  • FET Q1 is non-conductive.
  • FIG. 9 uses the description of FIG. 6 and omits the overlapping description.
  • FIGS. 1 to 9 exist.
  • the present invention can be realized by combining the respective characteristic portions shown in FIGS. That is, the combination of the presence or absence of the inductor L, the connection or opening of the base B and the emitter E of the bipolar transistor Q3, and the selection of the collector ground or emitter ground of the bipolar transistor Q2.

Landscapes

  • Power Conversion In General (AREA)
  • Electronic Switches (AREA)
  • Rectifiers (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

A rectification circuit free from low forward voltage drop and reverse current is realized. The circuit is equipped with a first semiconductor element having a first control terminal and one end and the other end of a current path, a second semiconductor element having a second control terminal and one end and the other end of a current path, a third semiconductor element having a third control terminal and one end and the other end of a current path, a first resistive element, a second resistive element, and an inductive element, and is configured such that: an external bias potential is applied to the second control terminal and the third control terminal by the second resistive element; an external direct-current power is supplied to the one end of the current path of the second semiconductor element via the first resistive element, and to the one end of the current path of the third semiconductor element via the second resistive element; the potential at the other end of the second semiconductor element is transmitted to the one end of the first semiconductor element; and the potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element from one end of the inductive element via the other end of the inductive element.

Description

整流回路、該整流回路の制御回路及びこれらそれぞれの回路を内蔵した集積回路素子Rectifier circuit, control circuit for the rectifier circuit, and integrated circuit element incorporating these circuits
 本発明は、FETを高度に制御した低損失整流回路により、ダイオード回路、ORingFETダイオード用途回路等を実現し、また、これを応用したスイッチング電源等の整流回路に適合するダイオード回路に関する。 The present invention relates to a diode circuit, an ORingFET diode application circuit, and the like realized by a low-loss rectifier circuit in which an FET is highly controlled, and to a diode circuit suitable for a rectifier circuit such as a switching power source to which this is applied.
従来から使用されている整流用ダイオードにおいて、通常のPN接合のシリコンダイオードでは、順方向電圧降下は0.6V~1V程度であり、近年、情報処理装置に採用される低電圧駆動のディバイスにおいては、電力損失が大きい。
 また、順方向電圧降下が比較的小さいショットキーバリアダイオードでも順方向電圧降下は、0.2V~0.4V程度であり、電力損失の大きさにおいてシリコンダイオードと大差はない。さらに、このダイオードは逆耐圧電圧が小さいので、高電圧の整流用途として向かない。
ORダイオード回路は、電力容量の小さい直流電源(たとえば、DC/DCコンバータなど)をダイオードにより並列接続し、大電力(大電流)を得たり、同様に並列接続されたディバイスを予備機として使用するためのものであり、すなわち、電源の出力をダイオードを通して複数並列接続するものである。
 最近では、情報処理機器の電力損失(高発熱)を抑えるため、これらの機器は低電圧駆動される。したがって、出力電圧の低い(12Vが標準になりつつある。)直流電源が使用されるため、ORダイオード回路に通常のPN接合のシリコンダイオード又はショットキーバリアダイオードを使用した場合、直流電源電圧に対する順方向電圧降下の割合が大きく電力損失及び電圧の無駄が大きい。したがって、FETを用いた低導通抵抗による低損失整流回路か考えられる。
 また、整流作用をもたせる同期整流回路に使用されるFET(a field-effect transistor)を制御すると複雑な回路となる。同様な目的に使用されるスイッチング電源のダイオードには高い周波数応答が求められる。
In a conventional rectifying diode, a normal PN-junction silicon diode has a forward voltage drop of about 0.6 V to 1 V. In recent years, in a low voltage drive device adopted in an information processing device. The power loss is great.
Even in the case of a Schottky barrier diode having a relatively small forward voltage drop, the forward voltage drop is about 0.2 V to 0.4 V, and the magnitude of power loss is not significantly different from that of a silicon diode. Further, since this diode has a small reverse withstand voltage, it is not suitable for high voltage rectification.
In the OR diode circuit, a DC power source (for example, a DC / DC converter) having a small power capacity is connected in parallel by a diode to obtain a large power (a large current), or similarly a device connected in parallel is used as a spare device. In other words, a plurality of power supply outputs are connected in parallel through diodes.
Recently, in order to suppress power loss (high heat generation) of information processing devices, these devices are driven at a low voltage. Therefore, since a DC power supply having a low output voltage (12 V is becoming standard) is used, when a normal PN junction silicon diode or Schottky barrier diode is used for the OR diode circuit, the order of the DC power supply voltage is reduced. The rate of directional voltage drop is large, and power loss and waste of voltage are large. Therefore, a low-loss rectifier circuit using a FET with a low conduction resistance can be considered.
Further, when a FET (a field-effect transistor) used in a synchronous rectifier circuit having a rectifying action is controlled, a complicated circuit is obtained. A switching power supply diode used for the same purpose is required to have a high frequency response.
特開2004-320873号公報JP 2004-320873 A
 特許文献1の動作は以下のとおりである。
 (1)FET1のソース電位がドレイン電位より低いとき、又は、端子12が開放されているときはバイポーラトランジスタ3のエミッタ電位は、ベース電位よりも低いため、バイポーラトランジスタ3は非導通であり、バイポーラトランジスタ3のコレクタ電位は高く、FET1は導通する。
 (2)バイポーラトランジスタ3のエミッタ電位がベース電位よりも高いとき、バイポーラトランジスタ3は導通する。したがって、バイポーラトランジスタ3のコレクタ電位が低下し、FET1は非導通となる。
 (3)さらにバイポーラトランジスタ3のエミッタ電位が高くなると、バイポーラトランジスタ3のエミッタ→ベース→抵抗素子9→抵抗素子6→バイポーラトランジスタ2のベースの経路でバイポーラトランジスタ3のエミッタ電位が、バイポーラトランジスタ2のベース印加され、仮に、ダイオード4がバイポーラトランジスタ2のベース、エミッタ間に挿入されていないとバイポーラトランジスタ2のベースが高電位となり破壊される。
 (4)上記(3)において、ダイオード4があるため、バイポーラトランジスタ2は破壊されないが、ダイオード4が導通(端子12から端子11へ電流が流れることと等価)し、逆流阻止回路として機能しない。
 (5)抵抗素子7による電位の印加は機能していない。すなわち、抵抗素子7の回路はオープンでよい。
 以上のように、特許文献1の動作は後述する本発明の動作と基本的に相違する。
The operation of Patent Document 1 is as follows.
(1) When the source potential of the FET 1 is lower than the drain potential or when the terminal 12 is open, the emitter potential of the bipolar transistor 3 is lower than the base potential, so that the bipolar transistor 3 is non-conductive. The collector potential of the transistor 3 is high and the FET 1 becomes conductive.
(2) When the emitter potential of the bipolar transistor 3 is higher than the base potential, the bipolar transistor 3 becomes conductive. Therefore, the collector potential of the bipolar transistor 3 is lowered and the FET 1 becomes non-conductive.
(3) When the emitter potential of the bipolar transistor 3 further increases, the emitter potential of the bipolar transistor 3 in the path of the emitter of the bipolar transistor 3 → the base → the resistance element 9 → the resistance element 6 → the base of the bipolar transistor 2 If a base is applied and the diode 4 is not inserted between the base and emitter of the bipolar transistor 2, the base of the bipolar transistor 2 becomes a high potential and is destroyed.
(4) In the above (3), since the diode 4 is present, the bipolar transistor 2 is not destroyed, but the diode 4 becomes conductive (equivalent to current flowing from the terminal 12 to the terminal 11) and does not function as a backflow prevention circuit.
(5) Application of potential by the resistance element 7 does not function. That is, the circuit of the resistance element 7 may be open.
As described above, the operation of Patent Document 1 is basically different from the operation of the present invention described later.
以上の現状に鑑み、本発明は、逆流阻止が確実である整流回路であり、ORingFETダイオード用途回路、スイッチング電源回路に適合するダイオード回路、等を実現する。 In view of the above situation, the present invention is a rectifier circuit that reliably prevents backflow, and realizes an ORingFET diode application circuit, a diode circuit suitable for a switching power supply circuit, and the like.
 上記の目的を実現するべく本発明は以下の構成とする。
(1)請求項1に係る整流回路は、
第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
第1抵抗素子と、第2抵抗素子と、誘導性素子と、を備え、
前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端には前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、
前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、
前記第1半導体素子の一端と前記誘導性素子の他端間を電流路とすることを特徴とする。
(2)請求項2に係る整流回路は、
第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
第1抵抗素子と、第2抵抗素子と、を備え、
前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端には前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、
前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、
前記第1半導体素子の一端と該第1半導体素子の他端間を電流路とすることを特徴とする。
(3)請求項3に係る整流回路は、
第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
第1抵抗素子と、第2抵抗素子と、誘導性素子と、を備え、
前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、
前記第3半導体素子の一端は開放され、
前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、
前記第1半導体素子の一端と前記誘導性素子の他端間を電流路とすることを特徴とする。
(4)請求項4に係る整流回路は、
第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
第1抵抗素子と、第2抵抗素子と、を備え、
前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、
前記第3半導体素子の一端は開放され、
前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、
前記第1半導体素子の一端と該第1半導体素子の他端間を電流路とすることを特徴とする。
(5)請求項5に係る制御回路は、
第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
第1抵抗素子と、第2抵抗素子と、誘導性素子と、を備え、
前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端には前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、
前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、前記第1半導体素子の一端と前記誘導性素子の他端間を電流路とする整流回路の一部を構成する制御回路であって、
該制御回路は、前記第2制御端及び前記第3制御端に、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、前記第2半導体素子の電流路の一端、他端間に前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端、他端間に前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記誘導性素子の他端の電位は前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位を低電位として出力し、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位を高電位として出力することを特徴とする。
(6)請求項6に係る制御回路は、
第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
第1抵抗素子と、第2抵抗素子と、を備え、
前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端には前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、
前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、前記第1半導体素子の一端と該第1半導体素子の他端間を電流路とする整流回路の一部を構成する制御回路であって、
該制御回路は、前記第2制御端及び前記第3制御端に前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、前記第2半導体素子の電流路の一端に前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端に前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は前記第3半導体素子の他端に伝達されるべく構成されることを特徴とする。
(7)請求項7に係る制御回路は、
第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
第1抵抗素子と、第2抵抗素子と、誘導性素子と、を備え、
前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、
前記第3半導体素子の一端は開放され、
前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、前記第1半導体素子の一端と前記誘導性素子の他端間を電流路とする整流回路の一部を構成する制御回路であって、
該制御回路は、前記第2制御端及び前記第3制御端に前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、前記第2半導体素子の電流路の一端に前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、前記第3半導体素子の一端は開放され、前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成されることを特徴とする。
(8)請求項8に係る制御回路は、
第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
第1抵抗素子と、第2抵抗素子と、を備え、
前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、
前記第3半導体素子の一端は開放され、
前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記第3半導体素子の他端に伝達されるべく構成され、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、前記第1半導体素子の一端と該第1半導体素子の他端間を電流路とする整流回路の一部を構成する制御回路であって、
該制御回路は、前記第2制御端及び前記第3制御端に前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、前記第2半導体素子の電流路の一端に前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、前記第3半導体素子の一端は開放され、前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は前記第3半導体素子の他端に伝達されるべく構成されることを特徴とする。
(9)請求項9に係る整流回路は、請求項1~4のいずれかに記載の整流回路において、前記第2半導体素子の一端は、バイポーラトランジスタのコレクタであり、該第2半導体素子他端は、バイポーラトランジスタのエミッタであり、前記第3半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第3半導体素子の他端は、バイポーラトランジスタのコレクタであることを特徴とする。
(10)請求項10に係る整流回路は、請求項1~4のいずれかに記載の整流回路において、前記第2半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第2半導体素子他端は、バイポーラトランジスタのコレクタであり、前記第3半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第3半導体素子の他端は、バイポーラトランジスタのコレクタであることを特徴とする。
(11)請求項11に係る制御回路は、請求項5~8のいずれかに記載の制御回路において、前記第2半導体素子の一端は、バイポーラトランジスタのコレクタであり、該第2半導体素子他端は、バイポーラトランジスタのエミッタであり、前記第3半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第3半導体素子の他端は、バイポーラトランジスタのコレクタであることを特徴とする。
(12)請求項12に係る制御回路は、請求項5~8のいずれかに記載の制御回路において、前記第2半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第2半導体素子他端は、バイポーラトランジスタのコレクタであり、前記第3半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第3半導体素子の他端は、バイポーラトランジスタのコレクタであることを特徴とする。
(13)請求項13に係る集積回路素子は、請求項1~4、9、10のいずれかに記載の整流回路を内蔵したことを特徴とする。
(14)請求項14に係る集積回路素子は、請求項5~8、11、12のいずれかに記載の制御回路を内蔵したことを特徴とする。
In order to achieve the above object, the present invention has the following configuration.
(1) A rectifier circuit according to claim 1 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A first resistance element, a second resistance element, and an inductive element;
An external bias potential is applied to the second control end and the third control end by the second resistance element,
A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow,
The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element. Configured to be transmitted to the other end of the third semiconductor element via the other end,
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted,
A current path is formed between one end of the first semiconductor element and the other end of the inductive element.
(2) A rectifier circuit according to claim 2 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A first resistance element and a second resistance element;
An external bias potential is applied to the second control end and the third control end by the second resistance element,
A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow,
A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element. Configured to
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted,
A current path is formed between one end of the first semiconductor element and the other end of the first semiconductor element.
(3) A rectifier circuit according to claim 3 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A first resistance element, a second resistance element, and an inductive element;
An external bias potential is applied to the second control end and the third control end by the second resistance element,
A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and
One end of the third semiconductor element is opened,
The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element. Configured to be transmitted to the other end of the third semiconductor element via the other end,
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted,
A current path is formed between one end of the first semiconductor element and the other end of the inductive element.
(4) A rectifier circuit according to claim 4 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A first resistance element and a second resistance element;
An external bias potential is applied to the second control end and the third control end by the second resistance element,
A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and
One end of the third semiconductor element is opened,
A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element. Configured to
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted,
A current path is formed between one end of the first semiconductor element and the other end of the first semiconductor element.
(5) A control circuit according to claim 5 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A first resistance element, a second resistance element, and an inductive element;
An external bias potential is applied to the second control end and the third control end by the second resistance element,
A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow,
The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element. Configured to be transmitted to the other end of the third semiconductor element via the other end,
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. Part of the rectifier circuit in which the potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and the current path is between one end of the first semiconductor element and the other end of the inductive element. A control circuit comprising:
The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and between the one end and the other end of the current path of the second semiconductor element. A current supplied by an external DC power source flows between the one end and the other end of the current path of the third semiconductor element via the first resistance element. 2 is configured to be transmitted to one end of the first semiconductor element, and is configured to be transmitted to the other end of the third semiconductor element.
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conducted, and the potential at one end of the second semiconductor element is output as a low potential,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is increased. It is output as a potential.
(6) A control circuit according to claim 6 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A first resistance element and a second resistance element;
An external bias potential is applied to the second control end and the third control end by the second resistance element,
A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow,
A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element. Configured to
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and one of the rectifier circuits having a current path between one end of the first semiconductor element and the other end of the first semiconductor element. A control circuit constituting a unit,
The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of the current path of the second semiconductor element. A current supplied by an external DC power source flows through one end of the current path of the third semiconductor element via the second resistance element via the element, and the potential at the other end of the second semiconductor element is The first semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is configured to be transmitted to the other end of the third semiconductor element.
(7) A control circuit according to claim 7 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A first resistance element, a second resistance element, and an inductive element;
An external bias potential is applied to the second control end and the third control end by the second resistance element,
A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and
One end of the third semiconductor element is opened,
The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element. Configured to be transmitted to the other end of the third semiconductor element via the other end,
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. Part of the rectifier circuit in which the potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and the current path is between one end of the first semiconductor element and the other end of the inductive element. A control circuit comprising:
The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of the current path of the second semiconductor element. A current supplied from an external DC power source is configured to flow through the element, one end of the third semiconductor element is opened, and the potential at the other end of the second semiconductor element is transmitted to one end of the first semiconductor element. And the potential at the other end of the first semiconductor element is transmitted from one end of the inductive element to the other end of the third semiconductor element through the other end of the inductive element. It is characterized by that.
(8) A control circuit according to claim 8 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A first resistance element and a second resistance element;
An external bias potential is applied to the second control end and the third control end by the second resistance element,
A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and
One end of the third semiconductor element is opened,
A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element. Configured to
The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and one of the rectifier circuits having a current path between one end of the first semiconductor element and the other end of the first semiconductor element. A control circuit constituting a unit,
The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of the current path of the second semiconductor element. A current supplied from an external DC power source is configured to flow through the element, one end of the third semiconductor element is opened, and the potential at the other end of the second semiconductor element is transmitted to one end of the first semiconductor element. The potential of the other end of the first semiconductor element is configured to be transmitted to the other end of the third semiconductor element.
(9) The rectifier circuit according to claim 9 is the rectifier circuit according to any one of claims 1 to 4, wherein one end of the second semiconductor element is a collector of a bipolar transistor, and the other end of the second semiconductor element. Is an emitter of a bipolar transistor, and one end of the third semiconductor element is an emitter of the bipolar transistor, and the other end of the third semiconductor element is a collector of the bipolar transistor.
(10) The rectifier circuit according to claim 10 is the rectifier circuit according to any one of claims 1 to 4, wherein one end of the second semiconductor element is an emitter of a bipolar transistor, and the other end of the second semiconductor element. Is a collector of the bipolar transistor, wherein one end of the third semiconductor element is an emitter of the bipolar transistor, and the other end of the third semiconductor element is a collector of the bipolar transistor.
(11) The control circuit according to claim 11 is the control circuit according to any one of claims 5 to 8, wherein one end of the second semiconductor element is a collector of a bipolar transistor, and the other end of the second semiconductor element Is an emitter of a bipolar transistor, and one end of the third semiconductor element is an emitter of the bipolar transistor, and the other end of the third semiconductor element is a collector of the bipolar transistor.
(12) A control circuit according to claim 12 is the control circuit according to any one of claims 5 to 8, wherein one end of the second semiconductor element is an emitter of a bipolar transistor, and the other end of the second semiconductor element. Is a collector of the bipolar transistor, wherein one end of the third semiconductor element is an emitter of the bipolar transistor, and the other end of the third semiconductor element is a collector of the bipolar transistor.
(13) An integrated circuit device according to a thirteenth aspect is characterized in that the rectifier circuit according to any one of the first to fourth aspects, the ninth aspect, and the tenth aspect is incorporated.
(14) An integrated circuit device according to a fourteenth aspect is characterized in that the control circuit according to any one of the fifth to eighth, eleventh and twelfth aspects is incorporated.
(A)本発明による整流回路は、FETを整流電流路に使用しているため、整流による順方向電圧降下が極めて小さく、極めて低電力損失である。
(B)本発明による整流回路は、FETを整流電流路に使用し、整流回路のアノードに相当する部分の電位と整流回路のカソードに相当する部分の電位を2つのバイポーラトランジスタが構成する制御回路が比較し、FETを導通/非導通の制御をするので、カソードからアノードに電流が逆流することがない。
(C)本発明による制御回路は、整流回路のアノードに相当する部分の電位と整流回路のカソードに相当する部分の電位を2つのバイポーラトランジスタが構成する制御回路が比較し、FETを導通/非導通の制御をするので、整流回路のカソードからアノードに電流が逆流することがない。
(D)本発明による整流回路は、インダクターがFETの他端と整流回路のカソードに相当する部分に挿入されているため、高い周波数の電流を整流する場合でも、整流回路のカソードからアノードに電流が逆流することがない。
(A) Since the rectifier circuit according to the present invention uses an FET for the rectification current path, the forward voltage drop due to rectification is extremely small, and the power loss is extremely low.
(B) A rectifier circuit according to the present invention uses an FET as a rectifier current path, and a control circuit in which two bipolar transistors constitute a potential of a portion corresponding to the anode of the rectifier circuit and a potential of a portion corresponding to the cathode of the rectifier circuit However, since the FET is controlled to be conductive / non-conductive, current does not flow backward from the cathode to the anode.
(C) In the control circuit according to the present invention, the potential of the portion corresponding to the anode of the rectifier circuit and the potential of the portion corresponding to the cathode of the rectifier circuit are compared by the control circuit formed by the two bipolar transistors, and the FET is turned on / off. Since conduction is controlled, current does not flow backward from the cathode to the anode of the rectifier circuit.
(D) In the rectifier circuit according to the present invention, since the inductor is inserted in the portion corresponding to the other end of the FET and the cathode of the rectifier circuit, the current from the cathode of the rectifier circuit to the anode is rectified even when rectifying a high-frequency current. Will not flow backwards.
は、本発明による整流回路、制御回路の第1の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 1st Embodiment of the rectifier circuit by this invention, and a control circuit. は、本発明による整流回路、制御回路の第2の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 2nd Embodiment of the rectifier circuit by this invention, and a control circuit. は、本発明による整流回路、制御回路の第3の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 3rd Embodiment of the rectifier circuit by this invention, and a control circuit. は、本発明による整流回路、制御回路の第4の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 4th Embodiment of the rectifier circuit by this invention, and a control circuit. は、本発明による整流回路、制御回路の第5の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 5th Embodiment of the rectifier circuit by this invention, and a control circuit. は、本発明による整流回路、制御回路の第6の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 6th Embodiment of the rectifier circuit by this invention, and a control circuit. は、本発明による整流回路、制御回路の第7の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 7th Embodiment of the rectifier circuit by this invention, and a control circuit. は、本発明による整流回路、制御回路の第8の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 8th Embodiment of the rectifier circuit by this invention, and a control circuit. は、本発明による整流回路、制御回路の第9の実施の形態を示す回路構成図である。These are the circuit block diagrams which show 9th Embodiment of the rectifier circuit by this invention, and a control circuit.
(1)第1の実施の形態
(1-1)回路構成
 図1は、本発明による第1の実施の形態である整流回路及び該整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。
図1において破線で囲まれた部分が該制御回路である。該制御回路は、第2半導体素子であるNPNバイポーラトランジスタQ2、第3半導体素子であるNPNバイポーラトランジスタQ3、第1抵抗素子である抵抗素子R1及び第2抵抗素子である抵抗素子R2で構成される。
(1) First Embodiment (1-1) Circuit Configuration FIG. 1 shows a rectifier circuit according to a first embodiment of the present invention and a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel FETQ1.
In FIG. 1, a portion surrounded by a broken line is the control circuit. The control circuit includes an NPN bipolar transistor Q2 that is a second semiconductor element, an NPN bipolar transistor Q3 that is a third semiconductor element, a resistance element R1 that is a first resistance element, and a resistance element R2 that is a second resistance element. .
以下、図1を参照して本発明の回路構成を説明する。
直流電源の正極電位を入力する端子T1(ダイオードでいうアノードに相当)、直流電源の正極電位を出力する端子T2(ダイオードでいうカソードに相当)が存在する。
端子T1にFETQ1のソースSが接続され、FETQ1のドレインDには誘導性素子であるインダクターLの一端が接続され、該インダクターLの他端は端子T2に接続されている。電流は端子T1から端子T2へ、すなわち、FETQ1のソースSからドレインDへ流れる。ドレインDからソースSに向かう電流は遮断されるように制御される。
The circuit configuration of the present invention will be described below with reference to FIG.
There is a terminal T1 (corresponding to an anode referred to as a diode) for inputting the positive potential of the DC power supply, and a terminal T2 (corresponding to a cathode referred to as a diode) for outputting the positive potential of the DC power supply.
The terminal S1 is connected to the source S of the FET Q1, the drain D of the FET Q1 is connected to one end of an inductor L, which is an inductive element, and the other end of the inductor L is connected to the terminal T2. The current flows from the terminal T1 to the terminal T2, that is, from the source S to the drain D of the FET Q1. The current from the drain D to the source S is controlled to be cut off.
さらに、端子T1には、第2半導体素子であるNPNバイポーラトランジスタQ2のコレクタCが接続され、端子T2には、第3半導体素子であるNPNバイポーラトランジスタQ3のコレクタCが接続される。 Further, a collector C of an NPN bipolar transistor Q2 which is a second semiconductor element is connected to the terminal T1, and a collector C of an NPN bipolar transistor Q3 which is a third semiconductor element is connected to the terminal T2.
バイポーラトランジスタQ2のベースBとバイポーラトランジスタQ3のベースBが接続され、この接続部に第2抵抗素子である抵抗素子R2の一端が接続され、抵抗素子R2の他端は、両バイポーラトランジスタQ2、Q3のベースBにバイアス電位を供給する直流電源が印加される端子T3に接続される。 The base B of the bipolar transistor Q2 and the base B of the bipolar transistor Q3 are connected, and one end of a resistance element R2 that is a second resistance element is connected to this connection portion, and the other end of the resistance element R2 is connected to both bipolar transistors Q2, Q3. Is connected to a terminal T3 to which a DC power supply for supplying a bias potential is applied to the base B.
バイポーラトランジスタQ3のエミッタEは、抵抗素子R2の一端に接続される。すなわち、バイポーラトランジスタQ3のベース、エミッタ間は短絡されている。
バイポーラトランジスタQ2のエミッタEは、第1抵抗素子である抵抗素子R1の一端に接続され、抵抗素子R1の他端は、バイポーラトランジスタQ2のエミッタE電位及びFETQ1のゲート電位を供給する直流電源が印加される端子T3に接続される。
なお、バイポーラトランジスタQ3はコレクタC接地として使用されるが、端子T2には外部の直流電源電位が印加されるため、耐圧がエミッタより高いコレクタを端子T2に接続している。また、バイポーラトランジスタQ2もコレクタC接地として使用され、両バイポーラトランジスタQ2、Q3の動作特性をそろえるようにしている。
The emitter E of the bipolar transistor Q3 is connected to one end of the resistance element R2. That is, the base and emitter of the bipolar transistor Q3 are short-circuited.
The emitter E of the bipolar transistor Q2 is connected to one end of a resistance element R1 which is a first resistance element, and the other end of the resistance element R1 is applied with a DC power supply for supplying the emitter E potential of the bipolar transistor Q2 and the gate potential of the FET Q1. Connected to terminal T3.
The bipolar transistor Q3 is used as a collector C ground, but since an external DC power supply potential is applied to the terminal T2, a collector whose breakdown voltage is higher than that of the emitter is connected to the terminal T2. The bipolar transistor Q2 is also used as the collector C ground so that the operating characteristics of both bipolar transistors Q2 and Q3 are made uniform.
バイポーラトランジスタQ2のエミッタEは、FETQ1のゲートGに接続され、バイポーラトランジスタQ2のコレクタCは、FETQ1のソースに接続される。 The emitter E of the bipolar transistor Q2 is connected to the gate G of the FET Q1, and the collector C of the bipolar transistor Q2 is connected to the source of the FET Q1.
バイポーラトランジスタQ2、バイポーラトランジスタQ3、抵抗素子R1及び抵抗素子R2で構成される破線で囲まれた回路は、本発明の整流回路の一部である本発明の制御回路である。 A circuit surrounded by a broken line composed of the bipolar transistor Q2, the bipolar transistor Q3, the resistor element R1, and the resistor element R2 is the control circuit of the present invention which is a part of the rectifier circuit of the present invention.
(1)第1の実施の形態
(1-2)回路動作
 図1を参照して本発明の第1の実施の形態である整流回路及び制御回路の回路動作を説明する。
(1) First Embodiment (1-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the first embodiment of the present invention will be described with reference to FIG.
 本発明の図1の回路における整流回路は、端子T1をアノードとし、端子T2をカソードとしたダイオードを構成し、端子T1、端子T2間に印加される電圧極性を制御回路が判別しFETQ1のゲートGに印加する電位を制御し、FETQ1の導通/非導通を制御する。 The rectifier circuit in the circuit of FIG. 1 of the present invention comprises a diode having the terminal T1 as an anode and the terminal T2 as a cathode, and the control circuit discriminates the voltage polarity applied between the terminals T1 and T2, and the gate of the FET Q1. The potential applied to G is controlled to control the conduction / non-conduction of the FET Q1.
 なお、本発明の回路動作説明において、各素子の電位はバイポーラトランジスタQ2のエミッタ電位を基準電位(=端子T1の電位、=FETQ1のソース電位)とし、各素子は端子T3に印加される直流正極性電位により動作する。
 端子T1に負荷動作用の直流電源の一端を接続し、端子T2には負荷の一端を接続する。図1の回路には示されていないが、別の電流路により、該直流電源の他端と負荷の他端を接続し直流電源と負荷の電流路を構成する。
 本発明の説明において、該直流電源の一端は正極性電位であり、該直流電源の他端は負極性電位とする。
In the description of the circuit operation of the present invention, the potential of each element is the direct current positive electrode applied to the terminal T3, with the emitter potential of the bipolar transistor Q2 being the reference potential (= the potential of the terminal T1, the source potential of the FET Q1). Operates with sex potential.
One end of a DC power source for load operation is connected to the terminal T1, and one end of the load is connected to the terminal T2. Although not shown in the circuit of FIG. 1, the other end of the DC power supply and the other end of the load are connected by another current path to form a current path of the DC power supply and the load.
In the description of the present invention, one end of the DC power source has a positive potential and the other end of the DC power source has a negative potential.
(1-2-1)FETQ1を非導通とする動作概要
端子T1の電位をV1、端子T2の電位をV2とすると、V1≦V2ではバイポーラトランジスタQ3は非導通又は少しだけ浅い導通状態にあり、バイポーラトランジスタQ2は確実に導通するため、抵抗素子R1による電圧降下によりバイポーラトランジスタQ2のエミッタEの電位は低下し略0Vである(制御回路の動作)。この電位が伝達されるFETQ1のゲート電位により、FETQ1は非導通である(制御回路の動作と併せて整流回路の動作となる。)。
すなわち、FETQ1のドレインDからソースSへ向かう電流は流れない。よって、端子T2は、ダイオードのカソード、端子T1は、ダイオードのアノードとして、図1の回路は動作する。
(1-2-1) Outline of operation for making FET Q1 non-conductive Assuming that the potential of the terminal T1 is V1 and the potential of the terminal T2 is V2, the bipolar transistor Q3 is nonconductive or slightly shallowly conductive when V1 ≦ V2, Since the bipolar transistor Q2 is surely turned on, the potential of the emitter E of the bipolar transistor Q2 is lowered by the voltage drop due to the resistance element R1, and is approximately 0V (operation of the control circuit). The FET Q1 is non-conductive due to the gate potential of the FET Q1 to which this potential is transmitted (the operation of the rectifier circuit is combined with the operation of the control circuit).
That is, no current flows from the drain D to the source S of the FET Q1. Accordingly, the circuit in FIG. 1 operates with the terminal T2 as the cathode of the diode and the terminal T1 as the anode of the diode.
 (1-2-2)FETQ1を導通とする動作概要
逆に、V1>V2ではバイポーラトランジスタQ3が導通し、バイポーラトランジスタQ2は非導通であるため、抵抗素子R1による電圧降下がなく、バイポーラトランジスタQ2のエミッタEの電位は端子T3に印加された直流電源電圧まで上昇し(制御回路の動作)、この電位が伝達されるFETQ1のゲート電位により、FETQ1を導通とする(制御回路の動作と併せて整流回路の動作となる。)。
すなわち、FETQ1のソースからドレインへ向かう電流は流れる。よって、端子T1は、ダイオードのアノード、端子T2は、ダイオードのカソードとして、図1の回路は動作する。
(1-2-2) Outline of operation for making FET Q1 conductive On the contrary, when V1> V2, the bipolar transistor Q3 is conductive and the bipolar transistor Q2 is nonconductive, so there is no voltage drop due to the resistance element R1, and the bipolar transistor Q2 The potential of the emitter E rises to the DC power supply voltage applied to the terminal T3 (operation of the control circuit), and the FET Q1 is turned on by the gate potential of the FET Q1 to which this potential is transmitted (in conjunction with the operation of the control circuit). The operation of the rectifier circuit.)
That is, a current flowing from the source to the drain of the FET Q1 flows. Therefore, the circuit of FIG. 1 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.
上記説明において補足すると、FETQ1が非導通のときは、FETQ1のドレインDからソースSに向かう電流は流れないことは勿論であるが、FETQ1のボディダイオードにより、ソースからドレイン方向へ向かう電流は流れることが可能である。ただし、V1≦V2においてFETQ1が非導通となる前提条件があるため、ソースからドレイン方向へ向かう電流は有り得ない。 As supplemented in the above description, when the FET Q1 is non-conductive, the current from the drain D to the source S of the FET Q1 does not flow, but the current from the source to the drain flows by the body diode of the FET Q1. Is possible. However, since there is a precondition that the FET Q1 is non-conductive when V1 ≦ V2, there is no current from the source toward the drain.
また、FETQ1が導通のときは、FETQ1のソースSからドレインDに向かう電流が流れることは勿論であるが、FETQ1のドレインDからソースS方向へ向かう電流も流れることが可能である。ただし、V1>V2のときにおいてFETQ1が導通となる前提条件があるため、FETQ1ドレインからソース方向へ向かう電流は有り得ない。
FETQ1の導通時は、FETQ1のボディダイオードによらずFETQ1の極めて低い導通抵抗によりソースからドレイン方向へ向かう電流を流すことができるので、PN接合ダイオードによる整流より遙かに有利である。
Further, when the FET Q1 is conductive, a current flowing from the source S to the drain D of the FET Q1 flows, but a current flowing from the drain D to the source S of the FET Q1 can also flow. However, since there is a precondition that the FET Q1 becomes conductive when V1> V2, there is no current from the drain of the FET Q1 toward the source.
When the FET Q1 is conductive, a current flowing from the source to the drain direction can be flowed by the extremely low conductive resistance of the FET Q1 regardless of the body diode of the FET Q1, which is far more advantageous than the rectification by the PN junction diode.
以下、図1を参照して本発明の第1の実施の形態について、詳細な説明をする。ただし、以下の式(1-1)、式(1-2)の前提条件が存在する。
EC3/hfe3>IEC2/hfe2・・・・式(1-1)
式(1-1)は、IBC3>IBC2を表している。
hfe2・r1>hfe3・r2・・・・・・式(1-2)
式(1-1)は式(1-2)と等価である。
式(1-2)に基づき、場合の条件式を展開すると、以下の式が考えられる。
hfe2=hfe3の場合、r1>r2・・・式(2)
hfe2>hfe3の場合、r1≧r2・・・式(3)
hfe2≫hfe3の場合、r1<r2・・・式(4)
hfe2<hfe3の場合は、ここでは考えない。
Hereinafter, the first embodiment of the present invention will be described in detail with reference to FIG. However, there are preconditions of the following equations (1-1) and (1-2).
I EC3 / hfe3> I EC2 / hfe2... Formula (1-1)
Formula (1-1) represents I BC3 > I BC2 .
hfe2 · r1> hfe3 · r2 ··· formula (1-2)
Expression (1-1) is equivalent to Expression (1-2).
When the conditional expression of the case is expanded based on the expression (1-2), the following expression can be considered.
When hfe2 = hfe3, r1> r2 (2)
When hfe2> hfe3, r1 ≧ r2 (3)
When hfe2 >> hfe3, r1 <r2 (4)
The case where hfe2 <hfe3 is not considered here.
ただし、hfe2はバイポーラトランジスタQ2のコレクタC接地時の電流増幅率、hfe3はバイポーラトランジスタQ3のコレクタC接地時の電流増幅率。
BC2は、バイポーラトランジスタQ2のベース電流、IBC3は、バイポーラトランジスタQ3のベース電流。
EC2は、バイポーラトランジスタQ2のエミッタ電流、IEC3はバイポーラトランジスタQ3のエミッタ電流。
r1は抵抗素子R1の抵抗値、r2は抵抗素子R2の抵抗値である。
バイポーラトランジスタQ2のコレクタ電位をVc2、バイポーラトランジスタQ3コレクタ電位をVc3とし、Vc2=V1、Vc3=V2とする。
However, hfe2 is a current amplification factor when the collector C of the bipolar transistor Q2 is grounded, and hfe3 is a current amplification factor when the collector C of the bipolar transistor Q3 is grounded.
I BC2 is the base current of the bipolar transistor Q2, and I BC3 is the base current of the bipolar transistor Q3.
IEC2 is the emitter current of the bipolar transistor Q2, and IEC3 is the emitter current of the bipolar transistor Q3.
r1 is the resistance value of the resistance element R1, and r2 is the resistance value of the resistance element R2.
The collector potential of the bipolar transistor Q2 is Vc2, the collector potential of the bipolar transistor Q3 is Vc3, and Vc2 = V1 and Vc3 = V2.
条件:A1
Vc2=Vc3(V1=V2の状態。バイポーラトランジスタQ2のコレクタ電位=バイポーラトランジスタQ3のコレクタ電位。)では、バイポーラトランジスタQ3が少しだけ浅く導通し、バイポーラトランジスタQ2が確実に導通する。
Condition: A1
In Vc2 = Vc3 (the state where V1 = V2, the collector potential of the bipolar transistor Q2 = the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 conducts slightly shallower and the bipolar transistor Q2 conducts reliably.
図1の回路では、hfe2>hfe3とするため、式(3)を適用する。
hfe2>hfe3である理由は、上記のように、IBC3>IBC2で表されるとおり、バイポーラトランジスタQ3のベース電流を多く流し、バイポーラトランジスタQ2のベース電流を少なく流すためである。
ただし、バイポーラトランジスタQ2、Q3は、同一の接地回路(両トランジスタをコレクタ接地又はエミッタ接地とした場合など)において略同一のhfeである場合の例である。また、温度特性なども略同一のものを使用することが好適である。
In the circuit of FIG. 1, since hfe2> hfe3, Expression (3) is applied.
The reason why hfe2> hfe3 is that, as described above, as shown by I BC3 > I BC2 , a large base current of the bipolar transistor Q3 is supplied and a low base current of the bipolar transistor Q2 is supplied.
However, the bipolar transistors Q2 and Q3 are examples in which they are substantially the same hfe in the same ground circuit (when both transistors are connected to the collector ground or the emitter ground). Further, it is preferable to use substantially the same temperature characteristics.
図1において、上記、「hfe2>hfe3の場合、r1≧r2・・・式(3)」が成立し、バイポーラトランジスタQ2のコレクタ、バイポーラトランジスタQ3のコレクタ間の電位が略同一であるとき、結果的に、IBC3>IBC2となる。したがって、バイポーラトランジスタQ3を導通させるためのベース順方向電圧VBC3が、VBC3>VBC2となる。 In FIG. 1, when “hfe2> hfe3, r1 ≧ r2 (formula (3)” is satisfied, and the potential between the collector of the bipolar transistor Q2 and the collector of the bipolar transistor Q3 is substantially the same. Thus, I BC3 > I BC2 . Therefore, the base forward voltage V BC3 for conducting the bipolar transistor Q3 is V BC3 > V BC2 .
上記の状態において、バイポーラトランジスタQ2とバイポーラトランジスタQ3のベースは接続されているため、両ベース電位はV’BC3=V’BC2となるように均衡し、
BC3>V’BC3=V’BC2>VBC2の状態で、VBC3とVBC2との中間的電位に落ち着く。
したがって、バイポーラトランジスタQ3を導通させるためのベース順方向電圧VBC3が、バイポーラトランジスタQ3の導通に必要な電位VBC3を下回り、このため、IBC3及びIEC3は、バイポーラトランジスタQ3のベースBに通常のベース順方向電圧VBC3が印加されたときより少なくなる。
In the above state, since the bases of the bipolar transistor Q2 and the bipolar transistor Q3 are connected, both base potentials are balanced so that V ′ BC3 = V ′ BC2 ,
In the state of V BC3 > V ′ BC3 = V ′ BC2 > V BC2 , the potential settles to an intermediate potential between V BC3 and V BC2 .
Therefore, the base forward voltage V BC3 for conducting the bipolar transistor Q3 is lower than the potential V BC3 required for conducting the bipolar transistor Q3, and therefore I BC3 and I EC3 are normally applied to the base B of the bipolar transistor Q3. Less than when the base forward voltage VBC3 is applied.
両バイポーラトランジスタのベース電位、V’BC3=V’BC2の均衡によってIBC3及びIEC3が減少するが、抵抗素子R2を流れる電流は、Ir2=V3/r2であり、r2により制限されて変わらないので、
BC3及びIEC3が減少した分だけIBC2が多く流れ、バイポーラトランジスタQ2は、確実な導通状態を維持できる。
Although I BC3 and I EC3 decrease due to the balance of the base potentials of both bipolar transistors, V ′ BC3 = V ′ BC2 , the current flowing through the resistance element R2 is Ir2 = V3 / r2, which is limited by r2 and does not change. So
As much I BC2 flows as I BC3 and I EC3 decrease, and the bipolar transistor Q2 can maintain a reliable conduction state.
ただし、VBC2は、バイポーラトランジスタQ2のコレクタ電位に対するベース電位、
BC3は、バイポーラトランジスタQ3のコレクタ電位に対するベース電位。
ベース順方向電圧VBC2は、バイポーラトランジスタQ2のエミッタE、コレクタC間が導通する電圧。
ベース順方向電圧VBC3は、バイポーラトランジスタQ3のエミッタE、コレクタC間が導通する電圧である。
However, V BC2 is the base potential with respect to the collector potential of the bipolar transistor Q2,
V BC3 is a base potential with respect to the collector potential of the bipolar transistor Q3.
The base forward voltage VBC2 is a voltage at which the emitter E and the collector C of the bipolar transistor Q2 are conducted.
The base forward voltage VBC3 is a voltage that conducts between the emitter E and the collector C of the bipolar transistor Q3.
BC3>IBC2についてさらに説明を加えると、
hfe2は、hfe2=IEC2/IBC2で表され、
hfe3は、hfe3=IEC3/IBC3で表される。
EC2はr1の逆数の関数、IEC3はr2の逆数の関数で表わされ、
EC3/hfe3>IEC2/hfe2・・・・式(1-1)と、
hfe2>hfe3の場合、r1≧r2・・・式(3)のr1≧r2の関係により、
EC3≧IEC2の傾向にあり、さらに式(3)のhfe2>hfe3の関係により、
結果としてIBC3>IBC2となる。
BC3>IBC2であるため、電流量の少ないIBC2が流れるバイポーラトランジスタQ2のベース順方向電圧VBE2は、電流量の多いIBC3が流れるバイポーラトランジスタQ3のベース順方向電圧VBC3よりも小さい。
 したがって、上記のとおり、VBC3>VBC2となる。
When I BC3 > I BC2 is further explained,
hfe2 is represented by hfe2 = I EC2 / I BC2 ,
hfe3 is represented by hfe3 = I EC3 / I BC3 .
I EC2 is represented by a reciprocal function of r1, I EC3 is represented by a reciprocal function of r2,
I EC3 / hfe3> I EC2 / hfe2... Formula (1-1),
In the case of hfe2> hfe3, r1 ≧ r2...
There is a tendency of I EC3 ≧ I EC2 , and further, due to the relationship of hfe2> hfe3 in formula (3),
As a result, I BC3 > I BC2 .
Since I BC3 > I BC2 , the base forward voltage V BE2 of the bipolar transistor Q2 through which I BC2 with a small amount of current flows is smaller than the base forward voltage V BC3 of the bipolar transistor Q3 through which I BC3 with a large amount of current flows. .
Therefore, as described above, V BC3 > V BC2 is satisfied .
 IEC3≒V3/r2、IEC2=V3/r1である。ただし、V3は端子T3に印加される直流電源電位である。
 ここで、IEC3≒V3/r2であり、IEC3=V3/r2ではないのは、抵抗素子R2には、バイポーラトランジスタQ2、Q3にベース電流を流すためである。
I EC3 ≈V3 / r2 and I EC2 = V3 / r1. However, V3 is a DC power supply potential applied to the terminal T3.
Here, I EC3 ≈V3 / r2, and I EC3 = V3 / r2 is not caused, because the base current is caused to flow through the bipolar transistors Q2 and Q3 through the resistance element R2.
バイポーラトランジスタQ2は確実に導通するため、バイポーラトランジスタQ2のコレクタC電位は低下し略0Vであり、この電位が印加されるFETQ1のゲートGにおいて、FETQ1は非導通である。このため、FETQ1のドレインDから、ソースSに電流は流れず、ダイオードの逆方向電流阻止の機能を有する。 Since the bipolar transistor Q2 is reliably turned on, the collector C potential of the bipolar transistor Q2 is reduced to about 0 V, and the FET Q1 is non-conductive at the gate G of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
条件:B1
Vc2<Vc3’(V1<V2の状態。バイポーラトランジスタQ2のコレクタ電位<バイポーラトランジスタQ3のコレクタ電位。)では、バイポーラトランジスタQ3が非導通であり、バイポーラトランジスタQ2が確実に導通する。
Vc2<Vc3’を別の表現をすると、Vc2<Vc3’は、Vc2<Vc3+Vαと表現できる。
上記条件:A1の説明に加え、バイポーラトランジスタQ3のコレクタCの電位がVc3からVα上昇すると、バイポーラトランジスタQ3は、定められた自己のコレクタC、ベースB間電位を維持するため、ベース電位がVα上昇することになる。このため、バイポーラトランジスタQ3のベースBと同電位であるバイポーラトランジスタQ2のベースB電位は、さらに上昇し、バイポーラトランジスタQ2は確実に導通する。
Condition: B1
In Vc2 <Vc3 ′ (the state where V1 <V2; the collector potential of the bipolar transistor Q2 <the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 is non-conductive and the bipolar transistor Q2 is reliably conductive.
If Vc2 <Vc3 ′ is expressed in another way, Vc2 <Vc3 ′ can be expressed as Vc2 <Vc3 + Vα.
The above condition: In addition to the description of A1, when the potential of the collector C of the bipolar transistor Q3 rises from Vc3 to Vα, the bipolar transistor Q3 maintains the predetermined potential between its collector C and base B, so that the base potential is Vα Will rise. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 further increases, and the bipolar transistor Q2 is surely turned on.
したがって、バイポーラトランジスタQ2のコレクタCの電位は低下し略0Vであり、この電位が印加されるFETQ1のゲートGにおいて、FETQ1は非導通である。このため、FETQ1のドレインDから、ソースSに電流は流れず、ダイオードの逆方向電流阻止の機能を有する。 Therefore, the potential of the collector C of the bipolar transistor Q2 decreases to approximately 0 V, and the FET Q1 is non-conductive at the gate G of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
なお、バイポーラトランジスタQ3が非導通となる理由は、バイポーラトランジスタQ3のベースBにとっては、コレクタ側から逆バイアス電圧が印加されたこととなり、ベース電流が流れなくなるためである。 The reason why the bipolar transistor Q3 becomes non-conductive is that, for the base B of the bipolar transistor Q3, the reverse bias voltage is applied from the collector side, and the base current does not flow.
条件:C1
Vc2>Vc3”(V1>V2の状態。バイポーラトランジスタQ2のコレクタ電位>バイポーラトランジスタQ3のコレクタ電位。)では、バイポーラトランジスタQ3が導通し、バイポーラトランジスタQ2が非導通となる。
Vc2>Vc3”を別の表現をすると、Vc2>Vc3”は、Vc2>Vc3-Vβと表現できる。
Condition: C1
In Vc2> Vc3 ″ (the state of V1> V2, the collector potential of the bipolar transistor Q2> the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 is turned on and the bipolar transistor Q2 is turned off.
In other words, Vc2> Vc3 ″ can be expressed as Vc2> Vc3-Vβ.
上記条件A1の説明に加え、バイポーラトランジスタQ3のコレクタCの電位がVc3からVβ低下すると、定められた自己のコレクタC、ベースB間電位を維持するため、ベース電位がVβ低下することになる。このため、バイポーラトランジスタQ3のベースBと同電位であるバイポーラトランジスタQ2のベースB電位は低下し、バイポーラトランジスタQ2は非導通となる。 In addition to the description of the condition A1, when the potential of the collector C of the bipolar transistor Q3 is lowered by Vβ from Vc3, the base potential is lowered by Vβ in order to maintain the predetermined self-collector C and base B potential. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 decreases, and the bipolar transistor Q2 becomes non-conductive.
したがって、バイポーラトランジスタQ2のエミッタE電位は上昇し、端子T3に印加される直流電源電位となり、この電位が印加されるFETQ1のゲート電位において、FETQ1は導通となる。このため、FETQ1のソースSから、ドレインDに電流が流れ、FETQ1のソースSは、ダイオードのアノード、FETQ1のドレインDは、ダイオードのカソードの機能を有する。 Therefore, the emitter E potential of the bipolar transistor Q2 rises and becomes the DC power supply potential applied to the terminal T3, and the FET Q1 becomes conductive at the gate potential of the FET Q1 to which this potential is applied. Therefore, a current flows from the source S of the FET Q1 to the drain D, the source S of the FET Q1 has a function of an anode of the diode, and the drain D of the FET Q1 has a function of a cathode of the diode.
なお、バイポーラトランジスタQ3が導通となる理由は、バイポーラトランジスタQ3のベースBにとっては、コレクタC側から順バイアス電圧が印加されたこととなり、ベース電流が充分流れるためである。 The reason why the bipolar transistor Q3 becomes conductive is that the forward bias voltage is applied from the collector C side to the base B of the bipolar transistor Q3, and the base current flows sufficiently.
図1の回路において、FETQ1のドレインDと端子T2間に誘導性素子であるインダクターLを挿入する理由は、当該回路のFETQ1を非導通とする電流路遮断に係る周波数特性を良くするためである。すなわち、高い周波数の電流の整流において逆流させることなく整流できる。つまり、高周波数対応となる。 In the circuit of FIG. 1, the reason why the inductor L, which is an inductive element, is inserted between the drain D of the FET Q1 and the terminal T2 is to improve the frequency characteristics related to current path interruption that makes the FET Q1 of the circuit non-conductive. . That is, rectification can be performed without backflow in rectification of high-frequency current. That is, it corresponds to a high frequency.
この動作原理は、V1>V2からV1≦V2に端子T1、端子T2間に印加される電位が遷移したとき、バイポーラトランジスタQ3のコレクタ電位は直ちにV2となるが、インダクターLにより、FETQ1のドレインに印加される電位V2に遅れが発生するため、FETQ1が非導通となるまでに時間を稼ぐためである。 This operating principle is that when the potential applied between the terminals T1 and T2 transitions from V1> V2 to V1 ≦ V2, the collector potential of the bipolar transistor Q3 immediately becomes V2, but the inductor L causes the drain of the FET Q1 to This is because a delay occurs in the applied potential V2, and time is taken until the FET Q1 becomes non-conductive.
仮に、インダクターLが、FETQ1が配設されている電流路のFETQ1のドレインD側電流路に挿入されていない場合、各素子、特にバイポーラトランジスタQ2、Q3及びFETQ1のゲートの電荷放電時間による電位伝達の遅れにより、FETQ1が導通から非導通に遷移するための時間的遅れが発生する。
したがって、FETQ1が導通状態のまま、電流がFETQ1のドレインDからソースSに逆流してしまう。
If the inductor L is not inserted in the drain D-side current path of the FET Q1 in the current path in which the FET Q1 is disposed, the potential transfer due to the charge discharge time of each element, particularly the bipolar transistors Q2 and Q3 and the gate of the FET Q1. This causes a time delay for the FET Q1 to transition from conduction to non-conduction.
Therefore, the current flows backward from the drain D to the source S of the FET Q1 while the FET Q1 is in the conductive state.
端子T2に別の電源による電位V2が印加されている状態において、上記のように、FETQ1の導通から非導通への遅れの発生と、端子T1の電位V1が、V1<V2なる条件が重なると端子T2に印加された電位V2により、端子T1に接続されている電源側へ電流が流れる。 When the potential V2 from another power source is applied to the terminal T2, as described above, when the delay from the conduction to the non-conduction of the FET Q1 and the condition that the potential V1 of the terminal T1 is V1 <V2 overlap. A current flows to the power supply side connected to the terminal T1 by the potential V2 applied to the terminal T2.
このような、事態が発生すると整流回路としての機能が失われる。インダクターLは、端子T2に印加される電位V2のFETQ1のドレインDへの伝達を遅らせる機能を有する。このインダクターLにより、高調波パルス電位が印加されるスイッチング電源等の整流回路に適合可能となる。 When such a situation occurs, the function as a rectifier circuit is lost. The inductor L has a function of delaying transmission of the potential V2 applied to the terminal T2 to the drain D of the FET Q1. This inductor L can be adapted to a rectifier circuit such as a switching power supply to which a harmonic pulse potential is applied.
(2)第2の実施の形態
(2-1)回路構成
 図2は、本発明による第2の実施の形態である整流回路及び該整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。
(2) Second Embodiment (2-1) Circuit Configuration FIG. 2 shows a rectifier circuit according to a second embodiment of the present invention and a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel FETQ1.
図2において破線で囲まれた部分が該制御回路である。該制御回路は、第2半導体素子であるNPNバイポーラトランジスタQ2、第3半導体素子であるNPNバイポーラトランジスタQ3、第1抵抗素子である抵抗素子R1及び第2抵抗素子である抵抗素子R2で構成される。 In FIG. 2, a portion surrounded by a broken line is the control circuit. The control circuit includes an NPN bipolar transistor Q2 as a second semiconductor element, an NPN bipolar transistor Q3 as a third semiconductor element, a resistance element R1 as a first resistance element, and a resistance element R2 as a second resistance element. .
以下、図2を参照して本発明の第2の実施の形態の回路構成と本発明の第1の実施の形態である図1との相違点を説明する。 Hereinafter, the difference between the circuit configuration of the second embodiment of the present invention and FIG. 1 which is the first embodiment of the present invention will be described with reference to FIG.
直流電源の正極電位を入力する端子T1(ダイオードでいうアノードに相当)、直流電源の正極電位を出力する端子T2(ダイオードでいうカソードに相当)が存在する。
直流電源の負極電位を入力する端子T1’、直流電源の負極電位を出力する端子T2’が存在する。
There is a terminal T1 (corresponding to an anode referred to as a diode) for inputting the positive potential of the DC power supply, and a terminal T2 (corresponding to a cathode referred to as a diode) for outputting the positive potential of the DC power supply.
There is a terminal T1 ′ for inputting the negative potential of the DC power supply and a terminal T2 ′ for outputting the negative potential of the DC power supply.
ただし、本発明において、端子T1、端子T2間でダイオードを構成するので、
端子T2’は必須ではなく存在しなくてもよい。
端子T1、端子T1’間に負荷に供給する直流電源を入力し、この電源を制御回路動作用電源に流用するが、図2において、本発明の第1の実施の形態の図1のように制御回路動作用電源を別に用意すれば、本発明において端子T1’も無くてもよい。
However, in the present invention, since a diode is formed between the terminal T1 and the terminal T2,
The terminal T2 ′ is not essential and may not be present.
A DC power supply to be supplied to the load is input between the terminals T1 and T1 ′, and this power supply is diverted to the power supply for operating the control circuit. In FIG. 2, as shown in FIG. If a separate power supply for operating the control circuit is prepared, the terminal T1 ′ may be omitted in the present invention.
端子T1には、第2半導体素子であるNPNバイポーラトランジスタQ2のコレクタ、容量素子であるコンデンサCの一端、制御回路用直流電源を構成する受光素子であるフォトダイオードPD1~PDnの直列回路のPDnカソード及びフォトダイオードを励起する発光素子である発光ダイオードLEDのアノードが接続される。
端子T1’と端子T2’は接続され、この接続部に定電流素子である定電流ダイオードRDのカソードが接続され、定電流ダイオードRDのアノードは、発光素子LEDのカソードに接続される。
The terminal T1 includes a collector of an NPN bipolar transistor Q2 as a second semiconductor element, one end of a capacitor C as a capacitive element, and a PDn cathode of a series circuit of photodiodes PD1 to PDn as light receiving elements constituting a DC power supply for a control circuit. And an anode of a light emitting diode LED which is a light emitting element for exciting the photodiode.
The terminal T1 ′ and the terminal T2 ′ are connected, and a cathode of a constant current diode RD that is a constant current element is connected to the connection portion, and an anode of the constant current diode RD is connected to a cathode of the light emitting element LED.
フォトダイオードPD1のアノード、コンデンサCの他端、抵抗素子である抵抗素子R1の他端及び抵抗素子である抵抗素子R2の他端は接続されている。
本発明の第2の実施の形態の図2においては、第1の実施の形態の図1に示される誘導性素子であるインダクターLが存在しないで、第1半導体素子であるFETQ1のドレインDと端子T2が直接接続されている。
The anode of the photodiode PD1, the other end of the capacitor C, the other end of the resistance element R1 that is a resistance element, and the other end of the resistance element R2 that is a resistance element are connected.
In FIG. 2 of the second embodiment of the present invention, the inductor L which is the inductive element shown in FIG. 1 of the first embodiment does not exist, and the drain D of the FET Q1 which is the first semiconductor element Terminal T2 is directly connected.
以上が、図2と図1の相違点である。 The above is the difference between FIG. 2 and FIG.
図2のその他の回路構成については、図1と同様に、破線で囲まれた第2半導体素子であるNPNバイポーラトランジスタQ2、第3半導体素子であるNPNバイポーラトランジスタQ3、抵抗素子である抵抗素子R1及び抵抗素子である抵抗素子R2で構成される制御回路並びに第1半導体素子であるNチャネルFETQ1が整流電流路を構成し、全体として整流回路を構成するという点について同様である。 2, similarly to FIG. 1, an NPN bipolar transistor Q2 that is a second semiconductor element surrounded by a broken line, an NPN bipolar transistor Q3 that is a third semiconductor element, and a resistance element R1 that is a resistance element The same is true in that the control circuit configured by the resistance element R2 that is a resistance element and the N-channel FET Q1 that is the first semiconductor element constitute a rectification current path and the rectification circuit as a whole.
したがって、第2の実施の形態である図2の回路に使用される符号は、第1の実施の形態である図1の符号と同様とし、回路構成の説明は、図1における説明を援用し、重複する説明を割愛する。 Therefore, the reference numerals used in the circuit of FIG. 2 which is the second embodiment are the same as the reference numerals of FIG. 1 of the first embodiment, and the description of the circuit configuration uses the description in FIG. , Omit duplicate explanations.
(2)第2の実施の形態
(2-2)回路動作
 図2を参照して本発明の第2の実施の形態である整流回路及び制御回路の回路動作を説明する。
(2) Second Embodiment (2-2) Circuit Operation The circuit operation of the rectifier circuit and control circuit according to the second embodiment of the present invention will be described with reference to FIG.
 図2において、図1と相違する点は、端子T1、端子T1’間に印加される直流電源を流用して、発光素子である発光ダイオードLEDを発光させ、この発光を受光する受光素子であるフォトダイオードPD1~PDnにより、制御回路動作用電源電圧を発生させている点である。 In FIG. 2, the difference from FIG. 1 is a light receiving element that emits light from a light emitting diode LED that is a light emitting element by using a DC power source applied between the terminal T1 and the terminal T1 ′, and receives this light emission. The control circuit operation power supply voltage is generated by the photodiodes PD1 to PDn.
 以上の点においては、図1の制御回路及び整流回路の動作に相違点はない。 In the above points, there is no difference in the operation of the control circuit and the rectifier circuit in FIG.
 さらに別の相違点は、図2にはインダクターLが存在しない。したがって、図1においては、端子T2の電位V2がバイポーラトランジスタQ3のコレクタCに直接印加されるのに対し、FETQ1のドレインDには、インダクターLを介して印加されるが、図2においては、端子T2の電位V2がバイポーラトランジスタQ3のコレクタCに対しても、FETQ1のドレインDに対しても直接印加される。 Another difference is that the inductor L does not exist in FIG. Therefore, in FIG. 1, the potential V2 of the terminal T2 is directly applied to the collector C of the bipolar transistor Q3, whereas it is applied to the drain D of the FET Q1 through the inductor L. In FIG. The potential V2 of the terminal T2 is applied directly to the collector C of the bipolar transistor Q3 and to the drain D of the FET Q1.
 したがって、インダクターLが存在しないことは、図1において、バイポーラトランジスタQ3のコレクタ電位Vc3、FETQ1のドレイン電位Vdとすると、Vc3≠Vd
であり、図2においては、Vc3=Vdとなる。この相違点においても、制御回路と整流電流路であるFETQ1との回路動作原理は同一である。
Therefore, the absence of the inductor L means that if the collector potential Vc3 of the bipolar transistor Q3 and the drain potential Vd of the FET Q1 in FIG. 1 are Vc3 ≠ Vd
In FIG. 2, Vc3 = Vd. Even in this difference, the circuit operation principle of the control circuit and the FET Q1, which is the rectification current path, is the same.
 ただし、第1の実施の形態で説明した特徴であるインダクターLを挿入した効果は発生しない。しかしながら、第1の実施の形態で説明した高い周波数での整流動作が要求されない用途であれば問題はない。 However, the effect of inserting the inductor L, which is the feature described in the first embodiment, does not occur. However, there is no problem if the application does not require a rectifying operation at a high frequency as described in the first embodiment.
 上記で説明したように、図1において、Vc3≠Vdであり、図2においては、Vc3=Vdとなる。このような相違点があっても、制御回路と整流電流路であるFETQ1との回路動作原理は同一であるため、図2における制御回路は、図1における制御回路と同様にFETQ1を導通/非導通とする制御が可能である。 As described above, Vc3 ≠ Vd in FIG. 1, and Vc3 = Vd in FIG. Even if there is such a difference, the circuit operation principle of the control circuit and the FET Q1 that is the rectification current path is the same. Therefore, the control circuit in FIG. 2 makes the FET Q1 conductive / non-conductive like the control circuit in FIG. Control to turn on is possible.
 したがって、第2の実施の形態である図2の回路動作の説明は、第1の実施の形態である図1の回路動作の説明をそのまま適用できる。よって、図1における回路動作の説明を図2の回路動作の説明に援用し、重複する説明を割愛する。 Therefore, the description of the circuit operation of FIG. 2 according to the second embodiment can be applied to the description of the circuit operation of FIG. 1 according to the first embodiment. Therefore, the description of the circuit operation in FIG. 1 is used for the description of the circuit operation in FIG. 2, and the overlapping description is omitted.
(3)第3の実施の形態
(3-1)回路構成
図3は、本発明による第3の実施の形態である整流回路及び整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。
(3) Third Embodiment (3-1) Circuit Configuration FIG. 3 shows a rectifier circuit according to a third embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
第3の実施の形態における図3の回路は、第1の実施の形態における図1の回路から誘導性素子であるインダクターLを取り除き、端子T2とFETQ1のドレインDを直接接続し、さらに、バイポーラトランジスタQ3のベースBとエミッタE間の接続を開放した回路である。すなわち、バイポーラトランジスタQ3のエミッタが開放されている。
したがって、図3の回路の各素子の符号は、図1の回路の各素子の符号と同一の符号を付し、図1の回路構成の説明を援用し、重複する説明を割愛する。
In the circuit of FIG. 3 in the third embodiment, the inductor L, which is an inductive element, is removed from the circuit of FIG. 1 in the first embodiment, and the terminal T2 and the drain D of the FET Q1 are directly connected. In this circuit, the connection between the base B and the emitter E of the transistor Q3 is opened. That is, the emitter of the bipolar transistor Q3 is open.
Therefore, the reference numerals of the elements in the circuit of FIG. 3 are the same as the reference numerals of the elements of the circuit in FIG. 1, and the description of the circuit configuration in FIG.
(3)第3の実施の形態
(3-2)回路動作
図3を参照して本発明の第3の実施の形態である整流回路及び制御回路の回路動作を説明する。
(3) Third Embodiment (3-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the third embodiment of the present invention will be described with reference to FIG.
第3の実施の形態における図3の回路は、第1の実施の形態における図1の回路から誘導性素子であるインダクターLを取り除き、端子T2とFETQ1のドレインDを直接接続し、さらに、バイポーラトランジスタQ3のベースBとエミッタE間の接続を開放した回路である。 In the circuit of FIG. 3 in the third embodiment, the inductor L, which is an inductive element, is removed from the circuit of FIG. 1 in the first embodiment, and the terminal T2 and the drain D of the FET Q1 are directly connected. In this circuit, the connection between the base B and the emitter E of the transistor Q3 is opened.
本発明の第3の実施の形態である図3の回路は、バイポーラトランジスタQ3のベースBとエミッタEが接続されていない回路であり、すなわち、本発明の第3の実施の形態における図3の破線で囲まれた制御回路が、本発明の第1の実施の形態である図1の破線で囲まれた制御回路の回路動作と相違するところは、この点に起因する。
本発明の第3の実施の形態の説明においても、第1の実施の形態の説明で使用した電位値、電流値、電流増幅率、抵抗値等の記号も同一の記号を使用し該記号の意義も同一とする。
The circuit of FIG. 3 which is the third embodiment of the present invention is a circuit in which the base B and the emitter E of the bipolar transistor Q3 are not connected, that is, the circuit of FIG. 3 in the third embodiment of the present invention. This is the reason why the control circuit surrounded by the broken line is different from the circuit operation of the control circuit surrounded by the broken line in FIG. 1 according to the first embodiment of the present invention.
Also in the description of the third embodiment of the present invention, the same symbols are used for symbols such as potential value, current value, current amplification factor, and resistance value used in the description of the first embodiment. The significance is the same.
したがって、図3の回路動作の説明は、図1の回路動作の説明から、誘導性素子であるインダクターLの動作説明を削除し、バイポーラトランジスタQ3のベースBとエミッタE間の接続を開放した回路動作について中心に説明し、図1と動作が共通する部分は図1の説明を援用し、重複する説明は割愛する。 Therefore, in the description of the circuit operation of FIG. 3, the description of the operation of the inductor L, which is an inductive element, is deleted from the description of the circuit operation of FIG. 1, and the connection between the base B and the emitter E of the bipolar transistor Q3 is opened. The operation will be mainly described, and the description of FIG. 1 will be used for the parts that are the same as those in FIG. 1, and the overlapping description will be omitted.
図3には、インダクターLが存在しないため、図1における動作説明の電流路遮断(FETQ1を非導通とする)に係る周波数特性を良くする必要のない、高周波数における遮断特性が要求されない整流回路、直流電源を並列接続するためのORingFETダイオード回路等に好適である。 In FIG. 3, since there is no inductor L, there is no need to improve the frequency characteristics related to the current path interruption (the FET Q1 is made non-conductive) in the operation description in FIG. It is suitable for an ORingFET diode circuit for connecting DC power supplies in parallel.
図3の回路において、バイポーラトランジスタQ3のベースBとエミッタE間は解放されているため、バイポーラトランジスタQ3は、ベースBがP型、コレクタCがN型のPN接合のダイオードとして機能する。 In the circuit of FIG. 3, since the base B and the emitter E of the bipolar transistor Q3 are open, the bipolar transistor Q3 functions as a PN junction diode with the base B being P-type and the collector C being N-type.
(3-2-1)FETQ1を非導通とする動作概要
端子T1の電位をV1、端子T2の電位をV2とすると、V1≦V2では、バイポーラトランジスタQ3のベースB、コレクタC間に、コレクタ電位を基準として、ベース順方向電圧V”BC3=約0.6Vの標準的PN接合電位差が発生し、バイポーラトランジスタQ3と共通ベース電位を有するバイポーラトランジスタQ2のベース電位によりバイポーラトランジスタQ2は確実に導通する。
(3-2-1) Outline of operation for making FETQ1 non-conducting When the potential of the terminal T1 is V1 and the potential of the terminal T2 is V2, when V1 ≦ V2, the collector potential is between the base B and the collector C of the bipolar transistor Q3. A standard PN junction potential difference of base forward voltage V ″ BC3 = about 0.6 V is generated with reference to the base potential of bipolar transistor Q2 and bipolar transistor Q2 having a common base potential and bipolar transistor Q2 is surely turned on. .
図3の回路では、バイポーラトランジスタQ3のエミッタ電流が流れないため、
BC3+IBC2=V3/r2であり、V3/r2が一定であれば、バイポーラトランジスタQ3のエミッタ電流が流れるときよりも、バイポーラトランジスタQ3のエミッタ電流が流れないときの方が、IBC3は大きい。
In the circuit of FIG. 3, since the emitter current of the bipolar transistor Q3 does not flow,
If I BC3 + I BC2 = V3 / r2 and V3 / r2 is constant, I BC3 is larger when the emitter current of bipolar transistor Q3 does not flow than when the emitter current of bipolar transistor Q3 flows. .
したがって、バイポーラトランジスタQ2の電流路に電流が流れるため、抵抗素子R1による電圧降下によりバイポーラトランジスタQ2のエミッタEの電位は低下し略0Vである(制御回路の動作)。
この電位が伝達されるFETQ1のゲート電位により、FETQ1は非導通である(制御回路の動作と併せて整流回路の動作)。
すなわち、FETQ1のドレインDからソースSへ向かう電流は流れない。よって、端子T1は、ダイオードのアノード、端子T2は、ダイオードのカソードとして、図3の回路は動作する。
Accordingly, since a current flows through the current path of the bipolar transistor Q2, the potential of the emitter E of the bipolar transistor Q2 is reduced to approximately 0 V due to a voltage drop caused by the resistance element R1 (operation of the control circuit).
The FET Q1 is non-conductive due to the gate potential of the FET Q1 to which this potential is transmitted (operation of the rectifier circuit in addition to the operation of the control circuit).
That is, no current flows from the drain D to the source S of the FET Q1. Therefore, the circuit of FIG. 3 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.
 (3-2-2)FETQ1を導通とする動作概要
逆に、V1>V2では、第1の実施の形態と同様にバイポーラトランジスタQ3のベースBの電位が低下し、バイポーラトランジスタQ2は非導通となるため、抵抗素子R1による電圧降下がなく、バイポーラトランジスタQ2のエミッタEの電位は端子T3に印加された直流電源電圧V3まで上昇し(制御回路の動作)、この電位が伝達されるFETQ1のゲート電位により、FETQ1を導通とする(制御回路の動作と併せて整流回路の動作)。
すなわち、FETQ1のソースからドレインへ向かう電流は流れる。よって、端子T1は、ダイオードのアノード、端子T2は、ダイオードのカソードとして、図3の回路は動作する。
(3-2-2) Outline of Operation for Making FET Q1 Conductive Conversely, when V1> V2, the potential at the base B of the bipolar transistor Q3 is lowered as in the first embodiment, and the bipolar transistor Q2 is turned off. Therefore, there is no voltage drop due to the resistance element R1, the potential of the emitter E of the bipolar transistor Q2 rises to the DC power supply voltage V3 applied to the terminal T3 (operation of the control circuit), and the gate of the FET Q1 to which this potential is transmitted The FET Q1 is turned on by the potential (operation of the rectifier circuit together with the operation of the control circuit).
That is, a current flowing from the source to the drain of the FET Q1 flows. Therefore, the circuit of FIG. 3 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.
以下、図3を参照して本発明の第3の実施の形態について、詳細な説明をする。ただし、以下の式(5)の前提条件が存在する。
I’BC3>IEC2/hfe2・・・式(5)
I’BC3>IBC2・・・式(6)
 式(5)は式(6)を意味する。すなわち、バイポーラトランジスタQ2のベース電流IBC2をバイポーラトランジスタQ3のベース電流I’BC3より小さく設定する。
The third embodiment of the present invention will be described in detail below with reference to FIG. However, there is a precondition of the following equation (5).
I ′ BC3 > I EC2 / hfe2 (5)
I ′ BC3 > I BC2 Formula (6)
Formula (5) means Formula (6). That is, the base current I BC2 of the bipolar transistor Q2 is set smaller than the base current I ′ BC3 of the bipolar transistor Q3.
 バイポーラトランジスタQ2のエミッタ電流IEC2は、IEC2=V3/r1であり、バイポーラトランジスタQ2の電流増幅率がhfe2のとき、バイポーラトランジスタQ2のベース電流IBC2は、IBC2=V3/r1/hfe2となる。
バイポーラトランジスタQ3のベース電流I’BC3と、バイポーラトランジスタQ2のベース電流IBC2の和、I’BC3+IBC2は、V3/r2で制限されるため、
I’BC3+IBC2=V3/r2となる。(I’BC3+V3/r1/hfe2)=V3/r2・・・式(7)となる。
The emitter current I EC2 of the bipolar transistor Q2 is I EC2 = V3 / r1, and when the current amplification factor of the bipolar transistor Q2 is hfe2, the base current I BC2 of the bipolar transistor Q2 is I BC2 = V3 / r1 / hfe2. Become.
Since the sum of the base current I ′ BC3 of the bipolar transistor Q3 and the base current I BC2 of the bipolar transistor Q2, I ′ BC3 + I BC2 is limited by V3 / r2,
I ′ BC3 + I BC2 = V3 / r2. (I ′ BC3 + V3 / r1 / hfe2) = V3 / r2 (7)
ただし、I’BC3は、バイポーラトランジスタQ3のエミッタE開放時のバイポーラトランジスタQ3のベース電流。V”BC3は、バイポーラトランジスタQ3のエミッタE開放時のバイポーラトランジスタQ3のコレクタ電位に対するベース電位。 However, I ′ BC3 is the base current of the bipolar transistor Q3 when the emitter E of the bipolar transistor Q3 is opened. V ″ BC3 is a base potential with respect to the collector potential of the bipolar transistor Q3 when the emitter E of the bipolar transistor Q3 is opened.
条件:A3
Vc2=Vc3(V1=V2の状態。FETQ1のソース電位=ドレイン電位。バイポーラトランジスタQ2のコレクタ電位=バイポーラトランジスタQ3のコレクタ電位。)
バイポーラトランジスタQ3のベース順方向電圧V”BC3が約0.6V(標準的PN接合ダイオードの順方向電圧)であるので、この電圧より低いバイポーラトランジスタQ2のベース順方向電圧VBC2において、バイポーラトランジスタQ3と共通ベース電位を有するバイポーラトランジスタQ2のベース電位によりバイポーラトランジスタQ2は確実に導通する。
Condition: A3
Vc2 = Vc3 (V1 = V2 state. Source potential of FETQ1 = drain potential. Collector potential of bipolar transistor Q2 = collector potential of bipolar transistor Q3.)
Since the base forward voltage V ″ BC3 of the bipolar transistor Q3 is about 0.6V (the forward voltage of a standard PN junction diode), the bipolar transistor Q3 has a base forward voltage V BC2 of the bipolar transistor Q2 lower than this voltage. The bipolar transistor Q2 is reliably turned on by the base potential of the bipolar transistor Q2 having the common base potential.
前提条件、I’BC3>IBC2・・・式(6)から、第1の実施の形態における図1の説明を援用し、V”BC3>V”’BC3=V”BC2>VBC2であり、バイポーラトランジスタQ2のコレクタ電位=バイポーラトランジスタQ3のコレクタ電位であれば(FETQ1のソース電位=ドレイン電位)、ベース電位を共通とするバイポーラトランジスタQ2とバイポーラトランジスタQ3において、このときのバイポーラトランジスタQ2のベース電位V”BC2は、バイポーラトランジスタQ2のベース電流IBC2=IEC2/hfe2で定められたバイポーラトランジスタQ2のベース順方向電圧VBC2より高い(V”BC2>VBC2)。
 バイポーラトランジスタQ2のベース順方向電圧VBC2と、バイポーラトランジスタQ3のベース順方向電圧V”BC3とで合成された電位(V”BC2=V”’BC3)となり、バイポーラトランジスタQ2を充分導通とするためのベース順方向電圧を得る。
From the precondition, I ′ BC3 > I BC2 (6), the description of FIG. 1 in the first embodiment is used, and V ″ BC3 > V ″ ′ BC3 = V ″ BC2 > VBC2 If the collector potential of the bipolar transistor Q2 = the collector potential of the bipolar transistor Q3 (the source potential of the FET Q1 = the drain potential), in the bipolar transistor Q2 and the bipolar transistor Q3 having the common base potential, the base of the bipolar transistor Q2 at this time potential V "BC2 is higher than the base forward voltage V BC2 of the bipolar transistor Q2 defined by the base current I BC2 = I EC2 / hfe2 bipolar transistor Q2 (V"BC2> V BC2 ).
A potential (V " BC2 = V"' BC3 ) synthesized by the base forward voltage V BC2 of the bipolar transistor Q2 and the base forward voltage V ″ BC3 of the bipolar transistor Q3 is set so that the bipolar transistor Q2 becomes sufficiently conductive. To obtain the base forward voltage.
ただし、V”’BC3、V”BC2は、ベースBを共通電位とするバイポーラトランジスタそれぞれQ3、Q2の条件A3におけるベース電位である。
すなわち、V”BC2は、電位V”BC3とVBC2が均衡した電位である。
バイポーラトランジスタQ2とバイポーラトランジスタQ3のベースは接続されているため、両ベース電位はV”’BC3=V” BC2となるよう、
V”BC3>V”’BC3=V”BC2>VBC2で均衡する。
However, V ″ ′ BC3 and V ″ BC2 are base potentials in the condition A3 of the bipolar transistors Q3 and Q2 having the base B as a common potential, respectively.
That is, V ″ BC2 is a potential in which the potentials V ″ BC3 and V BC2 are balanced.
Since the bases of the bipolar transistor Q2 and the bipolar transistor Q3 are connected, both base potentials are set to V ″ ′ BC3 = V ″ BC2 .
V ″ BC3 > V ″ ′ BC3 = V ″ BC2 > V BC2 is balanced.
このように、バイポーラトランジスタQ2は確実に導通するため、バイポーラトランジスタQ2のエミッタ電位は低下し略0Vであり、この電位が印加されるFETQ1のゲートにおいて、FETQ1は非導通である。このため、FETQ1のドレインDから、ソースSに電流は流れず、ダイオードの逆方向電流阻止の機能を有する。 Thus, since the bipolar transistor Q2 is surely turned on, the emitter potential of the bipolar transistor Q2 is reduced to about 0 V, and the FET Q1 is non-conductive at the gate of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
条件:B3
Vc2<Vc3’(V1<V2の状態。バイポーラトランジスタQ2のコレクタ電位<バイポーラトランジスタQ3のコレクタ電位。FETQ1のソース電位<ドレイン電位。)では、バイポーラトランジスタQ2が確実に導通する。
Vc2<Vc3’を別の表現をすると、Vc2<Vc3’は、Vc2<Vc3+Vαと表現できる。
上記条件A3の説明に加え、バイポーラトランジスタQ3のコレクタCの電位がVc3からVα上昇すると、バイポーラトランジスタQ3は、定められた自己のコレクタC、ベースB間電位差を維持するため、ベース電位がVα上昇することになる。このため、バイポーラトランジスタQ3のベースBと同電位であるバイポーラトランジスタQ2のベースB電位は、さらに上昇し、バイポーラトランジスタQ2は確実に導通する。
Condition: B3
When Vc2 <Vc3 ′ (V1 <V2 state. Collector potential of bipolar transistor Q2 <collector potential of bipolar transistor Q3. Source potential of FET Q1 <drain potential), bipolar transistor Q2 is surely turned on.
If Vc2 <Vc3 ′ is expressed in another way, Vc2 <Vc3 ′ can be expressed as Vc2 <Vc3 + Vα.
In addition to the description of the above condition A3, when the potential of the collector C of the bipolar transistor Q3 rises from Vc3 to Vα, the bipolar transistor Q3 maintains the potential difference between its own collector C and base B, so the base potential rises by Vα. Will do. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 further increases, and the bipolar transistor Q2 is surely turned on.
したがって、バイポーラトランジスタQ2のエミッタEの電位は低下し略0Vであり、この電位が印加されるFETQ1のゲートにおいて、FETQ1は非導通である。このため、FETQ1のドレインDから、ソースSに電流は流れず、ダイオードの逆方向電流阻止の機能を有する。 Therefore, the potential of the emitter E of the bipolar transistor Q2 decreases to about 0 V, and the FET Q1 is non-conductive at the gate of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
条件:C3
Vc2>Vc3”
これは、V1>V2(バイポーラトランジスタQ2のコレクタ電位>バイポーラトランジスタQ3のコレクタ電位。FETQ1のソース電位>ドレイン電位。)であり、バイポーラトランジスタQ2が非導通となる。
Vc2>Vc3”を別の表現をすると、Vc2>Vc3”は、Vc2>Vc3-Vβと表現できる。
上記条件A3の説明に加え、バイポーラトランジスタQ3のコレクタCの電位がVc3からVβ低下すると、定められた自己のコレクタC、ベースB間電位差を維持するため、ベース電位がVβ低下することになる。このため、バイポーラトランジスタQ3のベースBと同電位であるバイポーラトランジスタQ2のベースB電位は低下し、バイポーラトランジスタQ2は非導通となる。
Condition: C3
Vc2> Vc3 "
This is V1> V2 (the collector potential of the bipolar transistor Q2> the collector potential of the bipolar transistor Q3. The source potential of the FET Q1> the drain potential), and the bipolar transistor Q2 becomes non-conductive.
In other words, Vc2> Vc3 ″ can be expressed as Vc2> Vc3-Vβ.
In addition to the description of the above condition A3, when the potential of the collector C of the bipolar transistor Q3 is lowered by Vβ from Vc3, the base potential is lowered by Vβ in order to maintain a predetermined potential difference between the collector C and base B. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 decreases, and the bipolar transistor Q2 becomes non-conductive.
したがって、バイポーラトランジスタQ2のエミッタE電位は上昇し、端子T3に印加される直流電源電位となり、この電位が印加されるFETQ1のゲート電位において、FETQ1は導通となる。 Therefore, the emitter E potential of the bipolar transistor Q2 rises and becomes the DC power supply potential applied to the terminal T3, and the FET Q1 becomes conductive at the gate potential of the FET Q1 to which this potential is applied.
(4)第4の実施の形態
(4-1)回路構成
図4は、本発明による第4の実施の形態である整流回路及び整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。制御回路は、図4において破線で囲まれた回路である。
第4の実施の形態における図4の回路は、第2の実施の形態における図2の回路に第4半導体素子であるNPNバイポーラトランジスタQ4、第5半導体素子であるPNPバイポーラトランジスタQ5によるエミッタフォロア電流増幅回路を追加したものである。
図4と図2の回路において相違する点はこの部分のみである。したがって、図4の回路において、第2の実施の形態である図2の回路に共通する回路の各素子には図2の符号と同一の符号を付し、図2の回路構成の説明を援用し、重複する説明を割愛する。
(4) Fourth Embodiment (4-1) Circuit Configuration FIG. 4 shows a rectifier circuit according to a fourth embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1. The control circuit is a circuit surrounded by a broken line in FIG.
The circuit of FIG. 4 in the fourth embodiment is similar to the circuit of FIG. 2 in the second embodiment in that the emitter follower current is generated by an NPN bipolar transistor Q4 as a fourth semiconductor element and a PNP bipolar transistor Q5 as a fifth semiconductor element. An amplifier circuit is added.
This is the only difference between the circuits of FIG. 4 and FIG. Therefore, in the circuit of FIG. 4, each element of the circuit common to the circuit of FIG. 2 that is the second embodiment is denoted by the same reference numeral as that of FIG. 2, and the description of the circuit configuration of FIG. And omit duplicate explanations.
図4の回路において、バイポーラトランジスタQ4及びQ5のベースは、バイポーラトランジスタQ2のコレクタCに接続され、バイポーラトランジスタQ4とバイポーラトランジスタQ5のエミッタは、FETQ1のゲートGに接続され、バイポーラトランジスタQ4のコレクタは端子T3に、バイポーラトランジスタQ5のコレクタは端子T1に接続されている。 In the circuit of FIG. 4, the bases of the bipolar transistors Q4 and Q5 are connected to the collector C of the bipolar transistor Q2, the emitters of the bipolar transistors Q4 and Q5 are connected to the gate G of the FET Q1, and the collector of the bipolar transistor Q4 is The collector of the bipolar transistor Q5 is connected to the terminal T3 and the terminal T1.
(4)第4の実施の形態
(4-2)回路動作
図4を参照して本発明の第4の実施の形態である整流回路及び制御回路の回路動作を説明する。
図4は、第2の実施の形態である図2にエミッタフォロワ電流増幅回路が付加され、FETQ1のゲート容量を充電するに充分な電流を供給することができる。
バイポーラトランジスタQ2のエミッタ電位が高い(端子T3の電位)とき、バイポーラトランジスタQ4が導通し、バイポーラトランジスタQ5が非導通で、FETQ1を導通させ、バイポーラトランジスタQ2のエミッタ電位が低い(端子T1の電位)とき、バイポーラトランジスタQ4は非導通で、バイポーラトランジスタQ5が導通となり、FETQ1を非導通とさせる。
(4) Fourth Embodiment (4-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the fourth embodiment of the present invention will be described with reference to FIG.
In FIG. 4, an emitter follower current amplifier circuit is added to FIG. 2 which is the second embodiment, and a current sufficient to charge the gate capacitance of the FET Q1 can be supplied.
When the emitter potential of the bipolar transistor Q2 is high (the potential at the terminal T3), the bipolar transistor Q4 is turned on, the bipolar transistor Q5 is turned off, the FET Q1 is turned on, and the emitter potential of the bipolar transistor Q2 is low (the potential at the terminal T1). At this time, bipolar transistor Q4 is non-conductive, bipolar transistor Q5 is conductive, and FET Q1 is non-conductive.
 上記以外は第2の実施の形態である図2の回路動作の説明のとおりであり、第2の実施の形態の回路動作説明は、第1の実施の形態の回路動作説明を援用している。
したがって、第4の実施の形態である図4の回路動作説明は、第1及び第2の実施の形態である図1及び図2の回路動作説明を援用し、重複する説明を割愛する。
Other than the above, the circuit operation of the second embodiment is as described in FIG. 2, and the circuit operation description of the second embodiment uses the circuit operation description of the first embodiment. .
Therefore, the circuit operation description of FIG. 4 which is the fourth embodiment uses the circuit operation descriptions of FIG. 1 and FIG. 2 which are the first and second embodiments, and omits the overlapping description.
(5)第5の実施の形態
(5-1)回路構成
図5は、本発明による第5の実施の形態である整流回路及び整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。制御回路は、図5において破線で囲まれた回路である。
第5の実施の形態における図5の回路は、第4の実施の形態における図4の回路においてエミッタフォロア回路の一部を構成する第5半導体素子であるPNPバイポーラトランジスタQ5を整流素子であるダイオードDに置き換えたものである。
(5) Fifth Embodiment (5-1) Circuit Configuration FIG. 5 shows a rectifier circuit according to a fifth embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1. The control circuit is a circuit surrounded by a broken line in FIG.
In the circuit of FIG. 5 in the fifth embodiment, the PNP bipolar transistor Q5, which is a fifth semiconductor element constituting a part of the emitter follower circuit in the circuit of FIG. 4 in the fourth embodiment, is replaced with a diode that is a rectifier. D is replaced.
このダイオードDは、バイポーラトランジスタQ5のエミッタEとベースBが形成するPN接合ダイオードに相当する。 This diode D corresponds to a PN junction diode formed by the emitter E and base B of the bipolar transistor Q5.
図5と図4の回路において相違する点はこの部分のみである。したがって、図5の回路において、第4の実施の形態である図4の回路に共通する回路の各素子には図4の符号と同一の符号を付し、図4の回路構成の説明を援用し、重複する説明を割愛する。 This is the only difference between the circuits of FIG. 5 and FIG. Therefore, in the circuit of FIG. 5, the same reference numerals as those of FIG. 4 are given to the elements of the circuit common to the circuit of FIG. 4 which is the fourth embodiment, and the description of the circuit configuration of FIG. And omit duplicate explanations.
図5の回路において、ダイオードDのアノードはバイポーラトランジスタQ4のエミッタEに接続され、ダイオードDのカソードは、バイポーラトランジスタQ2のエミッタEに接続される。 In the circuit of FIG. 5, the anode of the diode D is connected to the emitter E of the bipolar transistor Q4, and the cathode of the diode D is connected to the emitter E of the bipolar transistor Q2.
(5)第5の実施の形態
(5-2)回路動作
図5を参照して本発明の第5の実施の形態である整流回路及び制御回路の回路動作を説明する。
図5におけるダイオードDは、FETQ1を導通とするときFETQ1のゲートGに蓄積された電荷を放電しFETQ1を非導通とする役割を果たす。FETQ1を非導通とするとき、バイポーラトランジスタQ2は導通するので、ダイオードDのカソードは、バイポーラトランジスタQ2のコレクタCと導通するので、これが可能である。
(5) Fifth Embodiment (5-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the fifth embodiment of the present invention will be described with reference to FIG.
The diode D in FIG. 5 plays a role of discharging the charge accumulated in the gate G of the FET Q1 and making the FET Q1 non-conductive when the FET Q1 is made conductive. This is possible because the bipolar transistor Q2 is conducting when the FET Q1 is non-conducting, so that the cathode of the diode D is conducting with the collector C of the bipolar transistor Q2.
 上記以外は第4の実施の形態である図4の回路動作の説明のとおりであり、第4の実施の形態の回路動作説明は、第2の実施の形態の回路動作説明を援用し、第2の実施の形態の回路動作説明は、第1の実施の形態の回路動作説明を援用している。
したがって、第5の実施の形態である図5の回路動作説明は、第1、第2及び第4の実施の形態である図1、図2及び図4の回路動作説明を援用し、重複する説明を割愛する。
Except for the above, the circuit operation of FIG. 4 is the description of the fourth embodiment. The circuit operation description of the fourth embodiment is based on the circuit operation description of the second embodiment. The circuit operation description of the second embodiment uses the circuit operation description of the first embodiment.
Therefore, the description of the circuit operation of FIG. 5 which is the fifth embodiment overlaps with the description of the circuit operation of FIG. 1, FIG. 2 and FIG. 4 which is the first, second and fourth embodiments. I will omit the explanation.
(6)第6の実施の形態
(6-1)回路構成
 図6は、本発明による第6の実施の形態である整流回路及び該整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。
図6において破線で囲まれた部分が該制御回路である。該制御回路は、第2半導体素子であるNPNバイポーラトランジスタQ2、第3半導体素子であるNPNバイポーラトランジスタQ3、第1抵抗素子である抵抗素子R1及び第2抵抗素子である抵抗素子R2で構成される。
(6) Sixth Embodiment (6-1) Circuit Configuration FIG. 6 shows a rectifier circuit according to a sixth embodiment of the present invention and a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel FETQ1.
In FIG. 6, the portion surrounded by a broken line is the control circuit. The control circuit includes an NPN bipolar transistor Q2 that is a second semiconductor element, an NPN bipolar transistor Q3 that is a third semiconductor element, a resistance element R1 that is a first resistance element, and a resistance element R2 that is a second resistance element. .
以下、図6を参照して本発明の回路構成を説明する。
直流電源の正極電位を入力する端子T1(ダイオードでいうアノードに相当)、直流電源の正極電位を出力する端子T2(ダイオードでいうカソードに相当)が存在する。
端子T1にFETQ1のソースSが接続され、FETQ1のドレインDには誘導性素子であるインダクターLの一端が接続され、該インダクターLの他端は端子T2に接続されている。電流は端子T1から端子T2へ、すなわち、FETQ1のソースSからドレインDへ流れる。ドレインDからソースSに向かう電流は遮断されるように制御される。
The circuit configuration of the present invention will be described below with reference to FIG.
There is a terminal T1 (corresponding to an anode referred to as a diode) for inputting the positive potential of the DC power supply, and a terminal T2 (corresponding to a cathode referred to as a diode) for outputting the positive potential of the DC power supply.
The terminal S1 is connected to the source S of the FET Q1, the drain D of the FET Q1 is connected to one end of an inductor L, which is an inductive element, and the other end of the inductor L is connected to the terminal T2. The current flows from the terminal T1 to the terminal T2, that is, from the source S to the drain D of the FET Q1. The current from the drain D to the source S is controlled to be cut off.
さらに、端子T1には、第2半導体素子であるNPNバイポーラトランジスタQ2のエミッタEが接続され、端子T2には、第3半導体素子であるNPNバイポーラトランジスタQ3のコレクタCが接続される。 Further, an emitter E of an NPN bipolar transistor Q2 that is a second semiconductor element is connected to the terminal T1, and a collector C of an NPN bipolar transistor Q3 that is a third semiconductor element is connected to the terminal T2.
バイポーラトランジスタQ2のベースBとバイポーラトランジスタQ3のベースBが接続され、この接続部に第2抵抗素子である抵抗素子R2の一端が接続され、抵抗素子R2の他端は、両バイポーラトランジスタQ2、Q3のベースBにバイアス電位を供給する直流電源が印加される端子T3に接続される。 The base B of the bipolar transistor Q2 and the base B of the bipolar transistor Q3 are connected, and one end of a resistance element R2 that is a second resistance element is connected to this connection portion, and the other end of the resistance element R2 is connected to both bipolar transistors Q2, Q3. Is connected to a terminal T3 to which a DC power supply for supplying a bias potential is applied to the base B.
バイポーラトランジスタQ3のエミッタEは、抵抗素子R2の一端に接続される。すなわち、バイポーラトランジスタQ3のベース、エミッタ間は短絡されている。
バイポーラトランジスタQ2のコレクタCは、第1抵抗素子である抵抗素子R1の一端に接続され、抵抗素子R1の他端は、バイポーラトランジスタQ2のコレクタC電位及びFETQ1のゲート電位を供給する直流電源が印加される端子T3に接続される。
The emitter E of the bipolar transistor Q3 is connected to one end of the resistance element R2. That is, the base and emitter of the bipolar transistor Q3 are short-circuited.
The collector C of the bipolar transistor Q2 is connected to one end of a resistance element R1 that is a first resistance element, and the other end of the resistance element R1 is applied with a DC power supply that supplies the collector C potential of the bipolar transistor Q2 and the gate potential of the FET Q1. Connected to terminal T3.
バイポーラトランジスタQ2のコレクタCは、FETQ1のゲートGに接続され、バイポーラトランジスタQ2のエミッタEは、FETQ1のソースに接続される。 The collector C of the bipolar transistor Q2 is connected to the gate G of the FET Q1, and the emitter E of the bipolar transistor Q2 is connected to the source of the FET Q1.
バイポーラトランジスタQ2、バイポーラトランジスタQ3、抵抗素子R1及び抵抗素子R2で構成される破線で囲まれた回路は、本発明の整流回路の一部である本発明の制御回路である。 A circuit surrounded by a broken line composed of the bipolar transistor Q2, the bipolar transistor Q3, the resistor element R1, and the resistor element R2 is the control circuit of the present invention which is a part of the rectifier circuit of the present invention.
(6)第6の実施の形態
(6-2)回路動作
 図6を参照して本発明の第1の実施の形態である整流回路及び制御回路の回路動作を説明する。
(6) Sixth Embodiment (6-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the first embodiment of the present invention will be described with reference to FIG.
 本発明の図1の回路における整流回路は、端子T1をアノードとし、端子T2をカソードとしたダイオードを構成し、端子T1、端子T2間に印加される電圧極性を制御回路が判別しFETQ1のゲートGに印加する電位を制御し、FETQ1の導通/非導通を制御する。 The rectifier circuit in the circuit of FIG. 1 of the present invention comprises a diode having the terminal T1 as an anode and the terminal T2 as a cathode, and the control circuit discriminates the voltage polarity applied between the terminals T1 and T2, and the gate of the FET Q1. The potential applied to G is controlled to control the conduction / non-conduction of the FET Q1.
 なお、本発明の回路動作説明において、各素子の電位はバイポーラトランジスタQ2のエミッタ電位を基準電位(=端子T1の電位、=FETQ1のソース電位)とし、各素子は端子T3に印加される直流正極性電位により動作する。
 端子T1に負荷動作用の直流電源の一端を接続し、端子T2には負荷の一端を接続する。図1の回路には示されていないが、別の電流路により、該直流電源の他端と負荷の他端を接続し直流電源と負荷の電流路を構成する。
 本発明の説明において、該直流電源の一端は正極性電位であり、該直流電源の他端は負極性電位とする。
In the description of the circuit operation of the present invention, the potential of each element is the direct current positive electrode applied to the terminal T3, with the emitter potential of the bipolar transistor Q2 being the reference potential (= the potential of the terminal T1, the source potential of the FET Q1). Operates with sex potential.
One end of a DC power source for load operation is connected to the terminal T1, and one end of the load is connected to the terminal T2. Although not shown in the circuit of FIG. 1, the other end of the DC power supply and the other end of the load are connected by another current path to form a current path of the DC power supply and the load.
In the description of the present invention, one end of the DC power source has a positive potential and the other end of the DC power source has a negative potential.
(6-2-1)FETQ1を非導通とする動作概要
端子T1の電位をV1、端子T2の電位をV2とすると、V1≦V2ではバイポーラトランジスタQ3は非導通又は少しだけ浅い導通状態にあり、バイポーラトランジスタQ2は確実に導通するため、抵抗素子R1による電圧降下によりバイポーラトランジスタQ2のコレクタCの電位は低下し略0Vである(制御回路の動作)。この電位が伝達されるFETQ1のゲート電位により、FETQ1は非導通である(制御回路の動作と併せて整流回路の動作となる。)。
すなわち、FETQ1のドレインDからソースSへ向かう電流は流れない。よって、端子T2は、ダイオードのカソード、端子T1は、ダイオードのアノードとして、図6の回路は動作する。
(6-2-1) Outline of operation for making FET Q1 non-conductive Assuming that the potential of the terminal T1 is V1 and the potential of the terminal T2 is V2, the bipolar transistor Q3 is non-conductive or slightly shallowly conductive when V1 ≦ V2, Since the bipolar transistor Q2 is surely turned on, the potential of the collector C of the bipolar transistor Q2 is reduced to approximately 0 V due to the voltage drop caused by the resistance element R1 (operation of the control circuit). The FET Q1 is non-conductive due to the gate potential of the FET Q1 to which this potential is transmitted (the operation of the rectifier circuit is combined with the operation of the control circuit).
That is, no current flows from the drain D to the source S of the FET Q1. Therefore, the circuit of FIG. 6 operates with the terminal T2 as the cathode of the diode and the terminal T1 as the anode of the diode.
 (6-2-2)FETQ1を導通とする動作概要
逆に、V1>V2ではバイポーラトランジスタQ3が導通し、バイポーラトランジスタQ2は非導通であるため、抵抗素子R1による電圧降下がなく、バイポーラトランジスタQ2のコレクタCの電位は端子T3に印加された直流電源電圧まで上昇し(制御回路の動作)、この電位が伝達されるFETQ1のゲート電位により、FETQ1を導通とする(制御回路の動作と併せて整流回路の動作となる。)。
すなわち、FETQ1のソースからドレインへ向かう電流は流れる。よって、端子T1は、ダイオードのアノード、端子T2は、ダイオードのカソードとして、図6の回路は動作する。
(6-2-2) Outline of operation for making FET Q1 conductive On the contrary, when V1> V2, bipolar transistor Q3 is conductive and bipolar transistor Q2 is nonconductive, so there is no voltage drop due to resistance element R1, and bipolar transistor Q2 The potential of the collector C rises to the DC power supply voltage applied to the terminal T3 (operation of the control circuit), and the FET Q1 is made conductive by the gate potential of the FET Q1 to which this potential is transmitted (in conjunction with the operation of the control circuit). The operation of the rectifier circuit.)
That is, a current flowing from the source to the drain of the FET Q1 flows. Therefore, the circuit of FIG. 6 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.
上記説明において補足すると、FETQ1が非導通のときは、FETQ1のドレインDからソースSに向かう電流は流れないことは勿論であるが、FETQ1のボディダイオードにより、ソースからドレイン方向へ向かう電流は流れることが可能である。ただし、V1≦V2においてFETQ1が非導通となる前提条件があるため、ソースからドレイン方向へ向かう電流は有り得ない。 As supplemented in the above description, when the FET Q1 is non-conductive, the current from the drain D to the source S of the FET Q1 does not flow, but the current from the source to the drain flows by the body diode of the FET Q1. Is possible. However, since there is a precondition that the FET Q1 is non-conductive when V1 ≦ V2, there is no current from the source toward the drain.
また、FETQ1が導通のときは、FETQ1のソースSからドレインDに向かう電流が流れることは勿論であるが、FETQ1のドレインDからソースS方向へ向かう電流も流れることが可能である。ただし、V1>V2のときにおいてFETQ1が導通となる前提条件があるため、FETQ1ドレインからソース方向へ向かう電流は有り得ない。
FETQ1の導通時は、FETQ1のボディダイオードによらずFETQ1の極めて低い導通抵抗によりソースからドレイン方向へ向かう電流を流すことができるので、PN接合ダイオードによる整流より遙かに有利である。
Further, when the FET Q1 is conductive, a current flowing from the source S to the drain D of the FET Q1 flows, but a current flowing from the drain D to the source S of the FET Q1 can also flow. However, since there is a precondition that the FET Q1 becomes conductive when V1> V2, there is no current from the drain of the FET Q1 toward the source.
When the FET Q1 is conductive, a current flowing from the source to the drain direction can be flowed by the extremely low conductive resistance of the FET Q1 regardless of the body diode of the FET Q1, which is far more advantageous than the rectification by the PN junction diode.
以下、図6を参照して本発明の第6の実施の形態について、詳細な説明をする。ただし、以下の式(1-1)、式(1-2)の前提条件が存在する。
EC3/hfe3>ICE2/hfe2・・・・式(1-1)
式(1-1)は、IBC3>IBE2を表している。
hfe2・r1>hfe3・r2・・・・・・式(1-2)
式(1-1)は式(1-2)と等価である。
式(1-2)に基づき、場合の条件式を展開すると、以下の式が考えられる。
hfe2=hfe3の場合、r1>r2・・・式(2)
hfe2>hfe3の場合、r1≧r2・・・式(3)
hfe2≫hfe3の場合、r1<r2・・・式(4)
hfe2<hfe3の場合は、ここでは考えない。
Hereinafter, a sixth embodiment of the present invention will be described in detail with reference to FIG. However, there are preconditions of the following equations (1-1) and (1-2).
I EC3 / hfe3> I CE2 / hfe2... Formula (1-1)
Formula (1-1) represents I BC3 > I BE2 .
hfe2 · r1> hfe3 · r2 ··· formula (1-2)
Expression (1-1) is equivalent to Expression (1-2).
When the conditional expression of the case is expanded based on the expression (1-2), the following expression can be considered.
When hfe2 = hfe3, r1> r2 (2)
When hfe2> hfe3, r1 ≧ r2 (3)
When hfe2 >> hfe3, r1 <r2 (4)
The case where hfe2 <hfe3 is not considered here.
ただし、hfe2はバイポーラトランジスタQ2のエミッタE接地時の電流増幅率、hfe3はバイポーラトランジスタQ3のコレクタC接地時の電流増幅率。
BE2は、バイポーラトランジスタQ2のベース電流、IBC3は、バイポーラトランジスタQ3のベース電流。
CE2は、バイポーラトランジスタQ2のコレクタ電流、IEC3はバイポーラトランジスタQ3のエミッタ電流。
r1は抵抗素子R1の抵抗値、r2は抵抗素子R2の抵抗値である。
バイポーラトランジスタQ2のエミッタ電位をVe2、バイポーラトランジスタQ3コレクタ電位をVc3、Ve2=V1、Vc3=V2とする。
However, hfe2 is the current amplification factor when the emitter E of the bipolar transistor Q2 is grounded, and hfe3 is the current amplification factor when the collector C of the bipolar transistor Q3 is grounded.
I BE2 is the base current of the bipolar transistor Q2, and I BC3 is the base current of the bipolar transistor Q3.
I CE2 is the collector current of the bipolar transistor Q2, and IEC3 is the emitter current of the bipolar transistor Q3.
r1 is the resistance value of the resistance element R1, and r2 is the resistance value of the resistance element R2.
The emitter potential of the bipolar transistor Q2 is Ve2, the collector potential of the bipolar transistor Q3 is Vc3, Ve2 = V1, and Vc3 = V2.
条件:A6
Ve2=Vc3(V1=V2の状態。バイポーラトランジスタQ2のエミッタ電位=バイポーラトランジスタQ3のコレクタ電位。)では、バイポーラトランジスタQ3が少しだけ浅く導通し、バイポーラトランジスタQ2が確実に導通する。
Condition: A6
In Ve2 = Vc3 (the state where V1 = V2, the emitter potential of the bipolar transistor Q2 = the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 conducts slightly shallower and the bipolar transistor Q2 conducts reliably.
図6の回路では、hfe2>hfe3であるため、式(3)を適用する。
hfe2>hfe3である理由は、バイポーラトランジスタQ2はエミッタ接地、バイポーラトランジスタQ3はコレクタ接地であるためである。よって、IBC3>IBE2で表されるとおり、バイポーラトランジスタQ3のベース電流は多く、バイポーラトランジスタQ2のベース電流は少ない。
ただし、バイポーラトランジスタQ2、Q3は、同一の接地回路(両トランジスタをエミッタ接地とした場合など)において略同一のhfeである場合の例である。また、温度特性なども略同一のものを使用することが好適である。
In the circuit of FIG. 6, since hfe2> hfe3, Expression (3) is applied.
The reason why hfe2> hfe3 is that the bipolar transistor Q2 is grounded on the emitter and the bipolar transistor Q3 is grounded on the collector. Therefore, as represented by I BC3 > I BE2 , the base current of the bipolar transistor Q3 is large and the base current of the bipolar transistor Q2 is small.
However, the bipolar transistors Q2 and Q3 are examples in the case where they are substantially the same hfe in the same ground circuit (such as when both transistors are connected to the emitter ground). Further, it is preferable to use substantially the same temperature characteristics.
図6において、上記、「hfe2>hfe3の場合、r1≧r2・・・式(3)が成立し、バイポーラトランジスタQ2のエミッタE、バイポーラトランジスタQ3のコレクタC間の電位が略同一であるとき、結果的に、IBC3>IBE2となる。したがって、バイポーラトランジスタQ3を導通させるためのベース順方向電圧VBC3が、VBC3>VBE2となる。 In FIG. 6, when “hfe2> hfe3”, r1 ≧ r2 (Equation (3)) is established, and the potential between the emitter E of the bipolar transistor Q2 and the collector C of the bipolar transistor Q3 is substantially the same. As a result, I BC3 > I BE 2. Therefore, the base forward voltage V BC3 for conducting the bipolar transistor Q3 becomes V BC3 > V BE2 .
上記の状態において、バイポーラトランジスタQ2とバイポーラトランジスタQ3のベースは接続されているため、両ベース電位はV’BC3=V’BE2となるように均衡し、
BC3>V’BC3=V’BE2>VBE2の状態で、VBC3とVBE2との中間的電位に落ち着く。
したがって、バイポーラトランジスタQ3を導通させるためのベース順方向電圧VBC3が、バイポーラトランジスタQ3の導通に必要な電位VBC3を下回り、このため、IBC3及びIEC3は、バイポーラトランジスタQ3のベースBに通常のベース順方向電圧VBC3が印加されたときより少なくなる。
In the above state, since the bases of the bipolar transistor Q2 and the bipolar transistor Q3 are connected, both base potentials are balanced so that V ′ BC3 = V ′ BE2 ,
In the state of V BC3 > V ′ BC3 = V ′ BE2 > V BE2 , the potential settles to an intermediate potential between V BC3 and V BE2 .
Therefore, the base forward voltage V BC3 for conducting the bipolar transistor Q3 is lower than the potential V BC3 required for conducting the bipolar transistor Q3, and therefore I BC3 and I EC3 are normally applied to the base B of the bipolar transistor Q3. Less than when the base forward voltage VBC3 is applied.
両バイポーラトランジスタのベース電位、V’BC3=V’BE2の均衡によってIBC3及びIEC3が減少するが、R2を流れる電流は、Ir2=V3/r2であり、r2により制限されて変わらないので、
BC3及びIEC3が減少した分だけIBE2が多く流れ、バイポーラトランジスタQ2は、確実な導通状態を維持できる。
I BC3 and I EC3 decrease due to the balance of the base potentials of both bipolar transistors, V ′ BC3 = V ′ BE2 , but the current flowing through R2 is Ir2 = V3 / r2 and is limited by r2 and does not change.
I BE2 flows as much as I BC3 and I EC3 decrease, and the bipolar transistor Q2 can maintain a reliable conduction state.
ただし、VBE2は、バイポーラトランジスタQ2のエミッタ電位に対するベース電位、
BC3は、バイポーラトランジスタQ3のコレクタ電位に対するベース電位。
ベース順方向電圧VBE2は、バイポーラトランジスタQ2のコレクタC、エミッタE間が導通する電圧。
ベース順方向電圧VBC3は、バイポーラトランジスタQ3のエミッタE、コレクタC間が導通する電圧である。
However, V BE2 is a base potential with respect to the emitter potential of the bipolar transistor Q2,
V BC3 is a base potential with respect to the collector potential of the bipolar transistor Q3.
The base forward voltage V BE2 is a voltage at which the collector C and the emitter E of the bipolar transistor Q2 are conducted.
The base forward voltage VBC3 is a voltage that conducts between the emitter E and the collector C of the bipolar transistor Q3.
BC3>IBE2についてさらに説明を加えると、
hfe2は、hfe2=ICE2/IBE2で表され、
hfe3は、hfe3=IEC3/IBC3で表される。
CE2はr1の逆数の関数、IEC3はr2の逆数の関数で表わされ、
EC3/hfe3>ICE2/hfe2・・・・式(1-1)と、
hfe2>hfe3の場合、r1≧r2・・・式(3)のr1≧r2の関係により、
EC3≧ICE2の傾向にあり、さらに式(3)のhfe2>hfe3の関係により、
結果としてIBC3>IBE2となる。
BC3>IBE2であるため、電流量の少ないIBE2が流れるバイポーラトランジスタQ2のベース順方向電圧VBE2は、電流量の多いIBC3が流れるバイポーラトランジスタQ3のベース順方向電圧VBC3よりも小さい。
 したがって、上記のとおり、VBC3>VBE2となる。
Further explanation of I BC3 > I BE2
hfe2 is represented by hfe2 = I CE2 / I BE2 ,
hfe3 is represented by hfe3 = I EC3 / I BC3 .
I CE2 is expressed as a function of the reciprocal of r1, and I EC3 is expressed as a function of the reciprocal of r2.
I EC3 / hfe3> I CE2 / hfe2... Formula (1-1),
In the case of hfe2> hfe3, r1 ≧ r2...
There is a tendency of I EC3 ≧ I CE2 , and further, due to the relationship of hfe2> hfe3 in the formula (3),
As a result, I BC3 > I BE2 .
Since I BC3 > I BE2 , the base forward voltage V BE2 of the bipolar transistor Q2 through which the low current amount I BE2 flows is smaller than the base forward voltage V BC3 of the bipolar transistor Q3 through which the large current amount I BC3 flows. .
Therefore, as described above, V BC3 > V BE2 is satisfied .
 IEC3≒V3/r2、ICE2=V3/r1である。ただし、V3は端子T3に印加される直流電源電位である。
 ここで、IEC3≒V3/r2であり、IEC3=V3/r2ではないのは、抵抗素子R2には、バイポーラトランジスタQ2、Q3にベース電流を流すためである。
I EC3 ≈V3 / r2 and I CE2 = V3 / r1. However, V3 is a DC power supply potential applied to the terminal T3.
Here, I EC3 ≈V3 / r2, and I EC3 = V3 / r2 is not caused, because the base current is caused to flow through the bipolar transistors Q2 and Q3 through the resistance element R2.
バイポーラトランジスタQ2は確実に導通するため、バイポーラトランジスタQ2のコレクタC電位は低下し略0Vであり、この電位が印加されるFETQ1のゲートGにおいて、FETQ1は非導通である。このため、FETQ1のドレインDから、ソースSに電流は流れず、ダイオードの逆方向電流阻止の機能を有する。 Since the bipolar transistor Q2 is reliably turned on, the collector C potential of the bipolar transistor Q2 is reduced to about 0 V, and the FET Q1 is non-conductive at the gate G of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
条件:B6
Ve2<Vc3’(V1<V2の状態。バイポーラトランジスタQ2のエミッタ電位<バイポーラトランジスタQ3のコレクタ電位。)では、バイポーラトランジスタQ3が非導通であり、バイポーラトランジスタQ2が確実に導通する。
Ve2<Vc3’を別の表現をすると、Vc2<Vc3’は、Ve2<Vc3+Vαと表現できる。
上記条件:A6の説明に加え、バイポーラトランジスタQ3のコレクタCの電位がVc3からVα上昇すると、バイポーラトランジスタQ3は、定められた自己のコレクタC、ベースB間電位を維持するため、ベース電位がVα上昇することになる。このため、バイポーラトランジスタQ3のベースBと同電位であるバイポーラトランジスタQ2のベースB電位は、さらに上昇し、バイポーラトランジスタQ2は確実に導通する。
Condition: B6
In Ve2 <Vc3 ′ (the state of V1 <V2, the emitter potential of the bipolar transistor Q2 <the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 is non-conductive, and the bipolar transistor Q2 is reliably conductive.
If Ve2 <Vc3 ′ is expressed in another way, Vc2 <Vc3 ′ can be expressed as Ve2 <Vc3 + Vα.
The above condition: In addition to the description of A6, when the potential of the collector C of the bipolar transistor Q3 rises from Vc3 to Vα, the bipolar transistor Q3 maintains the predetermined potential between its collector C and base B. Will rise. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 further increases, and the bipolar transistor Q2 is surely turned on.
したがって、バイポーラトランジスタQ2のコレクタCの電位は低下し略0Vであり、この電位が印加されるFETQ1のゲートGにおいて、FETQ1は非導通である。このため、FETQ1のドレインDから、ソースSに電流は流れず、ダイオードの逆方向電流阻止の機能を有する。 Therefore, the potential of the collector C of the bipolar transistor Q2 decreases to approximately 0 V, and the FET Q1 is non-conductive at the gate G of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
なお、バイポーラトランジスタQ3が非導通となる理由は、バイポーラトランジスタQ3のベースBにとっては、コレクタ側から逆バイアス電圧が印加されたこととなり、ベース電流が流れなくなるためである。 The reason why the bipolar transistor Q3 becomes non-conductive is that, for the base B of the bipolar transistor Q3, the reverse bias voltage is applied from the collector side, and the base current does not flow.
条件:C6
Ve2>Vc3”(V1>V2の状態。バイポーラトランジスタQ2のエミッタ電位>バイポーラトランジスタQ3のコレクタ電位。)では、バイポーラトランジスタQ3が導通し、バイポーラトランジスタQ2が非導通となる。
Ve2>Vc3”を別の表現をすると、Ve2>Vc3”は、Ve2>Vc3-Vβと表現できる。
Condition: C6
In Ve2> Vc3 ″ (the state of V1> V2, the emitter potential of the bipolar transistor Q2> the collector potential of the bipolar transistor Q3), the bipolar transistor Q3 becomes conductive and the bipolar transistor Q2 becomes nonconductive.
If Ve2> Vc3 ″ is expressed in another way, Ve2> Vc3 ″ can be expressed as Ve2> Vc3-Vβ.
上記条件A6の説明に加え、バイポーラトランジスタQ3のコレクタCの電位がVc3からVβ低下すると、定められた自己のコレクタC、ベースB間電位を維持するため、ベース電位がVβ低下することになる。このため、バイポーラトランジスタQ3のベースBと同電位であるバイポーラトランジスタQ2のベースB電位は低下し、バイポーラトランジスタQ2は非導通となる。 In addition to the description of the above condition A6, when the potential of the collector C of the bipolar transistor Q3 is lowered by Vβ from Vc3, the base potential is lowered by Vβ in order to maintain the predetermined self-collector C and base B potential. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 decreases, and the bipolar transistor Q2 becomes non-conductive.
したがって、バイポーラトランジスタQ2のコレクタC電位は上昇し、端子T3に印加される直流電源電位となり、この電位が印加されるFETQ1のゲートGにおいて、FETQ1は導通となる。このため、FETQ1のソースSから、ドレインDに電流が流れ、FETQ1のソースSは、ダイオードのアノード、FETQ1のドレインDは、ダイオードのカソードの機能を有する。 Therefore, the collector C potential of the bipolar transistor Q2 rises and becomes the DC power supply potential applied to the terminal T3, and the FET Q1 becomes conductive at the gate G of the FET Q1 to which this potential is applied. Therefore, a current flows from the source S of the FET Q1 to the drain D, the source S of the FET Q1 has a function of an anode of the diode, and the drain D of the FET Q1 has a function of a cathode of the diode.
なお、バイポーラトランジスタQ3が導通となる理由は、バイポーラトランジスタQ3のベースBにとっては、コレクタC側から順バイアス電圧が印加されたこととなり、ベース電流が充分流れるためである。 The reason why the bipolar transistor Q3 becomes conductive is that the forward bias voltage is applied from the collector C side to the base B of the bipolar transistor Q3, and the base current flows sufficiently.
図6の回路において、FETQ1のドレインDと端子T2間に誘導性素子であるインダクターLを挿入する理由は、当該回路のFETQ1を非導通とする電流路遮断に係る周波数特性を良くするためである。 In the circuit of FIG. 6, the reason why the inductor L, which is an inductive element, is inserted between the drain D of the FET Q1 and the terminal T2 is to improve the frequency characteristics related to the current path interruption that makes the FET Q1 of the circuit non-conductive. .
この動作原理は、V1>V2からV1≦V2に端子T1、端子T2間に印加される電位が遷移したとき、バイポーラトランジスタQ3のコレクタ電位は直ちにV2となるが、インダクターLにより、FETQ1のドレインに印加される電位V2に遅れが発生するため、FETQ1が非導通となるまでに時間を稼ぐためである。 This operating principle is that when the potential applied between the terminal T1 and the terminal T2 transitions from V1> V2 to V1 ≦ V2, the collector potential of the bipolar transistor Q3 immediately becomes V2, but the inductor L causes the drain of the FET Q1 to be drained. This is because a delay occurs in the applied potential V2, and time is taken until the FET Q1 becomes non-conductive.
仮に、インダクターLが、FETQ1が配設されている電流路のFETQ1のドレインD側電流路に挿入されていない場合、各素子、特にバイポーラトランジスタQ2、Q3及びFETQ1のゲートの電荷放電時間による電位の伝達の遅れにより、FETQ1が導通から非導通に遷移するための時間的遅れが発生する。
したがって、FETQ1が導通状態のまま、電流がFETQ1のドレインDからソースSに逆流してしまう。
If the inductor L is not inserted in the drain D-side current path of the FET Q1 in the current path in which the FET Q1 is disposed, the potential due to the charge discharge time of each element, in particular, the gates of the bipolar transistors Q2, Q3 and FET Q1 Due to the transmission delay, a time delay occurs for the FET Q1 to transition from conduction to non-conduction.
Therefore, the current flows backward from the drain D to the source S of the FET Q1 while the FET Q1 is in the conductive state.
端子T2に別の電源による電位V2が印加されている状態において、上記のように、FETQ1の導通から非導通への遅れの発生と、端子T1の電位V1が、V1<V2なる条件が重なると端子T2に印加された電位V2により、端子T1に接続されている電源側へ電流が流れる。 When the potential V2 from another power source is applied to the terminal T2, as described above, when the delay from the conduction to the non-conduction of the FET Q1 and the condition that the potential V1 of the terminal T1 is V1 <V2 overlap. A current flows to the power supply side connected to the terminal T1 by the potential V2 applied to the terminal T2.
このような、事態が発生すると整流回路としての機能が失われる。インダクターLは、端子T2に印加される電位V2のFETQ1のドレインDへの伝達を遅らせる機能を有する。このインダクターLにより、高調波パルス電位が印加されるスイッチング電源等の整流回路に適合可能となる。  When such a situation occurs, the function as a rectifier circuit is lost. The inductor L has a function of delaying transmission of the potential V2 applied to the terminal T2 to the drain D of the FET Q1. This inductor L can be adapted to a rectifier circuit such as a switching power supply to which a harmonic pulse potential is applied. *
(7)第7の実施の形態
(7-1)回路構成
図7は、本発明による第7の実施の形態である整流回路及び整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。
第7の実施の形態における図7は、第6の実施の形態における図6から誘導性素子であるインダクターLを取り除き、端子T2とFETQ1のドレインDを直接接続した回路である。
したがって、図7の回路は、インダクターLを除き各素子の符号は、図6の回路の各素子の符号と同一の符号を付し、図1の回路構成の説明を援用し、重複する説明を割愛する。
(7) Seventh Embodiment (7-1) Circuit Configuration FIG. 7 shows a rectifier circuit according to a seventh embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
FIG. 7 in the seventh embodiment is a circuit in which the inductor L, which is an inductive element, is removed from FIG. 6 in the sixth embodiment, and the terminal T2 and the drain D of the FET Q1 are directly connected.
Therefore, in the circuit of FIG. 7, the reference numerals of the elements other than the inductor L are the same as those of the elements of the circuit of FIG. 6, and the description of the circuit configuration of FIG. Omit.
(7)第7の実施の形態
(7-2)回路動作
第7の実施の形態における図7の回路は、第6の実施の形態における図6の回路から誘導性素子であるインダクターLを取り除き、端子T2とFETQ1のドレインDを直接接続した回路である。
 したがって、図7の回路動作の説明は、図6の回路動作の説明から、誘導性素子であるインダクターLの動作説明を削除したものと同一であり、同一である重複する説明は割愛する。
(7) Seventh Embodiment (7-2) Circuit Operation The circuit of FIG. 7 in the seventh embodiment removes the inductor L that is an inductive element from the circuit of FIG. 6 in the sixth embodiment. , A circuit in which the terminal T2 and the drain D of the FET Q1 are directly connected.
Therefore, the description of the circuit operation in FIG. 7 is the same as that in which the operation description of the inductor L, which is an inductive element, is deleted from the description of the circuit operation in FIG. 6, and the same overlapping description is omitted.
図7には、インダクターLが存在しないため、図6における動作説明のFETQ1を非導通とする電流路遮断に係る周波数特性を良くする必要のない高周波数における遮断特性が要求されない整流回路、直流電源を並列接続するためのORingFETダイオード回路等に好適である。 In FIG. 7, since there is no inductor L, there is no need to improve the frequency characteristic related to the current path interruption that makes the FET Q1 of the operation description in FIG. 6 non-conductive. Is suitable for an ORingFET diode circuit for connecting the two in parallel.
(8)第8の実施の形態
(8-1)回路構成
図8は、本発明による第8の実施の形態である整流回路及び整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。
(8) Eighth Embodiment (8-1) Circuit Configuration FIG. 8 shows a rectifier circuit according to an eighth embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1.
第8の実施の形態における図8の回路は、第6の実施の形態における図6の回路から誘導性素子であるインダクターLを取り除き、端子T2とFETQ1のドレインDを直接接続し、さらに、バイポーラトランジスタQ3のベースBとエミッタE間の接続を開放した回路である。すなわち、バイポーラトランジスタQ3のエミッタが開放されている。
したがって、図8の回路の各素子の符号は、図6の回路の各素子の符号と同一の符号を付し、図6の回路構成の説明を援用し、重複する説明を割愛する。
The circuit of FIG. 8 in the eighth embodiment removes the inductor L, which is an inductive element, from the circuit of FIG. 6 in the sixth embodiment, directly connects the terminal T2 and the drain D of the FET Q1, and is further bipolar. In this circuit, the connection between the base B and the emitter E of the transistor Q3 is opened. That is, the emitter of the bipolar transistor Q3 is open.
Therefore, the reference numerals of the elements of the circuit of FIG. 8 are the same as the reference numerals of the elements of the circuit of FIG. 6, the description of the circuit configuration of FIG. 6 is used, and the overlapping description is omitted.
(8)第8の実施の形態
(8-2)回路動作
図8を参照して本発明の第8の実施の形態である整流回路及び制御回路の回路動作を説明する。
(8) Eighth Embodiment (8-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the eighth embodiment of the present invention will be described with reference to FIG.
第8の実施の形態における図8の回路は、第6の実施の形態における図6の回路から誘導性素子であるインダクターLを取り除き、出力端子T2とFETQ1のドレインDを直接接続し、さらに、バイポーラトランジスタQ3のベースBとエミッタE間の接続を開放した回路である。 The circuit of FIG. 8 in the eighth embodiment removes the inductor L that is an inductive element from the circuit of FIG. 6 in the sixth embodiment, directly connects the output terminal T2 and the drain D of the FET Q1, In this circuit, the connection between the base B and the emitter E of the bipolar transistor Q3 is opened.
本発明の第8の実施の形態である図8の回路は、バイポーラトランジスタQ3のベースBとエミッタEが接続されていない回路であり、すなわち、本発明の第8の実施の形態における破線で囲まれた制御回路が、本発明の第6の実施の形態である図6の破線で囲まれた制御回路の回路動作と相違するところは、この点に起因する。
本発明の第8の実施の形態の説明においても、第6の実施の形態で使用した電位値、電流値、電流増幅率、抵抗値等の記号は同一の記号を使用し該記号の意義も同一とする。
The circuit of FIG. 8 which is the eighth embodiment of the present invention is a circuit in which the base B and the emitter E of the bipolar transistor Q3 are not connected, that is, surrounded by a broken line in the eighth embodiment of the present invention. This is the reason why the control circuit is different from the circuit operation of the control circuit surrounded by the broken line in FIG. 6 which is the sixth embodiment of the present invention.
In the description of the eighth embodiment of the present invention, the same symbols are used for symbols such as potential value, current value, current amplification factor, resistance value, etc. used in the sixth embodiment, and Identical.
したがって、図8の回路動作の説明は、図6の回路動作の説明から、誘導性素子であるインダクターLの動作説明を削除し、バイポーラトランジスタQ3のベースBとエミッタE間の接続を開放した回路動作について中心に説明し、図6の回路と動作が共通する部分は図6の回路の動作説明を援用し、重複する説明は割愛する。 Therefore, in the description of the circuit operation of FIG. 8, the description of the operation of the inductor L, which is an inductive element, is deleted from the description of the circuit operation of FIG. 6, and the connection between the base B and the emitter E of the bipolar transistor Q3 is opened. The operation will be mainly described, and the description of the operation of the circuit in FIG.
図8の回路には、インダクターLが存在しないため、図6の回路における動作説明の電流路遮断(FETQ1を非導通とする)に係る周波数特性を良くする必要のない高周波数における遮断特性が要求されない整流回路、直流電源を並列接続するためのORingFETダイオード回路等に好適である。 Since the inductor L does not exist in the circuit of FIG. 8, a high frequency cutoff characteristic that does not need to improve the frequency characteristic related to the current path cutoff (the FET Q1 is made non-conductive) in the operation of the circuit of FIG. 6 is required. This is suitable for a rectifier circuit that is not connected, an ORingFET diode circuit for connecting DC power supplies in parallel, and the like.
図8の回路において、バイポーラトランジスタQ3のベースBとエミッタE間は解放されているため、バイポーラトランジスタQ3は、ベースBがP型、コレクタCがN型のPN接合のダイオードとして機能する。 In the circuit of FIG. 8, since the base B and the emitter E of the bipolar transistor Q3 are open, the bipolar transistor Q3 functions as a PN junction diode with the base B being P-type and the collector C being N-type.
(8-2-1)FETQ1を非導通とする動作概要
端子T1の電位をV1、端子T2の電位をV2とすると、V1≦V2では、バイポーラトランジスタQ3のベースB、コレクタC間に、コレクタ電位を基準として、ベース順方向電圧V”BC3=約0.6Vの標準的PN接合電位差が発生し、バイポーラトランジスタQ3と共通ベース電位を有するバイポーラトランジスタQ2のベース電位によりバイポーラトランジスタQ2は確実に導通する。
(8-2-1) Outline of operation for making FET Q1 non-conducting When the potential of the terminal T1 is V1 and the potential of the terminal T2 is V2, the collector potential between the base B and the collector C of the bipolar transistor Q3 is V1 ≦ V2. A standard PN junction potential difference of base forward voltage V ″ BC3 = about 0.6 V is generated with reference to the base potential of bipolar transistor Q2 and bipolar transistor Q2 having a common base potential and bipolar transistor Q2 is surely turned on. .
図8の回路では、バイポーラトランジスタQ3のエミッタ電流が流れないため、
BC3+ICE2=V3/r2であり、V3/r2が一定であれば、バイポーラトランジスタQ3のエミッタ電流が流れるときよりも、バイポーラトランジスタQ3のエミッタ電流が流れないときの方が、IBC3は大きい。
In the circuit of FIG. 8, since the emitter current of the bipolar transistor Q3 does not flow,
If I BC3 + I CE2 = V3 / r2 and V3 / r2 is constant, I BC3 is larger when the emitter current of bipolar transistor Q3 does not flow than when the emitter current of bipolar transistor Q3 flows. .
したがって、バイポーラトランジスタQ2の電流路に電流が流れるため、抵抗素子R1による電圧降下によりバイポーラトランジスタQ2のコレクタCの電位は低下し略0Vである(制御回路の動作)。
この電位が伝達されるFETQ1のゲート電位により、FETQ1は非導通である(制御回路の動作と併せて整流回路の動作)。
すなわち、FETQ1のドレインDからソースSへ向かう電流は流れない。よって、端子T1は、ダイオードのアノード、端子T2は、ダイオードのカソードとして、図4の回路は動作する。
Therefore, since a current flows through the current path of the bipolar transistor Q2, the potential of the collector C of the bipolar transistor Q2 is reduced to approximately 0 V due to a voltage drop caused by the resistance element R1 (operation of the control circuit).
The FET Q1 is non-conductive due to the gate potential of the FET Q1 to which this potential is transmitted (operation of the rectifier circuit in addition to the operation of the control circuit).
That is, no current flows from the drain D to the source S of the FET Q1. Therefore, the circuit of FIG. 4 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.
 (8-2-2)FETQ1を導通とする動作概要
逆に、V1>V2では、第6の実施の形態と同様にバイポーラトランジスタQ3のベースBの電位が低下し、バイポーラトランジスタQ2は非導通となるため、抵抗素子R1による電圧降下がなく、バイポーラトランジスタQ2のコレクタCの電位は端子T3に印加された直流電源電圧まで上昇し(制御回路の動作)、この電位が伝達されるFETQ1のゲート電位により、FETQ1を導通とする(制御回路の動作と併せて整流回路の動作)。
すなわち、FETQ1のソースからドレインへ向かう電流は流れる。よって、端子T1は、ダイオードのアノード、端子T2は、ダイオードのカソードとして、図8の回路は動作する。
(8-2-2) Outline of Operation for Making FET Q1 Conductive On the contrary, when V1> V2, the potential of the base B of the bipolar transistor Q3 is lowered similarly to the sixth embodiment, and the bipolar transistor Q2 is non-conductive. Therefore, there is no voltage drop due to the resistor element R1, the potential of the collector C of the bipolar transistor Q2 rises to the DC power supply voltage applied to the terminal T3 (operation of the control circuit), and the gate potential of the FET Q1 to which this potential is transmitted Thus, the FET Q1 is made conductive (operation of the rectifier circuit together with the operation of the control circuit).
That is, a current flowing from the source to the drain of the FET Q1 flows. Therefore, the circuit of FIG. 8 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.
以下、図8を参照して本発明の第8の実施の形態について、詳細な説明をする。ただし、以下の式(5)の前提条件が存在する。
I’BC3>ICE2/hfe2・・・式(5)
I’BC3>IBE2・・・式(6)
 式(5)は式(6)を意味する。すなわち、バイポーラトランジスタQ2のベース電流IBE2をバイポーラトランジスタQ3のベース電流I’BC3より小さく設定する。
Hereinafter, the eighth embodiment of the present invention will be described in detail with reference to FIG. However, there is a precondition of the following equation (5).
I ′ BC3 > I CE2 / hfe2 (5)
I ′ BC3 > I BE2 Formula (6)
Formula (5) means Formula (6). That is, the base current I BE2 of the bipolar transistor Q2 is set smaller than the base current I ′ BC3 of the bipolar transistor Q3.
 バイポーラトランジスタQ2のコレクタ電流ICE2は、ICE2=V3/r1であり、バイポーラトランジスタQ2の電流増幅率がhfe2のとき、バイポーラトランジスタQ2のベース電流IBE2は、IBE2=V3/r1/hfe2となる。
バイポーラトランジスタQ3のベース電流I’BC3と、バイポーラトランジスタQ2のベース電流IBE2の和、I’BC3+IBE2は、V3/r2で制限されるため、
I’BC3+IBE2=V3/r2となる。(I’BC3+V3/r1/hfe2)=V3/r2・・・式(7)となる。
The collector current I CE2 of the bipolar transistor Q2 is I CE2 = V3 / r1, and when the current amplification factor of the bipolar transistor Q2 is hfe2, the base current I BE2 of the bipolar transistor Q2 is I BE2 = V3 / r1 / hfe2. Become.
Since the sum of the base current I ′ BC3 of the bipolar transistor Q3 and the base current I BE2 of the bipolar transistor Q2, I ′ BC3 + I BE2 is limited by V3 / r2,
I ′ BC3 + I BE2 = V3 / r2. (I ′ BC3 + V3 / r1 / hfe2) = V3 / r2 (7)
ただし、I’BC3は、バイポーラトランジスタQ3のエミッタE開放時のバイポーラトランジスタQ3のベース電流。V”BC3は、バイポーラトランジスタQ3のエミッタE開放時のバイポーラトランジスタQ3のコレクタ電位に対するベース電位。 However, I ′ BC3 is the base current of the bipolar transistor Q3 when the emitter E of the bipolar transistor Q3 is opened. V ″ BC3 is a base potential with respect to the collector potential of the bipolar transistor Q3 when the emitter E of the bipolar transistor Q3 is opened.
条件:A8
Ve2=Vc3(V1=V2の状態。バイポーラトランジスタQ2のエミッタ電位=バイポーラトランジスタQ3のコレクタ電位。FETQ1のソース電位=ドレイン電位。)
バイポーラトランジスタQ3のベース順方向電圧V”BC3が約0.6V(標準的PN接合ダイオードの順方向電圧)であるので、この電圧より低いバイポーラトランジスタQ2のベース順方向電圧VBE2において、バイポーラトランジスタQ3と共通ベース電位を有するバイポーラトランジスタQ2のベース電位によりバイポーラトランジスタQ2は確実に導通する。
Condition: A8
Ve2 = Vc3 (V1 = V2 state. Emitter potential of bipolar transistor Q2 = collector potential of bipolar transistor Q3. Source potential of FETQ1 = drain potential)
Since the base forward voltage V ″ BC3 of the bipolar transistor Q3 is about 0.6V (standard PN junction diode forward voltage), the bipolar transistor Q3 has a base forward voltage V BE2 of the bipolar transistor Q2 lower than this voltage. The bipolar transistor Q2 is reliably turned on by the base potential of the bipolar transistor Q2 having a common base potential.
前提条件、I’BC3>IBE2・・・式(6)から、第1の実施の形態における図1の説明を援用し、V”BC3>V”’BC3=V”BE2>VBE2であり、バイポーラトランジスタQ2のエミッタ電位=バイポーラトランジスタQ3のコレクタ電位であれば(FETQ1のソース電位=ドレイン電位)、ベース電位を共通とするバイポーラトランジスタQ2とバイポーラトランジスタQ3において、このときのバイポーラトランジスタQ2のベース電位V” BE2は、バイポーラトランジスタQ2のベース電流IBE2=ICE2/hfe2で定められたバイポーラトランジスタQ2のベース順方向電圧VBE2より高い(V” BE2>VBE2)。
 バイポーラトランジスタQ2のベース順方向電圧VBE2と、バイポーラトランジスタQ3のベース順方向電圧V”BC3とで合成された電位(V” BE2=V”’BC3)となり、バイポーラトランジスタQ2を充分導通とするためのベース順方向電圧を得る。
From the precondition, I ′ BC3 > I BE2 (6), the explanation of FIG. 1 in the first embodiment is used, and V ″ BC3 > V ″ ′ BC3 = V ″ BE2 > VBE2 . If the emitter potential of the bipolar transistor Q2 = the collector potential of the bipolar transistor Q3 (the source potential of the FET Q1 = the drain potential), in the bipolar transistor Q2 and the bipolar transistor Q3 having the same base potential, the base of the bipolar transistor Q2 at this time The potential V ″ BE2 is higher than the base forward voltage V BE2 of the bipolar transistor Q2 defined by the base current I BE2 = I CE2 / hfe2 of the bipolar transistor Q2 (V ″ BE2 > V BE2 ).
A potential (V ″ BE2 = V ″ ′ BC3 ) synthesized by the base forward voltage V BE2 of the bipolar transistor Q2 and the base forward voltage V ″ BC3 of the bipolar transistor Q3 is set so that the bipolar transistor Q2 becomes sufficiently conductive. To obtain the base forward voltage.
ただし、V”’BC3、V”BE2は、ベースBを共通電位とするバイポーラトランジスタそれぞれQ3、Q2の条件A8におけるベース電位である。すなわち、電位V”BC3とVBE2が均衡した電位である。
バイポーラトランジスタQ2とバイポーラトランジスタQ3のベースは接続されているため、両ベース電位はV”’BC3=V”BE2となるよう、V”BC3>V”’BC3=V”BE2>VBE2で均衡する。
However, V ″ ′ BC3 and V ″ BE2 are base potentials in the condition A8 of the bipolar transistors Q3 and Q2 having the base B as a common potential, respectively. That is, the potentials V ″ BC3 and V BE2 are balanced potentials.
Since the base of the bipolar transistor Q2 and the bipolar transistor Q3 is connected, both the base potential V " 'BC3 = V" BE2 and so as, V "BC3>V"' balanced at BC3 = V "BE2> V BE2 .
このように、バイポーラトランジスタQ2は確実に導通するため、バイポーラトランジスタQ2のコレクタC電位は低下し略0Vであり、この電位が印加されるFETQ1のゲートにおいて、FETQ1は非導通である。このため、FETQ1のドレインDから、ソースSに電流は流れず、ダイオードの逆方向電流阻止の機能を有する。 Thus, since the bipolar transistor Q2 is surely turned on, the collector C potential of the bipolar transistor Q2 is reduced to about 0 V, and the FET Q1 is non-conductive at the gate of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
条件:B8
Ve2<Vc3’(V1<V2の状態。バイポーラトランジスタQ2のエミッタ電位<バイポーラトランジスタQ3のコレクタ電位。FETQ1のソース電位<ドレイン電位。)では、バイポーラトランジスタQ2が確実に導通する。
Ve2<Vc3’を別の表現をすると、Vc2<Vc3’は、Ve2<Vc3+Vαと表現できる。
上記条件(A8)の説明に加え、バイポーラトランジスタQ3のコレクタCの電位がVc3からVα上昇すると、バイポーラトランジスタQ3は、定められた自己のコレクタC、ベースB間電位差を維持するため、ベース電位がVα上昇することになる。このため、バイポーラトランジスタQ3のベースBと同電位であるバイポーラトランジスタQ2のベースB電位は、さらに上昇し、バイポーラトランジスタQ2は確実に導通する。
Condition: B8
When Ve2 <Vc3 ′ (the state of V1 <V2, the emitter potential of the bipolar transistor Q2 <the collector potential of the bipolar transistor Q3. The source potential of the FET Q1 <the drain potential), the bipolar transistor Q2 is surely turned on.
If Ve2 <Vc3 ′ is expressed in another way, Vc2 <Vc3 ′ can be expressed as Ve2 <Vc3 + Vα.
In addition to the description of the above condition (A8), when the potential of the collector C of the bipolar transistor Q3 rises from Vc3 to Vα, the bipolar transistor Q3 maintains the determined potential difference between its own collector C and base B. Vα will rise. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 further increases, and the bipolar transistor Q2 is surely turned on.
したがって、バイポーラトランジスタQ2のコレクタCの電位は低下し略0Vであり、この電位が印加されるFETQ1のゲートにおいて、FETQ1は非導通である。このため、FETQ1のドレインDから、ソースSに電流は流れず、ダイオードの逆方向電流阻止の機能を有する。 Therefore, the potential of the collector C of the bipolar transistor Q2 decreases to approximately 0 V, and the FET Q1 is non-conductive at the gate of the FET Q1 to which this potential is applied. For this reason, no current flows from the drain D of the FET Q1 to the source S, and it has a function of blocking the reverse current of the diode.
条件:C8
Ve2>Vc3”
これは、V1>V2の状態であり、バイポーラトランジスタQ2のエミッタ電位>バイポーラトランジスタQ3のコレクタ電位、FETQ1のソース電位>ドレイン電位である。このとき、バイポーラトランジスタQ2が非導通となる。
Ve2>Vc3”を別の表現をすると、Ve2>Vc3”は、Ve2>Vc3-Vβと表現できる。
上記条件A8の説明に加え、バイポーラトランジスタQ3のコレクタCの電位がVc3からVβ低下すると、定められた自己のコレクタC、ベースB間電位を維持するため、ベース電位がVβ低下することになる。このため、バイポーラトランジスタQ3のベースBと同電位であるバイポーラトランジスタQ2のベースB電位は低下し、バイポーラトランジスタQ2は非導通となる。
Condition: C8
Ve2> Vc3 "
This is the state of V1> V2, where the emitter potential of the bipolar transistor Q2> the collector potential of the bipolar transistor Q3 and the source potential of the FET Q1> the drain potential. At this time, bipolar transistor Q2 becomes non-conductive.
If Ve2> Vc3 ″ is expressed in another way, Ve2> Vc3 ″ can be expressed as Ve2> Vc3-Vβ.
In addition to the description of the above condition A8, when the potential of the collector C of the bipolar transistor Q3 is lowered by Vβ from Vc3, the base potential is lowered by Vβ in order to maintain the predetermined potential between the collector C and base B. For this reason, the base B potential of the bipolar transistor Q2 which is the same potential as the base B of the bipolar transistor Q3 decreases, and the bipolar transistor Q2 becomes non-conductive.
したがって、バイポーラトランジスタQ2のコレクタC電位は上昇し、端子T3に印加される直流電源電位となり、この電位が印加されるFETQ1のゲートにおいて、FETQ1は導通となる。 Therefore, the collector C potential of the bipolar transistor Q2 rises and becomes the DC power supply potential applied to the terminal T3, and the FET Q1 becomes conductive at the gate of the FET Q1 to which this potential is applied.
(9)第9の実施の形態
(9-1)回路構成
図9は、本発明による第9の実施の形態である整流回路及び整流回路における整流電流路を構成する第1半導体素子であるNチャネルFETQ1を制御する制御回路を示す回路構成図である。制御回路は、図9において破線で囲まれた回路である。
第9の実施の形態における図9の回路は、第6の実施の形態における図6の回路に第4半導体素子であるNPNバイポーラトランジスタQ4、第5半導体素子であるPNPバイポーラトランジスタQ5によるエミッタフォロア電流増幅回路を追加したものである。
したがって、図9において、第6の実施の形態である図6の回路に共通する回路の各素子には図6の符号と同一の符号を付し、図6の回路構成の説明を援用し、重複する説明を割愛する。
(9) Ninth Embodiment (9-1) Circuit Configuration FIG. 9 shows a rectifier circuit according to a ninth embodiment of the present invention and N which is a first semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls channel FETQ1. The control circuit is a circuit surrounded by a broken line in FIG.
The circuit of FIG. 9 in the ninth embodiment is different from the circuit of FIG. 6 in the sixth embodiment in that an emitter follower current is generated by an NPN bipolar transistor Q4 as a fourth semiconductor element and a PNP bipolar transistor Q5 as a fifth semiconductor element. An amplifier circuit is added.
Therefore, in FIG. 9, the same reference numerals as those in FIG. 6 are given to the elements of the circuit common to the circuit in FIG. 6 as the sixth embodiment, and the description of the circuit configuration in FIG. Omit duplicate explanations.
図9において、バイポーラトランジスタQ4及びQ5のベースは、バイポーラトランジスタQ2のコレクタCに接続され、バイポーラトランジスタQ4とバイポーラトランジスタQ5のエミッタは、FETQ1のゲートGに接続され、バイポーラトランジスタQ4のコレクタは端子T3に、バイポーラトランジスタQ5のコレクタは端子T1に接続されている。 In FIG. 9, the bases of the bipolar transistors Q4 and Q5 are connected to the collector C of the bipolar transistor Q2, the emitters of the bipolar transistors Q4 and Q5 are connected to the gate G of the FET Q1, and the collector of the bipolar transistor Q4 is connected to the terminal T3. In addition, the collector of the bipolar transistor Q5 is connected to the terminal T1.
(9)第9の実施の形態
(9-2)回路動作
図9を参照して本発明の第5の実施の形態である整流回路及び制御回路の回路動作を説明する。
図9は、第6の実施の形態である図6にエミッタフォロワ電流増幅回路が付加され、FETQ1のゲート容量を充電するに充分な電流を供給することができる。
バイポーラトランジスタQ2のコレクタ電位が高い(端子T3の電位)とき、バイポーラトランジスタQ4が導通し、バイポーラトランジスタQ5が非導通で、FETQ1を導通させ、バイポーラトランジスタQ2のコレクタ電位が低い(端子T1の電位)とき、バイポーラトランジスタQ4は非導通で、バイポーラトランジスタQ5が導通となり、FETQ1を非導通とさせる。
(9) Ninth Embodiment (9-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the fifth embodiment of the present invention will be described with reference to FIG.
In FIG. 9, an emitter follower current amplifier circuit is added to FIG. 6 which is the sixth embodiment, and a current sufficient to charge the gate capacitance of the FET Q1 can be supplied.
When the collector potential of the bipolar transistor Q2 is high (the potential at the terminal T3), the bipolar transistor Q4 is turned on, the bipolar transistor Q5 is turned off, the FET Q1 is turned on, and the collector potential of the bipolar transistor Q2 is low (the potential at the terminal T1). At this time, bipolar transistor Q4 is non-conductive, bipolar transistor Q5 is conductive, and FET Q1 is non-conductive.
 上記以外は第6の実施の形態である図6の回路動作の説明のとおりであり、図9の説明は図6の説明を援用し、重複する説明を割愛する。 Other than the above, the circuit operation of FIG. 6 according to the sixth embodiment is described, and the description of FIG. 9 uses the description of FIG. 6 and omits the overlapping description.
本発明には、第1から第9の実施の形態が存在し、図1から図9が存在する。本発明は、図1~図9のそれぞれの特徴的部分をそれぞれ組み合わせて実現可能である。
すなわち、インダクターLの有無、バイポーラトランジスタQ3のベースBとエミッタEとの接続又は開放、バイポーラトランジスタQ2のコレクタ接地又はエミッタ接地の選択の組み合わせである。
In the present invention, first to ninth embodiments exist, and FIGS. 1 to 9 exist. The present invention can be realized by combining the respective characteristic portions shown in FIGS.
That is, the combination of the presence or absence of the inductor L, the connection or opening of the base B and the emitter E of the bipolar transistor Q3, and the selection of the collector ground or emitter ground of the bipolar transistor Q2.
 Q1~Q5    半導体素子
 R1~R3    抵抗素子
 D        整流素子
 C        容量素子
 LED      発光素子
 PD1~PDn  受光素子
 RD       定電流素子
 T1、T2    端子
 T1’、T2’  端子
Q1 to Q5 Semiconductor element R1 to R3 Resistance element D Rectifier element C Capacitance element LED Light emitting element PD1 to PDn Light receiving element RD Constant current element T1, T2 terminals T1 ', T2' terminals

Claims (14)

  1. 第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
    第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
    第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
    第1抵抗素子と、第2抵抗素子と、誘導性素子と、を備え、
    前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
    前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端には前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、
    前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、
    前記第1半導体素子の一端と前記誘導性素子の他端間を電流路とすることを特徴とする整流回路。
    A first semiconductor element having a first control end and having one end and the other end of a current path;
    A second semiconductor element having a second control end and having one end and the other end of a current path;
    A third semiconductor element having a third control end and having one end and the other end of a current path;
    A first resistance element, a second resistance element, and an inductive element;
    An external bias potential is applied to the second control end and the third control end by the second resistance element,
    A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow,
    The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element. Configured to be transmitted to the other end of the third semiconductor element via the other end,
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted,
    A rectifier circuit comprising a current path between one end of the first semiconductor element and the other end of the inductive element.
  2. 第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
    第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
    第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
    第1抵抗素子と、第2抵抗素子と、を備え、
    前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
    前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端には前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、
    前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、
    前記第1半導体素子の一端と該第1半導体素子の他端間を電流路とすることを特徴とする整流回路。
    A first semiconductor element having a first control end and having one end and the other end of a current path;
    A second semiconductor element having a second control end and having one end and the other end of a current path;
    A third semiconductor element having a third control end and having one end and the other end of a current path;
    A first resistance element and a second resistance element;
    An external bias potential is applied to the second control end and the third control end by the second resistance element,
    A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow,
    A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element. Configured to
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted,
    A rectifier circuit comprising a current path between one end of the first semiconductor element and the other end of the first semiconductor element.
  3. 第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
    第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
    第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
    第1抵抗素子と、第2抵抗素子と、誘導性素子と、を備え、
    前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
    前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、
    前記第3半導体素子の一端は開放され、
    前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、
    前記第1半導体素子の一端と前記誘導性素子の他端間を電流路とすることを特徴とする整流回路。
    A first semiconductor element having a first control end and having one end and the other end of a current path;
    A second semiconductor element having a second control end and having one end and the other end of a current path;
    A third semiconductor element having a third control end and having one end and the other end of a current path;
    A first resistance element, a second resistance element, and an inductive element;
    An external bias potential is applied to the second control end and the third control end by the second resistance element,
    A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and
    One end of the third semiconductor element is opened,
    The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element. Configured to be transmitted to the other end of the third semiconductor element via the other end,
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted,
    A rectifier circuit comprising a current path between one end of the first semiconductor element and the other end of the inductive element.
  4. 第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
    第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
    第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
    第1抵抗素子と、第2抵抗素子と、を備え、
    前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
    前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、
    前記第3半導体素子の一端は開放され、
    前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、
    前記第1半導体素子の一端と該第1半導体素子の他端間を電流路とすることを特徴とする整流回路。
    A first semiconductor element having a first control end and having one end and the other end of a current path;
    A second semiconductor element having a second control end and having one end and the other end of a current path;
    A third semiconductor element having a third control end and having one end and the other end of a current path;
    A first resistance element and a second resistance element;
    An external bias potential is applied to the second control end and the third control end by the second resistance element,
    A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and
    One end of the third semiconductor element is opened,
    A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element. Configured to
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted,
    A rectifier circuit comprising a current path between one end of the first semiconductor element and the other end of the first semiconductor element.
  5. 第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
    第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
    第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
    第1抵抗素子と、第2抵抗素子と、誘導性素子と、を備え、
    前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
    前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端には前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、
    前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、前記第1半導体素子の一端と前記誘導性素子の他端間を電流路とする整流回路の一部を構成する制御回路であって、
    該制御回路は、前記第2制御端及び前記第3制御端に、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、前記第2半導体素子の電流路の一端、他端間に前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端、他端間に前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記誘導性素子の他端の電位は前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位を低電位として出力し、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位を高電位として出力することを特徴とする制御回路。
    A first semiconductor element having a first control end and having one end and the other end of a current path;
    A second semiconductor element having a second control end and having one end and the other end of a current path;
    A third semiconductor element having a third control end and having one end and the other end of a current path;
    A first resistance element, a second resistance element, and an inductive element;
    An external bias potential is applied to the second control end and the third control end by the second resistance element,
    A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow,
    The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element. Configured to be transmitted to the other end of the third semiconductor element via the other end,
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. Part of the rectifier circuit in which the potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and the current path is between one end of the first semiconductor element and the other end of the inductive element. A control circuit comprising:
    The control circuit is configured such that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and between the one end and the other end of the current path of the second semiconductor element. A current supplied by an external DC power source flows between the one end and the other end of the current path of the third semiconductor element via the first resistance element. 2 is configured to be transmitted to one end of the first semiconductor element, and is configured to be transmitted to the other end of the third semiconductor element.
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conducted, and the potential at one end of the second semiconductor element is output as a low potential,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is increased. A control circuit which outputs as a potential.
  6. 第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
    第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
    第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
    第1抵抗素子と、第2抵抗素子と、を備え、
    前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
    前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端には前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、
    前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、前記第1半導体素子の一端と該第1半導体素子の他端間を電流路とする整流回路の一部を構成する制御回路であって、
    該制御回路は、前記第2制御端及び前記第3制御端に前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、前記第2半導体素子の電流路の一端に前記第1抵抗素子を介して、前記第3半導体素子の電流路の一端に前記第2抵抗素子を介して、外部の直流電源が供給する電流が流れるべく構成され、前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は前記第3半導体素子の他端に伝達されるべく構成されることを特徴とする制御回路。
    A first semiconductor element having a first control end and having one end and the other end of a current path;
    A second semiconductor element having a second control end and having one end and the other end of a current path;
    A third semiconductor element having a third control end and having one end and the other end of a current path;
    A first resistance element and a second resistance element;
    An external bias potential is applied to the second control end and the third control end by the second resistance element,
    A current supplied from an external DC power source to one end of the current path of the second semiconductor element via the first resistance element and to one end of the current path of the third semiconductor element via the second resistance element Is configured to flow,
    A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element. Configured to
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and one of the rectifier circuits having a current path between one end of the first semiconductor element and the other end of the first semiconductor element. A control circuit constituting a unit,
    The control circuit is configured so that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of a current path of the second semiconductor element. A current supplied from an external DC power source flows through one end of the current path of the third semiconductor element via the second resistance element via the element, and the potential at the other end of the second semiconductor element is A control circuit configured to be transmitted to one end of the first semiconductor element, and configured to transmit a potential of the other end of the first semiconductor element to the other end of the third semiconductor element.
  7. 第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
    第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
    第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
    第1抵抗素子と、第2抵抗素子と、誘導性素子と、を備え、
    前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
    前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、
    前記第3半導体素子の一端は開放され、
    前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、前記第1半導体素子の一端と前記誘導性素子の他端間を電流路とする整流回路の一部を構成する制御回路であって、
    該制御回路は、前記第2制御端及び前記第3制御端に前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、前記第2半導体素子の電流路の一端に前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、前記第3半導体素子の一端は開放され、前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記誘導性素子の一端から該誘導性素子の他端を介して前記第3半導体素子の他端に伝達されるべく構成されることを特徴とする制御回路。
    A first semiconductor element having a first control end and having one end and the other end of a current path;
    A second semiconductor element having a second control end and having one end and the other end of a current path;
    A third semiconductor element having a third control end and having one end and the other end of a current path;
    A first resistance element, a second resistance element, and an inductive element;
    An external bias potential is applied to the second control end and the third control end by the second resistance element,
    A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and
    One end of the third semiconductor element is opened,
    The potential of the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and the potential of the other end of the first semiconductor element is transmitted from one end of the inductive element to the inductive element. Configured to be transmitted to the other end of the third semiconductor element via the other end,
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. Part of the rectifier circuit in which the potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and the current path is between one end of the first semiconductor element and the other end of the inductive element. A control circuit comprising:
    The control circuit is configured so that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of a current path of the second semiconductor element. A current supplied from an external DC power source is configured to flow through the element, one end of the third semiconductor element is opened, and the potential at the other end of the second semiconductor element is transmitted to one end of the first semiconductor element. And the potential at the other end of the first semiconductor element is transmitted from one end of the inductive element to the other end of the third semiconductor element via the other end of the inductive element. A control circuit characterized by that.
  8. 第1制御端を有し電流路の一端及び他端を有する第1半導体素子と、
    第2制御端を有し電流路の一端及び他端を有する第2半導体素子と、
    第3制御端を有し電流路の一端及び他端を有する第3半導体素子と、
    第1抵抗素子と、第2抵抗素子と、を備え、
    前記第2制御端及び前記第3制御端には、前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、
    前記第2半導体素子の電流路の一端には前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、
    前記第3半導体素子の一端は開放され、
    前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は、前記第3半導体素子の他端に伝達されるべく構成され、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位と同電位であるか又は該第3半導体素子の他端の電位が該第2半導体素子の他端の電位より高い場合、該第2半導体素子の電流路は導通し、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は低下し該第1半導体素子の電流路は非導通であり、
    前記第3半導体素子の他端の電位が前記第2半導体素子の他端の電位より低下したとき、該第2半導体素子の電流路は非導通となり、該第2半導体素子の一端の電位が伝達される前記第1制御端の電位は上昇し該第1半導体素子の電流路は導通し、前記第1半導体素子の一端と該第1半導体素子の他端間を電流路とする整流回路の一部を構成する制御回路であって、
    該制御回路は、前記第2制御端及び前記第3制御端に前記第2抵抗素子により外部のバイアス電位が印加されるべく構成され、前記第2半導体素子の電流路の一端に前記第1抵抗素子を介して外部の直流電源が供給する電流が流れるべく構成され、前記第3半導体素子の一端は開放され、前記第2半導体素子の他端の電位は前記第1半導体素子の一端に伝達されるべく構成され、前記第1半導体素子の他端の電位は前記第3半導体素子の他端に伝達されるべく構成されることを特徴とする制御回路。
    A first semiconductor element having a first control end and having one end and the other end of a current path;
    A second semiconductor element having a second control end and having one end and the other end of a current path;
    A third semiconductor element having a third control end and having one end and the other end of a current path;
    A first resistance element and a second resistance element;
    An external bias potential is applied to the second control end and the third control end by the second resistance element,
    A current supplied from an external DC power source flows through one end of the current path of the second semiconductor element through the first resistance element, and
    One end of the third semiconductor element is opened,
    A potential at the other end of the second semiconductor element is configured to be transmitted to one end of the first semiconductor element, and a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element. Configured to
    The potential of the other end of the third semiconductor element is the same as the potential of the other end of the second semiconductor element, or the potential of the other end of the third semiconductor element is greater than the potential of the other end of the second semiconductor element. When it is high, the current path of the second semiconductor element is conductive, the potential of the first control terminal to which the potential of one end of the second semiconductor element is transmitted decreases, and the current path of the first semiconductor element is non-conductive. Yes,
    When the potential at the other end of the third semiconductor element is lower than the potential at the other end of the second semiconductor element, the current path of the second semiconductor element becomes non-conductive and the potential at one end of the second semiconductor element is transmitted. The potential of the first control terminal is increased, the current path of the first semiconductor element is conducted, and one of the rectifier circuits having a current path between one end of the first semiconductor element and the other end of the first semiconductor element. A control circuit constituting a unit,
    The control circuit is configured so that an external bias potential is applied to the second control terminal and the third control terminal by the second resistance element, and the first resistance is connected to one end of a current path of the second semiconductor element. A current supplied from an external DC power source is configured to flow through the element, one end of the third semiconductor element is opened, and the potential at the other end of the second semiconductor element is transmitted to one end of the first semiconductor element. And a potential at the other end of the first semiconductor element is transmitted to the other end of the third semiconductor element.
  9. 前記第2半導体素子の一端は、バイポーラトランジスタのコレクタであり、該第2半導体素子他端は、バイポーラトランジスタのエミッタであり、前記第3半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第3半導体素子の他端は、バイポーラトランジスタのコレクタであることを特徴とする請求項1~4のいずれかに記載の整流回路。 One end of the second semiconductor element is a collector of the bipolar transistor, the other end of the second semiconductor element is an emitter of the bipolar transistor, and one end of the third semiconductor element is an emitter of the bipolar transistor, The rectifier circuit according to any one of claims 1 to 4, wherein the other end of the three semiconductor elements is a collector of a bipolar transistor.
  10. 前記第2半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第2半導体素子他端は、バイポーラトランジスタのコレクタであり、前記第3半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第3半導体素子の他端は、バイポーラトランジスタのコレクタであることを特徴とする請求項1~4のいずれかに記載の整流回路。 One end of the second semiconductor element is an emitter of a bipolar transistor, the other end of the second semiconductor element is a collector of the bipolar transistor, and one end of the third semiconductor element is an emitter of the bipolar transistor, The rectifier circuit according to any one of claims 1 to 4, wherein the other end of the three semiconductor elements is a collector of a bipolar transistor.
  11. 前記第2半導体素子の一端は、バイポーラトランジスタのコレクタであり、該第2半導体素子他端は、バイポーラトランジスタのエミッタであり、前記第3半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第3半導体素子の他端は、バイポーラトランジスタのコレクタであることを特徴とする請求項5~8のいずれかに記載の制御回路。 One end of the second semiconductor element is a collector of the bipolar transistor, the other end of the second semiconductor element is an emitter of the bipolar transistor, and one end of the third semiconductor element is an emitter of the bipolar transistor, 9. The control circuit according to claim 5, wherein the other end of the three semiconductor elements is a collector of a bipolar transistor.
  12. 前記第2半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第2半導体素子他端は、バイポーラトランジスタのコレクタであり、前記第3半導体素子の一端は、バイポーラトランジスタのエミッタであり、該第3半導体素子の他端は、バイポーラトランジスタのコレクタであることを特徴とする請求項5~8のいずれかに記載の制御回路。 One end of the second semiconductor element is an emitter of a bipolar transistor, the other end of the second semiconductor element is a collector of the bipolar transistor, and one end of the third semiconductor element is an emitter of the bipolar transistor, 9. The control circuit according to claim 5, wherein the other end of the three semiconductor elements is a collector of a bipolar transistor.
  13. 請求項1~4、9、10のいずれかに記載の整流回路を内蔵したことを特徴とする集積回路素子。 An integrated circuit element comprising the rectifier circuit according to any one of claims 1 to 4, 9, and 10.
  14. 請求項5~8、11、12のいずれかに記載の制御回路を内蔵したことを特徴とする集積回路素子。 An integrated circuit device comprising the control circuit according to any one of claims 5 to 8, 11, and 12.
PCT/JP2010/000138 2009-01-13 2010-01-13 Rectification circuit, control circuit for said rectification circuit, and integrated circuit element containing said circuits WO2010082480A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2009004575 2009-01-13
JP2009-004575 2009-01-13
JP2010004088A JP5547496B2 (en) 2009-01-13 2010-01-12 Rectifier circuit and control circuit for the rectifier circuit
JP2010-004088 2010-01-12

Publications (1)

Publication Number Publication Date
WO2010082480A1 true WO2010082480A1 (en) 2010-07-22

Family

ID=42339732

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/000138 WO2010082480A1 (en) 2009-01-13 2010-01-13 Rectification circuit, control circuit for said rectification circuit, and integrated circuit element containing said circuits

Country Status (2)

Country Link
JP (1) JP5547496B2 (en)
WO (1) WO2010082480A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015170479A1 (en) * 2014-05-09 2015-11-12 パナソニックIpマネジメント株式会社 Rectifier circuit, and rectifier and wireless power supply device equipped with same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7496083B2 (en) 2020-01-31 2024-06-06 株式会社新陽社 Rectification control circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006050762A (en) * 2004-08-04 2006-02-16 Nidek Co Ltd Rectifying circuit and vision recovery assisting device provided therewith
JP2006087215A (en) * 2004-09-16 2006-03-30 Fuji Electric Holdings Co Ltd Switching regulator and its drive control method
JP2007215259A (en) * 2006-02-07 2007-08-23 Matsushita Electric Ind Co Ltd Drive circuit and switching regulator using the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006050762A (en) * 2004-08-04 2006-02-16 Nidek Co Ltd Rectifying circuit and vision recovery assisting device provided therewith
JP2006087215A (en) * 2004-09-16 2006-03-30 Fuji Electric Holdings Co Ltd Switching regulator and its drive control method
JP2007215259A (en) * 2006-02-07 2007-08-23 Matsushita Electric Ind Co Ltd Drive circuit and switching regulator using the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015170479A1 (en) * 2014-05-09 2015-11-12 パナソニックIpマネジメント株式会社 Rectifier circuit, and rectifier and wireless power supply device equipped with same
CN106464152A (en) * 2014-05-09 2017-02-22 松下知识产权经营株式会社 Rectifier circuit, and rectifier and wireless power supply device equipped with same
JPWO2015170479A1 (en) * 2014-05-09 2017-04-20 パナソニックIpマネジメント株式会社 Rectifier circuit, and rectifier and non-contact power supply device including the same
US10056787B2 (en) 2014-05-09 2018-08-21 Panasonic Intellectual Property Management Co., Ltd. Rectifier circuit, and contactless power supply device
CN106464152B (en) * 2014-05-09 2019-07-26 松下知识产权经营株式会社 Rectification circuit and contactless power supply device

Also Published As

Publication number Publication date
JP5547496B2 (en) 2014-07-16
JP2010187530A (en) 2010-08-26

Similar Documents

Publication Publication Date Title
TWI431898B (en) Power switching circuit
JP5354625B2 (en) Semiconductor device
US9118322B2 (en) Low leakage dynamic bi-directional body-snatching (LLDBBS) scheme for high speed analog switches
US8723564B2 (en) Driving circuit
JP5733330B2 (en) Driving circuit
KR101354232B1 (en) Amplifier system for a power converter
US9438032B2 (en) Semiconductor device
JP2019537417A (en) Bootstrap capacitor overvoltage management circuit for power converter based on GaN transistor
TWI509964B (en) Driver and driving control method for power converter
US8605399B2 (en) Load driving device
JP2014207412A (en) ESD protection circuit
US9374074B2 (en) Voltage selection circuit and semiconductor integrated circuit device having the same
US11209464B2 (en) Current detection circuit and power converter
JP4285036B2 (en) Power supply backflow prevention circuit
US8729927B2 (en) Cascode drive circuitry
JP5547496B2 (en) Rectifier circuit and control circuit for the rectifier circuit
US7642502B2 (en) Photo relay having an insulated gate field effect transistor with variable impedance
CN110545032B (en) Power transistor module and voltage conversion circuit integrating starting function
JP7002423B2 (en) Switch circuit
EP3736984A1 (en) A driving circuit and an under-voltage lockout circuit of a power circuit
JP5524717B2 (en) Rectifier circuit and control circuit for the rectifier circuit
JP5632179B2 (en) Rectifier circuit, control circuit for the rectifier circuit, and integrated circuit element incorporating these circuits
JP7055714B2 (en) Semiconductor device
CN111010164A (en) Output buffer circuit based on GaAs technology
TWI543528B (en) Bi-direction switch

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10731150

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 20.09.2011)

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 18/10/2011)

122 Ep: pct application non-entry in european phase

Ref document number: 10731150

Country of ref document: EP

Kind code of ref document: A1