TW201117357A - Semiconductor storage device and method for manufacturing same - Google Patents

Semiconductor storage device and method for manufacturing same Download PDF

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Publication number
TW201117357A
TW201117357A TW099116130A TW99116130A TW201117357A TW 201117357 A TW201117357 A TW 201117357A TW 099116130 A TW099116130 A TW 099116130A TW 99116130 A TW99116130 A TW 99116130A TW 201117357 A TW201117357 A TW 201117357A
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Taiwan
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resistance
memory cell
voltage
state
resistance state
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TW099116130A
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Chinese (zh)
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TWI416708B (en
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Yoshitaka Sasago
Masaharu Kinoshita
Norikatsu Takaura
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Hitachi Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Abstract

High reliability of a nonvolatile semiconductor storage device provided with the array of a memory cell in which a resistance change element and a selection element, such as a diode or a transistor, are connected is facilitated. The resistance change element of a memory cell provided with a selection element the performance of which is insufficient because of a large leakage current is brought into a state in which the resistance change element has a high resistance value not reaching the power required for rewriting even if a voltage used for recording of data is applied to the memory cell. As a result, malfunction of the device caused by a leakage current in a defective selection element is suppressed.

Description

201117357 六、發明說明 【發明所屬之技術領域】 本發明關於半導體記億裝置及其製造方法，特別關於 實現可以電氣改寫之非揮發性半導體記憶裝置之高信賴性 之技術。 【先前技術】 近年來，於記錄材料使用硫屬化合物材料之相變化記 憶體（專利文獻1)之硏究盛行。相變化記憶體之記憶體構 造，係以金屬電極挾持記錄材料者。相變化記憶體，係利 用電極間之記錄材料具有不同之電阻狀態而記憶資訊的電 阻變化型記憶體。 相變化記憶體，係利用Ge2Sb2Te5等之相變化材料之 電阻値在非晶質狀態與結晶狀態不同來記憶資訊。非晶質 狀態之電阻高、結晶狀態之電阻低。因此，讀出時係對元 件兩端供給電位差，測定流入元件之電流，藉由判斷元件 之高電阻狀態/低電阻狀態而進行。 相變化記憶體係藉由電流產生之焦耳熱使相變化膜之 電阻變化爲不同狀態而進行資料之改寫。變化爲重置動 作、亦即商電阻之非晶質狀態的動作，係藉由在短時間流 入大電流使相變化材料溶解之後，急速減少電流、急速冷 卻而進行。另外，變化爲設定動作、亦即低電阻之結晶狀 態的動作，係藉由長時間流入充分之電流使保持於相變化 材料之結晶化溫度而進行。 -5- 201117357 彼等電阻變化型元件，在集積時係將二極體或電晶體 等選擇元件附加於各個電阻變化型元件之構造予以使用。 例如將二極體與電阻變化型元件串聯連接組合之記憶格配 置成爲交叉點（cross point)型，而可以形成高密度之記憶 格陣列。二極體或電晶體，係由記憶格陣列之中選擇各個 記憶體而進行改寫或讀出。如專利文獻1將記憶格積層成 爲多層可以進展爲更大容量。 (專利文獻） 專利文獻1 :特開2005-2600 14號公報 【發明內容】 (發明所欲解決之課題） · 當和電阻變化型元件組合被使用之選擇元件存在有漏 電流大於容許値之不良元件時，即使電阻變化型元件處於 低電阻狀態下，記憶格陣列之電路亦會產生短路問題。亦 即，即使包含不良元件之記憶格處於非選擇情況下，改 寫、讀出時亦會流入大電流。寫入時，當包含不良元件之 記憶格之電阻變化型元件處於低電阻狀態時，基於記憶格 陣列之電路成爲短路狀態，而導致無法對記憶格陣列施加 所要之電壓，裝置有誤動作之可能。讀出時，依據不良元 件所連接之電阻變化型元件之爲低電阻狀態或高電阻狀 態，漏電流値會有大幅變動，對本來應被選擇之記憶格之 讀出電流之結果帶來大的變動，導致裝置之誤動作。 本發明目的在於提供具備相變化記憶格陣列之半導體 -6 - 201117357 記憶裝置，其可以抑制不良之選擇元件之漏電流所導致之 誤動作’可以促進半導體記憶裝置之高信賴化的技術。 本發明之目的及新特徵可由本說明書之記載及附加圖 面予以理解。 (用以解決課題的手段） 本發明係於具有相變化記憶格陣列之半導體記憶裝置 中，將具有不良選擇元件的記憶格之電阻變化型元件之電 阻値，設爲即使被進行改寫動作之情況下，亦不致於到達 產生改寫所要焦耳熱之高電阻値。如此則，可以使連接於 不良選擇元件之電阻變化型元件之電阻値保持爲高値，可 防止半導體記憶裝置之誤動作。 【實施方式】 以下參照圖面詳細說明本發明之實施形態。又，實施 形態說明之全圖中，具有同一機能之構件附加同一符號， 其重複說明被省略。 (第1實施形態） 圖1爲本發明第1實施形態之使用相變化記億體之半 導體記億裝置之全體圖。圖2爲記憶格陣列之一部分之立 體圖，表示相變化記憶體之電阻變化型元件與二極體串聯 連接的記憶格被配置爲交叉點型。圖4表示記憶格陣列之 讀出動作之電路圖。圖5表示寫入動作之電路圖。選擇元 201117357 件之二極體，可藉由N型雜質、P型雜質之分布（profile) 設計等之元件設計，而將逆向電壓之耐壓設爲例如4V。 本實施形態中，二極體之逆向電壓之耐壓例如爲4V。 如圖1所示，本發明第1實施形態之半導體記憶裝 置，係具備：I/O介面1001，其具備輸出入緩衝器用於進 行和外部間之資料之處理；記憶格陣列1 002 ;複數個電 源1003〜1007，用於供給不同之複數電壓；電壓選擇器 1 008，用於選擇來自電源1〇〇3〜1007之電壓：配線選擇 器1〇〇9，由記億格陣列1 002之位元線與字元線等之配線 之中，選擇電壓選擇器1 00 8之輸出之連接對象；及控制 部1 0 1 0，進行裝置全體之控制。於配線選擇器1 〇〇9，係 被連接具有感測放大器等之讀取部1011。另外，於記憶 格陣列1 002之中設置管理區域1 〇 1 2用於記憶裝置之各種 資訊。 由外部裝置對I/O介面1001有資料之輸入時，控制 部1010，係於電壓選擇器1 008進行資料寫入用之電壓之 選擇’於電源1003〜1 007之任一產生電壓脈衝，使用配 線選擇器1 009將電壓脈衝供給至記憶格陣列1〇〇2之特定 配線。如此則，可以將輸入至記憶格陣列之相變化記憶格 之資料予以寫入。 由外部裝置使資料之讀出信號被輸入至I/O介面 1001時，控制部1010，係於電壓選擇器1008進行資料讀 出用之電壓之選擇，於電源1〇〇3〜1007之任一產生電 壓’使用配線選擇器1 009將電壓供給至記憶格陣列1 0〇2 201117357 之特定配線。供給電壓之結果，讀出之電流，係於讀取部 1011被δ買取’此成爲gg憶資料之再生，介由控制部 1010、I/O介面1〇01使資料被供給至外部裝置。 圖2表示記憶格陣列10〇2之—部分擴大之立體圖。 如圖2所示，本發明第i實施形態之半導體記憶裝置，係 具備：形成於矽基板上方之複數字元線2;及設置於字元 線2之交叉方向的複數位元線3。於字元線2之上依序形 成P型多晶矽或p型半導體氧化物等之p型半導體層4, η型多晶矽或η型半導體氧化物等之η型半導體層5，電 阻變化型元件之下部電極8，電阻變化型元件之記錄層 6 ’電阻變化型元件之上部電極7，及位元線3。存在於下 部電極8與η型半導體層5之間之層1〇，係TiN等之阻 障金屬層、或Ti Si等之金屬矽化物層。另外，層10可爲 在相接於η型半導體層5之側具有金屬矽化物層，在相接 於下部電極8之側具有阻障金屬層的積層構造。 於Ρ型半導體層4與η型半導體層5，形成成爲選擇 元件的二極體。電阻變化型元件之記錄層6之材料可使用 例如相變化材料。相變化材料可爲例如包含Ge(鍺）、 Sb (錄）、Te(碲）之材料。 電阻變化型元件之記錄層6，可使用例如形成於下部 電極8上之包含金屬氧化物之層與包含相變化材料之層的 積層膜。其中，積層膜係指在下部電極8上形成包含金屬 氧化物之層，在包含金屬氧化物之層之上形成包含相變化 材料之層的具有層構造者，或者，相接於上部電極7存在 -9 - 201117357 有包含金屬氧化物之層，在包含金屬氧化物之層之下存在 包含相變化材料之層的具有層構造者。金屬氧化物可使用 例如Ta205 »藉由使用包含金屬氧化物之層與包含相變化 材料之層之積層膜作爲記錄層6，則和未設置包含金屬氧 化物之層的記錄層6比較，如後述說明，電阻變化型元件 之高電阻狀態就熱力學而言成爲較穩定。 以下稱一組串聯連接之電阻變化型元件與選擇元件爲 記億格。圖2所示記憶格陣列，係將記億格分別配置於複 數字元線2與複數位元線3之交叉點。選擇元件之二極體 係被連接於字元線2，電阻變化型元件之記錄層6係介由 上部電極7被連接於位元線3。 本發明之半導體記憶裝置，係利用記錄層6包含之 Ge2Sb2Te5等之相變化材料於非晶質狀態與結晶狀態之電 阻値不同來記憶資訊。於非晶質狀態電阻高、於結晶狀態 電阻低。因此，讀出係對電阻變化型元件兩端供給電位 差，測定流入元件之電流，判斷元件之高電阻狀態與低電 阻狀態來進行。 圖3表示本發明第1實施形態之相變化記憶體之改寫 動作時之記錄層之溫度變化。相變化材料由高電阻狀態之 非晶質狀態變化爲低電阻狀態之結晶狀態的動作’反之， 由低電阻狀態之結晶狀態變化爲高電阻狀態之非晶質狀態 的動作，係藉由對相變化材料供給圖3所示溫度變化而進 行。具體言之爲，非晶質狀態之相變化材料加熱至結晶化 溫度以上保持約1 (Γ6秒以上則可以設爲結晶狀態。另 -10- 201117357 外，結晶狀態之相變化材料加熱至融點以上之溫度設爲液 體狀態之後，急速冷卻則可以設爲非晶質狀態。 於本發明第1實施形態藉由電流產生之焦耳熱將記錄 層6之相變化材料加熱至融點以上之溫度，變化爲電阻不 同之狀態而進行資料之寫入。重置動作，變化爲高電阻之 非晶質狀態的動作，係藉由.短時間流入大電流使溶解之 後，急速減少電流、急速冷卻而進行。另外，設定動作， 亦即變化爲低電阻之結晶狀態的動作，係藉由長時間流入 保持於結晶化溫度之充分電流而進行。以下將藉由設定動 作設定記錄層成爲結晶狀態的記憶格之狀態，係被稱爲第 1狀態或設定狀態。另外，記憶格爲第1狀態時之，電阻 變化型元件之電阻狀態被稱爲第1電阻狀態。藉由重置動 作設定記錄層6成爲非晶質狀態的記憶格之狀態，係被稱 * 爲第2狀態或重置狀態。另外，記憶格爲第2狀態時之， 電阻變化型元件之電阻狀態被稱爲第2電阻狀態。 其中，第2狀態並非記錄層6之相變化材料全部設爲 非晶質化，而是一部分成爲非晶質化而成爲高電阻狀態。 因此，只要記錄層6之非晶質化之比例大於第2狀態，記 錄層6即可成爲較第2狀態爲高電阻之狀態。欲設爲更高 電阻化時，例如可對記憶格供給更高之電壓，設定記錄層 6之相變化材料成爲更高溫而實現。 如圖4所示，欲由記憶格陣列中選擇1格進行讀出 時，係對選擇格所連接之字元線（SWL :選擇字元線）、選 擇格未連接之字元線（USWL :非選擇字元線）、選擇格所 -11 - 201117357 連接之位元線（SB L :選擇位元線）、選擇格未連接之位元 線（USBL:非選擇字元線），使用電源1003〜1007之中之 1個，例如分別施加1V、0 V、0 V、1V之電壓。亦即，設 定 Vread爲IV。其中，0V意味著基準電壓。以下說明 中，0V亦爲基準電壓之意。基於選擇元件之二極體幾乎 未流通逆向電壓之漏電流，僅選擇格SMC流通電流，因 此藉由感測放大器之測定可判斷電阻狀態。 欲由記憶格陣列中選擇1格進行設定動作時，係如圖 5所示，使用電源1003〜1007之中之1個，對SWL、 USWL ' SBL ' USBL，例如分別施力口 2.5V、0V、0V、 2.5V之電壓。亦即，設定Vset爲2.5V。此時，USWL、 USBL所連接之CellD(格D)，基於被施加於選擇元件之二 極體的電壓爲逆向電壓之故而未流入電流。另外， USWL、SBL所連接之CellB，以及SWL、USBL所連接之 CellC(格C) ’基於位元線與字元線爲等電位而未流入電 流。僅選擇格SMC流入電流，焦耳熱使記錄層6被加 熱。施加於SBL與SWL之間的電壓Vset，只要是可使選 擇記憶格之相變化材料加熱至結晶化溫度之充分電壓即 可。以3 Onm製程製造相變化記憶格陣列時，結晶化需要 之電力Wth約爲lmW。藉由該結晶化需要之電力Wth及 第2電阻狀態之電阻變化型元件之電阻値，來決定結晶化 用之電壓。對結晶化施加充分之時間（約1 (Γ6秒以上）電壓 時，選擇格之記錄層6之相變化材料會成爲低電阻之結晶 狀態，選擇格之電阻變化型元件成爲設定動作、亦即第1 -12- 201117357 電阻狀態。其以外之格之狀態不被變化。 欲由s3億格陣列中選擇1格進行重置動作時，係使用 電源1003〜1007之中之1個’對圖5之SWL、USWL、 SBL、USBL分別施加例如3V、〇V' 〇V、3V之電壓。亦 即，設定Vreset爲3V。此時’ USWL、USBL所連接之 C el 1D’基於被施加於選擇元件之二極體的電壓爲逆向電 壓’而未流入電流。另外，USWL、SBL所連接之 CellB (格B)，以及SWL ' USBL所連接之CellC，基於位 兀線與字兀線爲寺電位而未流入電流。僅有選擇格S M C 流入電流，藉由焦耳熱使記錄層6之相變化材料被加熱。 施加於選擇位元線與選擇字元線的電壓，只要是可使選擇 記憶格之記錄層6之相變化材料加熱至融點以上之溫度之 充分電壓即可。急速下降施加電壓至OV，急速冷卻記錄 層6，則選擇格之記錄層6之相變化材料成爲高電阻之非 晶質狀態，選擇格之電阻變化型元件成爲第2電阻狀態。 其以外之格之狀態不被變化。 如上述說明，使選擇之格正確進行圖4之讀出動作、 圖5之設定/重置動作，係在選擇元件之二極體之耐壓以 內之施加電壓下之動作，因此漏電流、亦即逆偏壓施加時 之電流爲極小。假設CellB之選擇元件之逆偏壓施加時之 電流非爲極小時，圖4之CellA(格A)之讀出動作時，基 於RBL之電壓降之故，CellB之SBL電位V成爲正，因 而產生大的漏電流。漏電流之大小因CellB之電阻變化型 元件之電阻狀態 '亦即因被記錄之資訊之狀態而異’因此 -13- 201117357 即使流入CellA之Icell相同時感測放大器所判別之 Iread亦會隨CellB之狀態而變化，讀出將成爲誤動 因此，至少使其不產生誤動作時，漏電流需要設爲小 出電流。藉由50nm世代之製程製造本實施形態之半 記憶裝置時，讀出電流約爲1 μΑ(微安培）。因此，此 下，漏電流須抑制在小於1 μ Α。 同樣，圖5之CellA之設定/重置動作時，CellD 擇元件之逆偏壓電流大時，於CellD會流入大的電 RBL引起之電壓降導致CellD' CellC之USBL電位 低於 2.5V(設定時）、3V(重置時）。結果，未被選 CellC之二極體被施加順偏壓方向之電壓，流入之電 可能使未選擇之CellC之改寫被進行。 如上述說明，當記憶格陣列內存在具有逆偏壓施 之電流較大的選擇元件之不良記憶格（FC)時，不僅 就連其他正常格之讀出、設定/重置動作亦會產生 作，包含FC之陣列全體、進而包含FC之半導體記 置全體之不良率顯著變大。 誤動作，係因爲包含於FC之電阻變化型元件能 低電阻狀態（亦即設定狀態）而產生。因爲大漏電流之 體與低電阻之設定狀態之組合，使記憶體陣列之電 路。該電路之短路，在讀取時影響到與高電阻狀態之 讀出電流値而產生大的變動，引起誤動作。另外， 時，會妨礙對記憶格陣列施加所要之電壓。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and, in particular, to a technology for realizing high reliability of a non-volatile semiconductor memory device that can be electrically rewritten. [Prior Art] In recent years, research on the phase change memory of the chalcogen compound material (Patent Document 1) has been popular in the recording material. The memory structure of the phase change memory is the one in which the recording material is held by the metal electrode. The phase change memory is a resistive memory that uses a recording material between electrodes to have different resistance states and memorize information. The phase change memory uses a resistance 値 of a phase change material such as Ge2Sb2Te5 to store information in an amorphous state and a crystalline state. The resistance in the amorphous state is high, and the resistance in the crystalline state is low. Therefore, when reading, a potential difference is supplied to both ends of the element, and the current flowing into the element is measured, and the high resistance state/low resistance state of the element is judged. The phase change memory system rewrites the data by changing the resistance of the phase change film to a different state by the Joule heat generated by the current. The operation of changing to the amorphous state of the reset operation, that is, the quotient resistance, is performed by rapidly reducing the current and rapidly cooling after the phase change material is dissolved by flowing a large current in a short time. Further, the operation of changing to the setting operation, i.e., the low-resistance crystal state, is performed by maintaining a crystallization temperature of the phase change material by flowing a sufficient current for a long period of time. -5- 201117357 These variable resistance elements are used to add a selection element such as a diode or a transistor to each of the variable resistance elements during the accumulation. For example, a memory cell configuration in which a diode and a variable resistance element are connected in series is combined into a cross point type to form a high density memory cell array. A diode or a transistor is rewritten or read out by selecting each memory from among the memory cell arrays. As in Patent Document 1, the memory cell layer can be made into a larger capacity by forming it into a plurality of layers. (Patent Document 1) Patent Document 1: JP-A-2005-2600 No. 14 (Convention) The problem is that the selected element used in combination with the variable resistance element has a leakage current greater than the allowable defect. In the case of a component, even if the variable resistance component is in a low resistance state, the circuit of the memory cell array may cause a short circuit problem. That is, even if the memory cell containing the defective component is not selected, a large current flows during rewriting and reading. At the time of writing, when the resistance variable element including the memory cell of the defective element is in a low resistance state, the circuit based on the memory cell array becomes a short circuit state, and the desired voltage cannot be applied to the memory cell array, and the device may malfunction. When reading, depending on the resistance change type element connected to the defective component, the low current state or the high resistance state, the leakage current 値 greatly changes, and the result of the read current of the memory cell which should be selected is large. The change caused the device to malfunction. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor -6 - 201117357 memory device including a phase change memory cell array, which can suppress a malfunction caused by a leakage current of a defective selected element, and can promote a high reliability of the semiconductor memory device. The object and novel features of the present invention can be understood from the description and appended drawings. (Means for Solving the Problem) The present invention is directed to a semiconductor memory device having a phase change memory cell array, wherein a resistance 値 of a resistance variable element having a memory cell having a defective selection element is set to be a case where a rewriting operation is performed Underneath, it will not reach the high resistance 产生 that produces the Joule heat. In this way, the resistance 値 of the variable resistance element connected to the defective selection element can be kept high, and the malfunction of the semiconductor memory device can be prevented. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the entire description of the embodiments, the same reference numerals will be given to members having the same functions, and the repeated description thereof will be omitted. (First Embodiment) Fig. 1 is a view showing a whole of a semiconductor device using a phase change meter in the first embodiment of the present invention. Fig. 2 is a perspective view showing a portion of the memory cell array, showing that the memory cell in which the resistance variable element of the phase change memory is connected in series with the diode is configured as a cross point type. Fig. 4 is a circuit diagram showing the read operation of the memory cell array. Fig. 5 is a circuit diagram showing a write operation. The diode of the 201117357 element can be selected by a component design such as an N-type impurity or a P-type impurity profile design, and the withstand voltage of the reverse voltage is set to, for example, 4V. In the present embodiment, the withstand voltage of the reverse voltage of the diode is, for example, 4V. As shown in FIG. 1, a semiconductor memory device according to a first embodiment of the present invention includes an I/O interface 1001 including an input/output buffer for processing data with the outside; a memory cell array 1 002; The power supply 1003~1007 is used to supply different complex voltages; the voltage selector 1 008 is used to select the voltage from the power supply 1〇〇3~1007: the wiring selector 1〇〇9, the bit of the ICP array 1 002 Among the wirings such as the line and the word line, the connection target of the output of the voltage selector 1 00 8 is selected, and the control unit 1 0 1 0 controls the entire apparatus. The wiring selector 1 〇〇 9 is connected to a reading unit 1011 having a sense amplifier or the like. In addition, the management area 1 〇 1 2 is set in the memory array 1 002 for various information of the memory device. When an external device inputs data to the I/O interface 1001, the control unit 1010 selects a voltage for data writing by the voltage selector 1 008 to generate a voltage pulse for any of the power sources 1003 to 007. The wiring selector 1 009 supplies a voltage pulse to the specific wiring of the memory cell array 1〇〇2. In this way, the data input to the phase change memory cell of the memory array can be written. When the read signal of the data is input to the I/O interface 1001 by the external device, the control unit 1010 selects the voltage for reading the data by the voltage selector 1008, and selects one of the power sources 1〇〇3 to 1007. Generate Voltage 'Use the wiring selector 1 009 to supply voltage to the specific wiring of the memory cell array 1 0〇2 201117357. As a result of the supply voltage, the read current is acquired by the reading unit 1011. This is the reproduction of the gg recall data, and the data is supplied to the external device via the control unit 1010 and the I/O interface 1〇01. Figure 2 shows a partially enlarged perspective view of the memory cell array 10〇2. As shown in Fig. 2, a semiconductor memory device according to an eleventh embodiment of the present invention includes a complex digital line 2 formed above a germanium substrate, and a complex bit line 3 disposed in a direction intersecting the word line 2. A p-type semiconductor layer 4 such as a P-type polysilicon or a p-type semiconductor oxide, an n-type semiconductor layer 5 such as an n-type polysilicon or an n-type semiconductor oxide, and a lower portion of the variable resistance element are sequentially formed over the word line 2 The electrode 8, the recording layer 6 of the variable resistance element, the upper electrode 7 of the variable resistance element, and the bit line 3. The layer 1〇 existing between the lower electrode 8 and the n-type semiconductor layer 5 is a barrier metal layer such as TiN or a metal halide layer such as Ti Si. Further, the layer 10 may have a laminated structure having a metal telluride layer on the side adjacent to the n-type semiconductor layer 5 and a barrier metal layer on the side in contact with the lower electrode 8. A diode serving as a selection element is formed on the germanium-type semiconductor layer 4 and the n-type semiconductor layer 5. The material of the recording layer 6 of the variable resistance element can be, for example, a phase change material. The phase change material may be, for example, a material containing Ge (锗), Sb (recorded), or Te (碲). As the recording layer 6 of the variable resistance element, for example, a laminated film including a layer containing a metal oxide and a layer containing a phase change material formed on the lower electrode 8 can be used. Here, the laminated film means that a layer containing a metal oxide is formed on the lower electrode 8, a layer structure is formed on a layer containing a metal oxide layer, or a layer electrode is present in contact with the upper electrode 7. -9 - 201117357 There is a layer comprising a metal oxide having a layer construct comprising a layer comprising a phase change material below the layer comprising the metal oxide. As the metal oxide, for example, Ta205 can be used as the recording layer 6 by using a layer containing a layer of a metal oxide and a layer containing a phase change material, as compared with the recording layer 6 in which a layer containing a metal oxide is not provided, as will be described later. It is shown that the high resistance state of the resistance variable element is thermodynamically stable. Hereinafter, a series of series-connected variable resistance elements and selection elements are referred to as a billion. In the memory cell array shown in Fig. 2, the cells are arranged at the intersection of the complex digital line 2 and the complex bit line 3, respectively. The diode of the selection element is connected to the word line 2, and the recording layer 6 of the resistance variable element is connected to the bit line 3 via the upper electrode 7. In the semiconductor memory device of the present invention, information is stored by using a phase change material such as Ge2Sb2Te5 contained in the recording layer 6 in an amorphous state and a resistive state in a crystalline state. The resistance is high in the amorphous state and low in the crystalline state. Therefore, the readout system supplies a potential difference between both ends of the variable resistance element, measures the current flowing into the element, and determines the high resistance state and the low resistance state of the element. Fig. 3 is a view showing temperature changes of the recording layer during the rewriting operation of the phase change memory according to the first embodiment of the present invention. The change of the phase change material from the amorphous state in the high resistance state to the crystalline state in the low resistance state. On the contrary, the operation of changing from the crystalline state in the low resistance state to the amorphous state in the high resistance state is performed by the phase The change material is supplied to the temperature change shown in Fig. 3. Specifically, the phase change material in the amorphous state is heated to a temperature higher than the crystallization temperature by about 1 (the crystallization state can be set in the case of Γ6 seconds or more. In addition, the phase change material in the crystalline state is heated to the melting point. After the temperature is set to the liquid state, the rapid cooling can be made into an amorphous state. In the first embodiment of the present invention, the phase change material of the recording layer 6 is heated to a temperature higher than the melting point by Joule heat generated by the current. The data is written in a state in which the resistance is changed to a different resistance. The operation of changing to a high-resistance amorphous state is performed by rapidly flowing a large current and dissolving, and then rapidly reducing the current and rapidly cooling. In addition, the setting operation, that is, the operation of changing to the low-resistance crystal state is performed by flowing a sufficient current held at the crystallization temperature for a long period of time. Hereinafter, the memory layer in which the recording layer is in a crystalline state is set by the setting operation. The state is referred to as the first state or the set state. When the memory cell is in the first state, the resistance state of the resistance variable element is called In the first resistance state, the state of the memory cell in which the recording layer 6 is in an amorphous state is set by the reset operation, and is referred to as a second state or a reset state. Further, when the memory cell is in the second state, the resistance is In the second state, the phase change material of the changeable element is not amorphized, but a part of the material is amorphous and becomes a high resistance state. As long as the proportion of the amorphous layer of the recording layer 6 is larger than the second state, the recording layer 6 can be in a state of higher resistance than the second state. When it is desired to increase the resistance, for example, the memory cell can be supplied higher. The voltage is set to a higher temperature by setting the phase change material of the recording layer 6. As shown in Fig. 4, when one cell is selected for reading from the memory cell array, the word line to which the cell is connected is selected (SWL: Select the word line), select the unconnected word line (USWL: non-selected word line), select the grid -11 - 201117357 connected bit line (SB L: select the bit line), select the grid is not connected Bit line (USBL: non-selected word line), For example, one of the power supplies 1003 to 1007 is applied with a voltage of 1 V, 0 V, 0 V, and 1 V. That is, Vread is set to IV. 0 V is a reference voltage. In the following description, 0 V is also used as a reference. The meaning of the voltage is based on the leakage current of the reverse voltage of the diode of the selected component, and only the current flowing through the SMC is selected, so the resistance state can be judged by the measurement of the sense amplifier. In the setting operation, as shown in FIG. 5, one of the power sources 1003 to 1007 is used, and for SWL and USWL 'SBL 'USBL, for example, voltages of 2.5 V, 0 V, 0 V, and 2.5 V are applied, respectively. The Vset is set to 2.5 V. At this time, the CellD (cell D) to which the USWL and USBL are connected does not flow current because the voltage applied to the diode of the selection element is the reverse voltage. Further, the CellB to which the USWL and SBL are connected, and the CellC (cell C) to which the SWL and USBL are connected are based on the bit line and the word line are equipotential and do not flow into the current. Only the grid SMC inflow current is selected, and the Joule heat causes the recording layer 6 to be heated. The voltage Vset applied between SBL and SWL may be a sufficient voltage to heat the phase change material of the selected memory cell to the crystallization temperature. When a phase change memory cell array is fabricated by a 3 Onm process, the power Wth required for crystallization is about lmW. The voltage for crystallization is determined by the electric power Wth required for the crystallization and the electric resistance 値 of the resistance variable element of the second resistance state. When a sufficient time (about 1 (Γ6 seconds or more)) is applied to the crystallization, the phase change material of the recording layer 6 of the selected cell becomes a crystal state of low resistance, and the resistance variable element of the selected cell becomes the setting operation, that is, the first 1 -12- 201117357 Resistive state. The state of the grid is not changed. To select a cell from the s3 billion array to perform the reset operation, one of the power supplies 1003 to 1007 is used. SWL, USWL, SBL, and USBL respectively apply voltages of, for example, 3V, 〇V' 〇V, and 3V. That is, Vreset is set to 3 V. At this time, 'USWL, USBL connected C el 1D' is based on being applied to the selection element. The voltage of the diode is the reverse voltage 'and no current flows. In addition, the CellB connected to USWL and SBL, and the CellC connected to SWL 'USBL are based on the bit line and the word line. Current is flowed in. Only the SMC inflow current is selected, and the phase change material of the recording layer 6 is heated by Joule heat. The voltage applied to the selected bit line and the selected word line is as long as the recording layer of the selected memory cell can be selected. 6 phase change materials heated to melt A sufficient voltage of the above temperature may be applied. When the voltage is applied to the OV at a rapid rate, the recording layer 6 is rapidly cooled, and the phase change material of the recording layer 6 of the cell is selected to be a high-resistance amorphous state, and the resistor-variable component of the cell is selected. In the second resistance state, the state of the other cells is not changed. As described above, the selection operation is performed correctly in the read operation of FIG. 4, and the setting/reset operation of FIG. 5 is performed in the diode of the selection component. The operation under the applied voltage within the withstand voltage, so the leakage current, that is, the current when the reverse bias is applied is extremely small. It is assumed that the current when the reverse bias of the selected component of CellB is not extremely small, CellA of Figure 4 In the read operation of A), the SBL potential V of CellB becomes positive based on the voltage drop of RBL, and thus a large leakage current is generated. The magnitude of the leakage current is due to the resistance state of the resistance variable element of CellB. The status of the recorded information varies. Therefore, even if the Icell flowing into CellA is the same, the Iread determined by the sense amplifier will change with the state of CellB, and the readout will become a malfunction. Therefore, at least When no malfunction occurs, the leakage current needs to be set to a small current. When the half memory device of this embodiment is manufactured by the process of 50 nm generation, the read current is about 1 μΑ (microamperes). Therefore, the leakage current must be The suppression is less than 1 μ Α. Similarly, when the CellA selects the reverse bias current of the CellA in the setting/reset operation of Figure 5, the voltage drop caused by the large electrical RBL flowing into the CellD causes the CellD' CellC USBL. The potential is lower than 2.5V (when set) and 3V (when reset). As a result, the diode of the unselected CellC is applied with a voltage in the forward bias direction, and the incoming power may cause the rewriting of the unselected CellC to be performed. As described above, when there is a bad memory cell (FC) of a selection element having a large reverse current applied to the memory array, not only the reading, setting/resetting operations of other normal cells are generated. The defect rate including the entire array of FCs and the semiconductors including FC is significantly increased. The malfunction occurs because the resistance variable element included in the FC can be in a low resistance state (that is, a set state). Because of the combination of the large leakage current and the low resistance setting state, the circuit of the memory array is made. The short circuit of this circuit causes a large fluctuation in the read current 与 with the high resistance state during reading, causing malfunction. In addition, it will prevent the application of the required voltage to the memory array.

因此，本發明中，係將包含於FC之電阻變化I 電流 作。 於讀 導體 情況 之選 流， 變爲 擇之 流有 加時 FC， 誤動 憶裝 取得 二極 路短 間之 寫入 元件 -14- 201117357 設爲高電阻化。此時，係將包含於F C之電阻變化型元件 設爲較第2電阻狀態（亦即重置狀態）具有更高電阻値之第 3電阻狀態。於此，第3電阻狀態之電阻値係指，即使將 資料記錄使用之最大電壓（本實施形態中爲重置動作之電 壓、亦即重置電壓）施加於記憶格之情況下，亦不致於供 給使記錄層6之相變化材料成爲結晶化之焦耳熱（亦即電 力）的高的電阻値。於此條件下，即使將小於重置電壓之 設定動作用的電壓（亦即設定電壓），施加於具有第3電阻 狀態之電阻變化型元件的記憶格之情況下，亦不致於供給 使記錄層6之相變化材料成爲結晶化之焦耳熱（亦即電 力）。因此，於第3電阻狀態，對應於設定動作及重置動 作，記錄層6之相變化材料不致於到達結晶化溫度，因此 電阻變化型元件保持高電阻之第3電阻狀態。 藉由將F C之電阻變化型元件設定成爲上述電阻狀 態，則於記憶格陣列存在：電阻變化型元件基於重置電壓 之脈衝之施加而由第1電阻狀態變化爲第2電阻狀態，藉 由設定動作用之電壓之脈衝而由第2電阻狀態變化爲第1 電阻狀態，如此而進行資料之記憶的記億格；以及不論設 定電壓之脈衝及重置電壓之脈衝之施加亦處於第3電阻狀 態的記憶格。以下稱重置電壓之脈衝爲重置脈衝，設定電 壓之脈衝爲設定脈衝。 於本發明之半導體記憶裝置中，FC之電阻變化型元 件係被保持於高電阻之第3電阻狀態，因此可以解決上述 FC之選擇元件之漏電流引起之資料讀出時之誤動作問Therefore, in the present invention, the resistance change I current included in the FC is used. In the case of reading the conductor, the selected stream becomes the selected stream with the add-time FC, and the erroneous memory recalls the write element of the two-pole short-term. -14- 201117357 Set to high resistance. At this time, the resistance variable element included in F C is set to have a higher resistance 値 in the third resistance state than the second resistance state (that is, the reset state). Here, the resistance 第 of the third resistance state means that even if the maximum voltage used for data recording (the voltage of the reset operation in the present embodiment, that is, the reset voltage) is applied to the memory cell, it is not The high-resistance 使 which supplies the phase change material of the recording layer 6 to the crystallized Joule heat (that is, electric power) is supplied. Under these conditions, even if a voltage for setting operation (that is, a set voltage) smaller than the reset voltage is applied to the memory cell of the variable resistance element having the third resistance state, the recording layer is not supplied. The phase change material of 6 becomes the crystallization of Joule heat (ie, electricity). Therefore, in the third resistance state, the phase change material of the recording layer 6 does not reach the crystallization temperature in accordance with the setting operation and the reset operation, and therefore the variable resistance element maintains the third resistance state of high resistance. When the resistance variable element of the FC is set to the resistance state, the memory cell array has a resistance change element that is changed from the first resistance state to the second resistance state by the application of a pulse of the reset voltage, and is set by the first resistance state. The pulse of the voltage of the action changes from the second resistance state to the first resistance state, so that the data is memorized; and the pulse of the set voltage and the pulse of the reset voltage are also in the third resistance state. Memory of the grid. Hereinafter, the pulse of the reset voltage is a reset pulse, and the pulse of the set voltage is a set pulse. In the semiconductor memory device of the present invention, the resistance variable element of the FC is held in the third resistance state of the high resistance, so that the malfunction of the data read by the leakage current of the selected element of the FC can be solved.

I -15- 201117357 題。另外，於上述設定、重置時之問題，於第3電阻狀 態，電阻變化型元件係處於較重置狀態更高電阻之狀態， 因此可以防止逆偏壓電流之變大，可防止誤動作。 圖6爲本發明第1實施形態之半導體記憶裝置之對於 記憶格之施加電壓與所得之電阻値之關係。橫軸表示施加 於記憶格之電壓脈衝之電壓，縱軸表示電阻變化型元件之 電阻。 如圖6所示，第1電阻狀態（亦即設定狀態）爲低電阻 狀態。對記憶格施加重置脈衝時焦耳熱使記錄層6之相變 化材料被加熱至融點以上，如虛線箭頭所示，非晶質相比 例之增加而產生高電阻化。藉由重置脈衝而獲得A點所 示第2電阻狀態（亦即重置狀態）之電阻値。反之，由第2 狀態，藉由施加大於圖6之電壓V2的電壓藉由焦耳熱使 記錄層6之相變化材料被加熱至結晶化溫度以上，記錄層 6之相變化材料之結晶化比例增加，如虛線箭頭所示回復 第1電阻狀態（亦即設定狀態）。如上述說明，藉由對記憶 格之電壓施加，使第1電阻狀態與第2電阻狀態呈可逆之 變化，而可以進行資料之記憶。 不良選擇元件所連接之電阻變化型元件之電阻値，係 設爲圖6之第3電阻狀態之臨限値以上。第3電阻狀態之 臨限値係表示：將資料記憶時使用之最大電壓、於此爲重 置電壓施加於記憶格之情況下，亦不致於供給相變化材料 之結晶化必要之焦耳熱、亦即相變化材料之結晶化必要之 電力之，第3電阻狀態之電阻値之下限者。低於該下限的 -16- 201117357 電阻値時，基於重置脈衝之施加會漸漸進展爲結晶化，電 阻變化型元件有可能變爲低電阻化。因此，將FC之記億 格之電阻變化型元件之電阻値設爲該臨限値以上之第3電 阻狀態，可防止FC之記憶格之低電阻化，可防止裝置之 誤動作。結果，可以高良品率、亦即低成本提供高信賴性 之非揮發性半導體記憶裝置。另外，欲更進一步提升信賴 性時，藉由對記憶格之更高電壓之施加，使記錄層6之相 變化材料汽化而於記錄層6形成孔洞（void)，將第3電阻 狀態之電阻値設爲更高電阻値，如此則，可進行更確實之 電阻變化型元件之高電阻化。另外，如上述說明，將記錄 層6設爲包含金屬氧化物之層與包含相變化材料之層的積 層膜，如此則，和未設置包含金屬氧化物之層之記錄層6 比較，第3電阻狀態更能獲致熱力學之穩定，可實現更確 實之電阻變化型元件之高電阻化。 對具有第3電阻狀態之電阻變化型元件的記憶格進行 讀出時，基於第3電阻狀態之電阻値爲高於第2電阻狀態 之電阻値，因而被讀出爲高電阻狀態。例如對具有第3電 阻狀態之電阻變化型元件的記憶格進行設定動作之後期待 以第1電阻狀態被讀出時，被讀出爲錯誤之高電阻狀態之 結果。但是，對第3電阻狀態之記憶格進行寫入動作時之 錯誤，於資訊之記錄再生時可以適用錯誤訂正碼之技術進 行充分之訂正，不會有問題。另外，於記憶格陣列之管理 區域1 0 1 2，將具有第3電阻狀態之電阻變化型元件的記 憶格之位址予以保存，依據記憶之位址資訊，控制部 -17- 201117357 1 ο 1 0在資料之寫入時可以進行控制據以避開第3狀態之 記億格而進行寫入。 上述第3電阻狀態，係藉由具有高於重置電壓之電壓 値的電壓脈衝之施加於記憶格而實現。 圖7表示FC所包含之電阻變化型元件之遷移至第3 電阻狀態之高電阻化的裝置動作模態時之’各位元線、字 元線之施加電壓之圖案。如圖 7所示’可以藉由對 SWL、USWL、SBL、USBL 分別施加 3.5V、0V、0V、 3.5V之電壓，而將電壓VFC(此情況下爲3.5V)施加於FC 之二極體之順向之方法來進行。電壓施加’係依據和圖3 之重置脈衝同樣之脈衝進行，進行急速之下降使熔融之記 錄層之相變化材料急速冷卻。對FC之施加電壓係較通常 之重置動作時之3.0V爲更大的3.5V，因此可將FC之電 阻變化型元件之電阻設爲較重置狀態更高的第3電阻狀 態。 另外，亦可以藉由對SWL、USWL、SBL、USBL分別 施加例如7V、0V、OV、3.5V，而將電壓VFC (此情況下爲 7V)施加於FC之二極體之順向之模態來進行。該電壓條 件之情況下，於圖8在FC以外之記億格兩端之電位差爲 0V，另外，於二極體之逆向被施加3.5V之較正常二極體 之逆向耐壓（於此爲4 V)小的電壓，因此未流入電流。亦 即，7V之施加電壓，係較二極體之耐壓大，而且選擇爲 二極體之耐壓之2倍以內，3.5V之施加電壓，其本身爲 二極體之耐壓以內，而且和7 V之施加電壓間之差亦設爲 -18- 201117357 二極體之耐壓以內。 使用圖1說明動作。電源1003〜1007之中2個分別 7V與3.5V之電源。基準電壓設爲〇V，使成爲圖7之圖 案的方式依據控制部1010之控制資訊使電壓選擇器1008 與配線選擇器1 009動作，將電源與字元線與位元線連 接。藉由控制部1010由電源產生電壓脈衝，進行FC之 電阻變化型元件之高電阻化。於FC，基於兩端被施加之 電位差7 v而流入大電流，F C之記錄層之相變化材料被熔 融。進行施加電壓之急速下降，使F C之記錄層之相變化 材料急速冷卻，而進行電阻變化型元件之變爲第3電阻狀 態之高電阻化動作。本實施形態中，可施加較選擇元件之 二極體之耐壓更高之電壓，因此可將電阻變化型元件之第 3電阻狀態之電阻値設爲更高，如此則可以擴大重置狀態 之電阻之獲取之範圍，有利於例如使用不同之3個以上之 電阻狀態進行多値記憶。另外，藉由高的電壓之施加，使 記錄層6之相變化材料汽化而於記錄層6產生之孔洞 (void)，更有利於將第3電阻狀態設爲更高之電阻値。 圖9表示使電阻變化型元件變爲第3電阻狀態之高電 阻化之動作序列。首先，將二極體之順向電壓施加於記憶 格，使全部記憶格之電阻變化型元件成爲低電阻化 (S 901)。之後，施加二極體之逆向電壓選出漏電流大於特 定臨限値之記憶格（S902)，針對漏電流大的記憶格（FC) ’ 於上述圖7或圖8所示模態施加電壓，使FC之電阻變化 型元件變爲第3電阻狀態之高電阻化（S 903 )。於S901 ’藉 -19- 201117357 由使記億格之電阻變化型元件成爲低電阻化，使電阻變化 型元件之上述之影響變小，可以正確判斷選擇二極體之漏 電流。 欲使和OFF(非導通）電流較大的二極體成組之電阻變 化型元件設爲第3電阻狀態之高電阻化，係另有其他構 成。圖1 0表示設爲第3電阻狀態用之各位元線、字元線 之施加電壓之圖案。於圖10，對3界1^、1；51^1^、381^、 USBL分別施加例如 0V、〇V、4V、4V，亦即 VFC設爲 4V，不僅FC之二極體，就連具有正常二極體之記憶格亦 對二極體之逆向施加4V之電壓。於具有正常二極體之記 憶格，在二極體之逆向被施加耐壓以下之電壓，電流幾乎 未流入記憶格，因此電壓施加後電阻變化型元件之電阻値 不變。於FC’二極體之逆向耐壓低，因此兩端施加之電 位差4V引起大電流’記錄層6之相變化材料熔融。施加 電壓之急速下降使相變化材料急速冷卻，如此則，可對 FC之電阻變化型元件進行變爲第3電阻狀態之高電阻化 動作。使用此一電壓條件，則無須對選擇元件之漏電流較 大的格進行選別，可以自動使電流僅流入FC，而將電阻 變化型元件設爲第3電阻狀態之高電阻化。 動作時序係如圖1 1所示’於圖1 〇之模態施加電壓而 使FC之電阻變化型元件設爲高電阻化（S1101)。因此，可 獲得在短時間設定FC之電阻變化型元件成爲第3電阻狀 態，正常動作之半導體記憶裝置。 上述不良格之高電阻化動作，可藉由控制部1 〇 1 〇， -20- 201117357 使半導體記億裝置於上述個別之模態下動作而予以進行。 另外，於半導體記憶裝置之製造階段，依據如圖7-11所 示圖案，由外部施加上述電壓，可將FC設爲第3電阻狀 態之高電阻化。 圖12爲本發明第1實施形態之效果之圖。在FC之 電阻變化型元件被設爲高電阻化的非揮發性半導體記憶裝 置，和不進行該處理之情況比較，可以大幅降低二極體之 漏電流引起之非揮發性半導體記憶裝置之不良。 以結晶缺陷、金屬污染等引起之OFF電流不良之頻 度較少的單晶矽二極體、形成於單晶矽基板上的電晶體作 爲選擇元件使用時亦會有效果，但是，以如圖1 3或1 4所 示之可以多層積層化之多晶矽二極體、氧化物二極體作爲 選擇元件使用時效果更大。 (第2實施形態） 第2實施形態係表示使用電晶體作爲選擇元件。圖 1 5表示第2實施形態使用之相變化記憶體與電晶體連接 而成的記憶格。如圖1 5所示，將字元線2連接於電晶體 之閘極，在電晶體之源極或汲極信號線所電連接之電阻變 化型元件之下部電極8上，依序形成電阻變化型元件之記 錄層6、電阻變化型元件之上部電極7、位元線3。相當 於第1實施形態之半導體記憶裝置之電阻變化型元件由二 極體替換爲電晶體者，如圖1 6所示作成交叉點型之陣列 而達成高密度化。 I. "21 - 201117357 如圖1 6所示，欲由記憶格陣列中選擇1格進行讀出 時，係對選擇格所連接之字元線（SWL :選擇字元線）、未 被選擇格連接之字元線（USWL :非選擇字元線）、選擇格 所連接之位元線（SBL :選擇位元線）、未被選擇格連接之 位元線（USBL :非選擇位元線），例如分別施加2V、OV、 IV、0V之電壓。選擇電晶體係使用N通道電晶體。選擇 電晶體之閘極電位爲0V時，幾乎未流通漏電流，僅選擇 格SMC流通電流，因此藉由感測放大器之測定可判斷電 阻狀態。 欲由記憶格陣列中選擇1格進行設定動作時，係對 SWL、USWL、SBL、USBL 例如分別施加 3V、0V、 1.5V、0V 之電壓。此時，USWL、USBL 所連接之 CellD(格D)，基於USBL與接地電位均爲OV而未流入電 流。另外，USWL、SBL所連接之CellB，基於選擇電晶 體爲 OFF狀態而未流入電流。SWL、USBL所連接之 CellC(格C)，基於位元線電位與接地電位爲等電位而未流 入電流。僅選擇格SMC流入電流，焦耳熱使相變化材料 被加熱。施加於選擇位元線、選擇字元線的電壓，只要是 可使選擇記億格之相變化材料加熱至結晶化溫度之充分電 壓即可。施加結晶化所需充分之時間（約1(Γ6秒以上）電壓 時，選擇格之電阻變化型元件，其之記錄層6之相變化材 料會進行結晶化，而成爲低電阻之第1電阻狀態。其以外 之格之狀態不被變化。 欲由記憶格陣列中選擇1格進行重置動作時，係對 -22- 201117357 SWL ' USWL ' SBL、USBL 分別施加例如 3V、0V、2V、 〇V之電壓。此時’ USWL、USBL所連接之CellD，基於 USBL與接地電位皆爲〇V而未流入電流。另外，USWL、 SBL所連接之CellB(格B)，基於選擇電晶體爲OFF狀態 而未流入電流。SWL、USBL所連接之CellC(格C)，基於 位元線電位與接地電位爲等電位而未流入電流。僅選擇格 S M C流入電流，焦耳熱使相變化材料被加熱。施加於選 擇位元線、選擇字元線的電壓，只要是可使選擇記憶格之 相變化材料加熱至融點以上之溫度之充分電壓即可。急速 下降施加電壓至0V，急速冷卻相變化材料，則選擇格之 記錄層6之相變化材料成爲高電阻之非晶質狀態，電阻變 化型元件成爲第2電阻狀態。其以外之格之狀態不被變 化。 欲使選擇之格正確進行圖1 6之讀出動作、設定/重置 動作，係在選擇元件之電晶體之耐壓以內動作，因此漏電 流、亦即 OFF狀態之電流爲極小。假設圖 16之之 CellA(格 A)之讀出動作時，基於 RBL之電壓降之故， CellB之SBL電位V成爲正，假設CellB之選擇電晶體之 OFF狀態之電流大時會產生大的漏電流。漏電流之大小因 CellB之電阻變化型元件之電阻狀態、亦即所記錄之資訊 之狀態而異，因此即使流入CellA之Icell相同時感測放 大器所判別之電流Iread亦會隨CellB之狀態而變化，讀 出將成爲誤動作。因此’和第1實施形態同樣，至少使其 不產生誤動作時，漏電流需要設爲小於讀出電流。 -23- 201117357 同樣，圖16之CellA之設定/重置動作時，CellB之 選擇元件之OFF狀態之電流大時，於CellB會流入大的電 流，RBL引起之電壓降導致CellA之SBL電位變爲低於 1.5V(設定時）、2V(重置時）。結果，對CellA之設定/重置 動作有可能未被正常進行。如上述說明，記憶格陣列內存 在具有OFF狀態之電流大的選擇元件之記憶格（FC)時， 不僅FC，舊聯合FC連接於同一位元線的其他正常格之讀 出、設定/重置動作亦會產生誤動作，半導體記憶裝置全 體之不良率顯著增大。 欲防止FC以外之記憶格之不良，而使包含於FC之 電阻變化型元件設爲高電阻化。此時，和第1實施形態同 樣，將包含於FC之電阻變化型元件設爲第3電阻狀態β 如此則，和第1實施形態同樣，藉由上述之FC之選擇元 件之漏電流，使讀出之誤動作問題被解決。另外，和第1 實施形態同樣，第3電阻狀態之記憶格引起之誤動作，藉 由載資訊再生時適用錯誤訂正碼之技術可以充分訂正，不 會成爲問題。另外，於記憶格陣列之管理區域1 〇 1 2，保 存具有第3電阻狀態之電阻變化型元件的記億格之位址， 依據記憶之位址資訊，控制部1 〇 1 〇可以進行控制使資料 寫入時避開處於第3電阻狀態之記憶格而進行寫入。 FC所包含之電阻變化型元件之高電阻化，係如圖1 7 所示，藉由對SWL、USWL、SBL、USBL分別施加3V、 0V、2.5V、0V之電壓，而將VFC(此情況下爲2.5V)施加 於FC來進行。電壓施加，係依據和圖1之重置脈衝同樣 -24- 201117357 之脈衝進行，進行急速之下降使熔融之相變化材料急速冷 卻。對FC之施加電壓係較通常之重置動作時之2.0V爲 更大，因此電流亦較通常之重置動作時大。因此，可將 FC之相變化元件之電阻設爲較重置狀態更高的第3電阻 狀態。 圖18表示動作序列之全體。首先，使電晶體成爲ON 狀態而設定選擇電晶體之閘極電壓，對記憶格之兩端施加 電壓，設定全部記憶格之電阻變化型元件成爲低電阻化 (S1 801)。之後，使電晶體成爲OFF狀態而設定選擇電晶 體之閘極電壓，對記憶格之兩端施加電壓，選出漏電流大 於特定臨限値的記憶格（S 18 02)。使電晶體成爲ON狀態而 設定漏電流大的記憶格FC之選擇電晶體之閘極電壓，對 記憶格之兩端施加電壓，設定記憶格之電阻變化型元件成 爲第3電阻狀態之高電阻化（S 1 803)。 欲使和OFF電流較大的電晶體成組之電阻變化型元 件設爲第3電阻狀態之高電阻化，可使用圖1 9所示電壓 條件。於圖 19，係對8\^1^、1^\\^、361^、1；38[分別施 加例如〇V、0V、2.5V、2.5V，不僅FC，就連具有正常之 選擇電晶體之記憶格亦對記憶格之兩端施加2.5V之電 壓。於具有正常之選擇電晶體之記憶格，基於閘極電壓爲 0V，電流幾乎未流入記憶格，因此電壓施加後電阻變化 型元件之電阻値不變。於FC，選擇電晶體之OFF電流較 大，因此，藉由兩端施加之電位差2.5V引起大電流使記 錄層之相變化材料熔融。施加電壓之急速下降使相變化材 -25- 201117357 料急速冷卻，如此則，可對電阻變化型元件進行變化爲第 3電阻狀態之高電阻化動作。使用此一電壓條件’則無須 對選擇電晶體之OFF電流較大的格進行選別’可以自動 使電流僅流入FC，而將電阻變化型元件設爲第3電阻狀 態之高電阻化》 動作時序係如圖20所示’於圖19之模態施加電壓。 而使FC之電阻變化型元件設爲高電阻化（S2001)。 上述不良格之高電阻化動作，係和第1實施形態同 樣，可藉由控制部1010，使半導體記憶裝置於上述個別 之模態下動作而予以進行。另外’由外部施加上述電壓’ 亦可將FC設爲第3狀態之高電阻化。 如圖21所示縱型之多晶矽電晶體或氧化物電晶體作 爲選擇元件使用的積層相變化記憶格陣列’亦可使用本實 施形態之方法。 (第3實施形態） 第3實施形態係表示，控制部1 〇 1 〇針對處於第3電 阻狀態之記憶格之位址之管理區域1 〇 12之保存之實施形 態。控制部1 〇 1 〇，係如圖2 2所示，將記億格區分爲由1 個或複數個構成之群，針對各個分配記憶體管理區域’而 將包含於群的記憶格設爲第3狀態之高電阻化時’將該資 訊記錄於管理區域1012。圖23〜25表示第3實施形態之 控制部之序列。 使用二極體作爲選擇元件時’係對應於第1實施形態 -26- 201117357 之圖9之動作序列，可以使用圖2 3之序列。藉由和圖9 相同之序列設定FC之電阻變化型元件爲第3電阻狀態之 高電阻化（S2301、S2302、S2303)之後’將FC之位址記錄 於包含FC之群之記憶體管理區域（S23〇4)。 又，對應於第1實施形態之圖1 1之動作序列，可以 使用圖24之序列。藉由對記憶格施加二極體之順向電壓 等之方法，設定全部記憶格之電阻變化型元件爲低電阻化 (S240 1 )之後，藉由和圖11相同之序列設定FC之電阻變 化型元件爲第3電阻狀態之高電阻化（S 2 402)之後’對記 憶格進行通常之讀出動作，以高電阻化之記憶格判斷爲 FC(S2403)，將FC之位址記錄於包含FC之群之記憶體管 理區域（S2404)。於S2401之所以設定全部記憶格之電阻 變化型元件成爲低電阻化’係爲將S2404之高電阻狀態之 格判斷爲不良記憶格FC。 使用電晶體作爲選擇元件時，係對應於第2實施形態 之圖1 8之動作序列’可以使用圖2 5之序列。和圖1 8相 同，設定全部記億格之電阻變化型元件爲低電阻化（S25 0 1 ) 之後，選出不良格FC(S25 02) ’設定FC之電阻變化型元 件爲第3電阻狀態之高電阻化（S 2 5 03 )之後，將FC之位址 記錄於包含FC之群之記憶體管理區域（S 2504)。 又，對應於第2實施形態之圖2 0之動作序列’可以 使用圖26之序列。設定全部記憶格之電阻變化型元件爲 低電阻化（S 2 6 0 1 )之後’藉由和圖2 1相同之序列設定F C 之電阻變化型元件爲第3電阻狀態之高電阻化（S2602)之 m -27- 201117357 後，對記憶格進行通常之讀出動作，以高電阻化之記憶格 判斷爲FC(S2603)，將FC之位址記錄於包含FC之群之記 億體管理區域（S2604)。於S2601之所以設定全部記憶格 之電阻變化型元件成爲低電阻化，係爲將S2604之成爲高 電阻狀態之格判斷爲不良記憶格FC。 以彼等序列記錄FC之位址資訊之後，於通常之資訊 之改寫或讀出時設定成爲不使用FC的方式，而可以正確 記憶資料。另外，設定成爲在記憶體管理區域之記憶格使 用無不良之記億格之事乃重要者。 於圖22之同一記憶格群，可以包含物理上位於接近 位置的記憶格、例如同一位址內之記億格而構成，但是， 亦可由晶片內存在之複數個之各個記億格陣列選擇個別之 記憶格，分配給同一記憶格群。 (第4實施形態） 於第3實施形態並未針對記錄通常資料的記憶格與管 理區域之記憶格予以區分而作成，但是，亦可如第4實施 形態所示將兩者設爲物理上不同之記億格構造，設爲製作 在物理上不同位置之記憶格》例如用於記憶需要大容量之 通常資料的記憶格，係藉由如圖13、14、21所示構造被 製作’小容量即可但需要構成無不良之管理區域之記憶 格，可如圖15所示藉由形成於矽基板上之電晶體作爲選 擇元件予以製作。 另外，用於記錄需要大容量之通常資料的記憶格，係 -28- 201117357 由圖14、21之上藉由較第2層更下層來製作，小容量即 可但需要構成無不良之管理區域之記憶格，可藉由製程之 熱負荷較小的圖1 4、2 1之最上層予以製作。本實施形態 中，亦可正確記憶資料。 (第5實施形態） 第5實施形態係表示將第1實施形態之半導體記憶裝 置之包含於FC之電阻變化型元件，藉由由半導體記憶裝 置外部之電壓施加設爲高電阻化的半導體記憶裝置之製造 方法。 圖27表示製程。於第1實施形態之半導體記憶裝 置，由外部進行位元線、字元線與電極間之連接，對記憶 格，於二極體之逆向施加第1檢測用電壓，測定二極體之 漏電流値（S 270 1 )。又，和第1實施形態同樣，對記憶格 施加二極體之順向電壓，設定電阻變化型元件爲低電阻 化，可以正確判斷漏電流値。當二極體之漏電流爲第1特 定電流値以上時（S 2702)，亦即爲FC時，係對包含該二極 體之記憶格施加電壓値較設定脈衝及重置脈衝爲高的第3 電壓脈衝，設定電阻變化型元件爲高電阻化（S 27 0 3 )。第1 特定電流値，可設爲例如正常二極體之漏電流値。另外， 如上述說明，藉由5 Onm世代製程製造第1實施形態之半 導體記憶裝置時，讀出電流約爲1 μ A(微安培）。因此，此 情況下，第1特定電流値設爲1 μ A即可。 欲設爲更確實之製程時，係針對被施加有第3電壓脈 1. -29- 201117357 衝的記憶格，對二極體之順向施加第2檢測用電壓，測定 流入之電流之電流値（S 2704)。當施加第2檢測用電壓時 流入之電流之電流値爲第2特定電流値以上時（S2705)， 係對施加有第3電壓脈衝的記憶格，施加較第3電壓脈衝 具有更高電壓値之第4電壓脈衝，設定電阻變化型元件爲 更高電阻化（S2706)。此時，係設爲滿足第2檢測用電壓 之電壓値與第2特定電流値之比之値，較半導體記憶裝置 之記錄所使用之電壓之中最大的電壓之電壓値、亦即重置 電壓之電壓値與第1特定電流値之比之値爲更大之關係。 藉由第4電壓脈衝之施加亦無法滿足該關係時對記憶格施 加更進一步高電壓之電壓脈衝，設定電阻變化型元件爲更 高電阻化 依據本實施形態之製造方法，當施加半導體記憶裝置 之記錄使用的電壓之中最大之電壓，於此爲施加重置電壓 時，流入FC之電流爲小於第1特定電流値。亦即，藉由 滿足上述關係’可以將FC之電阻變化型元件設定成爲， 即使對F C施加重置電壓時亦僅流入小於第丨特定電流値 之電流的高電阻狀態。 例如藉由將第1特定電流値設爲正常之二極體之漏電 流値’可使FC藉由設定動作、重置動作僅能流通較正常 之二極體之漏電流爲小的電流。如此則，F c之電阻變化 型元件之記錄層6之相變化材料，不會因爲設定動作、重 置動作而到達結晶化溫度，可以防止電阻變化型元件成爲 低電阻狀態。亦即，可使FC之電阻變化型元件之電阻 -30- 201117357 値，以滿足第1實施形態所示第3電阻狀態之臨限値以上 之條件的方式來製造半導體記憶裝置。 又，例如在以第1特定電流値作爲讀出電流時，針對 FC，亦可以設爲藉由設定動作、重置動作而僅流入小於 讀出電流之電流。因此，FC之電阻變化型元件之記錄層 6之相變化材料，不會因爲設定動作、重置動作而到達結 晶化溫度，可以防止電阻變化型元件成爲低電阻狀態。亦 即，可使FC之電阻變化型元件之電阻値，以滿足第1實 施形態所示第3電阻狀態之臨限値以上之條件的方式來製 造半導體記憶裝置。 如上述說明，依據本實施形態之製造方法，可以防止 FC之電阻變化型元件成爲低電阻狀態引起之裝置之誤動 作’可以高良品率、製造高信賴性之半導體記億裝置。 (產業上可利用性） 本發明之非揮發性半導體記憶裝置可以適用於行動個 人電腦或數位相機等之小型行動資訊機器用之記憶裝置。 (發明效果） 依據本發明，可以高良品率、低成本提供大容量 '高 性能而且高信賴性之非揮發性半導體記憶裝置。 【圖式簡單說明】 圖1爲本發明之半導體記憶裝置之模式圖。 -31 - 201117357 圖2爲本發明之記憶格陣列之立體模式圖° 圖3爲本發明之相變化記億體之高電阻化、及低電阻 化動作之說明圖。 圖4爲本發明之記憶格陣列之讀出動作之說明之電路 圖。 圖5爲本發明之記億格陣列之設定動作、重置動作之 說明之電路圖。 圖6爲本發明之相變化記憶體之高電阻化、及低電阻 化動作之說明圖。 圖7爲本發明第1實施形態之一例使用之不良格之高 電阻化動作之電路圖。 圖8爲本發明第1實施形態之一例使用之不良格之高 電阻化動作之電路圖。 圖9爲本發明第1實施形態之一例之動作序列圖。 圖1 0爲本發明第1實施形態之一例使用之不良格之 高電阻化動作之電路圖。 圖1 1爲本發明第1實施形態之一例之動作序列圖。 圖1 2爲本發明第1實施形態之效果之圖。 圖1 3爲第1實施形態可適用之記憶格陣列之立體 圖。 圖14爲第1實施形態可適用之記憶格陣列之立體 圖。 圖1 5爲具備電晶體與電阻變化型元件之串聯構造之 記憶格被配置於交叉點而成的記億格陣列之斷面圖。 -32- 201117357 圖1 6爲圖1 5之記憶格陣列之讀出動作 '設定動作、 重置動作之說明之電路圖。 圖1 7爲本發明第2實施形態之一例使用之不良格之 高電阻化動作之電路圖。 圖1 8爲本發明第2實施形態之一例之動作序列圖。 圖19爲本發明第2實施形態之一例使用之不良格之 高電阻化動作之電路圖。 圖2 0爲本發明第2實施形態之一例之動作序列圖。 圖2 1爲第2實施形態可適用之記憶格陣列之立體 圖。 圖22爲本發明第3實施形態之半導體記憶裝置之一 例之記憶體階層圖。 圖23爲本發明第3實施形態之一例之動作序列圖。 圖24爲本發明第3實施形態之一例之動作序列圖。 圖25爲本發明第3實施形態之一例之動作序列圖。 圖26爲本發明第3實施形態之一例之動作序列圖。 圖27爲本發明第5實施形態之一例之動作序列圖。 【主要元件符號說明】 1 :半導體基板（矽基板） 2 :字元線 3 :位元線 4: p型多晶矽、或p型半導體氧化物等之p型半導 -33- 201117357 5: η型多晶砂、或η型半導體氧化物等之π型半導 體層 6 :電阻變化型元件之記錄層 7:電阻變化型元件之上部電極 8 ··電阻變化型元件之下部電極 9: ρ型半導體界面之阻障金屬、或矽化物 1 〇 ·· η型半導體界面之阻障金屬、或矽化物 2 1、2 2 :閘極絕緣膜 1 0 0 :板電極 101 :阱 1 1 1 :源極線 1 1 2 :電極 1 00 1 : I/O 介面 1 0 0 2 :記憶格陣列 1003〜1007:電源 1 008 :電壓選擇器 1 009 :配線選擇器 1 0 1 0 :控制部 1 0 1 1 :讀取部 1012 ：管理區域 Dif :擴散層 RB L :位元線之格間距單位之阻抗 RWL :字元線之格間距單位之阻抗 SWL :選擇字元線 -34- 201117357 U S W L :非選擇字元線 S B L :選擇位元線 U S B L :非選擇位元線 S M C :選擇記億格I -15- 201117357. Further, in the above-described setting and resetting, in the third resistance state, the variable resistance element is in a state of higher resistance than the reset state, so that the reverse bias current can be prevented from becoming large, and malfunction can be prevented. Fig. 6 is a view showing the relationship between the applied voltage of the memory cell and the obtained resistance 半导体 in the semiconductor memory device according to the first embodiment of the present invention. The horizontal axis represents the voltage applied to the voltage pulse of the memory cell, and the vertical axis represents the resistance of the resistance variable element. As shown in Fig. 6, the first resistance state (i.e., the set state) is a low resistance state. When a reset pulse is applied to the memory cell, the Joule heat causes the phase change material of the recording layer 6 to be heated above the melting point, and as indicated by the dotted arrow, the amorphous ratio is increased to cause high resistance. The resistance 値 of the second resistance state (i.e., the reset state) indicated by the point A is obtained by resetting the pulse. On the other hand, in the second state, by applying a voltage greater than the voltage V2 of FIG. 6 by the Joule heat, the phase change material of the recording layer 6 is heated to a temperature higher than the crystallization temperature, and the crystallization ratio of the phase change material of the recording layer 6 is increased. The first resistance state (ie, the set state) is returned as indicated by the dotted arrow. As described above, by applying a voltage to the memory, the first resistance state and the second resistance state are reversibly changed, and data can be memorized. The resistance 値 of the variable resistance element to which the defective selection element is connected is set to be equal to or higher than the threshold of the third resistance state of Fig. 6 . The threshold of the third resistance state means that the maximum voltage used for data storage, and the case where the reset voltage is applied to the memory cell, is not required to supply the Joule heat necessary for the crystallization of the phase change material. That is, the power required for the crystallization of the phase change material, and the lower limit of the resistance 第 of the third resistance state. When the resistance is less than -16 - 201117357 below this lower limit, the application of the reset pulse gradually progresses to crystallization, and the resistance change type element may become low resistance. Therefore, by setting the resistance 値 of the resistance variable element of the FC to the third resistance state of the threshold , or more, it is possible to prevent the memory of the FC from being reduced in resistance and to prevent malfunction of the device. As a result, a highly reliable non-volatile semiconductor memory device can be provided at a high yield, that is, at a low cost. Further, in order to further improve the reliability, by applying a higher voltage to the memory cell, the phase change material of the recording layer 6 is vaporized to form a void in the recording layer 6, and the resistance of the third resistance state is 値When the resistance is higher, the higher resistance of the variable resistance variable element can be achieved. Further, as described above, the recording layer 6 is a laminated film including a layer of a metal oxide and a layer containing a phase change material, and thus, the third resistor is compared with the recording layer 6 in which a layer containing a metal oxide is not provided. The state is more stable to thermodynamics, and the higher resistance of the variable resistance variable element can be realized. When the memory cell of the variable resistance element having the third resistance state is read, the resistance 値 based on the third resistance state is higher than the resistance 値 of the second resistance state, and thus is read as a high resistance state. For example, when the memory cell of the variable resistance element having the third resistance state is set, it is expected to be read as an erroneous high resistance state when it is read in the first resistance state. However, the error in the write operation of the memory cell of the third resistance state can be sufficiently corrected by applying the technique of the error correction code during recording and reproduction of information, and there is no problem. In addition, in the management area 1 0 1 2 of the memory cell array, the address of the memory cell of the resistance variable element having the third resistance state is saved, and according to the memory address information, the control unit -17-201117357 1 ο 1 0 When the data is written, the control can be performed to avoid writing in the third state. The third resistance state is achieved by applying a voltage pulse having a voltage 高于 higher than the reset voltage to the memory cell. Fig. 7 is a view showing a pattern of applied voltages of the respective bit lines and word lines when the resistance variable element included in the FC is shifted to the high resistance of the device in the third resistance state. As shown in FIG. 7 , voltage VFC (3.5 V in this case) can be applied to the diode of FC by applying voltages of 3.5 V, 0 V, 0 V, and 3.5 V to SWL, USWL, SBL, and USBL, respectively. The method of going forward is carried out. The voltage application is performed in accordance with the same pulse as the reset pulse of Fig. 3, and the rapid decrease is performed to rapidly cool the phase change material of the molten recording layer. The applied voltage to the FC is 3.5 V larger than 3.0 V at the time of the normal reset operation, so that the resistance of the resistance variable element of the FC can be set to a third resistance state higher than the reset state. Alternatively, a voltage VFC (in this case, 7 V) may be applied to the forward mode of the diode of the FC by applying, for example, 7 V, 0 V, OV, and 3.5 V to SWL, USWL, SBL, and USBL, respectively. Come on. In the case of this voltage condition, the potential difference between the two ends of the cell outside the FC in FIG. 8 is 0 V, and the reverse voltage of the normal diode of 3.5 V is applied in the reverse direction of the diode (this is 4 V) Small voltage, so no current flows. That is, the applied voltage of 7V is larger than the withstand voltage of the diode, and is selected to be within 2 times of the withstand voltage of the diode, and the applied voltage of 3.5V is itself within the withstand voltage of the diode, and The difference between the applied voltage and 7 V is also set within the withstand voltage of -18-201117357 diode. The action will be described using FIG. 1. Two of the power supplies 1003 to 1007 are respectively 7V and 3.5V power supplies. The reference voltage is set to 〇V, and the mode of Fig. 7 is made to operate the voltage selector 1008 and the wiring selector 1 009 in accordance with the control information of the control unit 1010, and the power supply is connected to the word line and the bit line. The control unit 1010 generates a voltage pulse from the power source to increase the resistance of the variable resistance element of the FC. In the FC, a large current flows due to the potential difference 7 v applied to both ends, and the phase change material of the recording layer of F C is melted. The rapid decrease of the applied voltage is performed, and the phase change material of the recording layer of F C is rapidly cooled to perform the high resistance operation of the variable resistance element to the third resistance state. In this embodiment, since the voltage higher than the withstand voltage of the diode of the selected element can be applied, the resistance 値 of the third resistance state of the variable resistance element can be set higher, so that the reset state can be expanded. The range in which the resistance is obtained is advantageous for, for example, using more than three different resistance states for multi-turn memory. Further, by the application of a high voltage, the phase change material of the recording layer 6 is vaporized to form a void in the recording layer 6, which is more advantageous in setting the third resistance state to a higher resistance 値. Fig. 9 is a view showing an operational sequence of high resistance of the variable resistance element in the third resistance state. First, the forward voltage of the diode is applied to the memory cell, and the resistance variable element of all the memory cells is made low-resistance (S 901). Thereafter, the reverse voltage of the diode is applied to select a memory cell with a leakage current greater than a certain threshold (S902), and a voltage (F) for a large leakage current is applied to the modal state shown in FIG. 7 or FIG. The resistance variable element of the FC becomes high resistance in the third resistance state (S 903 ). In S901 ' Borrowing -19-201117357, the resistance variable element of the hexagram is reduced in resistance, and the above-described influence of the variable resistance element is made small, so that the leakage current of the selected diode can be accurately determined. The resistor-variable element in which the diodes having a large OFF current (non-conduction current) is set to have a high resistance in the third resistance state is another configuration. Fig. 10 shows a pattern of voltages applied to respective bit lines and word lines for the third resistance state. In FIG. 10, for example, 0V, 〇V, 4V, and 4V are applied to the three boundaries 1^, 1; 51^1^, 381^, and USBL, that is, the VFC is set to 4V, not only the diode of the FC but also has The memory of the normal diode also applies a voltage of 4V to the reverse of the diode. In the memory cell having the normal diode, a voltage below the withstand voltage is applied in the reverse direction of the diode, and the current hardly flows into the memory cell, so that the resistance 値 of the resistance variable element does not change after the voltage is applied. Since the reverse withstand voltage of the FC' diode is low, a potential difference of 4 V applied across the terminals causes a large current 'phase change material of the recording layer 6 to be melted. When the rapid drop of the applied voltage causes the phase change material to be rapidly cooled, the resistance variable element of the FC can be made to have a high resistance in the third resistance state. By using this voltage condition, it is not necessary to select a cell having a large leakage current of the selected element, and it is possible to automatically cause the current to flow only into the FC and the resistance variable element to have a high resistance in the third resistance state. The operation timing is as shown in Fig. 11. The voltage is applied to the mode of Fig. 1 to increase the resistance of the variable resistance element of the FC (S1101). Therefore, it is possible to obtain a semiconductor memory device in which the resistance variable element of the FC is set to the third resistance state in a short period of time and operates normally. The high resistance operation of the defective cell can be performed by the control unit 1 〇 1 〇, -20-201117357, by operating the semiconductor device in the above-described individual modes. Further, in the manufacturing stage of the semiconductor memory device, by applying the voltage from the outside in accordance with the pattern shown in Figs. 7-11, the FC can be made high in resistance in the third resistance state. Fig. 12 is a view showing the effects of the first embodiment of the present invention. The non-volatile semiconductor memory device in which the resistance variable element of the FC is set to be high-resistance can significantly reduce the defect of the nonvolatile semiconductor memory device caused by the leakage current of the diode as compared with the case where the processing is not performed. A single crystal germanium diode having a low frequency of OFF current caused by crystal defects, metal contamination, or the like, and a transistor formed on a single crystal germanium substrate may also be used as a selection element, but as shown in FIG. The polycrystalline germanium diode or the oxide diode which can be multi-layered as shown in 3 or 14 is more effective as a selective element. (Second Embodiment) The second embodiment shows the use of a transistor as a selection element. Fig. 15 shows a memory cell in which a phase change memory used in the second embodiment is connected to a transistor. As shown in FIG. 15, the word line 2 is connected to the gate of the transistor, and the resistance change is sequentially formed on the lower electrode 8 of the variable resistance element electrically connected to the source or the drain signal line of the transistor. The recording layer 6 of the type element, the upper electrode 7 of the variable resistance element, and the bit line 3. The variable resistance element of the semiconductor memory device of the first embodiment is replaced with a diode by a diode, and is formed into an array of cross-point types as shown in Fig. 16 to achieve high density. I. "21 - 201117357 As shown in Figure 16. When you want to select 1 cell from the memory cell array, the word line (SWL: select word line) connected to the selection cell is not selected. The character line connected by the cell (USWL: non-selected word line), the bit line connected to the selection cell (SBL: select bit line), the bit line not connected by the selected cell (USBL: non-selected bit line) For example, voltages of 2V, OV, IV, and 0V are applied, respectively. The electron crystal system was chosen to use an N-channel transistor. When the gate potential of the transistor is selected to be 0 V, almost no leakage current flows, and only the current flowing through the SMC is selected. Therefore, the resistance state can be judged by the measurement of the sense amplifier. To select a cell from the memory cell array for setting operation, apply voltages of 3V, 0V, 1.5V, and 0V to SWL, USWL, SBL, and USBL, for example. At this time, the CellD (cell D) connected to USWL and USBL is based on USBL and the ground potential is OV and does not flow into the current. Further, the CellB to which the USWL and SBL are connected does not flow current based on the selection of the transistor being in the OFF state. The CellC (cell C) to which SWL and USBL are connected is based on the potential of the bit line and the ground potential, and no current flows. Only the grid SMC inflow current is selected, and the Joule heat causes the phase change material to be heated. The voltage applied to the selected bit line and the selected word line may be a sufficient voltage to heat the phase change material of the selected cell to the crystallization temperature. When a sufficient time (about 1 Γ 6 seconds or more) is applied for the crystallization, the resistance variable element of the cell is selected, and the phase change material of the recording layer 6 is crystallized to become the first resistance state of the low resistance. The state of the other cells is not changed. To select a cell from the memory cell array for reset operation, apply -22-201117357 SWL 'USWL 'SBL, USBL, for example, 3V, 0V, 2V, 〇V At this time, the CellD connected to USWL and USBL is based on USBL and the ground potential is 〇V and no current flows. In addition, the CellB connected to USWL and SBL is based on the selected transistor. The current does not flow in. The CellC (cell C) to which SWL and USBL are connected does not flow current based on the bit line potential and the ground potential. Only the cell SMC inflow current is selected, and the Joule heat causes the phase change material to be heated. Selecting the bit line and selecting the voltage of the word line may be sufficient voltage to heat the phase change material of the selected memory cell to a temperature above the melting point. The voltage is applied to 0 V, and the phase change material is rapidly cooled. The phase change material of the recording layer 6 of the selected cell is in an amorphous state with high resistance, and the variable resistance element is in the second resistance state. The state of the other cells is not changed. The cell to be selected is correctly performed. Since the read operation and the set/reset operation operate within the withstand voltage of the transistor of the selected device, the leakage current, that is, the current in the OFF state is extremely small. It is assumed that the read operation of CellA (A) in FIG. At the time of the voltage drop of the RBL, the SBL potential V of the CellB becomes positive, and a large leakage current is generated when the current of the OFF state of the selected transistor of CellB is large. The magnitude of the leakage current is due to the resistance variable element of CellB. The state of the resistance, that is, the state of the information to be recorded varies. Therefore, even if the Icell flowing into CellA is the same, the current Iread discriminated by the sense amplifier changes with the state of CellB, and the readout becomes a malfunction. Therefore, 'and the first Similarly, in the embodiment, the leakage current needs to be set to be smaller than the read current when at least the malfunction is not caused. -23- 201117357 Similarly, the CellB selection in the setting/resetting operation of CellA in Fig. 16 When the current in the OFF state of the device is large, a large current flows in CellB, and the voltage drop caused by RBL causes the SBL potential of CellA to become lower than 1.5V (set time) and 2V (at reset). As a result, for CellA The setting/resetting action may not be performed normally. As described above, when the memory cell (FC) of the selection element having a large current with an OFF state exists in the memory cell array, not only the FC but the old joint FC is connected to the same bit line. Other normal reading, setting/resetting operations also cause malfunctions, and the overall defect rate of the semiconductor memory device is significantly increased. In order to prevent the failure of the memory cell other than the FC, the resistance variable element included in the FC is made high-resistance. In this case, as in the case of the first embodiment, the resistance variable element included in the FC is set to the third resistance state β. As in the first embodiment, the leakage current of the selected element of the FC is read. The malfunction was solved. Further, similarly to the first embodiment, the malfunction caused by the memory cell of the third resistance state can be sufficiently corrected by the technique of applying the error correction code during the information reproduction, and this does not become a problem. In addition, in the management area 1 〇 1 2 of the memory cell array, the address of the sigma grid of the resistance variable element having the third resistance state is stored, and the control unit 1 〇 1 〇 can be controlled according to the memory address information. When data is written, writing is performed while avoiding the memory cell in the third resistance state. The high resistance of the variable resistance element included in the FC is as shown in Fig. 17. The VFC is applied by applying voltages of 3V, 0V, 2.5V, and 0V to SWL, USWL, SBL, and USBL, respectively. The following is 2.5V) applied to the FC. The voltage application is performed according to the pulse of -24-201117357, which is the same as the reset pulse of Fig. 1, and the rapid decrease is made so that the molten phase change material is rapidly cooled. The applied voltage to the FC is greater than the 2.0V at the time of the normal reset operation, so the current is also larger than in the normal reset operation. Therefore, the resistance of the phase change element of the FC can be set to a third resistance state higher than the reset state. Fig. 18 shows the entire operation sequence. First, the gate voltage of the selected transistor is set to the ON state, and a voltage is applied to both ends of the memory cell, and the resistance variable element in which all the memory cells are set is reduced in resistance (S1 801). Thereafter, the transistor is turned OFF, the gate voltage of the selected transistor is set, a voltage is applied to both ends of the memory cell, and a memory cell having a leakage current greater than a certain threshold is selected (S 18 02). When the transistor is turned on, the gate voltage of the selected transistor of the memory cell FC having a large leak current is set, and a voltage is applied to both ends of the memory cell, and the resistance variable element of the memory cell is set to have a high resistance in the third resistance state. (S 1 803). In order to make the resistance change element in which the transistor having a large OFF current is set to have a high resistance in the third resistance state, the voltage condition shown in Fig. 19 can be used. In Fig. 19, it is a pair of 8\^1^, 1^\\^, 361^, 1; 38 [applying, for example, 〇V, 0V, 2.5V, 2.5V, not only FC, but also has a normal selection transistor. The memory cell also applies a voltage of 2.5V to both ends of the memory cell. In the memory cell with a normal selection transistor, based on the gate voltage of 0V, the current hardly flows into the memory cell, so the resistance 値 of the resistance variable element does not change after the voltage is applied. In FC, the OFF current of the selected transistor is large, and therefore, a large current is caused by the potential difference of 2.5 V applied across the both ends to melt the phase change material of the recording layer. The sudden drop in the applied voltage causes the phase change material -25-201117357 to be rapidly cooled. Thus, the variable resistance element can be changed to the third resistance state. By using this voltage condition, it is not necessary to select the cell with a large OFF current of the selected transistor. 'It is possible to automatically cause the current to flow only into the FC and the resistance variable element to be the third resistor state." As shown in Fig. 20, a voltage is applied in the mode of Fig. 19. On the other hand, the variable resistance element of the FC is made high-resistance (S2001). The high resistance operation of the defective cell is performed in the same manner as in the first embodiment, and the semiconductor memory device can be operated in the above-described individual mode by the control unit 1010. Further, the application of the voltage from the outside can also increase the resistance of the FC to the third state. The method of the present embodiment can also be used as shown in Fig. 21 for a polycrystalline germanium transistor or an oxide transistor as a selective element for a laminated phase change memory cell array. (Third Embodiment) The third embodiment shows an embodiment in which the control unit 1 〇 1 保存 stores the management area 1 〇 12 of the address of the memory cell in the third resistance state. The control unit 1 〇1 〇, as shown in Fig. 22, divides the cell into a group consisting of one or a plurality of cells, and sets the memory cell included in the group for each of the allocated memory management regions. When the state of the three states is high, the information is recorded in the management area 1012. 23 to 25 show the sequence of the control unit in the third embodiment. When the diode is used as the selection element, the sequence of Fig. 23 can be used in accordance with the operation sequence of Fig. 9 of the first embodiment -26-201117357. By setting the resistance variable element of the FC to the high resistance of the third resistance state (S2301, S2302, S2303) in the same sequence as in FIG. 9, the address of the FC is recorded in the memory management area of the group including the FC ( S23〇4). Further, the sequence of Fig. 24 can be used in accordance with the operation sequence of Fig. 11 in the first embodiment. By applying a forward voltage of the diode to the memory cell, the resistance variable element of all the memory cells is set to have a low resistance (S240 1 ), and then the resistance change type of the FC is set by the same sequence as that of FIG. After the device has a high resistance in the third resistance state (S 2 402), the memory cell is normally read, and the memory cell with high resistance is judged as FC (S2403), and the address of the FC is recorded in the FC. The memory management area of the group (S2404). The reason why S241 sets the resistance of all the memory cells to the low-resistance type is to judge the high resistance state of S2404 as the defective memory cell FC. When a transistor is used as the selection element, the sequence of Fig. 25 can be used corresponding to the operation sequence of Fig. 18 of the second embodiment. In the same manner as in Fig. 18, after setting the resistance variable element of all the cells to reduce the resistance (S25 0 1 ), the defective cell FC is selected (S25 02) 'The resistance variable element of the FC is set to the third resistance state. After the resistance (S 2 5 03 ), the address of the FC is recorded in the memory management area (S 2504) of the group including the FC. Further, the sequence of Fig. 26 can be used in accordance with the operation sequence ' of Fig. 20 of the second embodiment. After the resistance variable element of all the memory cells is set to have a low resistance (S 2 6 0 1 ), the resistance variable element having the same sequence as that of FIG. 21 is set to have a high resistance in the third resistance state (S2602). After m -27-201117357, the normal reading operation of the memory cell is performed, and the memory of the high resistance is judged as FC (S2603), and the address of the FC is recorded in the management area of the group containing the FC ( S2604). In S2601, the resistance variable element in which all the memory cells are set is reduced in resistance, and the state in which S2604 is in the high resistance state is determined as the defective memory cell FC. After the address information of the FC is recorded in the same sequence, the method of not using the FC is set when the normal information is rewritten or read, and the data can be correctly memorized. In addition, it is important to set the memory of the memory management area to be used without any defects. The same memory cell group in FIG. 22 may include a memory cell physically located in a close position, for example, a cell in the same address, but may also be selected by a plurality of individual cells in the chip. The memory cells are assigned to the same memory group. (Fourth Embodiment) In the third embodiment, the memory cells of the normal data are not distinguished from the memory cells of the management area. However, the two may be physically different as shown in the fourth embodiment. The memory of the hexagram structure is set to create a memory cell in a physically different position. For example, a memory cell for storing a general data requiring a large capacity is made of a small capacity by the configuration shown in Figs. 13, 14, and 21. Alternatively, it is necessary to form a memory cell having no defective management area, and it can be fabricated by using a transistor formed on the germanium substrate as a selection element as shown in FIG. In addition, the memory cell used to record the general data that requires a large capacity is -28-201117357. It is made by the second layer and the lower layer from the top of Figure 14 and 21. The small capacity can be used but it needs to form a management area without defects. The memory cell can be fabricated by the uppermost layer of Figure 14 and 2 of the process with a small thermal load. In this embodiment, the data can be correctly memorized. (Fifth Embodiment) The fifth embodiment shows a semiconductor memory device in which a resistance variable element included in an FC of the semiconductor memory device according to the first embodiment is applied with a voltage applied from a voltage outside the semiconductor memory device. Manufacturing method. Figure 27 shows the process. In the semiconductor memory device of the first embodiment, the bit line, the word line, and the electrode are connected externally, and the first detection voltage is applied to the memory cell in the reverse direction of the diode, and the leakage current of the diode is measured.値 (S 270 1 ). Further, similarly to the first embodiment, the forward voltage of the diode is applied to the memory cell, and the resistance variable element is set to have a low resistance, so that the leakage current 可以 can be accurately determined. When the leakage current of the diode is equal to or higher than the first specific current ( (S 2702), that is, FC, the voltage applied to the memory cell including the diode is higher than the set pulse and the reset pulse. 3 Voltage pulse, set the resistance variable element to high resistance (S 27 0 3 ). The first specific current 値 can be set, for example, to the leakage current 正常 of the normal diode. Further, as described above, when the semiconductor memory device of the first embodiment is manufactured by the 5 Onm generation process, the read current is about 1 μA (microamperes). Therefore, in this case, the first specific current 値 can be set to 1 μA. When it is desired to set the process to be more accurate, the second detection voltage is applied to the forward direction of the diode for the memory cell to which the third voltage pulse is applied. -29-201117357, and the current flowing in the current is measured. (S 2704). When the current 値 of the current flowing in when the second detection voltage is applied is equal to or higher than the second specific current ( (S2705), the memory cell to which the third voltage pulse is applied is applied with a higher voltage than the third voltage pulse. In the fourth voltage pulse, the resistance variable element is set to have a higher resistance (S2706). In this case, the ratio of the voltage 値 of the second detection voltage to the second specific current 値 is set to be the voltage 値 of the maximum voltage among the voltages used for recording by the semiconductor memory device, that is, the reset voltage. The ratio of the voltage 値 to the first specific current 値 is a greater relationship. When the fourth voltage pulse is applied, the voltage pulse is applied to the memory cell at a higher voltage, and the resistance variable element is set to have a higher resistance. According to the manufacturing method of the embodiment, when the semiconductor memory device is applied The maximum voltage among the used voltages is recorded. When the reset voltage is applied, the current flowing into the FC is less than the first specific current 値. That is, by satisfying the above relationship, the resistance variable element of the FC can be set such that even when a reset voltage is applied to F C , only a high resistance state of a current smaller than the second specific current 流入 flows. For example, by setting the first specific current 値 to the leakage current 正常 of the normal diode, the FC can only flow a current smaller than the leakage current of the normal diode by the setting operation and the reset operation. In this case, the phase change material of the recording layer 6 of the variable resistance element of F c does not reach the crystallization temperature by the setting operation or the reset operation, and the resistance variable element can be prevented from being in a low resistance state. In other words, the semiconductor memory device can be manufactured such that the resistance of the resistance variable element of the FC is -30-201117357 以满足 to satisfy the condition of the third resistance state of the first embodiment. Further, for example, when the first specific current 値 is used as the read current, it is also possible for the FC to flow only a current smaller than the read current by the setting operation and the reset operation. Therefore, the phase change material of the recording layer 6 of the resistance variable element of the FC does not reach the crystallization temperature by the setting operation or the reset operation, and the resistance variable element can be prevented from being in a low resistance state. In other words, the semiconductor memory device can be manufactured such that the resistance of the resistance variable element of the FC is set to satisfy the condition of the threshold of the third resistance state shown in the first embodiment. As described above, according to the manufacturing method of the present embodiment, it is possible to prevent the malfunction of the device in which the resistance variable element of the FC is caused by the low resistance state, which is a semiconductor device capable of high yield and high reliability. (Industrial Applicability) The nonvolatile semiconductor memory device of the present invention can be applied to a memory device for a small mobile information device such as a mobile personal computer or a digital camera. (Effect of the Invention) According to the present invention, it is possible to provide a large-capacity 'high-performance and high-reliability non-volatile semiconductor memory device with high yield and low cost. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a semiconductor memory device of the present invention. -31 - 201117357 Fig. 2 is a perspective view of the memory cell array of the present invention. Fig. 3 is an explanatory view showing the high resistance and low resistance of the phase change of the phase change of the present invention. Figure 4 is a circuit diagram showing the description of the read operation of the memory cell array of the present invention. Fig. 5 is a circuit diagram showing the setting operation and the reset operation of the Jiage array according to the present invention. Fig. 6 is an explanatory view showing the high resistance and low resistance operation of the phase change memory of the present invention. Fig. 7 is a circuit diagram showing a high resistance operation of a defective cell used in an example of the first embodiment of the present invention. Fig. 8 is a circuit diagram showing a high resistance operation of a defective cell used in an example of the first embodiment of the present invention. Fig. 9 is a sequence diagram showing the operation of an example of the first embodiment of the present invention. Fig. 10 is a circuit diagram showing a high resistance operation of a defective cell used in an example of the first embodiment of the present invention. Fig. 1 is a sequence diagram showing the operation of an example of the first embodiment of the present invention. Fig. 1 is a view showing the effect of the first embodiment of the present invention. Fig. 13 is a perspective view of a memory cell array to which the first embodiment is applicable. Fig. 14 is a perspective view of a memory cell array to which the first embodiment is applicable. Fig. 15 is a cross-sectional view showing a memory array in which memory cells having a series structure of a transistor and a variable resistance element are arranged at intersections. -32- 201117357 Figure 16 is the read operation of the memory cell array of Figure 15. The circuit diagram of the description of the set operation and reset operation. Fig. 17 is a circuit diagram showing a high resistance operation of a defective cell used in an example of the second embodiment of the present invention. Fig. 18 is a sequence diagram showing the operation of an example of the second embodiment of the present invention. Fig. 19 is a circuit diagram showing a high resistance operation of a defective cell used in an example of the second embodiment of the present invention. Figure 20 is a sequence diagram showing the operation of an example of the second embodiment of the present invention. Fig. 21 is a perspective view of a memory cell array to which the second embodiment is applicable. Fig. 22 is a memory block diagram showing an example of a semiconductor memory device according to a third embodiment of the present invention. Figure 23 is a sequence diagram showing the operation of an example of the third embodiment of the present invention. Figure 24 is a sequence diagram showing the operation of an example of the third embodiment of the present invention. Figure 25 is a sequence diagram showing the operation of an example of the third embodiment of the present invention. Figure 26 is a sequence diagram showing the operation of an example of the third embodiment of the present invention. Figure 27 is a sequence diagram showing the operation of an example of the fifth embodiment of the present invention. [Description of main component symbols] 1 : Semiconductor substrate (矽 substrate) 2 : Word line 3 : Bit line 4: p-type polycrystalline germanium, or p-type semiconductor oxide, etc. p-type semiconductor -33- 201117357 5: η type Π-type semiconductor layer 6 such as polycrystalline sand or n-type semiconductor oxide: recording layer 7 of variable resistance element: upper electrode 8 of resistance variable element · lower electrode of resistance variable element 9: p-type semiconductor interface Barrier metal, or germanium 1 阻 · · n-type semiconductor interface barrier metal, or germanium 2 1 , 2 2 : gate insulating film 1 0 0 : plate electrode 101: well 1 1 1 : source line 1 1 2 : Electrode 1 00 1 : I/O interface 1 0 0 2 : Memory cell array 1003 to 1007: Power supply 1 008 : Voltage selector 1 009 : Wiring selector 1 0 1 0 : Control unit 1 0 1 1 : The reading unit 1012: the management area Dif: the diffusion layer RB L : the impedance of the bit line of the bit line RWL : the spacing of the word line spacing unit SWL : the selected word line -34 - 201117357 USWL : the non-selected character Line SBL: Select bit line USBL: Non-select bit line SMC: Select remember

CellA :選擇字元線、選擇位元線記憶格（選擇記憶格） CellB :非選擇字元線、選擇位元線記憶格 CellC :選擇字元線、非選擇位元線記憶格 CellD :非選擇字元線、非選擇位元線記憶格 FC :具有大漏電流之選擇元件的記憶格： SenseAmp:感測放大器 V r e a d :讀出時之記億格施加電壓 V s et :設定時之記憶格施力口電壓 Vreset :重置時之記憶格施加電壓 Icell :讀出時選擇格電流CellA: Select word line, select bit line memory cell (select memory cell) CellB: non-select word line, select bit line memory cell CellC: select word line, non-select bit line memory cell CellD: non-selection Word line, non-selected bit line memory cell FC: Memory cell with selected components with large leakage current: SenseAmp: sense amplifier V read : remembered voltage when read out V s et : memory when set Shili port voltage Vreset: memory cell applied voltage Icell when reset: select grid current when reading

Iread :讀出時感測放大器電流 Iset :設定時選擇格電流 Ireset :重置時選擇格電流 VON :設定選擇元件電晶體之通道成爲ON狀態時之 閘極電壓 VOFF :設定選擇元件電晶體之通道成爲OFF狀態時 之聞極電壓 VFC :設定FC之電阻變化型元件成爲高電阻化時之 記憶格施加電壓 VFCUSWL :設定FC之電阻變化型元件成爲高電阻化 -35- 201117357 時之USWL施加電壓 VFCUSBL:設定FC之電阻變化型元件成爲高電阻化 時之USBL施加電壓 -36-Iread : sense amplifier current Iset when reading: select grid current Ireset when setting: select grid current VON when reset: set the gate voltage VOFF when the channel of the selected component transistor is turned ON: set the channel of the selection component transistor When the voltage is changed to the OFF state, the voltage VFC is set to the voltage of the device. VFCUSWL is set when the resistance variable element of the FC is set to a high resistance. The resistance variable element of the FC is set to a high resistance. -35-201117357 USWL applied voltage VFCUSBL : Setting the resistance variable element of the FC to the USBL applied voltage when the resistance is high -36-

Claims (1)

201117357 七、申請專利範圍 1. 一種半導體記憶裝置，其特徵爲： 具備： 複數第1配線； 複數第2配線，和上述複數第1配線呈交叉；及 複數記憶格，被配置於上述複數第1配線與上述複數 第2配線之交叉點； 上述複數記憶格之各個，係由電阻變化型元件與二極 體串聯連接而構成； 上述電阻變化型元件係具有包含相變化材料之記錄 層，上述電阻變化型元件，係可以獲得：第1電阻狀態； 第2電阻狀態，具有較上述第1電阻狀態之電阻値爲高的 電阻値：及第3電阻狀態，具有較上述第2電阻狀態之電 阻値爲高的電阻値； 藉由對上述記憶格施加第1電壓脈衝，藉由焦耳熱使 上述第1電阻狀態之電阻變化型元件之相變化材料加熱至 融點以上，增加上述相變化材料之非晶質相之比例而遷移 至上述第2電阻狀態，藉由對上述記憶格施加較上述第1 電壓脈衝低的第2電壓脈衝，藉由焦耳熱使上述第2電阻 狀態之電阻變化型元件之相變化材料加熱至結晶化溫度以 上，增加上述相變化材料之結晶相之比例而遷移至上述第 1電阻狀態，據此而進行資料之記憶； 上述第3電阻狀態之電阻値爲，即使對具有上述第3 電阻狀態之上述電阻變化型元件的上述記憶格施加上述第 -37- 201117357 1電壓脈衝情況下，亦不會產生使上述相變化材料設爲結 晶化溫度之焦耳熱的電阻値； 上述複數記憶格之中漏電流値達特定値以上的，具有 上述二極體之記憶格之上述電阻變化型元件，係處於上述 第3電阻狀態。 2.如申請專利範圍第1項之半導體記憶裝置，其中 上述相變化材料，係包含Ge(鍺）、Sb(銻）、Te(碲）。 3·如申請專利範圍第1項之半導體記憶裝置，其中 上述電阻變化型元件係具有：包含金屬氧化物之層與 包含相變化材料之層的積層構造。 4. 如申請專利範圍第1項之半導體記億裝置，其中 上述特定之漏電流値爲1μΑ(微安培）。 5. —種半導體記憶裝置，其特徵爲： 具有記憶格陣列； 上述記憶格陣列之記憶格之各個，其之電阻變化型元 件與選擇元件係被連接而構成； 上述電阻變化型元件係具有包含相變化材料之記錄 層； 上述電阻變化型元件，係至少存在：第1電阻狀態； 第2電阻狀態，具有較上述第1電阻狀態之電阻値爲高的 電阻値；及第3電阻狀態，具有較上述第2電阻狀態之電 阻値爲高的電阻値； 於上述記憶格內存在： 第1記憶格，其藉由施加重置脈衝使上述電阻變化型 -38- 201117357 元件由上述第1電阻狀態遷移至上述第2電阻狀態，藉由 施加設定脈衝使上述電阻變化型元件由上述第2電阻狀態 遷移至上述第1電阻狀態，依此而進行資料之記憶；及 第2記憶格，其之施加有上述重置脈衝的上述記憶格 之上述電阻變化型元件係處於上述第3電阻狀態，而且， 施加有上述設定脈衝的上述記憶格之上述電阻變化型元件 係處於上述第3電阻狀態。 6.如申請專利範圍第5項之半導體記憶裝置，其中 於上述記億格陣列中具有管理區域； 於上述管理區域’係被記憶有上述第2記憶格之位 址。 7如申請專利範圍第6項之半導體記憶裝置，其中 具有控制部； 上述控制部係依據上述管理區域所記憶之上述第2記 億格之位址資訊’來決定資料之記憶所使用之上述記憶 格。 8. 如申請專利範圍第5項之半導體記憶裝置，其中 上述相變化材料’係包含Ge(鍺）' sb(銻）、Te(碲）。 9. 如申請專利範圍第5項之半導體記憶裝置，其中 上述選擇元件爲二極體。 1 〇·如申請專利範圍第5項之半導體記憶裝置，其中 上述選擇元件爲電晶體。 11. 一種半導體iE憶裝置之製造方法，其特徵爲具備： 準備半導體記憶裝置之工程，該半導體記憶裝置，係 -39- 201117357 具有記憶格陣列， 上述記憶格陣列之記億格之各個，其之電阻變化型元 件與二極體係被串聯連接而構成， 上述電阻變化型元件係具有包含相變化材料之記錄 層， 藉由對上述記憶格施加設定脈衝與重置脈衝而進行資 料之記憶者； 針對上述記憶格，於上述二極體之逆向施加第1檢測 用電壓，測定上述二極體之漏電流値的工程；及 對上述記憶格施加電壓値較上述重置脈衝高的第3電 壓脈衝之工程，該記憶格係包含上述漏電流値爲第1特定 電流値以上之上述二極體者。 12-如申請專利範圍第11項之半導體記億裝置之製 造方法，其中 具有： 對施加有上述第3電壓脈衝的記億格，針對在上述二 極體之順向施加第2檢測用電壓所流入之電流之電流値進 行測定的工程：及 當施加上述第2檢測用電壓而流入之電流之電流値爲 第2特定電流値以上時，將電壓値較上述第3電壓脈衝高 的第4電壓脈衝，施加於被施加有上述第3電壓脈衝的記 憶格之工程； 上述第2檢測用電壓之電壓値與上述第2特定電流値 之比之値’係大於上述重置脈衝之電壓値與上述第1特定 -40- 201117357 電流値之比之値。 13.如申請專利範圍第1 1項之半導體記憶裝置之製 造方法，其中 上述第1特定電流値爲1 μ A。 -41 -201117357 VII. Patent application scope 1. A semiconductor memory device comprising: a plurality of first wirings; a plurality of second wirings intersecting with said plurality of first wirings; and a plurality of memory cells arranged at said plural first a cross between the wiring and the plurality of second wirings; wherein each of the plurality of memory cells is formed by connecting a resistance variable element and a diode in series; and the variable resistance element has a recording layer including a phase change material, and the resistor The variable element is: a first resistance state; a second resistance state having a resistance 较 higher than the resistance 上述 of the first resistance state: and a third resistance state having a resistance 较 higher than the second resistance state a high resistance 値; by applying a first voltage pulse to the memory cell, the phase change material of the resistance variable element of the first resistance state is heated to a melting point or higher by Joule heat, thereby increasing the non-phase change material The ratio of the crystal phase shifts to the second resistance state, and the second memory pulse is applied to the memory cell to be lower than the first voltage pulse. a voltage pulse, wherein the phase change material of the variable resistance element in the second resistance state is heated to a crystallization temperature or higher by Joule heat, and the ratio of the crystal phase of the phase change material is increased to migrate to the first resistance state, thereby And storing the data; the resistance 値 of the third resistance state is such that even when the voltage pulse of the -37-201117357 1 is applied to the memory cell of the variable resistance element having the third resistance state, a resistor 値 that generates Joule heat having the phase change material as a crystallization temperature; wherein the resistance variable element having the memory cell of the diode is greater than or equal to a specific 値 in the plurality of memory cells The third resistance state described above. 2. The semiconductor memory device of claim 1, wherein the phase change material comprises Ge (锗), Sb (锑), Te (碲). 3. The semiconductor memory device according to claim 1, wherein the variable resistance element has a laminated structure including a layer of a metal oxide and a layer containing a phase change material. 4. For the semiconductor device of claim 1, the specific leakage current 値 is 1 μΑ (microamperes). 5. A semiconductor memory device, comprising: a memory cell array; each of the memory cells of the memory cell array, wherein the variable resistance element and the selection element are connected; wherein the resistance variable element has a recording layer of a phase change material; the resistance variable element having at least a first resistance state; a second resistance state having a resistance 较 higher than a resistance 上述 of the first resistance state; and a third resistance state having a resistor 値 higher than the resistance 値 of the second resistance state; wherein the memory cell has: a first memory cell, wherein the resistor-type-38-201117357 component is caused by the first resistor state by applying a reset pulse Moving to the second resistance state, the resistance variable element is transferred from the second resistance state to the first resistance state by applying a set pulse, thereby storing data; and the second memory cell is applied The resistance variable element of the memory cell having the reset pulse is in the third resistance state, and is applied Above the above-described variable resistance element based memory cell of the set pulse is in the third resistance state. 6. The semiconductor memory device of claim 5, wherein the management area is provided in the above-mentioned memory array; and the address of the second memory cell is stored in the management area. 7. The semiconductor memory device of claim 6, wherein the control unit has a control unit; and the control unit determines the memory used for memory of the data based on the information of the second address of the second memory stored in the management area. grid. 8. The semiconductor memory device of claim 5, wherein the phase change material 'includes Ge(锗)' sb(锑), Te(碲). 9. The semiconductor memory device of claim 5, wherein the selection element is a diode. The semiconductor memory device of claim 5, wherein the selection element is a transistor. A method of manufacturing a semiconductor iE memory device, comprising: a project for preparing a semiconductor memory device, wherein the semiconductor memory device has a memory cell array, and each of said memory cell arrays The variable resistance element and the two-pole system are connected in series, and the variable resistance element has a recording layer including a phase change material, and the data is stored by applying a set pulse and a reset pulse to the memory cell; In the memory cell, a first detection voltage is applied to the diode in a reverse direction, and a leakage current 値 of the diode is measured; and a voltage 値 is applied to the memory cell, and a third voltage pulse is higher than the reset pulse. In the project, the memory cell includes the diode having the leakage current 値 above the first specific current 値. [12] The method of manufacturing a semiconductor device according to claim 11, wherein: the second detection voltage is applied to the forward direction of the diode for the third voltage pulse to which the third voltage pulse is applied The current of the current flowing in the current measurement : and the fourth voltage that is higher than the third voltage pulse when the current 値 of the current flowing in the second detection voltage is equal to or higher than the second specific current 値a pulse applied to a memory cell to which the third voltage pulse is applied; a ratio of a voltage 値 of the second detection voltage to the second specific current 値 is greater than a voltage 上述 of the reset pulse The first specific -40 - 201117357 ratio of current 値. 13. The method of fabricating a semiconductor memory device according to claim 11, wherein the first specific current 値 is 1 μA. -41 -
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