201115782 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種發光二極體(light emitting diode，以下簡稱 為LED)之製作方法，尤指一種可降低材料間應力之LED製作方法。 【先前技術】 發光二極體因具有低耗電、體積小以及安裝容易等優點而大量 應用於照明光源以及顯示器技術中。而在led中，三族氮化物，如 氮化鎵(GaN)、氮化鋁鎵(AlGaN)、氮化銦鎵(inGaN)與氮化鋁銦鎵 (AlInGaN)等因寬能隙、高發光效率以及幾乎涵蓋整個可見光範圍的 優點，在發光元件中扮演著重要的角色。 請參閱第1圖與第2圖，第1圖與第2圖係為一習知LED之剖 面示意圖，主要包含上述氮化鎵系列的半導體材料之習知LED1〇〇 φ 通常成長於藍寶石(sapphire)或碳化石夕(SiC)等基板上，如第1圖所 示，習知LED係於一藍寶石基板1〇2上依序全面性形成一緩衝層 104、一 η型磊晶層1〇6、一活性層(active layer) 1〇8、一 p型磊晶層 110、一接觸層112。接下來如第2圖所示，再形成一 n型電極114 與一 ρ型電極116，最後利用切割製程分離各個獨立的LED 1〇〇。 然而，由於緩衝層、磊晶層與活性層等半導體材料層所包含之氮化 鎵的晶格常數(lattice constant)與藍寶石基板102的晶格常數差異超 過·，因此當前述氮化鎵系列的半導體材料層利用蟲晶製程成長 201115782 於藍寶石基板1〇2時，常因為蟲晶層與基板間因晶格不匹配(lattice mismatch)，導致蟲晶層中形成大量的缺陷，例如差排(disi〇cati〇n)。 且差排會隨著成長的磊晶層厚度增加而加以延伸並累積應力(s杜ah stress)，而材料間應力的影響會降低LED的光電效能、操作性能與 使用壽命。熟習該項技藝之人士應知，材料_應力會循應力釋放 邊界(strain release boundary)釋放，而應力釋放邊界容易出現在led 的邊緣；因此在切赚程前各半導體㈣層内部無轉放的應力會 累積於蠢晶射，至終會造成裂縫(⑽ek)的產生，以作為應力的釋 放管道，而裂縫的產生甚至會造成LED的失效。 因此，驾头口技術莫不以降低蟲晶層中的差排密度繼而降低應力 的累積為目標加以研究。舉例來說，考慮到設置於蟲晶層應與藍 寳石基板102中間的緩衝層1()4涉及異質成長㈣啊咖麵目歷也) 的特性’習知技術係以改善緩衝；| 1G4的成紐術如细有機金屬 化學氣相沈積法(metal-organic chemiealvapw ，m(x：vd) 形成氮化織衝層或氮化鎵緩衝層，或製作多層超晶格(亭舰㈣ 結構作為緩衝層等方法嘗試獲得較高品質触晶層。或者如第i圖 所示’於緩衝㈣4上形成複數條阻擋結構118，_ _結構ιι8 截斷差排，使緩衝層KH内的差排無法向上延伸至蟲晶層ι〇6、ιι〇 與活性層_巾，即所謂触晶側向成長_itaxiallateral ’ EL0G) ’·但助㈣然無法避免阻擔結構ιΐ8的間隙 120部分處的η型蟲晶層1〇6產生密集的差排及應力的累積。另外， 習知技術甚或有在晶層1G6中加入—裂縫阻擋層（圖未示） 201115782 之設置，用以阻擋差排在磊晶層中延伸。 ° 7___的上述方法除需增加製 μ戈 飾臨錢餘雜且騎触賴制，以及各膜 構的均勻度與統不易控制等問題，導致製程控管困難、生 降似穌提高祕點；且加設於LED⑽201115782 VI. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a light emitting diode (LED), and more particularly to an LED manufacturing method for reducing stress between materials. [Prior Art] Light-emitting diodes are widely used in illumination light sources and display technologies due to their advantages of low power consumption, small size, and ease of installation. In LED, three groups of nitrides, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (inGaN), and aluminum indium gallium nitride (AlInGaN), have wide energy gaps and high luminescence. Efficiency and the advantages of covering almost the entire visible range play an important role in the illuminating element. Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are schematic cross-sectional views of a conventional LED, and the conventional LED 1 〇〇 φ mainly containing the above-mentioned GaN series semiconductor materials is generally grown in sapphire (sapphire). Or on a substrate such as carbon carbide (SiC), as shown in Fig. 1, a conventional LED is formed on a sapphire substrate 1〇2 in a comprehensive manner to form a buffer layer 104 and an n-type epitaxial layer 1〇6. An active layer 1〇8, a p-type epitaxial layer 110, and a contact layer 112. Next, as shown in Fig. 2, an n-type electrode 114 and a p-type electrode 116 are further formed, and finally, the individual LEDs 1〇〇 are separated by a cutting process. However, since the lattice constant of the gallium nitride contained in the semiconductor material layer such as the buffer layer, the epitaxial layer, and the active layer is different from the lattice constant of the sapphire substrate 102, the gallium nitride series is The semiconductor material layer is grown by the insect crystal process 201115782. When the sapphire substrate is 1〇2, often due to lattice mismatch between the crystal layer and the substrate, a large number of defects are formed in the crystal layer, such as the difference (disi 〇cati〇n). The difference will be extended and accumulated stress (sho ah stress) as the thickness of the grown epitaxial layer increases, and the effect of stress between materials will reduce the photoelectric efficacy, operational performance and service life of the LED. Those skilled in the art should be aware that the material _ stress will be released by the strain release boundary, and the stress release boundary is likely to appear at the edge of the led; therefore, there is no transfer inside the semiconductor (four) layer before the cutting process. The stress will accumulate in the stray crystal, which will eventually cause the crack ((10) ek) to be generated as a stress release pipe, and the crack will even cause the LED to fail. Therefore, the driving technology does not aim to reduce the differential density in the insect layer and then reduce the accumulation of stress. For example, considering that the buffer layer 1 () 4 disposed between the wormhole layer and the sapphire substrate 102 is involved in the heterogeneous growth (four), the characteristics of the conventional technique are to improve the buffer; | 1G4 Inorganic techniques such as metal-organic chemiealvapw (m:vd) to form a nitrided woven layer or a gallium nitride buffer layer, or to make a multilayer superlattice (the pavilion (four) structure as a buffer Layers and other methods attempt to obtain a higher quality crystallographic layer. Or as shown in Fig. i, a plurality of barrier structures 118 are formed on the buffer (four) 4, and the _ _ structure ιι8 intercepts the difference rows, so that the difference rows in the buffer layer KH cannot be extended upward. To the insect layer ι〇6, ιι〇 and the active layer _ towel, the so-called contact lateral growth _itaxiallateral 'EL0G) '· but help (four) can not avoid the η type insect crystal at the 120 part of the gap of the structure ιΐ8 Layer 1〇6 produces dense rows and stress accumulation. In addition, the prior art even has a crack-blocking layer (not shown) set in the layer 1G6 to block the difference in the epitaxial layer. Extension. ° 7___ of the above method in addition to the need to increase the system Heteroaryl and money I ride Lai made contact, and the configuration of each film uniformity and control of the system difficult problems, leading to difficulties tube made programmable, like Jesus raw drop point increase secret; and adding disposed LED⑽
:内亦1可能降低LED的光學表現。因此，目前仍須—種有^降: 力、錢裂難生’且不過度增加製鋪誠之製作LED 的万法。 【發明内容】 b本發明之—目的係為提供—種可有效降低材料内部之應 力且不過度增加製程複雜度之LED製作方法及LED。 根據本發簡提供之申請專利糊係提供—種led，包含一 基板 a置於絲板±且暴露出部分該基㈣形成複數個裸露區 域之凸出_層、以及複數個設置於該等裸露區域喃立的島狀半 導體複合層。 、、根據本發明所提供之巾請專利範圍，更提供-種製作LED之方 法°玄方法首先提供—基板，隨後於該基板上形成-凸出圖案層， 且該凸出®朗縣露出部分該基板而軸複數備魏域，接下 來係於該等裸露區域内分卿成—駐之島狀半導體複合層。 201115782 根據本發明所提供的LED，係藉由形成於基板上的凸出圖案層 劃分基板上可形成半導體層之表面，而形成複數個裸露區域，並於 該等裸露區域内分別形成-獨立的島狀半導體複合層，藉由此一化 整為零的概念提升LED絲單麵積t應力釋放邊界的比例，增加 應力釋放的效率，故可降财複合針的應力，獲得無裂縫的 高品質半導體複合層。 【實施方式】 ❼閱第3圖至第7圖’第3圖至第7圖係為本發明所提供之 製作LED之方法之一較佳實施例之示意圖。首先請參閱第3圖與第 4圖，其中第4圖係第3圖_沿A_A，切線之剖面示意圖。如第3圖 與所示，本發明所提供之製作㈣之方法首先提供-基板202，基 板2〇2可包含藍寶石(saPPhire)、碳切(SiC)、⑦、氧化鋅(ZnO)、 乳化鎮(Mg〇)或石申化鎵(GaAs)等。接下來於基板搬上形成一凸出 圖案層204，凸出圖案層綱係可如第3圖所示，為一網格㈣也） 、如第4圖所示暴露出部分基板202而形成複數個裸露區域 (exposed regi〇n) 2〇6 〇 〇月繼續參閱第3圖與第4圖。如前所述，凸出圖案層204包含 _ 茶，而在本較佳實施例中，凸出圖案層204係以互相垂直 六 方式形成於基板2〇2上，因此本較佳實施例所提供之裸露區 域206係為正方形。但值得注意的是，凸出圖案層2〇4亦可以包含 、他鏤二圖_佈局方式設置於基板上 ，因此本發明之裸露區域 201115782 206亦可為矩形、菱形、六邊形、甚或圓形等，而不限於本較佳實 施例及圖式所揭露者。另外，凸出圖案層2〇4之高度Η係大於〇〇1 微米(micrometer，以下簡稱為μιη);其寬度w係大於2^m，而在 本較佳實施例中，各裸露區域2%之寬度D係介於5()〜2_哗。 此外，由於後、續製作LED其他膜層時製程的溫度限制，凸出圖 案層204必需能抵抗1〇〇〇。〇以上的高溫，而在本較佳實施例中，凸 出圖案層2〇4係包含-抗高溫材料，如介電材料：氧化石夕㈣）、氮 #化石夕_)或氮氡化石夕(SiON)等，利用化學氣相沈齡⑽士啊 deposition，CVD)如低壓化學氣相沈積(1〇w_pres麵chemicalvapw deposition ’ LPCVD)或電漿輔助式化學氣相沈積⑽.—— chemical vapOTdeposition，PECVD)等方法，並輔以圖案化步驟而形 成於基板202上，但不限於此。 請參閱第5圖。接下來，係於基板2〇2上依序形成一緩衝層 212、一 n型蟲晶層214、一活性層216與一 p型蟲晶層218，其中 _活性層216即為發光層，其可為多一重量子井(multiple卿_ well ’ MQW)結構。緩衝層212、η型蟲晶層214、活性層216與p 型磊晶層218係構成一島狀半導體複合層22〇。本較佳實施例中之 島狀半導體複合層220係包含三五魏化物等之半導體材料，較佳 為AlxGai-xN，且X值係大於〇·2。另外值得注意的是，由於遙晶成 長時會沿著基板材料成長的特性，因此緩衝層212、η型磊晶層214、 活性層216與晶層218將逐漸累積成長構成如第5圖所示之 複數個不相連接且彼此獨立的島狀半導體複合層22〇，故本發明中 201115782 所提供之包含有介電材料_出圖案層崩係直接作為各島狀半導 體複合層220的分界界線。由於本較佳實施例中之島狀半導體複合 層22〇所包含的各元件層及其適用之材料如三五族氮化物半導體材 料係為該領域中具通常知識者所熟知者，故於此係不再贅述。 請參閱第6圖。接下來於p型蟲晶層218上再形成一透明導電 層222，以避免電流壅塞(cr〇wding)。隨後係移除部分透明導電層 222'部分P型磊晶層218、部分活性層216與部分n型磊晶層21\， 而暴露出η型磊晶層214。隨後係如第6圖所示，於透明導電\ 222 與η型磊晶層214上分別形成一 η型電極224與一 ρ型電極。 請參閱第7圖。在形成島狀半導體複合層22〇與η型電極224 以及ρ型電極226後’係進行-切割製程，切割凸出圖案層2〇4與 基板202，用以形成複數個LED元件2〇卜由於凸出圖案層2〇4係 作為島狀半導體複合層220之分界線，因此在切割製程中凸出圖案 層204亦可作為切割道，而切割器材係直接切割凸出圖案層2〇4及 其所覆蓋之基板202，獲得LED元件200。 根據本發明所提供的LED之製作方法，係藉由形成於基板2〇2 上的凸出圖案層204將基板202劃分為複數個裸露區域2〇6，而各 裸露區域206内則分別形成一獨立的島狀半導體複合層22〇，因此 凸出圖案層204可說是作為後續形成的島狀半導體複合層22〇之分 界線，而各島狀半導體複合層220在進行後續切割製程之後成為各 LED元件。如前所述，由於LED半導體膜層中可釋放應力的應力 201115782 釋放邊界多出現在膜層的邊緣處，故提升應力釋放邊界與膜層邊緣 面積的百分比即可增加應力釋放的管道。舉例來說，習知技術中在 切割製程w為-整體晶圓的半導體複合層，其應力釋放邊界與整體 磊晶邊緣面積之比例百分比約為78% ;與習知技術相較，本案所提 供的LED製作方法係在切割製程前即將所欲取得的元件的各 半導體複合層以島狀形式形成於裸露區域内，藉由此一化整為零的 概念將應力釋放邊界與單體磊晶面積之比例百分比提升至 φ 112.6〇/0。換句話說’藍寶石基板2〇2上單位面積内的應力釋放邊界 增加了，應力釋放的管道繼而增加，故本發明所提供之LED及其製 作方法係可提升應力釋放的效率，有效降低半導體複合層中的累積 應力’獲得無裂縫的高品質半導體複合層。 此外，相較於習知技術中以設置Μ阻擋結構齡應力累積的 方式’本發明所提供< LED t作方法可在不增加膜層或結構的製程 複雜度以及不影響LED絲表現的前提下後地將應力疏洪，故更 •適合用以製作氮化铭鎵(AW^N)層中鋁含量，即χ大於〇乃之磊 晶層。 以上所述僅為本發明之較佳實施例，凡依本發明 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。° 【圖式簡單說明】 第1圖與第2圖係為一習知LED之剖面示意圖 201115782 第3圖至第7圖係為本發明所提供之製作LED之方法之一較佳 實施例之示意圖；且第4圖係第3圖中沿A-A’切線之剖面示意圖。 【主要元件符號說明】 100 發光二極體 102 藍寶石基板 104 缓衝層 106 η型蟲晶層 108 活性層 110 ρ型蟲晶層 112 接觸層 114 η型電極 116 p型電極 118 阻擋結構 120 間隙 200 LED元件 202 基板 204 凸出圖案層 206 裸露區域 212 緩衝層 214 η型蠢晶層 216 活性層 218 ρ型蟲晶層 220 島狀半導體複合層 222 透明導電層 224 η型電極 226 ρ型電極: 1 also may reduce the optical performance of the LED. Therefore, it is still necessary to have a kind of reduction: force, money, and hardship, and not excessively increase the production of LEDs. SUMMARY OF THE INVENTION The present invention is directed to providing an LED manufacturing method and LED that can effectively reduce the stress inside the material without excessively increasing the complexity of the process. According to the patent application provided in the present disclosure, a type of led includes a substrate a placed on the wire plate ± and a portion of the base (4) is exposed to form a plurality of exposed regions, and a plurality of exposed portions are disposed on the bare An island-shaped semiconductor composite layer that is erected in the area. According to the patent scope provided by the present invention, a method for fabricating an LED is provided. First, a substrate is provided, and then a - protruding pattern layer is formed on the substrate, and the protruding portion is exposed. The substrate and the plurality of axes are prepared in the Wei domain, and then in the exposed regions, the island-shaped semiconductor composite layer is formed. According to the present invention, an LED is provided by forming a surface of a semiconductor layer on a substrate by a protruding pattern layer formed on a substrate, thereby forming a plurality of bare regions, and forming separate-independent regions in the bare regions. The island-shaped semiconductor composite layer enhances the ratio of the single-area-t stress release boundary of the LED wire by the concept of zeroing and zeroing, and increases the efficiency of stress release, so that the stress of the composite needle can be reduced, and the high quality without cracks can be obtained. Semiconductor composite layer. [Embodiment] Referring to Figures 3 through 7, Figures 3 through 7 are schematic views of a preferred embodiment of a method of fabricating an LED provided by the present invention. First, please refer to Figure 3 and Figure 4, where Figure 4 is a cross-sectional view of the tangential line along the third figure _ along A_A. As shown in FIG. 3 and FIG. 3, the method for fabricating (4) provided by the present invention first provides a substrate 202, which may include sapphire, carbon cut (SiC), 7, zinc oxide (ZnO), and emulsified town. (Mg〇) or Shishenhua gallium (GaAs). Next, a protruding pattern layer 204 is formed on the substrate, and the protruding pattern layer system can be a grid (4) as shown in FIG. 3, and a part of the substrate 202 is exposed as shown in FIG. Exposed areas (exposed regi〇n) 2〇6 继续 Continue to refer to Figures 3 and 4. As described above, the embossed pattern layer 204 includes _ tea, and in the preferred embodiment, the embossed pattern layer 204 is formed on the substrate 2 〇 2 in a manner perpendicular to each other, so that the preferred embodiment provides The bare areas 206 are square. However, it is worth noting that the protruding pattern layer 2〇4 may also be disposed on the substrate in a manner similar to the layout, so that the exposed area 201115782 206 of the present invention may also be rectangular, rhombic, hexagonal, or even round. Shapes and the like are not limited to those disclosed in the preferred embodiments and figures. In addition, the height of the convex pattern layer 2〇4 is greater than 〇〇1 μm (hereinafter referred to as μιη); the width w is greater than 2 μm, and in the preferred embodiment, each exposed area is 2%. The width D is between 5 () and 2 _ 哗. In addition, the embossed pattern layer 204 must be resistant to 1 由于 due to the temperature limitations of the process during subsequent fabrication of other layers of the LED. 〇 The above high temperature, and in the preferred embodiment, the convex pattern layer 2〇4 comprises - a high temperature resistant material, such as a dielectric material: oxidized stone eve (four), nitrogen #石石夕_) or a nitrogen bismuth fossil (SiON), etc., using chemical vapor deposition (10) deposition, CVD) such as low pressure chemical vapor deposition (1〇w_pres surface chemicalvapw deposition 'LPCVD) or plasma-assisted chemical vapor deposition (10). - chemical vapOTdeposition, A method such as PECVD) is formed on the substrate 202 by a patterning step, but is not limited thereto. Please refer to Figure 5. Next, a buffer layer 212, an n-type silicon oxide layer 214, an active layer 216 and a p-type silicon oxide layer 218 are sequentially formed on the substrate 2〇2, wherein the active layer 216 is a light-emitting layer. It can be a multiple weighted well (multiple _ well ' MQW) structure. The buffer layer 212, the n-type crystal layer 214, the active layer 216, and the p-type epitaxial layer 218 constitute an island-shaped semiconductor composite layer 22A. The island-shaped semiconductor composite layer 220 in the preferred embodiment comprises a semiconductor material such as tri-five-wort compound, preferably AlxGai-xN, and the X value is greater than 〇·2. It is also worth noting that the buffer layer 212, the n-type epitaxial layer 214, the active layer 216 and the crystal layer 218 will gradually accumulate and grow as shown in FIG. 5 due to the characteristics that the crystallite grows along the substrate material during growth. The plurality of island-shaped semiconductor composite layers 22 which are not connected and independent of each other, the dielectric material-exit pattern layer collapse provided in 201115782 is directly used as a boundary line between the island-shaped semiconductor composite layers 220. Since the element layers included in the island-shaped semiconductor composite layer 22 of the preferred embodiment and the materials suitable for use thereof, such as the Group III and N-type nitride semiconductor materials, are well known to those of ordinary skill in the art, Let me repeat. Please refer to Figure 6. Next, a transparent conductive layer 222 is formed on the p-type silicon layer 218 to avoid current enthalpy (cr〇wding). Subsequently, a portion of the transparent conductive layer 222' portion P-type epitaxial layer 218, a portion of the active layer 216 and a portion of the n-type epitaxial layer 21\ are removed, and the n-type epitaxial layer 214 is exposed. Subsequently, as shown in Fig. 6, an n-type electrode 224 and a p-type electrode are formed on the transparent conductive 222 and the n-type epitaxial layer 214, respectively. Please refer to Figure 7. After the island-shaped semiconductor composite layer 22 and the n-type electrode 224 and the p-type electrode 226 are formed, a process is performed, and the convex pattern layer 2〇4 and the substrate 202 are cut to form a plurality of LED elements. The protruding pattern layer 2〇4 is used as a boundary line of the island-shaped semiconductor composite layer 220, so that the protruding pattern layer 204 can also serve as a cutting path in the cutting process, and the cutting device directly cuts the protruding pattern layer 2〇4 and The substrate 202 is covered to obtain the LED element 200. According to the method for fabricating the LED provided by the present invention, the substrate 202 is divided into a plurality of bare regions 2〇6 by the convex pattern layer 204 formed on the substrate 2〇2, and each of the exposed regions 206 is formed with a The island-shaped semiconductor composite layer 22 is independent, so that the convex pattern layer 204 can be said to be a boundary line of the subsequently formed island-shaped semiconductor composite layer 22, and each of the island-shaped semiconductor composite layers 220 becomes each after performing a subsequent cutting process. LED components. As mentioned above, since the stress releasing stress in the LED semiconductor film layer 201115782 release boundary is mostly present at the edge of the film layer, increasing the stress release boundary and the edge area of the film layer can increase the stress release pipe. For example, in the prior art, the ratio of the stress release boundary to the overall epitaxial edge area is about 78% in the semiconductor composite layer in which the dicing process w is an integral wafer; compared with the prior art, the present invention provides The LED manufacturing method is that the semiconductor composite layers of the components to be obtained before the cutting process are formed in the bare region in an island form, and the stress release boundary and the monomer epitaxial area are obtained by the concept of zeroing out. The percentage ratio is increased to φ 112.6 〇 / 0. In other words, the stress release boundary per unit area on the sapphire substrate 2〇2 is increased, and the stress relief pipe is increased. Therefore, the LED provided by the present invention and the manufacturing method thereof can improve the efficiency of stress release and effectively reduce the semiconductor compound. The cumulative stress in the layer 'obtains a high quality semiconductor composite layer without cracks. In addition, the LED t-method provided by the present invention can improve the process complexity of the film layer or structure without affecting the performance of the LED wire, as compared with the prior art in which the stress accumulation of the barrier structure is set. The stress will be dredged in the lower part, so it is more suitable for the aluminum content in the layer of GaN (AW^N), that is, the bismuth layer is larger than 磊. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the present invention are intended to be within the scope of the present invention. ° [Simple description of the drawings] Fig. 1 and Fig. 2 are schematic cross-sectional views of a conventional LED 201115782. Figs. 3 to 7 are schematic views showing a preferred embodiment of a method for fabricating an LED provided by the present invention. And Fig. 4 is a schematic cross-sectional view taken along line A-A' in Fig. 3; [Main component symbol description] 100 light-emitting diode 102 sapphire substrate 104 buffer layer 106 n-type crystal layer 108 active layer 110 p-type crystal layer 112 contact layer 114 n-type electrode 116 p-type electrode 118 blocking structure 120 gap 200 LED element 202 substrate 204 convex pattern layer 206 bare region 212 buffer layer 214 n-type stray layer 216 active layer 218 p-type crystal layer 220 island-shaped semiconductor composite layer 222 transparent conductive layer 224 n-type electrode 226 p-type electrode