201113708 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種處理模組，特別是有關於具有繪 圖處理器（Graphic Processing Unit ; GPU)的處理模組。 【先前技術】 在目前的產品中，繪圖處理器（GPU)係與一記憶單元進 行資料傳輸。該記憶單元具有繪圖處理器的操作頻率。因 此’^圖處理器可根據記憶單元所儲存的操作頻率而運作。 ^騎圖處理器達到更高的效能，使用者可能會調 间記憶所儲存的操作頻率，也就是超頻。缺而，一旦 超頻失敗，很有可能會造錢圖處理器無法正常 【發明内容】 本發明提供一種處理模组，白虹 m么 -第-記憶單元、一第二記憶單包 _處理器進行資料傳輸。當第致 可與繪圖處理器進行資料傳輸 單=二牯’1 & ’控制單錢能第二記憶單元。 ^仃貝㈣$ 本發明另提供一種操作系統， 入系統(System BI0S)、一給圖^匕括一系統基本輸出4 單元、-第二記憶單U-圖控處 ，統進行-設定動作。繪圖處理^有u本輪出！ 二讀單元被致能時’便可鱗“理 ，。當j 當第二記'It單元被致糾，便可進仃1料傳輪 才使了與繪圖處理器進行資… 4 201113708 輸。控制單元先致能第一記憶單元。當第一記憶單元無法 與繪圖處理器進行資料傳輸時，控制單元致能第二記憶單 元。 本發明更提供一種處理方法，包括致能一第一記憶單 元，用以與一繪圖處理器進行資料傳輸；判斷該繪圖處理 器與該第一記憶單元之間的資料傳輸是否正常；以及當該 繪圖處理器無法與該第一記憶單元進行資料傳輸時，致能 一第二記憶單元，使得該繪圖處理器與該第二記憶單元進 行資料傳輸。 ® 為讓本發明之特徵和優點能更明顯易懂，下文特舉出 較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 第1圖為本發明之操作系統之一可能示意圖。如圖所 示，操作系統100包括，處理模組120以及系統基本輸出 輸入系統（system basic input/output system ;以下簡稱 SBIOS)130。本發明並不限定操作系統100之種類。在本實 φ 施例中，操作系統100係為一主機板（mother board ; MB)110。 SBIOS 130進行一設定動作。SBIOS 130係儲存在一記 憶體中，其所進行的設定動作係扮演硬體與作業系統溝通 的角色。透過SBIOS 130，便可設定系統的操作模式。由 於SBIOS的動作原理以及其所進行的設定動作，係為本領 域人士所深知，故不再贅述。 在本實施例中，處理模組120包括，繪圖處理器 (Graphic Processing Unit ; GPU)121、記憶單元 122、123 以及控制單元124。繪圖處理器121具有暫存器125。當記 201113708201113708 VI. Description of the Invention: [Technical Field] The present invention relates to a processing module, and more particularly to a processing module having a Graphic Processing Unit (GPU). [Prior Art] In the current product, a graphics processing unit (GPU) performs data transmission with a memory unit. The memory unit has an operating frequency of the graphics processor. Therefore, the processor can operate according to the operating frequency stored in the memory unit. ^The rider processor achieves higher performance, and the user may adjust the stored operating frequency, that is, overclocking. However, once overclocking fails, it is very likely that the money-making processor cannot be normal. [Invention] The present invention provides a processing module, a white-mo-me-memory unit, a second memory single-packet_processor for data transmission. When the first data can be transmitted with the graphics processor, the single = two 牯 '1 & ' control single money can be the second memory unit. ^仃贝(四)$ The present invention further provides an operating system, a system BIOS, a system basic output 4 unit, a second memory single U-picture control unit, and a system-setting operation. Drawing processing ^ There are u this round! When the second reading unit is enabled, it can be 'scaled'. When j is the second unit of the 'It unit is corrected, you can enter the material transfer wheel to make the drawing processor... 4 201113708 Lose. The control unit first enables the first memory unit. When the first memory unit is unable to perform data transmission with the graphics processor, the control unit enables the second memory unit. The present invention further provides a processing method, including enabling a first memory unit For performing data transmission with a graphics processor; determining whether data transmission between the graphics processor and the first memory unit is normal; and when the graphics processor is unable to perform data transmission with the first memory unit, A second memory unit enables data transfer between the graphics processor and the second memory unit. To make the features and advantages of the present invention more apparent, the preferred embodiments are described below, and The drawings are described in detail as follows: [Embodiment] FIG. 1 is a schematic diagram of one of the operating systems of the present invention. As shown, the operating system 100 includes a processing module 120 and a system. The present invention is not limited to the type of the operating system 100. In the present embodiment, the operating system 100 is a motherboard (mother board; MB). 110. The SBIOS 130 performs a setting operation. The SBIOS 130 is stored in a memory, and the setting operation is played as a function of communication between the hardware and the operating system. Through the SBIOS 130, the operating mode of the system can be set. The operation principle of the SBIOS and the setting operation performed by the SBIOS are well known to those skilled in the art, and therefore will not be described again. In this embodiment, the processing module 120 includes a graphics processing unit (GPU) 121, The memory unit 122, 123 and the control unit 124. The drawing processor 121 has a register 125. When remembering 201113708
Hi便可與記憶單元ΐ22 便可儲存來自記憶單元 憶單元122被致能時’繪圖處理器 進行資料傳輸。因此，暫存器125 122的資料。 °° 同樣地’當記憶單元123被致能時， 便可與記憶單元123進行資料傳輸。此時：二理二121 存來自記憶單元123的資料。在太眚#常存态I25儲 及⑵不會同時被致能W在本貫施例中’記憶單元⑵ 一 :，a圖處理器121係透過傳輸匯流排126，愈記情 二6的=3^_輸。本發明並不限料輸匯 排126 _類。在一可能實施例中，傳輪匯流排126 内部1合電路(I-squared-C ; Pc)匯流排。 另外 在一可能實施例中，暫存器' 125儲存緣圖處理哭 =裝置#ft(deviceID)’也就是儲存繪圖處理器ΐ2ι的識別 另-可能實施例中，暫存器125係儲存一旗標(flag)。 ，由項取該旗標，便可得知繪圖處理器ΐ2ι正與哪個記 單元進行資料傳輸。 μ .舉例而言，當暫存器125所儲存的旗標為〇時，則表 :圖處理器121係與記憶單元122進行資料傳輸。當暫 所儲存的旗標為1時，則表示繪圖處理器121係 二記憶單元123進行資料傳輸。在本實施例中，不論暫存 斋=25。係儲存繪圖處理器121的裝置標籤，或是儲存代表 ^憶單元122及123的旗標，其所儲存的内容均係由記憶 早元122及123所提供。 ,在本實施例中，記憶單元122及123的致能與否，均 =由控制單兀124所決定。控制單元124根據一預先設定， 先致能記憶單Α 122，其中該預先設定，可由使用者透過 201113708 自⑽，㈣㈣物㈣前，便 為預實施例’均以記憶單元122 在致能記憶單元3係為備用記憶體。 早兀122進行資料傳輪。在 。21便可與記憶 將一裝置標籤或是一旗坪 Η中，記憶單元122 置標籤係為繪圖處理器二二器：二之中，其中農 凡122的識別碼。 #識別馬而旗標係為記憶單 當記憶單元122 &、土找 時，暫存考 …、决與綠圖處理器121進耔咨』， ，存益125可能無法繼 進仃貪料傳輪 或是記億單元122 ' 處，⑵的識 能記憶單元123，使得碼。因此，控制單元124勒 行資料傳輪。 3处理器121與記憶單元丨23進 由於/記憶單元123 因此，當给亦，、有繪圖處理器121的 暫存圖處理器⑵與記憶單元123紅j識別碼’ 125可持續儲 ;3進仃-貝料傳輪時， 儲存記憶f元⑵的識別褐°。⑵的識別竭，或是改 ^在本實施例_，藉由讀取暫 便可得知綠圖處理 暫存益⑵所錯存的資料， $資料傳輪。舉例$言，1 I亡常地與記憶單元12 2進 器丨25便可鍺存妗 田°己拖單元122被致能時，暫存 122的識別碼。"处理器121的識別碼，或是記憶單元 …；而’ ¥續'圖處理哭 料傳輪時，暫存哭°。21無法與記憶單元122進行資 碼，或是記憶單5便無法儲存繪圖處理器121的識別 70 22的識別碼。因此，藉由讀取暫存器 201113708 125所儲存的資料’便可得知繪圖處理器m是否可正當 地與記憶單元122進行資料傳輸。 疋货」节 本發明並不限制讀取暫存器125的動作係由何者完 成。在一可能實施例中，可藉由SBI0S130 124，讀取暫存器125所暫存的資料。 工制早凡 若利用SBIOS 130讀取暫存器125所暫存 S則S U0將根據讀取結果，發出一控制信號&。、控制單 疋124根據控制信號Sc，致能記憶單元122或。在此 =中’ SBIOS 130係透過系統管理匯流排（⑽咖 anagement Bus ; SMBUS)14〇，讀取暫存器 12 控制信號Sc。 赞出 右利用控制單元124讀取暫存器125時，則控制單元 124可根據讀取結果，致能記憶單元122或123。在此例中， 控制單元！24係透過通用型輸入輸出(咖 Τ^；Γ0)127 J 125 ^ ^ “號至_處理器m。另外，若利用控制單元i2 取暫存器125時，則可省略第1圖中，SBIOS 130與控制 单元124之間的連接。 在上述的實施例中，係根據暫存器125 =_處理器m是否正f地與記憶單元122進行貝^料 傳輸，但並非用以限制本發明。在其它實施例中，可利用 其它方式’得知输圖處理器121是否正常地與記憶單元122 進行資料傳輸。 —第2,為本發明之控制單元之一可能實施例。如圖所 示才工制單S 124包括，微控制||(micr〇_c〇ntr〇Uer)21〇以 及切換器230。微控制器21G根據控制信號&，產生一切 201113708 換k號ss。在一可能實施例中，微控制器21〇係利用通用 型輸入輸出（GPIO)端，傳送切換信號心。 在本貫施例中，控制信號Sc係由SBIOS 130所產生。 SBIOS 130偵測暫存器125，並根據偵測結果，產生控制俨 號 Sc 。 - 口 切換器230根據切換信號Ss，將操作電壓Vcc傳送至 記憶單=122或123。當切換器230將操作電壓Vcc傳送 至記憶單兀122時，則可致能記憶單元122。當切換器23〇 將操作電壓vcc傳送至記憶單元123日寺，則可致能& 胃元123。 在一可能實施例+，切換器23〇係根據切換信號^的 位準，將操作電壓Vcc傳送至記憶單元122或123。舉例 3二Γ刀換信？Ss為低位準時，切換器230將操作電壓 憶早兀122 ;若切換信號Ss為高位準時，切 換益230將操作電壓Va：傳送至記憶單元123。 在其它實施例中，控制單元124更包括重 據控制信號Sc，贈圖處理器121。微控制 。250 均係透過 SMBus，輕接 SBi〇s 13〇。 所干二Λ本=之控制單元之另―可能實施例。如圖 尸坏不，控制早兀124包括，斜伙釗吳Λ 微控制器31Μ貞測暫存„ =控制m31°以及切換器330。 切換信號Ss。在、二ΐ:广並根據偵測結果，產生- 用型輸入輪出_〇): 控制器310係透過通 暫存器Π5所暫存的^；^取暫存器125所暫存的資料。 是記憶單元122或為繪圖處理器121的識別碼或 4 的識別碼。 切換器330根據切換信號Ss，將操作電屋&傳送至 201113708 122時，則記侉單亓190 ; L cc低得迗主。己隐早το H被致能。當操作電壓Vcc被傳送 至5己憶^ 123時’則記憶單幻23被致能。 在只施例中，控制單元124更包括重置n 35〇。重$Hi can be stored with the memory unit ΐ22 from the memory unit when the memory unit 122 is enabled. Therefore, the data of the register 125 122. °° Similarly, when the memory unit 123 is enabled, data transfer can be performed with the memory unit 123. At this time: the second rule 121 stores the data from the memory unit 123. In the Taiji #常存state I25 storage and (2) will not be enabled at the same time in the present example, 'memory unit (2) one:, a map processor 121 through the transmission bus 126, more than two 6 = 3^_ lose. The invention is not limited to the transmission 126 class. In a possible embodiment, the transfer bus 126 has an internal 1 (I-squared-C; Pc) bus. In another possible embodiment, the register '125 stores the edge map processing cry = device # ft (deviceID) 'that is, the identification of the storage drawing processor ΐ 2 ι - in another possible embodiment, the register 125 stores a flag Flag. By taking the flag from the item, it is possible to know which recording unit the drawing processor ΐ2 is transmitting. For example, when the flag stored in the register 125 is 〇, the map processor 121 performs data transmission with the memory unit 122. When the temporarily stored flag is 1, it indicates that the drawing processor 121 is the two memory unit 123 for data transmission. In this embodiment, regardless of the temporary storage fast = 25. The device tag storing the graphics processor 121, or the flag representing the memory units 122 and 123, is stored by the memory elements 122 and 123. In this embodiment, the enabling or disabling of the memory units 122 and 123 is determined by the control unit 124. The control unit 124 can firstly memorize the unit 122 according to a preset setting, wherein the pre-setting can be performed by the user through the 201113708 (10), (4) and (4) (4), and the pre-embodiment is the memory unit 122 in the enabling unit. 3 is a spare memory. As early as 122, the data was transmitted. In. 21 can be remembered with a device label or a flag, the memory unit 122 is labeled as a graphics processor two: two, of which the identification code of the farmer 122. #识别马和旗标系系系系系系系系系系系系为为记忆的记忆单为记忆单元, The round or the unit of the unit 122', (2) the memory unit 123, makes the code. Therefore, the control unit 124 performs the data transfer. 3 processor 121 and memory unit 丨 23 enter / memory unit 123 Therefore, when given, there is a temporary processor (2) of the graphics processor 121 and the memory unit 123 red j identification code '125 sustainable storage; 3 into When the 仃-bee feeds the wheel, the recognition memory f element (2) is identified as brown. (2) The identification is exhausted, or in the present embodiment _, by reading the data, the information stored in the temporary storage benefit (2) is temporarily read, and the data is transmitted. For example, the statement ID can be temporarily stored with the memory unit 12, and the identification code of 122 can be temporarily stored. "The identifier of the processor 121, or the memory unit ...; and the '¥续' map handles the crying material, temporarily cries. 21 cannot be authenticated with the memory unit 122, or the memory list 5 cannot store the identification code of the recognition processor 121 of the graphics processor 121. Therefore, by reading the data stored in the register 201113708 125, it can be known whether the graphics processor m can properly perform data transmission with the memory unit 122.疋货”节 The present invention does not limit which of the actions of the read register 125 is performed. In a possible embodiment, the data temporarily stored in the register 125 can be read by the SBI0S130 124. If the SBIOS 130 reads the temporary storage S of the scratchpad 125, the S U0 will issue a control signal & The control unit 124 enables the memory unit 122 or according to the control signal Sc. In this = mid-SBIOS 130 system reads the register 12 control signal Sc through the system management bus ((10) coffee station; SMBUS) 14〇. Appreciating that when the right-use control unit 124 reads the register 125, the control unit 124 can enable the memory unit 122 or 123 based on the read result. In this case, the control unit! The 24 series through the general-purpose input and output (Caf Τ; Γ 0) 127 J 125 ^ ^ "number to _ processor m. In addition, if the register 125 is taken by the control unit i2, the SBIOS in the first figure can be omitted. The connection between the control unit 124 and the control unit 124. In the above embodiment, the memory transfer is performed with the memory unit 122 according to whether the register 125 = _ processor m is positively f, but is not intended to limit the present invention. In other embodiments, other means can be used to know whether the map processor 121 is normally transmitting data with the memory unit 122. - Second, it is a possible embodiment of the control unit of the present invention. The work order S 124 includes, micro control ||(micr〇_c〇ntr〇Uer) 21〇 and the switch 230. The microcontroller 21G generates all 201113708 for the k number ss according to the control signal & In the example, the microcontroller 21 transmits a switching signal heart using a general-purpose input/output (GPIO) terminal. In the present embodiment, the control signal Sc is generated by the SBIOS 130. The SBIOS 130 detects the register 125, And according to the detection result, a control nickname Sc is generated. - Port switcher 230 According to the switching signal Ss, the operating voltage Vcc is transferred to the memory list = 122 or 123. When the switch 230 transmits the operating voltage Vcc to the memory unit 122, the memory unit 122 can be enabled. When the switch 23 is operating the voltage The vcc is transmitted to the memory unit 123, and the stomach element 123 can be enabled. In a possible embodiment, the switch 23 transmits the operating voltage Vcc to the memory unit 122 or 123 according to the level of the switching signal ^. For example, if the Ss is low-level, the switch 230 will operate the operating voltage as early as 122; if the switching signal Ss is high, the switching benefit 230 will transfer the operating voltage Va: to the memory unit 123. For example, the control unit 124 further includes a re-information control signal Sc, a gift map processor 121. The micro-controller 250 is transmitted through the SMBus, and is lightly connected to the SBi〇s 13〇. The other two control units of the control unit = possible For example, if the corpse is not damaged, the control early 兀 124 includes, the slanting 钊 钊 Λ Λ Λ Λ Λ 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 Switch signal Ss. In the second and the second: according to the detection result, the generation-type input wheel _〇): The controller 310 is temporarily stored in the temporary register Π5; . It is the identification code of the memory unit 122 or the identification code of the graphics processor 121 or 4. When the switcher 330 transmits the operation electric house & to 201113708 122 according to the switching signal Ss, it records 侉 亓 190; L cc is low. It is already early το H is enabled. When the operating voltage Vcc is transmitted to 5, it is enabled. In the embodiment only, the control unit 124 further includes a reset n 35 。. Heavy $
的^ 貫施例中’重置器350係根據切換信號S 4的“，決疋疋否重置繪圖處理1 121。舉例而言，當切 if It:低位準時，重置器350不重置繪圖處理器121。 =刀齡就Ss為高位準時，重置器35G重輯圖處理器 丄21 〇 第4圖為本發明之控制單元之另一可能實施例。如圖 所不，控制單元124包括，微控制器41〇、切換器43〇、計 數器470以及處理器490。微控制器410讀取暫存器125。 ，理态490根據計數器470之計數值以及微控制器41〇的 讀取結果，產生切換信號Ss。切換器430根據切換信號Ss， 將操作電壓vcc傳送至記憶單元122或123。由^切"換3器 430的特性與切換器230相似，故不再贅述。 、° 在其它實施例中，控制單元124更包括一重置器45〇。 重置器450根據切換信號Ss，重置繪圖處理器121。另外， 當計數器470計數到一預設值時’則可產生一觸發信號St 予處理器490。在本實實施例中，該預設值與SBIOS 130 所進行的一設定動作的時間有關。 舉例而言，計數器470計數到該預設值的時間係大於 SBI0S 130進行該預設動作的時間。也就是說，當計數器 470計數到該預設值時，SBI0S 130已進行完該預設動作。 因此，當計數器470產生觸發信號ST，並且微控制器41〇 201113708 無法讀取暫存器125所儲存的資料時，切換器430改將操 作電壓Vcc傳送至記憶單元123。 在其它實施例中，假設，SBIOS 130所進行的預設動 作係為電腦裝置的開機動作。當計數器470未產生觸發信 號ST時，表示SBIOS 130尚未完成預設動作。在此情況下， 可能是電腦裝置發生當機。因此，切換器430並不會將將 操作電壓Vcc改傳送至記憶單元123，以避免使用者誤以 為記憶單元122發生異常。 第5圖為本發明之處理方法之一可能流程圖。本發明 ® 之處理方法適用於一處理模組，其中處理模組包括，一第 一記憶單元、一第二記憶單元以及一纟會圖處理器。 首先，致能一第一記憶單元（步驟S510)，使得繪圖處 理器與第一記憶單元進行資料傳輸。本發明並不限制致能 記憶單元的方法。在本實施例中，係提供一操作電壓予第 一記憶單元，以達到致能第一記憶單元的目的。 判斷繪圖處理器與第一記憶單元之間的資料傳輸是否 正常（步驟S530)。本發明並不限制步驟S530的判斷方式。 • 在一可能實施例中，可藉由判斷繪圖處理器的一暫存器所 儲存的資料，得知繪圖處理器與第一記憶單元之間的資料 傳輸是否正常。 舉例而言，當繪圖處理器與第一記憶單元進行資料傳 輸時，由於第一記憶單元具有一第一識別碼，故繪圖處理 器的一暫存器便可儲存該第一識別碼。當該暫存器無法再 繼續儲存該第一識別碼時，表示繪圖處理器無法繼續與第 一記憶單元進行資料傳輸。 若繪圖處理器與第一記憶單元之間的資料傳輸正常 201113708 二:：，步驟S510’繼續致能第一 單= 與第一記憶單元進行資料傳輸時' 會圖處 （步驟S550)，使得繪圖處理器與 致此第二記憶 料傳輸。 〜5己憶單元進行資 舉例而言’第一及第二記憶單元均 識別碼。因此，當第一< 、有繪圖處理器的 輸時，圖處二理器進行資料傳 存器無法繼續儲存繪圖處t存器=理器的識別 憶早70無法與繪圖處理器進行正當二別碼時，表示 此，致能第二記憶單元。 吊的資料傳輸。因 由於第二記憶單元亦具有。 二’當第二記憶單元與綠圖處理器的識別碼。因 '理，暫存器便可繼續健存_處“=輸時，緣圖 在另—可能實施例中，第一 “的識別碼。 一第-旗標以及―第二旗標。憶單元分別儲存 器進行資料傳輸時，繪：二己憶單元與繪圖處理 標，是第 元的二:暫存器便可儲存第一旗 一富暫存斋無法繼續儲存第一始挪士 凡無法與緣圖處理器進行正常的資表示第一記憶單 :記憶單元。當第二記憶單專輪:因此，致能第 * ’緣圖處理器的暫存 ^ :理$進行資料傳輸 標。 錯存弟二記憶單元的第二旗 進行資料m當繪圖處理器無法斑第 、丁寸得翰知，除了致 〇第—記憶單元 可重置綠圖處理器。 冗憶車元（步驟S550)，更 综上所述，在第—記 …無法輿、緣圖處理器進行資 12 201113708 料傳輸時，可改由第二記憶單元與繪圖處理器進行資料傳 輸，以維持緣圖處理器的運作。 另外，當第一記憶單元所儲存的資料(如繪圖處理器的 操作頻率）造成繪圖處理器無法正常運作時，可在致能第二 記憶單元之前，單獨地重置繪圖處理器。由於繪圖處理器 可單獨地被重置，故不需重新啟動操作系統。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。In the embodiment, the resetter 350 is based on the switching signal S4, and the resetting process 1 121 is reset. For example, when the cut if It: low level, the resetter 350 does not reset. The graphics processor 121. = the age of the Ss is high, the resetter 35G replays the processor 丄 21 〇 Figure 4 is another possible embodiment of the control unit of the present invention. As shown, the control unit 124 The microcontroller 41, the switch 43, the counter 470, and the processor 490. The microcontroller 410 reads the register 125. The state 490 is based on the count value of the counter 470 and the reading of the microcontroller 41. As a result, the switching signal Ss is generated. The switch 430 transmits the operating voltage vcc to the memory unit 122 or 123 according to the switching signal Ss. The characteristics of the switching device 430 are similar to those of the switch 230, and therefore will not be described again. In other embodiments, the control unit 124 further includes a resetter 45. The resetter 450 resets the graphics processor 121 according to the switching signal Ss. In addition, when the counter 470 counts to a preset value, A trigger signal St is generated to the processor 490. In the present embodiment, The preset value is related to the time of a set action performed by the SBIOS 130. For example, the time that the counter 470 counts to the preset value is greater than the time at which the SBI0S 130 performs the preset action. That is, when the counter 470 When the preset value is counted, the SBI0S 130 has completed the preset action. Therefore, when the counter 470 generates the trigger signal ST and the microcontroller 41〇201113708 cannot read the data stored in the register 125, the switcher 430 changes the operating voltage Vcc to the memory unit 123. In other embodiments, it is assumed that the preset action performed by the SBIOS 130 is the booting action of the computer device. When the counter 470 does not generate the trigger signal ST, it indicates that the SBIOS 130 has not yet been The preset action is completed. In this case, the computer device may be down. Therefore, the switch 430 does not transmit the operating voltage Vcc to the memory unit 123 to prevent the user from mistakenly thinking that the memory unit 122 is abnormal. Figure 5 is a flow chart of one of the processing methods of the present invention. The processing method of the present invention is applicable to a processing module, wherein the processing module includes a memory unit, a second memory unit, and a graphics processor. First, a first memory unit is enabled (step S510), so that the graphics processor and the first memory unit perform data transmission. The invention is not limited thereto. The method for memorizing the unit. In this embodiment, an operating voltage is supplied to the first memory unit to achieve the purpose of enabling the first memory unit. It is determined whether the data transmission between the drawing processor and the first memory unit is normal. (Step S530) The present invention does not limit the manner of determination of step S530. • In a possible embodiment, it can be determined whether the data transmission between the graphics processor and the first memory unit is normal by determining the data stored in a register of the graphics processor. For example, when the graphics processor and the first memory unit perform data transmission, since the first memory unit has a first identification code, a temporary memory of the graphics processor can store the first identification code. When the register is no longer able to continue storing the first identification code, it indicates that the graphics processor cannot continue data transmission with the first memory unit. If the data transmission between the graphics processor and the first memory unit is normal 201113708 2::, step S510' continues to enable the first single = when the data is transmitted with the first memory unit, the picture is taken (step S550), so that the drawing The processor transmits the second memory material. ~5 Recalling Units For example, the first and second memory units are both identification codes. Therefore, when the first < has a graphics processor to lose, the image processor at the image is unable to continue to store the data at the drawing memory. The identification of the processor is not able to be properly performed with the graphics processor. When the code is different, it indicates that the second memory unit is enabled. Hanging data transmission. Because the second memory unit also has. Two 'as the identification code of the second memory unit and the green map processor. Because of the rationale, the scratchpad can continue to store _ at the "= when the input, the edge map is another - in the possible embodiment, the first "identification code. A flag - and a second flag. Recall that when the unit separates the memory for data transmission, it depicts: the second memory unit and the drawing processing standard, which is the second element: the temporary storage device can store the first flag, the rich temporary storage can not continue to store the first beginning of the Norse Unable to perform normal capital representation with the edge map processor. First memory list: memory unit. When the second memory is a special wheel: therefore, the temporary storage of the *'th edge processor is enabled. The second flag of the memory unit of the second memory is the data. When the graphics processor is unable to be spotted, the digital memory processor can be reset. Recalling the car element (step S550), in more detail, when the first note can not be used, the edge map processor can transfer data to the second memory unit and the drawing processor. To maintain the operation of the edge map processor. In addition, when the data stored by the first memory unit (such as the operating frequency of the graphics processor) causes the graphics processor to malfunction, the graphics processor can be individually reset before the second memory unit is enabled. Since the graphics processor can be reset individually, there is no need to restart the operating system. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
13 201113708 【圖式簡單說明】 第1圖為本發明之操作系統之一可能示意圖。 第2圖為本發明之控制單元之一可能實施例。 第3、4圖為本發明之控制單元之其它可能實施例。 第5圖為本發明之處理方法之一可能流程圖。 【主要元件符號說明】 100 :操作系統； 120 :處理模組； 140 :系統管理匯流排； 122、123 :記憶單元； 125 :暫存器； 127 :通用型輸入輸出； 230、330、430 :切換器； 470 :計數器； S510〜S550 :步驟。 110 :主機板； 130 ： SBIOS ； 121 :繪圖處理器； 124 :控制單元； 126 :傳輸匯流排； 210、310、410:微控制器； 250、350、450 :重置器； 490 :處理器；13 201113708 [Simple description of the diagram] Figure 1 is a schematic diagram of one of the operating systems of the present invention. Figure 2 is a possible embodiment of one of the control units of the present invention. Figures 3 and 4 show other possible embodiments of the control unit of the present invention. Figure 5 is a possible flow chart of one of the processing methods of the present invention. [Main component symbol description] 100: operating system; 120: processing module; 140: system management bus; 122, 123: memory unit; 125: register; 127: general-purpose input and output; 230, 330, 430: Switcher; 470: Counter; S510~S550: Steps. 110: motherboard; 130: SBIOS; 121: graphics processor; 124: control unit; 126: transmission bus; 210, 310, 410: microcontroller; 250, 350, 450: resetter; ;