TW201112650A - Amplifier and receiver for a wireless communication system - Google Patents

Abstract

One exemplary receiver for a wireless communication system includes a plurality of signal processing components arranged to generate a receiver output according to a radio frequency (RF) signal. The signal processing components include amplifiers having a class-AB biased amplifier included therein. The signal processing components are disposed in a chip, and the class-AB biased amplifier is an amplifier which processes a signal corresponding to the RF signal before any other amplifier included in the chip. Another exemplary receiver for a wireless communication system includes an RF signal processor and a frequency conversion interface. The RF signal processor is to generate an RF signal, and has a class-AB biased amplifier arranged to apply amplification upon the RF signal. The frequency conversion interface is coupled to the RF signal processor, and used for receiving the RF signal generated from the RF signal processor and generating a down-converted result of the RF signal.

Description

201112650 VI. Description of the Invention: [Technical Field] The present invention relates to a wireless communication system receiver, particularly a receiver capable of suppressing interference-robust, which can provide a high linear fundamental frequency for a wireless communication system. Signals and have high dynamic range and improved power efficiency. [Prior Art] When designing a radio frequency (RF) receiver for a wireless communication system, an important consideration is to be able to detect weak frequencies in the face of strong 〇ut-of-band interference ( In-band) signal. If the linearity of the receiver is insufficient, the extra-frequency signal interference will saturate the receiver and will block the intra-frequency signal. Therefore, a surface acoustic wave (SAW) filter is usually set in the receiver stage. To improve this problem. The SAW filter is a band-pass filter with a high quality factor (Q), so it can provide a high rejection ratio (rejecti〇n ratio) of usually more than 20dB for the out-of-band signal to meet the reception. Linearity requirements of the device. Figure 1 is a functional block diagram of the first application of the first application to the receiver 1 in a wireless communication system. The receiver 1A includes a SAW filter 1A2, an RF signal processor 110, a frequency conversion interface 12A, and an analog signal processor 13A. The saw filter 102 is a frequency selection device capable of transmitting a ruler!? The intra-frequency portion of the signal is also attenuated by the extra-frequency portion of the RF signal. The RF signal processor 11 includes a matching network 201112650 matching network 112 and a low noise amplifier (LNA) 114, the matching network 112 can provide power or noise matching, and the low noise amplifier 114 can Enhance signal strength. The prior art frequency conversion interface 12A includes a mixer 126' which operates in accordance with a local vibration (iocai 〇sciiiat〇r, l〇) signal. After signal filtering and signal enhancement, the mixer 126 downconverts the RF signal to an intermediate frequency signal to provide the signals needed for operation of the subsequent stage (e.g., the analog signal processor 13A).

The prior art receiver 1〇0 has a number of disadvantages: first, the attenuation of the intra-frequency signal of the SAW filter reduces the signal detection capability, so the prior art requires the use of a more sensitive receiver 1 after the SAW filter; More importantly, in today's common complementary metal oxide semiconductor (CMOS) process or dual-carrier complementary metal oxide semiconductor (9) CMOS process using silicon technology or silic〇nger_ium technology, At present, there is no economical way to make SAW filters and active circuits in the subsequent stages in the same process. Therefore, the filter will occupy a large circuit space in the communication device, and the above problem is more significant when the production cost is applied to the multi-frequency wireless communication system. Also, the low noise amplifier 114 operates in the Class A (D-A) mode and requires a large power consumption. SUMMARY OF THE INVENTION The present invention provides a wireless communication system receiver and an amplifier to solve the above problems. 201112650 The present invention provides a wireless communication system receiver, comprising: a plurality of signal processing components 'for generating a receiver wheel according to an RF signal, the plurality of signal processing components including an amplifier, wherein the amplifier includes an AB A bias-like amplifier; wherein the plurality of signal processing components are disposed on a wafer, and the class AB bias amplifier processes a signal corresponding to the RF signal prior to other amplifiers included in the wafer. The present invention further provides a wireless communication system receiver, comprising: an RF signal processor for providing an RF signal, comprising a Class AB bias amplifier for amplifying the RF signal; and a frequency conversion interface, coupled Receiving, by the RF signal processor, the RF signal from the RF signal processor to generate a down conversion result of the RF signal. The present invention further provides an amplifier comprising: a first amplifier block consuming an input 璋 and an output 璋 of the amplifier for amplifying an input signal, the first amplifier block having an input stage For receiving the input signal at the input port of the amplifier; a second amplifier block coupled to the input port and the output port for amplifying the input signal, The first amplifier unit includes: a first input stage for receiving the input signal; and a first switching unit coupled to the first input stage, the first switching unit The output of the first ~.1 'outlet point selectivity_ 接接A|| is referenced to two voltages; a bias circuit 'lights up the first-amplifier block and the The second amplification == is provided for the first amplifier block and the second enemy unit, and a switching controller is configured to control the operation of at least the first switching unit 201112650, Wherein when the amplifier enters a first gain mode, The bias circuit applies a class A bias to the input stage in the ___ amplifier block and the first input stage in the first amp block, the switching control 0 controls the a -i knife changing unit to consume the output node of the first input stage to the reference voltage. The present invention further provides an amplifier comprising: a first amplifier block coupled to the input and output ports of the amplifier for placing an input signal to the first amplifier block An input stage for receiving the input signal at a predetermined input port of the amplifier; a second amplifier block coupled to the input port and the output port of the amplifier for amplifying the input signal The second amplifier block includes: a plurality of input stages, each of the plurality of input stages is configured to receive the input signal at the input port of the amplifier; and the switching unit is respectively connected And the plurality of input stages, wherein one of the plurality of switching units is for controlling a connection of an output node of a corresponding input stage, a bias circuit is coupled to the first amplifier block, and the a second amplifier_block for biasing the first amplifier block and the second amplifier block; and a switching controller for controlling operation of the plurality of switching units; Input signal input When the power exceeds a predetermined level, the bias circuit applies a class A bias to the input stage in the first amplifier block and the plurality of input stages in the first amplifier block, The switching controller controls the plurality of switching units to disconnect a connection of an output node of the plurality of input stages in the second amplifier block to the output port of the amplifier, and in the At least one input stage of the first amplification block is disabled by at least one switching unit controlled by the switching control 201112650. The wireless communication system receiver and amplifier provided by the present invention are capable of suppressing noise and having improved dynamic range and power efficiency, and can reduce generation of waves. [Embodiment] Certain terms are used throughout the specification and subsequent claims to refer to a particular component. Those of ordinary skill in the art should understand that hardware manufacturers may refer to the same component by different nouns. The scope of this specification and subsequent patent applications does not use the difference in name as a means of distinguishing components, but rather as a criterion for distinguishing between functional differences of components. The "contains" mentioned in the general statement and subsequent claims are open-type and should be interpreted as "including but not limited to". In addition, the term "depletion" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected. The fifth device is electrically connected to the second device indirectly via other devices or connection means. 2A and 2B are diagrams for suppressing miscellaneous in a wireless communication system according to an embodiment of the present invention;

(interference-robust) a functional block diagram of the receiver 200. The receivers 200 shown in Figures 2A and 2B each include an RF signal processor 210, a frequency conversion interface 220, and an analog signal processor 230 that can receive the wide frequency rf signal and down-convert it to a specific intermediate frequency. The receiver 200 shown in Fig. 2B further includes a DC 201112650 blocking circuit 240 for providing DC isolation between the RF signal processor 210 and the frequency conversion interface 220. The RF signal processor 210 can be implemented in a variety of designs, such as the matching network 212 and the low noise amplifier 214 to provide the RF signal to the frequency conversion interface 220. Depending on the system requirements for different applications or circuit designs, matching network 212 can provide power or noise matching to improve power gain or noise figure. The low noise amplifier 214 is capable of amplifying the RF signal' and thereby improving the ability to drive the frequency conversion interface 220. In the embodiment of the present invention, the low noise amplifier 214 can be a pseudo-differential LNA, a single-ended low noise amplifier (Singie_en (ied LNA), a fully differential low noise amplifier ( Fuiiy differential LNA), or other types of low noise amplifiers. The matching network 212 can also provide signal conversion. For example, when the low noise amplifier 214 uses a differential input, the matching network 212 can convert the single-ended RF signal into The frequency conversion interface 220 includes a passive mixer 206 and a wave 216. The passive mixer 206 operates according to the LO signal and can down-convert the RF signal provided by the #RF signal processor 210. A predetermined intermediate frequency is provided to provide a corresponding intermediate frequency signal. Further, the intra-frequency portion and the extra-frequency portion of the RF signal are respectively down-converted to a passband and a stopband of the filter 216. In an embodiment, the passband of the filter 216 can be designed in a specific frequency range centered on the LO signal; in other embodiments, the intra-frequency portion of the RF signal can also be designed to be far away from the signal. The specific frequency range is "in other words." According to different designs, the intra-frequency portion of the RF signal can be included or not included in a specific frequency range centered on the LO signal. This feature is not t S) 9 201112650 The scope of the invention. At the same time, the 'filter 216 can provide signal suppression: when the frequency of the input signal is within the passband of the filter 216, the filter 216 transmits the input signal; when the frequency of the input signal is in the rejection band of the filter 216 In the meantime, the filter 216 blocks the input signal. Since the passive mixer 206 down-converts the intra-frequency portion and the out-of-frequency portion of the RF signal to the passband and reject bands of the filter 216, the analog signal processor 230 is substantially only The intermediate frequency signal in the passband is received, so that the analog signal processor 230 can be prevented from being saturated by the unwanted intermediate frequency signal (ie, the RF signal that is down-converted to the reject band). In other words, the frequency conversion interface The 220 can be used as a current driving interface of the RF signal processor 210 to process the extra-frequency portion of the RF signal. On the other hand, the filter 216 suppresses the noise intermediate frequency signal. The voltage swing at its input. Due to the nature of the passive components, the passive mixer 206 also up-converts the voltage developed at the input of the filter 216. Thus 'as the filter 216 suppresses its input formation The voltage formed by the input of the passive mixer 206 is also suppressed, thereby avoiding saturation of the RF signal processor 210 due to the extra-frequency portion of the rf signal. The RF signal processor 210 can be any type of amplifier. For example, a transc〇nductance amplifier' acts to provide an RF signal to the frequency conversion interface 22〇. In the present invention = embodiment, the filter 216 may be a passive ferrite that uses all passive components or a passive filter that uses both active and passive components. 3A, 3B, 4 and 5 are circuit diagrams of the receiver 200 of the embodiment shown in the first embodiment of the present invention. In the 201112650_receiver 200a of the first embodiment of the present invention shown in FIG. 3A, the passive mixer 206 includes four sets of switches SW1 SWSW4; and the filter 216 is a resistor-capacitor (RC) current input/current output. A low-pass filter comprising a capacitor C1 and two resistors R1, R2; the DC isolation circuit 240a comprises two capacitors CD1*CD2. In the receiver 200b of the first embodiment of the present invention shown in FIG. 3B, the passive mixer 206 includes four sets of switches SW1 SWSW4; the filter 216 is a low pass filter of the RC type current input/current output, which includes Capacitor C1 and two resistors R1, R2; DC isolation circuit 240b includes a transformer. The passive mixer 206 receives the RF signal (not indicated by the current IRF flowing into the first input node N1 and the second input node N2), and outputs an intermediate frequency signal (from the first output node N3 and the first output node) The current of N4 is represented by IMIXX BB). In the DC isolation circuit 24A, a capacitor CD1 is disposed between the RF signal processor 21A and the first input node N1, and a capacitor CD2 is disposed between the RF signal processor 21A and the second input node N2 for Isolation; DC isolation circuit % (10) uses voltage transformation to provide DC isolation. The switches SW1 to SW4 operate according to the differential local oscillation signal pair [〇+ and L〇_] where the phase difference between the positive differential local oscillation signal LO+ and the negative differential oscillation oscillation signal B is WO degrees. The switch SW1 selectively turns on/off the signal transmission path between the first input node and the first output point N3 according to the positive differential local vibration LO+, and the switch SW2 is oscillating according to the negative differential local oscillation L〇_ To selectively turn on/off the _ signal transmission path # of the first input node N1 and the output node N4, the switch SW3 selectively turns on/off the second input according to the negative differential local ground vibration I afL number L The signal transmission path between the node N2 and the first output pain point N3 < and the switch sw4 selectively turns on/off the second input node N2 and the first according to the positive differential 201112650 ground oscillation signal L〇+ The signal transmission path between the two output nodes N4. Therefore, the switches SW1 SWSW4 mix the differential local oscillation signals LO+ and LO- and the RF signal 1". For example, the RF signal IRF having the frequency (ίίο+Δί) can be used by the passive mixer 206. The frequency is down to the intermediate frequency signal Imixer bb. Therefore, the frequency of the RF signal can be reduced from (ίίο+Afi), and the frequency of the RF signal can be reduced from (fL0+M2). After the down-conversion, the internal and extra-frequency portions of the RF signal are represented by IBB and I』AMMER BB. When Δίι <Δί*2, the value of the corner frequency of the low-pass chopper (IMttR) ^) It needs to be between Af2 and Af2. After this frequency reduction, the intra-frequency part Ibb of the RF signal will be in the passband of the low-pass filter and the waver 216, and the extra-frequency part of the RF signal after the down-conversion I]ammer_bb will In the rejection band of the low pass filter 216, the IBB is transmitted to the analog signal processor 230 through the resistors R1 and R2, and the Immmer_bb is blocked by the capacitor C1, thereby preventing the analog signal processor 230 from interfering with the intermediate frequency signal Ijammer_bb. While presenting saturation 0, the first output node N3 and the second output node N4 Inevitably, an intermediate frequency voltage swing ΔVmixer_bb is formed. Due to the characteristics of the passive component, the passive mixer 206 also upconverts the intermediate frequency voltage swing ΔVmixer_bb to the first input node N1 and the second input node N2. The RF voltage AVRf. If the corner frequency of the low-pass filter 216 is much smaller (for example, more than 10 times), the intermediate frequency voltage swing AVmixer_bb has a value approximately equal to hAMMELBB /27tAf2C丨 at the frequency Af2. The value of the internal capacitor C丨 of 216 can suppress the intermediate frequency voltage swing ΔVmixer bb formed between the first output section 201112650 and the point N3 and the second output node N4 due to the extra-frequency portion of the RF signal, and at the first The RF voltage formed between the input node N1 and the second input node N2 is also suppressed at the same ratio, thereby preventing the RF signal processor 210 from being saturated due to the RF voltage Αν" caused by the extra-frequency portion of the RF signal. In the receiver 200c of the second embodiment of the present invention shown in FIG. 4, the filter 216 is a high-pass filter of the RC type current input/current output, which is a package. Resistor R1 and two capacitors C1, C2. In this embodiment, Δ &> Δ &, therefore, the corner frequency of the high-pass filter 216 (1/TrRiC!) and (I/ttR/O value needs to be between Δ Between the sum and the frequency, the intra-frequency portion IBB of the RF signal is in the passband of the high-pass filter 216, and the out-of-band portion of the RF signal Lammer-bb after the down-conversion is in the reject band of the high-pass filter 216. Therefore, the IBB is transmitted to the analog signal processor 230 through the capacitors C1 and C2, and the IAMMER BB is filtered by the resistor R1, thereby preventing the analog signal processor 230 from being saturated due to the noise intermediate frequency signal I]AMMER_BB. The angle of the corner of the right south passer 216 is much larger than Δ& (for example, more than 1 〇). The intermediate frequency voltage swing ΔVMIxER BB is approximately equal to Lammer-bb^Ri at the frequency Af^. Therefore, by reducing the value of the resistor core in the filter 216, the intermediate frequency voltage swing ΔνΜ丨XERBB formed between the first output node N 3 and the second output node N4 due to the extra-frequency portion of the RF signal can be suppressed. The rf voltage ΔVrf -· formed between the first input angstrom point N1 and the younger input angstrom point N2 is also suppressed by the same ratio', thereby avoiding the RF signal processor 210 due to the extra frequency portion of the rf. The resulting RF voltage AVRf is saturated. The other side 13 201112650, the receiver 200c can also use the DC isolation circuit 240b as shown in FIG. 3B. In the receiver 200d of the third embodiment of the present invention shown in Fig. 5, the filter 216 is a low-pass filter of an RC type current input/voltage output, which includes a capacitor C1 and a resistor R1. In this embodiment, Δίι <Δί2 'so the corner frequency of the low-pass filter Boeing 216 (1/27^/,) needs to be between Af2 and the frequency range of the RF signal. Will be within the passband of low pass filter 216. Therefore, the intra-frequency intermediate frequency voltage swing Δν formed between the first output node N3 and the second output node N4 and outputted to the analog signal processor 230 is approximately equal to IBB*R丨. On the other hand, the out-of-frequency portion IjAMMER RF of the down-converted RF signal is within the rejection band of the low-pass filter 216, so the intermediate frequency voltage of the noise formed between the first output node Ν3 and the second output node Ν4 The value of the wobble ΔVMIXER_BB is approximately equal to I_IAMMER_BB ΟπΔίΆ!. Therefore, by increasing the value of the capacitance Ci in the filter 216, the intermediate frequency voltage swing ΔνΜΙΧΕ1ι_ΒΒ formed between the first output node N3 and the second output node N4 due to the extra-frequency portion of the RF signal can be suppressed. In this embodiment, the analog signal processor 230 is prevented from being saturated by suppressing the value of the intermediate frequency voltage swing ΔVmIXER_BB at the frequency Δί*2. As described above, the RF voltage swing formed between the first input node Ν1 and the second input node Ν2 is also suppressed at the same rate, thereby preventing the RF signal processor 21 from being caused by the extra-frequency portion of the RF signal. The RF voltage swings AVRF and appears saturated. At the same time, the receiver 2〇〇 (1) uses the DC isolation circuit 240b as shown in Fig. 3. The 6A and 6B are schematic diagrams of the operation of the frequency conversion interface 220 according to the embodiment of the present invention. FIG. 6A shows the passive type. The input impedance of the mixer 2〇6 is 201112650 • (lmPedance) ' and the 6B is a frequency response diagram of the filter 216. The curves M1 and M1' represent the equivalent resistance of the filter 216 to l〇〇〇hm The equivalent capacitance is the result at 400 pF, and the curves m2 and M2 represent the results when the equivalent resistance of the filter 216 is 100 〇hm and the equivalent capacitance is 8 〇〇pF. As shown in Figures 6A and 6B It is shown that the out-of-frequency rejection ratio (i.e., the ability to suppress the out-of-frequency voltage swing) can be determined by appropriately selecting the resistance value and the capacitance value of the filter 216. Figure 7 is the fifth of the receiver 200 of the present invention as in Figure 2B. The circuit diagram of the embodiment. In the receiver 2〇〇e of the fifth embodiment of the present invention shown in Fig. 7, the passive mixer 206 includes eight sets of switches SW1 SWSW8, and the DC isolation circuit 240a includes two capacitors (: 01). And CD2. Passive mixer 206 is at the first input node N1 and the second input Node N2, and third input node N5 and fourth input node N6 receive RF signals (represented by current IRF flowing into and out of passive mixer 2〇6), and at first output node N3 and second output node N4, and outputting an intermediate frequency signal at the third output node N7 and the fourth output node N8. The capacitor CD1 can provide DC isolation between the RF signal processor 210 and the first input node N1 and the rf signal processor 210 DC isolation is provided between the third input node N5 and the third input node N5; the capacitor CD2 can provide DC isolation between the RF signal processor 210 and the second input node N2, and provide DC between the RF signal processor 210 and the fourth input node N6. The receiver 200e can also use the DC isolation circuit 240b as shown in FIG. 3B. The switches SW1 SWSW4 operate according to the differential local oscillation signal for LOI+ and LOI-, and the switches SW5 SWSW8 - are based on differential local oscillation. The signal operates on LOQ+ and LOQ-. In other words, the switches SW1 to SW8 are selectively turned on/off according to the corresponding local oscillation signal. 201112650 The signal transmission path between the corresponding input terminal and the corresponding output terminal is opened. Therefore, the switches SW1 SWSW4 can mix the differential local oscillation signal pair LOI+ and LOI- with the RF signal Irf, and the switches SW5 SWSW8 can mix the differential local oscillation signal LOQ+ and LOQ- with the RF signal IRF. In the receiver 200e, the mixer 206 operates according to a quadrature local oscillation signal, wherein the phase difference between the differential local oscillation signal LOI+ and the differential local oscillation signal LOI- is 180 degrees, and differential local oscillation The phase difference between the signal and the differential local oscillation signal LOQ+ is 90 degrees, and the phase difference between the differential local oscillation signal LOI+ and the differential local oscillation signal LOQ- is 270 degrees. As shown in FIG. 7, the filter 216 may include two RC filters 'each RC filter including a capacitor C1 and two resistors R1, R2; or other waveforms as shown in FIGS. 4 and 5 Device. The out-of-band rejection ratio can be determined by appropriately selecting the resistance value and capacitance value of the chopper 216. 8A and 8B are circuit diagrams of the analog signal processor 230 in the embodiment of the present invention. As shown in FIG. 8A, for the RC type current input/current output filter shown in FIGS. 3A, 3B, and 4, the analog signal processor 230 can be a transimpedance amplifier including an operational amplifier having rc feedback. . As shown in FIG. 8B, for the RC type current input/voltage output RC filter shown in FIG. 5, the analog signal processor 230 can be a voltage amplifier. Embodiments of the present invention may also use other architecture RC filters to provide low pass, band pass or high pass frequency response, or other types of analog signal processors, depending on the requirements of different wireless communication systems. 3A to 5, and 8A and 8B, 201112650, are merely examples of the present invention, and do not limit the scope of the present invention. Embodiments of the present invention provide a wireless communication system receiver for wireless communication systems that can suppress noise' without the use of large and expensive sAW filters, filters or the like. The passive frequency converter and the appropriately designed chopper [the frequency conversion interface of the embodiment of the invention can suppress the RF voltage swing formed at the input end of the extra-frequency portion of the RF signal and suppress the formation at the output end thereof. The frequency of the intermediate frequency swings. Therefore, the RF signal processor and the analog signal processor respectively set before and after the frequency conversion interface are not saturated due to the extra frequency portion of the RF signal. Since both the RF signal processor and the analog signal processor can operate normally under the interference of strong extra-frequency noise signals, the receiver of the present invention can detect weak intra-frequency signals to provide subsequent operations. As shown in Figures 2A and 2B, the RF ^ Tiger Processor 21 includes a signal booster amplifier (e.g., low noise amplifier 214), wherein the low noise amplifier 214 can be implemented by a Class-A amplifier. Therefore, as shown in Fig. 9A, the metal oxide semiconductor (MOS) transistor of the class A amplifier is biased so that it operates in the class A mode and the bias current should be correctly set. Idc~a, the average current 'is greater than the peak value of the intra-frequency signal Isig_peak. That is, the figure is a schematic diagram of the operation of the MOS transistor which is biased to operate in the Class A mode. For example, when a specific transduction is 120 mA/V and +1 dBm of extra-frequency 5, ie, extra-frequency jitter/isolation/interference, the bias current IDC_A is required to be greater than the % of transmission and this results in a large amount of power. Consumption. To reduce power consumption, the exemplary embodiment of the present invention employs a class-AB amplifier. As shown in Figure 9B, the bias current IDC_AB of the AB 4 is smaller than the bias current of the A mode.

[SJ 17 201112650

Idc_a '' is a schematic diagram of the operation of the M〇s transistor operating in the class AB mode when biased. According to the above, the present invention can also employ a class AB amplifier in a wireless communication receiver. Figure 10 is a block diagram of a wireless communication receiver employing a Class AB amplifier. The receiver 1 of the wireless communication system includes a plurality of signal processing components 1002, 1, 2, 2, 2, ..., 1002_Ν, and generates a receiver output signal S_OUT according to the RF signal RF_IN, wherein the signal processing components i 〇〇 2_1, 1002 2... The amplifier included in 1002-N can be an ab type biased amplifier. In this embodiment (the invention is not limited thereto), the signal processing elements 1002_2 and 1〇〇2_Ν-1 are amplifiers, wherein the signal processing elements 1002-2 are class AB bias amplifiers. As shown in the first diagram, the signal processing elements 1002_1...1〇〇2_Ν are disposed on the wafer 1〇〇1, and the class AB bias amplifier (eg, the signal processing element 1〇〇2_2) is on the wafer 1〇〇1. The other amplifiers above (e.g., signal processing component 1002_N-1) previously process RF signal RF_IN. According to the actual design of the signal processing components 1002_1...1〇〇2_N, the receiver output signal S_OUT can be obtained by processing the RF signal RF_IN. For example, the receiver output signal S_OUT is the base frequency output, the signal processing component 1002_2 is a low noise amplifier, and the signal processing component 1〇〇2_Ν-1 is a programmable gain amplifier (PGA). Since the Class AB amplifier is the first amplifier used to process the signal from the RF signal, the receiver performance improvement achieved by the Class AB amplifier can be optimized. Figure 11 is a block diagram of another wireless communication receiver using a Class AB amplifier. The receiver 1100 of the wireless communication system includes an RF signal processor 201112650 • 1102 and a frequency conversion interface 1104. The frequency conversion interface 1104 is coupled to the RF signal processor 1102. The rf signal processor 1102 processes the RF signal RF_IN and transmits it to the frequency conversion. The interface 1104, the frequency conversion interface 1104, down-converts the RF signal received from the RF processor 1102 to generate a down-converted signal SD_OUT. As shown in the figure, the RF signal processor 11〇2 includes a class AB bias amplifier Π08 for amplifying the RF signal rf—in, and the rf signal processor 11〇2 may also include other circuits 1106 to process the input RF. Signal RF-IN. For example, φ έ 'other circuits 1106 may include a matching network. Since the frequency conversion interface 1104 performs frequency reduction on the RF signal, the 偏压 class bias amplifier 11 〇 8 processes the RF signal. The receiver performance improvement by the 偏压 type bias amplifier is optimized. The receiver architecture shown in Figures 10 and 11 suppresses noise and has improved dynamic range/power efficiency. 12 and 12 are functional diagrams of another receiver 1200 of the wireless communication system according to an embodiment of the present invention. Receiver 1200 is similar to Receiver 2A in Figures 2 and 2, with the main difference being that low noise amplifier 1214 in RF signal processor 1210 is a Class AB bias amplifier. The DC isolation circuit 24A, the frequency conversion interface 220, and the analog signal processor 23A of the 12A and 12B can also be implemented according to the circuits of the 3rd, 3β, 4, 5, 7 8 and 8 ϋ 前述 described above. . Except for the 低-type low noise amplifier 1214, the operation and function of other components can be derived by those skilled in the art from the above description, and will not be described herein. In an example, when the receiver architecture shown in FIG. 1 is used, the RF < apostrophe processing If 1210, the step rate conversion interface 22 is similar to the signal processor 2 (10). Or the RF signal processor 121, the DC isolation circuit 19 201112650 240, the frequency conversion interface 220, and the analog signal processor 230 are disposed on the same wafer. The Class AB low noise amplifier 1214 is a Class AB bias amplifier on the same wafer. The other amplifiers (e.g., PGAs included in the analog signal processor 230) process the RF signals. In another example, when the receiver architecture shown in Figure η is employed, it is apparent that the passive mixer 206 in the frequency conversion interface 220 performs a down-conversion process on the RF signal before class AB low noise amplifier 1214. (Class AB low noise amplifier 1214 is also a bias amplifier) for rF signal processing. In short, noise suppression and improved dynamic range/power efficiency due to the novel filters placed behind the passive mixer and the novel Class AB low noise amplifiers placed before the passive mixer Receiver. The following is a detailed description of the class AB low noise amplifier 1214. Figure 13 is a block diagram of a class AB bias amplifier in accordance with an embodiment of the present invention. The class AB bias amplifier 13A includes a first amplifier block 13A2, a second amplifier block 1304, and a bias circuit 1306, but the present invention is not limited thereto. The first amplifier block 1302 is coupled to the input 埠N-IN of the class AB bias amplifier 13A and receives the input signal 81 at the input 槔N_IN. The bias circuit 1306 is coupled to the first amplifier block 13〇2 for biasing the first amplifier block 13〇2 to operate in the class AB mode. For example, the first amplifier block 1 go] includes at least one transistor 1308 as an input transistor, and the transistor 13〇8 has a control terminal NC coupled to the bias circuit 1306, which is biased by the bias circuit 1306. Operates in Class AB mode. More specifically, the transistor 1308 is guaranteed to operate in class AB mode when the signal is an out-of-band signal. Note that the Class AB mode operation of the first amplifier block 13〇2 can be achieved by simply setting the bias point of the transistor. 20 201112650 . Here, the class AB bias amplifier 1300 is different from the class AB push-pull amplifier (push_pu) amplifier). The second amplifier block 13〇4 is coupled to the first amplifier block ι3〇2 and the output 埠Ν_ΟϋΤ of the class AB bias amplifier 1300, and generates an output at the output 埠Ν_〇υΤ according to the output of the first amplifier block 1302. Signal s2. For simplicity, only one transistor is shown in Figure 13, however, the number of transistors used to receive the input signal si in the first amplifier block 1302 is adjustable, depending on actual design considerations and application requirements. For example, when the aforementioned _ 低 low noise amplifier 1214 is implemented by a 偏压 type bias amplifier 13 ,, the 低 type low noise amplifier 1214 can be a differential low noise amplifier, a single-ended low noise amplifier, or a total difference. Dynamic low noise amplifier. In addition, to reduce power consumption without affecting gain compression performance, the current voltage of transistor 1308 is exponential, allowing for gain expansion to achieve a higher dynamic range. More specifically, since the current flowing through the transistor 308 changes exponentially when the control voltage at the control terminal NC changes linearly, the bias current (ie, the average current) flowing through the transistor 1308 is based on the input power rate. The change is automatically changed without any detection and feedback circuits. Therefore, the current consumption of class AB low noise amplifier 1214 will vary with the input power of rf', so a large amount of power can be saved under actual operating conditions that do not always have strong out-of-band signals.

In an exemplary embodiment, transistor 1308 is a bipolar junction transistor (BJT). Also, since the MOS transistor operating in the weak inversion region has an exponential current-voltage characteristic, the transistor 1308 may be a MOS 201112650 transistor biased by the bias circuit 1306, and operates in Weak reversal zone. For example, the exponential current-voltage characteristic can be simplified as 々*e~, where Id represents the current flowing through the MOS transistor operating in the weak reversal zone, and V〇s is not gated. The source voltage 'Vt indicates Gate right voltage. Figure 14 is a schematic circuit diagram of a class AB bias amplifier 1300. The class AB bias amplifier 1300 is a differential differential transconductance amplifier that outputs a current signal. Since the frequency conversion interface 220 serves as the current driving interface of the RF signal processor 1210 to input the extra-frequency portion of the RF signal, the class AB bias amplifier 13 can be used to implement the class AB low noise amplifier 1214 shown in FIGS. 12A and 12B. . As shown in Fig. 14, the input terminal of the class AB bias amplifier 13A includes the input nodes N1 and N2 receiving the differential wheeling signal pair RFin+ and the team-, and the output of the class AB bias amplifier 1300 includes the wheel-out node N3 Port N4 output differential output signal sub-RFout+ Temple RFout bias circuit torn to generate bias % (eg 45〇mV) to MOS transistors Ml and . . . π M2 'to make it work in the weak reversal zone, The bias 曰曰B is determined by the bias current 1B and the diode-shaped M3 s electric body M3. For example, the size of the MOS electric-day-body M3 in the form of a diode can be selected to be only included in the weak reversal zone. Such a pressure can make the brain M1 and M2 work bias circuits measure the work of the forest (4). The invention can be used to generate any square of the required bias voltage applied to the M〇s transistor. And M2 goes up to 0 with MOS transistors Ml and M2.

The situation in the class mode refers to the bias current (ie, the lower average current) that is better than the 彳M2 operating in the A transistor m and the M2 star "mode in the weak reversal zone", thus improving the power efficiency / The power is 18mA, but the bias current of each 22 201112650 .MOS transistor in class AB mode can be reduced to 4mA. In the second amplifier block 1304, the inductive load Lload is used to make the dynamic range of the active device (headroom) In addition, a low dropout (LDO) regulator 1402 provides a supply voltage of, for example, 2.7V. The supply voltage of 2.7V and the low impedance provided by the filter 216 that suppresses the out-of-band signal can avoid output. It is limited and can suppress output distortion. The circuit described in Fig. 14 is for illustrative purposes only. The present invention is not limited thereto. Any amplifier architecture that follows the spirit of the present invention can be used to implement a class AB bias amplifier 13〇〇 Or class AB low noise amplifier 1214, other alternative amplifier designs are within the scope of the present invention. As described above, the signal boost amplifier (such as low noise amplifier 214) can be realized by class AB bias amplification n In order to achieve low power consumption. However, when the input power of the frequency portion of the received RF signal is large (for example, -15dBm), the secondary waves of the class AB bias I amplifier are more significant and cannot be ignored. For example, passive The local oscillation signal of the mixer 206 can be generated by an oscillation signal generated by, for example, a voltage controlled oscillator. The second harmonic of the Αβ-type bias amplifier may leak to the voltage controlled oscillator, resulting in undesired glitch noise. (spur) Therefore, undesired glitch noise down-converts the intra-frequency portion of the received RF signal to the desired fundamental frequency and corrupts the desired intra-frequency portion of the fundamental-frequency condition number. It is difficult to influence the influence of other circuit components on the second wave of the wave, so it is difficult to filter out the real (four) leakage of the second read wave of the 偏压 bias bias || The interference caused by the second harmonic leakage is possible. The method is to reduce the second harmonic of the class AB bias amplifier. Based on this, various exemplary amplifiers for lowering and lower harmonics are proposed. More specifically, when Input power of input signal [S3 23 201112650 More than the pre-clamping on time', that is, the secondary spectrum wave can not be ignored, the proposed amplifier will leave the gain mode and enter another gain mode to reduce the second harmonic. The details are described below. The figure shows an amplifier that supports different gain modes in accordance with an embodiment of the present invention. The amplifier 1500 includes a first amplifier block 15A2, a second amplifier block 1504, a bias circuit 1506, and a switching controller 15A8, but The present invention is not limited thereto. The first amplifier block 15〇2 and the second amplifier block 15〇4 are both coupled to the input 埠n_IN of the amplifier 1500, and the output 埠n_〇UT. The first amplifier block 1502 amplifies the input signal S1' (for example, an RF signal), and includes an input stage 1510 and an optional switching unit 1512, wherein the input stage 丨51〇 receives the input signal si' at the input 埠n_in, and the switching unit 丨512 is coupled to input stage 151 and controls the connection of output node N11 of input stage 1510. The second amplifier block 15〇4 includes an input stage i5i4 and a switching unit 1516, wherein the input stage 1514 receives the input signal S1 at the input 埠N_IN, the switching unit 1516 is coupled to the input stage 1514 and controls the output node N12 of the input stage 1514. connection. In the exemplary embodiment, the input stages 1510 and 1514 are transduction stages, and are implemented by MOS transistors Mil and Ml 2 as input/electric BB bodies, respectively; the switching unit 1512 is implemented by the MOS electric aa body M21, and the switching unit 1516 It is realized by the MOS transistor M22. It is obvious that the transduction size of the MOS transistor M12 is larger than the transduction size of the M〇s transistor M11. The bias circuit 1506 is coupled to the first amplifier block 15〇2 and the second amplifier block 1504 for biasing the first amplifier block 15〇2 and the second amplifier block 1504 to operate in the AB Class mode. More specifically, the bias voltage circuit 1506 is connected to the MOS transistors Mil and U12, and generates a bias voltage VBab 24 201112650. The MOS transistors Mil and M12 are operated in the AB mode. Therefore, the AB operation of the first amplifier block 1502 and the second amplifier block 15〇4 can be realized by simply setting the bias points of the MOS transistors M1 1 and M12. For example, the bias circuit 1506 can be implemented by the circuit of the bias circuit 1306 shown in Fig. 14, but the invention is not limited thereto. The switching controller 15〇8 controls the operation of the switching units 1512 and 1516. For example, the switching controller 15A generates switching control signals S21 and S22 to control the on/off states of the MOS transistors M21 and M22, respectively. When the input power of the input signal sr is low, the amplifier 15 〇〇 enters the first gain mode, the first gain is applied to the input A number S1 ', and the output signal S2' is generated at the output 埠n out. When the amplifier 15 is operating in the first gain mode, the switching controller 1508 sets the switching control signals S2i and S22 to conduct the transistors M21 and M22. Accordingly, since the bias circuit 15〇6 applies the class AB bias to each input stage of the first amplifier block 1502 and the second amplifier block 15〇4, the output nodes Nil and N12 are switched by the switching controller control. The units 1512 and 1516 are coupled to the output 埠N_〇UT', and the amplifier 15 is amplified in the first gain mode by the first gain of the input signal S1' with the gain value. However, when the input power of the input signal S1' increases and exceeds the predetermined level, the amplifier 1500 enters the second gain mode, and the gain value of the second gain in the second gain mode is smaller than the gain value of the aforementioned first gain. Further, in order to reduce the amplification to the gain and the undesired second harmonic, the switching controller 15A8 sets the switching control signals S21 and S22 to turn on the MOS transistor M21 and turn off the M?s electric crystal M22. Although the bias circuit 15 〇 6 applies the bias voltage VBab to the transistor title, 25 201112650, since the switching controller 1508 causes the transistor M22 to be in the off state, the transistor M12 is disconnected from the output 埠Ν-〇υτ'. In other words, the input stage 1514 in the second amplifier block 1504 is disabled by the switching unit 1516 controlled by the switching controller 1508. Since the number of active input stages (eg, active transduction stages) in the second gain mode is less than the first gain. The number of active input stages in the mode, thus reducing the undesirable secondary spectral waves generated in amplifier 1500. Please note that the electric s level of the partial vbab in the first gain mode and the bias u electric dust level in the second gain mode may be the same or different. Figure 16 is a schematic diagram of an amplifier supporting different gain modes in accordance with another embodiment of the present invention. The amplifier 1600 includes a first amplifier block 1502, a second amplifier block 16〇4, a bias circuit secret and a switching controller 1608 as shown in Fig. 15, but the present invention is not limited thereto. The difference between the second amplifier block and the second amplifier block 16〇4 includes a switching unit 1616 implemented by two M〇s transistors M22 and M23. It can be seen from FIG. 16 that the switching unit 1616 will input the input stage 1514. The output node N12 is selectively coupled to the reference voltage (eg, the supply voltage v_ or the output of the amplification n__Ν_〇υτ. Further, the bias circuit 1606 is coupled to the first amplifier block 15〇2 and the The second amplifier block 1604 selectively biases the first amplifier block 15〇2 and the second amplifier block 1604 to operate in a 模式 mode or a 模式 mode. More specifically, the bias circuit 1606 The MOS transistors M11 and Μ12 are coupled. Further, the bias circuit 1606 provides a bias voltage VBab to the MOS transistors Mil and Μ12 to operate in the class AB mode and to bias the m〇S transistors M11 and M12. Press VBa to make it operate in Class A mode, where VBa> 26 201112650

.VBab. And the switching controller 1608 controls the switching units 1512 and 1616 from the "D". For example, the switching controller 1608 generates the switching control signals S21, S22, and S23, respectively, which are controlled by the 0s electric body M21, On/off status of M22 and M23. ^Input, when the input power of 81' is low, the amplifier leg enters the first cup mode, and at the input 埠N IN, the input signal S1 (for example, RF signal) is used. The first gain 'generates the input signal S2 at the output 埠N 〇UT,*. When the amplifier 1600 operates in the first gain mode, the sinking __^ switching controller 1608 sets the switching control signals S21, S22, and S23 to be turned on. Mnc a M〇s transistors M21 and M22 and turn off the MOS transistor M23. Accordingly, since the pseudo-twisting circuit 1606 applies the class AB bias to the first amplifier block 1502 and the first-a-bit For each input stage of the block 1604, the output nodes Nil and N12 are coupled to the output 埠N 〇 ut, by the switching units 1512 and 1616 controlled by the switching controller 1608, and the U1 'amplifier 1600 is in the first gain mode. Next, the first increase in the value of the input signal S1' is increased by X & Amplifying. However, when the input power of the input signal S1' is increased and exceeds the predetermined level, the amplifier 1600 enters a second gain mode, and the gain of the second gain in the first gain mode is smaller than the first The gain is increased by only a few 9. In addition, to reduce the amplifier gain in the amplifier pin and the undesired secondary spectrum, the switching control number !6〇8 sets the switching control signals S21, S22 and S23 to turn on the M〇s The crystals M2i and M23' turn off the MOS transistor M22. The bias circuit secretly applies a class A bias to the input stage 1510 and 1514 instead of the ab bias. Although the bias circuit 1606 applies a bias voltage VBA to the transistor M12' Since the output node N12 consumes a reference voltage (e.g., supply voltage VDD) through an electrically conductive MOS transistor M23, the current flowing through the transistor M12 is bypassed. m 27 201112650 Compared with a class AB bias amplifier The class A bias amplifier produces less unwanted secondary waves. Therefore, by biasing the MOS transistors Μ11 and M12 to operate in the Class A mode, the second harmonic of the amplifier 1600 can be mitigated. 2A and 2B As shown, the matching network 212 is placed before the low noise amplifier 214. When the low noise amplifier 214 is implemented with the amplifier 1500 as shown in Fig. 15, the change in the input impedance caused by the disabled input stage 1514 causes The gain value of the second gain is drastically affected by the matching gain of the matching network 212, which is undesirable for receiver design. In another case, when the low noise amplifier 214 is implemented by the amplifier 1600 shown in FIG. 16, since the class A bias voltage VBA is higher than the class AB bias voltage VBab, the class A bias voltage is substituted for the class AB bias. Increase the DC current. Therefore, in the low gain (i.e., class A) mode, suppressing the unwanted second harmonic increases the DC current. However, when the input power is moderate (e.g., -40dBm to -22dBm), a low gain low noise amplifier is required, and the undesired primary hunting wave is still small enough to be ignored. In this case, the amplifier needs to switch to the low gain mode but still in class AB bias mode to save power. Accordingly, the present invention further proposes an improved amplifier design, which is described in detail below. φ is a schematic diagram of an amplifier supporting different gain modes in accordance with another exemplary embodiment of the present invention. The amplifier 17A includes, for example, a first amplifier block 1702 'second amplifier block 1704, a bias circuit 17〇6, and a switching controller 1708, but the present invention is not limited thereto. The first amplifier block 17〇2 and the second amplifier block 1704 are coupled to the inputs 槔N~IN of the amplifier 1700, and the outputs 璋n~out'. The first amplifier block 1702 amplifies the input signal S1 (eg, a ruler signal) and includes an input stage 1710 and an optional switching unit 1712, wherein the input 28 201112650 • the stage 1710 receives the input signal SI, at the input 埠N_IN, and switches Unit 1712 is coupled to input stage 1710 and controls the connection of output node Nil of input stage 171A. The second amplifier block 1704 includes a plurality of input stages 1714, 1718, and 1722 and a plurality of switching units 1716, 172, and 1724, wherein each of the input stages 1710, 1714, 1718, and 1722 receives an input signal S1 at an input 埠N_IN, Each switching unit 1712, 1716, 1720, and 1724 controls the I connection of the corresponding output node Nil, /N12'N13V N14' of the input stage 171017/714/1718/1722. More specifically, as shown in FIG. 17, the switching unit Π16 selectively couples the output node N12' of the input stage 1714 to a reference voltage (eg, supply voltage VDD) or an output 埠N_out of the amplifier ποο, the switching unit 1720 selectively couples output node N13 of input stage 1718 to a reference voltage or output 埠N_OUT'' switching unit 1724 to selectively couple output node N14 of input stage 1722 to a reference voltage or output 槔N_〇 UT'. In this exemplary embodiment, input stages 1710, 1714, 1718, and 1722 are transducing stages, and are implemented by MOS transistors Mil, M12', M13', and M14', respectively, as input transistors; switching elements πΐ2 are The MOS transistor M21, realized, the switching unit Π16 is realized by the MOS transistors M22, and M23', the switching unit 1720 is realized by the MOS transistors M24, and M25, and the switching unit 1724 is realized by the MOS transistors M26' and M27'. Further, the transduction sizes of the MOS transistors M13, and M14' are larger than those of the MOS transistors Mil, and M12. For example, the ratio of the transmissive size of the 'MOS transistors Mil', M12, M13, and M14' may be 0.5:0.5:10:10. The bias circuit Π06 is coupled to the first amplifier block Π02 and the second amplifier region 29 201112650. The block 1704' is used to provide a bias to the first amplifier block 17〇2 and the second amplifier block (7)* to operate Class AB mode or Class A mode. For example, the bias circuit 1706 is coupled to the ^1〇8 transistor ^111, ^112, elbow 13, and 1^4, to generate a bias voltage 丑 心 使 ] 〇 电 电 电 电 电 电 电 电 电 电 电 电,,]^12,,]^13, and ]^14, working in AB mode, or generating bias ▽8-8 to make one or more of M〇s transistors mu, mi2, Μ13', and Μ14' One works in a mode. The switching controller 17〇8 controls the operations of the switching units 1712, 1716, 1720, and 1724. For example, the switching controller 1708 generates switching control signals S21, -s27 for controlling the on/off states of the M〇s electric crystals M21-M27, respectively. The Amplifier 1700 supports different gain modes, including high gain modes (such as high gain class AB mode) and two low gain modes (such as low gain class AB mode and low gain class A mode). When the input power of the input signal sl is low, the amplifier 1700 enters the high gain ab mode, the first gain is applied to the input signal S1 at the input 埠N_IN', and the output signal S2' is generated at the output 槔n OUT'. When the amplifier 1700 enters the high gain ab mode, the bias circuit 17〇6 generates a bias VBab to each input stage 17丨〇, 丨7丨4, j 718, and 1722 'the switching controller 1708 sets the switching control signal S21, _S27' to turn on M〇S transistors Μ21, M22', M24', and M26, and turn off] V10S transistors M23', M25', and M27'. Accordingly, since the bias circuit 17〇6 is biased to each of the input stages 1710, 1714, 1718, and 1722 by the class AB, the output nodes Ν11, ·14, the switching units m2, 1716, 1720 controlled by the switching controller 1708. The 1724 is evenly connected to the output 埠N-OUT, and the amplifier 17 放大 can amplify the input signal S1' with a first gain having a high gain value in the high gain ΑΒ mode. 201112650 When the input power of the input signal si' increases, but does not exceed the predetermined level, the amplifier 1700 enters the low gain class AB mode, using the second gain, wherein the gain value of the second gain is lower than the gain value of the first gain described above. . When the amplifier 1700 enters the low gain class AB mode, the bias circuit 1706 generates a bias voltage VBab to each of the input stages 1710, 1714, 1718, and 1722, and the switching controller Π08 sets the switching control signals S2T-S27' to turn on the MOS transistor M21. ', M22, M25' and M27' and turn off MOS transistors M23', M24' and M26. Although the bias circuit 1706 applies the class AB to the input stages 1718 and 1722, since the output ® nodes N13' and N14' are coupled to the reference voltage (eg, supply voltage VDD) through the conductive MOS transistor M25, and M27', the transistor flows through the transistor. The currents of M13' and M14' are bypassed. Accordingly, the amplifier 1700 in the low gain class AB mode can amplify the input signal S1' with a second gain having a low gain value. The voltage level of the bias voltage 乂8^ in the high-enhanced class AB mode and the voltage level of the bias voltage VBab in the low-gain class AB mode may be the same or different. When the input power of the input number S1' is further increased, exceeding the predetermined level, the amplifier 1700 enters the low gain class A mode, adopting a third gain, wherein the gain value of the second boost is substantially equal to or smaller than the aforementioned second gain. Gain value. When amplifier 1700 enters the low gain class a mode, bias circuit 17〇6 generates a bias voltage VBA to each of input stages 17, 1714, 1718, and 1722, i.e., bias circuit 1706 applies a type A bias to the first amplifier region. Block 17〇2 and second amplifier block 1704. As described above, when the amplifier 17 is operating in the low gain ab mode, the control switching units 1712 and 1716 couple the output nodes Nil' and N12 to the output 埠N_OUT'; and, with the class A bias VBA replaces class AB bias 201112650 vbab to increase amplifier gain. In order to make the gain value of the third gain substantially equal to or smaller than the gain value of the second gain described above, the switching controller 17〇8 sets the switching control signals S21'-S23' to turn on the M〇s transistors M21, and Μ23. , and turn off the MOS transistor Μ 22'. Although the M〇s transistors Μη, and Μ12 are biased to operate in the Α mode, the ]vi〇s transistor Μ12 disconnects the output 埠N_OUT' of the amplifier 1700. Thereby, the gain of the amplifier is increased due to the application of the type a bias voltage to the MOS transistor Mil', and the amplifier gain is reduced due to the connection of the M 〇s transistor M12' and the output 埠Ν_〇υτ of the amplifier 1700. The gain value of the third gain in the low gain Α mode may be substantially equal to the gain value of the second gain in the low gain class AB mode. Also, since the bias circuit 1706 outputs the class A bias voltage VBA instead of the ab type bias voltage VBab, the undesired second harmonic can be effectively reduced. Further, when the amplifier 1700 operates in the low gain class a mode, the switching controller 1708 further sets the switching control signals S24, -S27 to turn on the MOS transistor M25' and turn off the MOS transistors M24, M26, and M27. Therefore, since the MOS transistors M26' and M27 are turned off by the switching controller 1708, the MOS transistor M14' is disconnected from the output 埠NJDUT. Briefly, switching controller 1708 controls switching units 1716, 1720, and 1724 to disconnect the output nodes N12'-N14' from the output of amplifier 1700, N_OUT', at least one of which is (eg, input stage 1722) At least one switching unit (e.g., switching unit 1724) controlled by the switching controller 1708 is disabled. Since the number of active input stages (eg, active transduction stage) is lower than the number of active input stages in low gain class AB mode/high gain class AB mode in low gain class a mode, put 32 201112650, bulk 1700 The undesired one-time spectral wave is effectively reduced. As mentioned above, the Guans input stage MOS transistor will change the input impedance of the amplifier. Therefore, in the exemplary embodiment, in the low gain class A mode, not all of the input stages in the second amplifier block 17〇4 are disabled. For example, at least input stage 1718 remains active to avoid too much matching gain variation. When the transducing size of the MOS transistor M12' is smaller than the transducing size of the MOS transistor M13, the matching gain due to the disabled input stage 1714 is negligible, and the MOS transistor is in the low gain class A mode. M12, can be turned off. Referring to Figures 18 to 20, Figure 18 is a diagram showing the relationship between the gain of the low noise amplifier and the bias current in the low gain mode, and Fig. 19 is the relationship between the matching gain and the bias current in the low gain mode. The schematic diagram of the second diagram is a schematic diagram of the relationship between the current and the bias current in the S-mode current mode. The point Case-Ι represents that the low noise amplifier of the receiver in low gain mode is implemented by an amplifier without harmonic attenuation technology; the point Case-2 represents the case: in the low _ 4 margin mode, the receiver A low noise amplifier (such as amplifier 15 〇〇) uses a class AB bias and enables the input stage in the first amplifier block and disables each input stage in the second amplifier block; the point Case-3 represents the case: In the low gain mode, the receiver's low noise amplifier (eg, amplifier 1600) uses a Class A bias and enables all input stages in the first amplifier block and the second amplifier block; point Case-4 represents the situation: In low gain mode, the receiver's low noise amplifier (such as amplifier Π〇〇) uses a Class A bias, and in the first amplifier block enables the input stage 'in the second amplifier block disable section input level. Compared with amplifiers 1500 and .16, the amplifier 1700 shown in Figure 17 can reduce the amplifier's

E SI 33 201112650 Undesired secondary waves' does not drastically increase power consumption and change matching gain. As mentioned above, the amplifier 1700 shown in Figure 17 supports three gain modes (ie, high gain class AB mode 'low gain class AB mode and low gain class a mode) and employs multiple harmonic attenuation techniques (eg, using class A bias) , the input stage 1722 is disabled and the connection between the input stage 1714 and the output 埠N_OUT is disconnected). This is to be construed as merely illustrative of the invention. Any amplifier design incorporating one or more of the technical features of the present invention is within the scope of the present invention. For the sake of clarity, an alternative design of amplifier 1700 in Figure 17 is described below. Regarding the first alternative design, the amplifier 1700 in Fig. 17 can be modified, the input stage 1722 and the corresponding switching unit 1724 are omitted; the modified amplifier Π00 can still support the above-mentioned high gain class AB mode, low gain class AB mode. And low gain class A mode. When the modified amplifier 17〇〇 enters the high gain class AB mode, ^108 transistor 1\111'-]^13' is biased in the eight-class mode, ^[〇8 transistors M21', M22' and M24' turns on, MOS transistors M23' and M25, turn off. When the modified amplifier 1700 enters the low gain class AB mode, the MOS call transistors M11'-M13' are still biased in the class AB mode,]y[〇S transistors M21, M22' and M25' are turned on, M0S The crystals M23' and M24 are turned off. When the modified amplifier 1700 enters the low gain class A mode, the M0S transistors Mil, -13, bias in the class A mode, the MOS transistors Μ2Γ, Μ23, and M25, turn on, the MOS transistors M22' and M24' off Broken. Regarding the second alternative design, the amplifier 1700 in Fig. 17 can be modified, the input stage 1714 and the corresponding switching unit 1716 are omitted; the modified amplifier 34 201112650 .1700 can only support the above-mentioned high gain ab mode and low gain a Class mode. When the modified amplifier 1700 enters the high gain class AB mode, the MOS transistors Mil', M13, and M14' are biased in the class AB mode, and the MOS transistors Μ2, M24', and M26' are turned on the MOS transistor M25, and M27' is turned off. When the modified amplifier Π〇〇 enters the low gain class A mode, the MOS transistor Μ1Γ and ]VI13' are biased in the class A mode, the MOS transistor M21, and the M25' turn-on MOS transistor M24, M26, and M27' is turned off. φ Regarding the third alternative design, the amplifier 1700 in Fig. 17 can be modified, the input stages 1714 and 1722 and the corresponding switching units 1716 and 1724 are omitted; the modified amplifier 1700 can only support the high gain class AB mode described above and low. Gain class A mode. When the modified amplifier 17 〇〇 enters the high gain class AB mode, the MOS transistors Mil, and M13' are biased in the class AB mode, the MOS transistors Μ2 Γ and M24' are turned on, and the MOS transistor M25' is turned off. When the modified amplified state 1700 enters the low gain class A mode, the MOS transistors Mil, and 3 are biased in the class A mode, the MOS transistors M21, and M25 are turned on, and the MOS transistor M24' is turned off. Based on the above-described technical features, those skilled in the art will appreciate that each of the amplifiers 1500, 1600, 1700 and amplifiers 17 associated alternative designs can be properly designed to have a single-ended amplifier configuration or a differential amplifier. The configuration 'depends on the actual design requirements, when the low noise amplification of the receiver (eg low noise amplifier 214) is implemented by the amplifiers 15 〇〇, _, 17 〇〇 and the amplifier Π 00 related alternative design The low noise amplifier can be a differential differential. Low noise amplifier, single-ended low noise amplifier ||, fully differential low noise amplifier. The above description is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a functional block diagram of a prior art for a receiver in a wireless communication system. 2A and 2B are block diagrams showing the function of the noise suppressing receiver of the wireless communication system in the embodiment of the present invention. 3A, 3B, 4 and 5 are circuit diagrams of the receiver of the embodiment of the present invention as shown in Fig. 2B. Figs. 6A and 6B are diagrams showing the operation of the frequency conversion interface in accordance with an embodiment of the present invention. Fig. 7 is a circuit diagram of a receiver in the embodiment shown in Fig. 2B of the present invention. 8A and 8B are circuit diagrams of an analog signal processor in an embodiment of the present invention. Figure 9A shows the operation of the M〇s transistor that is biased and operates in the Class A mode. Figure 9B shows the operation of the M〇s transistor operating in the Class AB mode without bias. Figure 10 is a block diagram of a wireless communication receiver employing a Class AB amplifier. Figure 11 is a block diagram of another wireless communication receiver employing a Class AB amplifier. 12A and 12B are diagrams showing the function of another receiver of the wireless communication system according to an embodiment of the present invention. Figure 13 is a block diagram showing a class AB bias amplifier in accordance with an embodiment of the present invention. Figure 14 is a schematic circuit diagram of a class AB bias amplifier. Figure 15 is a schematic diagram of an amplifier supporting different gain modes in accordance with an embodiment of the present invention. Figure 16 is a schematic diagram of an amplifier supporting different gain modes in accordance with another embodiment of the present invention. Figure 17 is a diagram showing an amplifier supporting different gain modes in accordance with another exemplary embodiment of the present invention. Figure 18 is a diagram showing the relationship between low noise amplifier gain and bias current in low gain mode. Figure 19 is a diagram showing the relationship between matching gain and bias current in low gain mode. Figure 20 shows the relationship between the second harmonic current and the bias current in the low gain mode. [Main component symbol description] 100, 200, 200a, 200b, 200c, 200d, 200e Receiver 102 SAW filter 112, 212 matching network

126 Mixer 114, 214 LNA 110, 210 RF signal processor 120, 220 frequency conversion interface [S] 37 201112650 130, 230 analog signal processor 216 filter 206 passive mixer 240, 240a, 240b DC isolation circuit 1000 Receiver 1001 chip 1002 1~1002 N signal processing component 1100 receiver 1102 RF signal processor 1106 other circuit 1200 receiver 1210 RF signal processor 1300 class AB bias amplifier 1302 first amplifier block 1308 transistor 1500 amplifier 1502 An amplifier block 1506 bias circuit 1510, 1514 input stage 1600 amplifier 1604 second amplifier block 1608 switching controller 1700 amplifier 1702 first amplifier block 1706 bias circuit 1104 frequency conversion interface 1108 class AB bias amplifier 1214 Low noise amplifier 1306 bias circuit 1304 second amplifier block 1402 LDO adjuster 1504 second amplifier block 1508 switching controller 1512, 1516 switching unit 1606 bias circuit 1616 switching unit 1704 second amplifier block 1708 switching Controller

1710, 1714, 1718, 1722 input stage 38 201112650 1712, 1716, 1720, 1724 switching unit

39

Claims (1)

201112650 VII. Patent application scope: 1. A wireless communication system receiver, comprising: a plurality of signal processing components for generating a receiver output according to an RF signal, wherein the plurality of signal processing components comprise an amplifier, wherein the amplifier A class AB bias amplifier is included; wherein the plurality of signal processing components are disposed on a wafer, and the class AB bias amplifier processes a signal corresponding to the RF signal before other amplifiers included in the chip . 2. The wireless communication system receiver of claim 1, wherein the class AB bias amplifier comprises an input port and an output port, and includes: a first amplifier block coupled to the input port Receiving an input signal at the input port; a bias circuit for engaging the first amplifier block for biasing the first amplifier block in an AB mode operation; a second amplifier block coupled to the first amplifier block and the output port for generating an output signal at the output port; wherein the first amplifier block includes at least one transistor, A bias circuit is coupled to a control terminal of the transistor and provides a bias voltage; and the transistor has an exponential current voltage characteristic. 3. The wireless communication system receiver of claim 1, wherein the class AB bias amplifier comprises an input port and an output port, and includes: a first amplifier block coupled to the input port Receiving an input signal at the input port; 201112650, a bias circuit coupled to the first amplifier block for biasing the first amplifier block in an AB mode operation And a first amplifier block coupled to the first amplifier block and the output port for generating an output signal at the output port; wherein the first amplifier block includes at least one transistor The bias circuit is hybridized to the - control terminal of the transistor and provides a bias voltage; and the bias current flowing through the transistor is automatically changed in response to an input power level change, without _ any detection And feedback circuit. 4. The wireless communication system receiver according to claim 2, wherein the transistor is a metal oxide semiconductor transistor, and the bias circuit provides a bias voltage to operate in a weak reverse Transfer zone. 5' The wireless communication system receiver of claim 2, wherein the transistor is a bipolar junction transistor. 6. The wireless communication system receiver of claim 1, wherein the epoch processing component comprises an RF signal processor and a frequency conversion &gt; interface, the RF signal processor generating And the RF signal is used to amplify the RF signal, and the frequency conversion interface is lightly connected to the RF signal processor for receiving the RF signal from the RF signal processor. And generating a down conversion result of the RF signal. 7. The wireless communication system receiver according to claim 6, wherein the 偏压-type bias amplifier is a transconductance amplifier, and the frequency conversion interface is used as a current driving interface of the RF signal processor. To process the extra-frequency portion of the RF signal. 201112650 8. The wireless communication system of claim 7, wherein the frequency conversion interface is used to reduce the frequency of the RF signal, wherein the voltage swings to avoid the voltage of the RF signal. Swinging, thereby preventing the RF signal processor from being saturated due to the electrical portion. The frequency of the L-type communication is 9. The wireless-containing DC-isolated circuit described in claim 6 of the patent application is consumed by the RF signal processing device, and the switching interface is between the DC circuit. Used to rape and hide. RF signal 丄 丄 10 · A wireless communication system receiver, comprising, an RF signal m processor, used to provide a bias amplifier 'to the RF, number, including a frequency conversion interface, _ And the signal processor receives the RF signal, and the processor changes the result. Returning to the RF signal - Down frequency conversion 11. As described in the scope of claim 1 of the scope of the helmet type AB bias amplifier includes - the transmission line communication system receiver, a first amplifier block, connected to the station = And receiving: receiving an input signal; 'dry' is used in the input first bias circuit, and the first amplifier block is coupled to the -AB type mode, the block is </ RTI> for making the first and second amplifier blocks two 乂 and 埠 for generating an iteration in the wheel - the output of the amplifier block and the output of the first amplifier region c transistor, The biasing circuit 42 201112650 is coupled to a control terminal of the transistor and provides a bias voltage; and the transistor has an exponential current voltage characteristic. 12. The wireless communication system receiver of claim 10, wherein the class AB bias amplifier comprises an input 埠 and an output 埠, and comprises: a first amplifier block coupled to the input 埠For receiving an input signal at the input port; a bias circuit coupled to the first amplifier block for biasing the first amplifier block in an AB mode operation; a second amplifier block coupled to the first amplifier block and the output port for generating an output signal at the output port; wherein the first amplifier block includes at least one transistor, The bias circuit is coupled to a control terminal of the transistor and provides a bias voltage; and a bias current flowing through the transistor is automatically changed according to an input power level change, without any detection and feedback Circuit. 13. The wireless communication system receiver according to claim 11 or 12, wherein the transistor is a metal oxide semiconductor transistor, and the bias circuit provides a bias voltage to operate in a weak Reverse zone. 14. The wireless communication system receiver of claim 11 or 12, wherein the transistor is a bipolar junction transistor. 15. The wireless communication system receiver of claim 10, wherein the class AB bias amplifier is a transconductance amplifier, and the frequency conversion interface is a current driving interface of the radio frequency signal processor. To process the extra-frequency portion of the RF signal. The wireless communication system receiver of claim 15, wherein the frequency conversion interface is configured to reduce a voltage swing of the extra-frequency portion of the RF signal, thereby avoiding the RF signal processor. Saturated due to the extra-frequency portion of the RF signal. 17. The wireless communication system receiver of claim 10, further comprising a DC isolation circuit coupled between the RF signal processor and the frequency conversion interface, wherein the DC isolation circuit is used Providing DC isolation to the RF signal. 18. An amplifier comprising: a first amplifier block coupled to an input port and an output port of the amplifier for amplifying an input signal, the first amplifier block having an input stage for Receiving the input signal at the input port of the amplifier; a second amplifier block coupled to the input port and the output port of the amplifier for amplifying the input signal, the The second amplifier block includes: a first input stage for receiving the input signal at the input port of the amplifier; and a first switching unit coupled to the first input stage, the first switch The unit selectively couples an output node of the first input stage to the output port or a reference voltage of the amplifier; a bias circuit coupled to the first amplifier block and the first a second amplifier block for biasing the first amplifier block and the second amplifier block; and a switching controller for controlling operation of at least the first switching unit; 44 201112650. The bias circuit applies a class A bias to the input stage in the first amplifier block and the second amplifier block when the amplifier enters a first gain mode a first input stage, the switching controller controlling the first switching unit to couple the output node of the first input stage to the reference voltage. The amplifier of claim 18, wherein the second amplifier block further comprises: φ a second input stage for receiving the input signal at the input port of the amplifier; And a second switching unit coupled to the second input stage for selectively coupling an output node of the second input stage to the output port or the reference voltage of the amplifier; Wherein, when the amplifier enters the first gain mode, the bias circuit further applies a type A bias to the second input stage, and the switching controller further controls the a second switching unit, configured to connect the output section of the second input stage to the reference voltage; and when the A-|input-second gain mode is performed, the bias circuit Applying a class AB bias to the input stage in the first amplifier block and the first stage and the second input stage in the second amplifier block The sickle change control (4) controls the first switch list to the said output of the input level The node is lightly connected to the reference power f, and controls the second switching unit to couple the output node of the second input stage to the output port of the amplifier. The amplifier of claim 19, wherein the second block 45 201112650 block further comprises: a third input stage for receiving the input signal at the input port of the amplifier; and a third a switching unit coupled to the third input stage for selectively coupling an output node of the third input stage to the output port or the reference voltage of the amplifier; wherein, when The switching controller further controls the third switching unit to disconnect the output node of the third input stage from the reference voltage and the amplifier when the amplifier enters the first gain mode Outputting a connection of 埠; the bias circuit further applying the class AB bias to the third input stage when the amplifier enters the second gain mode, the switching controller further controlling the a switching unit to couple the output node of the third input stage to the reference voltage. 21. The amplifier of claim 20, wherein when the amplifier enters a third gain mode The bias circuit applies the class AB bias to the input stage in the first amplifier block and the first input stage, the second input in the second amplifier block And the third input stage, the switching controller controlling the first switching unit to couple the output node of the first input stage to the output port of the amplifier and to control the a second switching unit to couple the output node of the second input stage to the output port of the amplifier, and to control the third switching unit to output the output node of the third input stage The output port coupled to the amplifier. The amplifier of claim 19, wherein the bias circuit applies the class AB bias to the first amplifier region when the amplifier enters a third gain mode The input stage in the block and the first input stage and the second input stage in the second amplifier block, the switching controller controlling the first switching unit to convert the first input The output node of the stage is coupled to the output port of the amplifier and controls the second switching unit to couple the output node of the second input stage to the output of the amplifier . The amplifier of claim 18, wherein the bias circuit applies a class AB bias to the first amplifier block when the amplifier enters a second gain mode The input stage and the first input stage of the second amplifier block, the switching controller controls the first switching unit to couple the output node of the first input stage to Said output of the amplifier. 24. The amplifier of claim 23, wherein the second amplifier block further comprises: a second input stage for receiving the input signal at the input port of the amplifier And a second switching unit coupled to the second input stage for selectively coupling an output node of the second input stage to the output port or the reference voltage of the amplifier; Wherein, when the amplifier enters the first gain mode, the switching controller further controls the second switching unit to disconnect the output node of the second input stage m [S.] 47 201112650 a connection with the reference voltage and the amplification; when the amplifier enters the second gain mode = the factory circuit step-by-steps the class AB bias to the jth 'the eccentricity The input switching control step-by-step controls the second switching unit to couple the point of the input of the rim "Ή® E « J· ^ ^ an input stage to the amplifier The output is 埠. An amplifier comprising: an amplifier block coupled to an input 埠 and a second of the amplifier, a field M 一 垾 and an output = for a pair-input signal amplification, the first amplification stage For receiving the input signal at the input port of the amplifier; and a second amplifier block, connecting the input port of the amplifier and the vehicle for amplifying the input signal, The second amplifier block includes: a rural input level, each of the plurality of input levels for receiving the input signal at the input port of the amplification; and a plurality of switching units, a plurality of input stages, wherein each of the plurality of switching units is used to control a connection of an output point of a corresponding input stage; a bias circuit coupled to the first An amplifier block and the second amplifier block for biasing the first amplifier block and the second amplifier block; and a switching controller for controlling the plurality of switching units Operation; wherein when the input power of the input signal exceeds a biasing circuit applying a bias to the input in the first amplifier block, and to the plurality of input stages in the second amplifier block, The switching control 48 201112650 controls the plurality of switching units to disconnect the output nodes of the plurality of input stages of the second amplifier block from the output port of the amplifier, and At least one input stage in the second amplifier block is disabled by at least one switching unit controlled by the switching controller. 26. An amplifier comprising: a first amplifier block coupled to an input port and an output port of the amplifier for amplifying an input signal, the first amplifier block having a first input stage For receiving the input signal at the input port of the amplifier; ^ a second amplifier block coupled to the input port and the output port of the amplifier, the second amplifier block comprising a second input stage for receiving the input signal at the input port of the amplifier; and a switching unit coupled to the second input stage for controlling one of the second input stages a connection of the output node; a bias circuit coupled to the first amplifier block and the second amplifier block to provide a bias to the first amplifier block and the second amplifier block And a switching controller for controlling operation of the switching unit; wherein when the input power of the input signal exceeds a predetermined level, the bias circuit applies a class AB bias to the first Input level and Said second input stage, the second stage is input by the switching controller controls the switching unit