201112414 六、發明說明： 【發明所屬之技術領域】 本發明係有關於主動元件陣列基板及有機發光二極體 顯示器裝置，特別有關於結合低漏電的非晶矽薄膜電晶體 與尚載子移動率的結晶矽薄膜電晶體的主動元件陣列基板 及有機發光二極體顯示器裝置。 【先前技術】 傳統的主動元件陣列基板可應用於液晶顯示器、有機 發光二極體等面板裝置，其主動元件陣列主要包括多晶石夕/ 微結晶矽薄膜電晶體和非晶矽薄膜電晶體兩大類。多晶矽/ 微結晶石夕薄膜電晶體具有高可靠度和高載子移動率I優 但其兀件均勻度較差，且由於高漏電流’使得儲存電 容不易控制電塵準位。相反地，非晶石夕薄膜電晶體的均句 邑佳的漏電流抑制，但是以非晶石夕電晶體構 H 基板’其元件可靠度不佳且载子移動率小 致使顯示畫素開口率小。 ，統的主動式有機發光二極體面板，不論是上閘極式 : :結晶擊PS〜Sl)電晶體陣列或下閉 ^曰曰石夕(’電晶體陣列均需七道光罩製程完成。例如，製 =上閘極式電晶體陣列所需的七道光罩' =二沉積保護層―形成^ ^積第-導電層並形朗σ。若採鮮日日日梦/微結 —陣列，則漏電流過Α，健存電容易由切換電晶體處漏i曰 201112414 二，電壓準位改變。若採用非晶矽電晶體陣列，則元件的 可罪度不佳，受電流應力（stress)之後，易造成臨界電壓飄 移，導致顯示器面板的壽命降低。 【發明内容】 本發明之實施例提供一種有機發光二極體顯示器裝 置金包括.一基板上具有主動元件所構成的一畫素陣列， 各畫素包括：-畫素電極；—儲存電容；以及—頂閉極式 或底閑極式結料薄膜電晶體；其中該晝素電極接觸洞及 金屬接觸洞為同—道製程定義；以及其中該畫素電極與該 頂閘極式或底閘極式結晶石夕薄膜電晶體的源極/沒極電性 遠接。 •本發明之貫施例另提供一種主動元件陣列基板，包 括.-基板上具有主動元件所構成的一畫素陣列，各晝素 匕括·-底閘極式非晶⑦薄膜電晶體；—儲存電容；以及 一頂閘極式結晶石夕薄膜電晶體；其中該底閘極式非晶 體的問極與該頂閘極式結晶石夕薄膜電晶體的源極/ =疋由㈣材制所構成；以及其巾該錢極式非晶石夕 =電^的源極/沒極與該·極式結晶㈣膜電晶體 的閘極疋由相同材料層所構成。 ^發明之實施例另提供—種有機發光二極 ί全基板上具有主動元件所構成的-晝素陣列 一里素i括·-底閘極式非晶石夕薄膜電晶體；—儲存電容. -頂閑極式結晶石夕薄膜電晶體；一有機發光二極體元件包 201112414 括一有機發光二極體電極、一右 其中該底•蝴…_電晶體=== :=該頂閘極式結晶彻電晶體的源二= 極她=二中該ί閘極式非晶彻電晶體的源 】晶體的閉極是由相同材料層構成；以；：夕雷專膜 與該=極式結_電晶體的源崎極電；;=電極 置的一:r發先二極體顯示器裝 於該基板的第一區域上，·形成-第-:電 於第二、第三和第四£域/ 成一圖案化第一導電層 的源勘及極電頂_式薄膜電晶體 -結晶彻第：=式，電晶體的閉極電極;形成 域上，覆蓋該頂η托斗、兹 曰；第一、第二和第四區 晶_該底閘L切臈極電極二該結 石夕島於第四區域的第二介電肩上：;二，形成一非晶 晶體的間極電極;形成一圖宰化第二 =閉極式薄膜電 於第二、第三和第四區域，形成-弟三介電層 和該底閘極式薄臈電晶體覆/5亥頂閘極式薄膜電晶體 極’·形成-有機發光層於該第三:二:=的該晝素電 電性接觸;形成有機發光二極體電心機 201112414 以及形成一保護層於該電極上 下文特舉實施例，並配合 為使本發明能更明顯易懂 所附圖式’作詳細說明如下： 【實施方式】 做為本發明說明並伴隨著圖式說明之範例’ ==考依據。在圖式或說明書描述中，相似或 相冋之邛刀白使用相同之圖號。且在 並·或是方便標示 別的是，圖 式立另外’特定之實施例僅為揭示本發明使用 之特疋方式，其並非用以限定本發明。 率並it高Ϊ動式有機發光二極體顯示器裝置的製程良 it !’本發明實施例提供m有機發光 道製程定義以減少製程數目以達到增加製 極體：為漏電流及高穩定度之主動式有機發光二 板兼罝裝置’本發明實施例，亦提供主動元件陣列基 的優點夕晶微結晶碎薄膜電晶體和非晶㈣膜電晶體 =罩Π者整合在一個晝素上。在製程中，不增加 主動式隍H人數’且與傳統主動元件製程相容，完成該 "列基板’做為低漏電、高可靠度之有機發光二極 201112414 體的主動元件陣列基板。 本發明實施例的主動元件陣列基板利用非晶矽薄膜電 晶體的低漏電特性，應用於切換電晶體（Switching TFT)可 有效地降低電容漏電，並結合微結晶矽薄膜電晶體的高載 子移動率與高可靠度特性，應用於驅動電晶體(Driving TFT) 上，以提高有機發光二極體的亮度，並提高顯示元件的壽 命。相較於先前技術，本發明實施例不需倚靠電路的方式 僅以兩電晶體和一電容(2T-1C)的簡單晝素設計，製作高穩 定度的有機發光二極體面板。 第1A-1F圖顯示根據本發明實施例有機發光二極體下 板製造方法各步驟的剖面示意圖。請參閱第1A圖，提供 一基板100，例如玻璃、石英、可撓式高分子透明基板或 金屬薄板。一介電層112可形成於基板100上。接著，形 成一圖案化晝素電極114於該基板的第一區域上。晝素電 極114例如為一金屬電極或一銦錫氧化物電極。 請參閱第1B圖，形成一第一介電層120覆蓋該圖案晝 電極114和基板100。接著，以金屬及重摻雜矽島形成一 圖案化第一導電層125以做為頂閘極式薄膜電晶體的源極/ 汲·極電極。 請參閱第1C圖，形成微結晶矽島130或低溫多晶矽島 覆蓋該頂閘極式薄膜電晶體的源極/汲極電極125，做為頂 閘極式薄膜電晶體的主動層。請參閱第1D圖，形成一第 二介電層140覆蓋該頂閘極式薄膜電晶體的源極/汲極電極 125、該微結晶矽島130。該第二介電層140的材質可為氮 化矽層、氧化矽層、或氮氧化矽層、或其他合適的介電層 201112414 材料。接著，形成接觸洞開口 142，露出畫素電極114與 源極/汲極電極125，如第1D圖所示。應注意的是’利用 晝素電極(ITO)和其他材料有蝕刻選擇比，在打開接觸洞 142時，使其不至於被破壞。 清參閱第1E圖，形成圖案化第二導電層ι5〇以做為頂 閘極式薄膜電晶體的閘極電極。上述圖案化第二導電層另 包括電性接觸150連接晝素電極ι14與源極/汲極電極 125。接著’形成一第三介電層ι6〇覆蓋該頂閘極式薄膜電 # 晶體且露出第一區域的該晝素電極114,如第1F圖所示。 第二導電層（例如金屬）材料的選擇必須與底下的介電層有 钱刻選擇比。 第2A圖係顯示根據本發明之一實施例的2T-1C的晝 素結構10a的電路示意圖，第2B圖係顯示第2A圖中的 2T-1C的晝素結構i〇a的剖面示意圖。請參閱第2A圖，一 主動元件2T-1C所構成的顯示晝素10a包括由掃描線22和 資料線24所構成的晝素區域。顯示晝素1〇a另包括一切換 φ 電晶體（Switching TFT) 12例如一底閘極式非晶矽薄膜電晶 體’可有效地降低儲存電容16漏電，以及一驅動電晶體 (Driving TFT) 14例如一頂閘極式結晶矽薄膜電晶體，以提 高有機發光二極體(OLED) 18的亮度，並提高顯示元件的 壽命。請參閱第2B圖，於此實施例中，電容50的上電極 51與底閘極式薄膜電晶體(bottom gate TFT) 60的源極/汲 極（S/D)相接，並連接於頂閘極式薄膜電晶體(t〇p gate TFT) 70之閘極端。再者，電容5〇的下電極53與GND相接， 而不與頂閘極式薄膜電晶體(top gate TFT) 70的源極/汲極 r 201112414 (S/D)相接。 第2C圖係顯示根據本發明另一實施例的2T-1C的晝 素結構10b的電路示意圖，第2D圖係顯示第2C圖中的 2T-1C的晝素結構10b的剖面示意圖。於此實施例中，電 容50的上電極55與底閘極式薄膜電晶體60的源極/汲極 (S/D)相接，並連接於頂閘極式薄膜電晶體70之閘極端。再 者，電容50的下電極57與VDD相接，且與頂閘極式薄膜 電晶體70的源極/汲極(S/D)電性相接。 根據本發明之實施例，製作上述整合微結晶矽電晶體 和非晶矽電晶體於一 2T-1C顯示晝素的製程亦為七道光罩 製程，因此並沒有因為元件整合而增加製程光罩數，而能 提高主動元件基板電路的可靠度與面板壽命。該2T-1C顯 示晝素的製程包括形成圖案化晝素電極、形成圖案化汲極/ 源極區（例如微結晶矽電晶體）與定義圖案化金屬閘極區 (例如非晶矽電晶體），定義第一主動層（例如微結晶矽電晶 體）、定義第二主動層（例如非晶矽電晶體）、形成接觸洞、 定義閘極區（例如微結晶砍電晶體）與定義及極/源極區（例 如非晶矽電晶體）、定義保護層。 第3A-3H圖顯示根據本發明實施例有機發光二極體顯 示器裝置的製造方法各步驟的剖面示意圖。請參閱第3A 圖，提供一基板100具有四個區域，例如玻璃、石英、可 撓式高分子透明基板或金屬薄板。一介電層112可形成於 基板100上。接著，形成一圖案化晝素電極114於該基板 的第一區域上。畫素電極114例如為一金屬電極或一銦錫 氧化物電極。 201112414 請參閱第3B圖，形成一第一介電層120覆蓋該圖案晝 電極114和基板100。接著，形成一圖案化第一導電層 125a、125b、和125c分別位於第二、第三和第四區域上， 以做為頂閘極式薄膜電晶體的源極/汲極電極及底閘極式 薄膜電晶體的閘極電極。 請參閱第3C圖，形成微結晶矽島130或低溫多晶矽島 於第二區域上，覆蓋該頂閘極式薄膜電晶體的源極/汲極電 極125a和125b，做為頂閘極式薄膜電晶體的主動層。請 φ 參閱第3D圖，形成一第二介電層140於第二、第三和第 四區域上，覆蓋該頂閘極式薄膜電晶體的源極/汲極電極 125a和125b、該微結晶矽島130和該底閘極式薄膜電晶體 的閘極電極125c。該第二介電層140的材質可為氮化矽 層、氧化矽層、或氮氧化矽層、或其他合適的介電層材料。 接著，形成一非晶矽島145於第四區域的第二介電層140 上，對應該底閘極式薄膜電晶體的閘極電極125c，做為底 閘極式薄膜電晶體的主動層。例如，於一實施例中，完成 • 頂閘極式微結晶電晶體主動層的定義步驟後，直接以化學 氣象沉積法（CVD)沈積SiN/a-Si/n+ a-Si三層連續沈積，其 中SiN為頂閘極式電晶體與底閘極式電晶體的共同介電 層。接著，形成接觸洞開口 H2，露出晝素電極114與源 極/>及極電極12 5 a ’如弟3 E圖所不。應注意的是’利用畫 素電極(ITO)和其他材料有蝕刻選擇比，在打開接觸洞142 時，使其不至於被破壞。 請參閱第3F圖，形成圖案化第二導電層150a、150b 和150c於第二、第三和第四區域上，以做為頂閘極式薄膜 r »7* 201112414 電晶體的閘極電極及底閘極式薄膜電晶體的源極/汲極電 極。上述圖案化第二導電層另包括電性接觸150d連接晝素 電極114與源極/汲極電極125a。接著，形成一第三介電層 160於第二、第三和第四區域上，覆蓋該頂閘極式薄膜電 晶體和該底閘極式薄膜電晶體，且露出第一區域的該晝素 電極114，如第3G圖所示。第二導電層（例如金屬）材料的 選擇必須與底下的介電層有蝕刻選擇比。 請參閱第3H圖，接著形成一有機發光層170於該第 三介電層160上並與該晝素電極114電性接觸，形成一有 機發光二極體180於該有機發光層170上，有機發光層170 可為小分子型OLED或高分子型PLED。再者，各晝素的 有機發光層170可為對應不同顏色晝素（例如紅、綠、藍）， 或者為白光OLED元件。接著，形成一保護層190或對向 基板於該有機發光二極體180上。晝素電極114、有機發 光層170、和有機發光二極體電極180構成一有機發光二 極體元件。例如，有機發光二極體元件可為一上發光式二 極體或一下發光式二極體。 第4圖顯示根據本發明實施例的主動元件陣列基板的 剖面示意圖，有鑑於此，根據上述實施例的揭露，提供一 種主動元件陣列基板200包括一基板上具有主動元件所構 成的一畫素陣列，各晝素包括一底閘極式非晶矽薄膜電晶 體(a-Si TFT)、一儲存電容Cs、以及一頂閘極式結晶矽薄膜 電晶體(C-Si TFT)，該底閘極式非晶矽薄膜電晶體的閘極與 該頂閘極式結晶矽薄膜電晶體的源極/汲極是由相同材料 層所構成’以及該底閘極式非晶砍薄膜電晶體的源極/及極 201112414 與該頂閘極式結晶矽薄膜電晶體的閘極是由相同材料層所 構成。由於主動元件陣列基板200包含頂閘極式微結晶矽 電晶體及底閘極式非晶矽電晶體於同一畫素上，並且由於 同時具有微結晶矽電晶體與非晶矽電晶體，因此可同時具 有南驅動電晶體可靠度與低漏電流之切換電晶體。依此晝 素電晶體設計，有機發光二極體面板可以擁有較佳的面板 特性。再者，在製程中整合非晶矽電晶體和微結晶矽電晶 體於一晝素中，在不增加額外製程光罩數下提高有機發光 Φ 二極體面板的品質，如此的晝素與製程結構設計能符合量 產與效能兼備的需求。 本發明雖以各種實施例揭露如上，然其並非用以限定 本發明的範圍，任何所屬技術領域中具有通常知識者，在 不脫離本發明之精神和範圍内，當可做些許的更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 201112414 【圖式簡單說明】 第1A-1F圖顯示根據本發明實施例有機發光二極體下 板製造方法各步驟的剖面示意圖； 第2A圖係顯示根據本發明之一實施例的2T-1C的晝 素結構10 a的電路不意圖， 第2B圖係顯示第2A圖中的2T-1C的晝素結構10a的 剖面示意圖； 第2C圖係顯示根據本發明另一實施例的2T-1C的晝 素結構1 Ob的電路不意圖， 第2D圖係顯示第2C圖中的2T-1C的晝素結構10b的 剖面示意圖； 第3A-3H圖顯示根據本發明實施例有機發光二極體顯 示器裝置的製造方法各步驟的剖面示意圖；以及 第4圖顯示根據本發明實施例的主動元件陣列基板的 剖面示意圖。 【主要元件符號說明】 10a、10b〜顯示晝素； 12〜切換電晶體（Switching TFT); 14〜驅動電晶體(Driving TFT); 16〜儲存電容； 18〜有機發光二極體； 22~掃描線， 14 201112414 24〜資料線； 50〜電容； 51、55〜上電極； 53、57〜下電極； 60〜底閘極式薄膜電晶體， 70〜頂閘極式薄膜電晶體； 100〜基板； 112〜介電層； φ II4〜晝素電極； 120〜第一介電層； 125、125a、125b、和125c〜圖案化第一導電層； 130〜微結晶矽島； 140〜第二介電層； 145〜非晶碎島， 142〜接觸洞； 150、150a-150d〜第二導電層； • 160〜第三介電層； 170〜有機發光層； 180~有機發光二極體電極； 190〜保護層； 200〜主動元件陣列基板。 15201112414 VI. Description of the Invention: [Technical Field] The present invention relates to an active device array substrate and an organic light emitting diode display device, and more particularly to an amorphous germanium thin film transistor combined with low leakage current and a carrier mobility An active device array substrate of a crystalline germanium thin film transistor and an organic light emitting diode display device. [Prior Art] The conventional active device array substrate can be applied to a panel device such as a liquid crystal display, an organic light emitting diode, etc., and the active device array mainly includes a polycrystalline quartz/microcrystalline germanium thin film transistor and an amorphous germanium thin film transistor. Big class. The polycrystalline germanium/microcrystalline sinusoidal thin film transistor has high reliability and high carrier mobility I, but its component uniformity is poor, and the storage capacitor is difficult to control the electric dust level due to high leakage current. On the contrary, the uniform leakage current of the amorphous sinusoidal thin film transistor is suppressed, but the amorphous phase is a low-accuracy component and the carrier mobility is small, resulting in a pixel opening ratio. small. , the active active organic light-emitting diode panel, whether it is the upper gate type: : crystal shot PS ~ Sl) transistor array or lower closed ^ 曰曰 夕 夕 ('transistor array requires seven reticle processes to complete. For example, the seven masks required for the upper gate transistor array = the two deposition protection layer - form the first conductive layer and form a σ. If the daydream/microjunction-array is used, Then, the leakage current is too high, and the stored electricity is easily leaked by the switching transistor. The voltage level is changed. If an amorphous germanium transistor array is used, the component is less sinful and subjected to current stress. After that, the threshold voltage drift is caused, which results in a decrease in the lifetime of the display panel. SUMMARY OF THE INVENTION Embodiments of the present invention provide an organic light emitting diode display device comprising: a pixel array having active elements on a substrate; Each pixel includes: - a pixel electrode; - a storage capacitor; and - a top closed pole or a bottom idle junction film transistor; wherein the halogen electrode contact hole and the metal contact hole are defined by the same process; Where the pixel electrode is The source/non-polarity of the top gate or the bottom gate crystal silicon oxide transistor is remotely connected. • The embodiment of the present invention further provides an active device array substrate, including: an active component on the substrate a pixel array, each of which includes a bottom-gate amorphous 7 thin film transistor; a storage capacitor; and a top gate crystal crystal film; wherein the bottom gate amorphous The source of the top gate and the source of the top gate crystal film / = 疋 is composed of (4) material; and the source of the money of the amorphous austenite = electric source / the pole and the Polar crystal (4) The gate electrode of the film transistor is composed of the same material layer. The embodiment of the invention further provides an organic light-emitting diode, which has an active element formed on the whole substrate - a halogen element array Included--Bottom-gate amorphous Aussie thin film transistor; - storage capacitor. - Top idle-type crystalline lithography thin-film transistor; an organic light-emitting diode package 201112414 includes an organic light-emitting diode electrode, Right one of the bottom • butterfly... _ transistor === := the top gate crystal crystal clear crystal Two = pole she = two in the source of the ί gate-type amorphous crystal; the crystal's closed pole is composed of the same material layer; to: 夕雷专膜 and the = pole junction _ transistor source Electropolar;; = one of the electrodes: the r-diode display is mounted on the first region of the substrate, forming - the first: the second, the third, and the fourth domain / forming a pattern Source of a conductive layer and polar top _-type thin film transistor - crystal clear: =, the closed electrode of the transistor; forming a domain, covering the top n bucket, 曰; first, second and The fourth region crystal _ the bottom gate L-cut electrode 2 the stone island is on the second dielectric shoulder of the fourth region: 2, forming an amorphous crystal inter-electrode electrode; forming a pattern = a closed-cell film is electrically connected to the second, third and fourth regions, forming a three-dielectric layer and the bottom-gate thin-film transistor-coated / galvanic gate-type thin film transistor pole - forming - The organic light-emitting layer is electrically contacted with the third: two:= the halogen; the organic light-emitting diode motor 201112414 is formed and a protective layer is formed in the electrode context embodiment, and Combined order that the invention will become apparent from the accompanying drawings 'described in detail below: [Embodiment] The present invention is described as an example accompanied by drawings illustrate the' == test basis. In the description of the drawings or the description, similar or equivalent knives use the same figure number. It is to be understood that the specific embodiments are merely illustrative of the features of the invention and are not intended to limit the invention. The process of the present invention provides an organic light-emitting diode process definition to reduce the number of processes to increase the number of electrodes: for leakage current and high stability. The active organic light-emitting two-plate Twisting Device 'is an embodiment of the present invention, and also provides the advantages of the active device array base. The crystal microcrystalline crystal film and the amorphous (tetra) film transistor are integrated on one element. In the process, the active 隍H number is not increased and is compatible with the conventional active component process, and the "column substrate' is used as the low-leakage, high-reliability organic light-emitting diode 201112414 active device array substrate. The active device array substrate of the embodiment of the present invention utilizes the low leakage characteristics of the amorphous germanium thin film transistor, and is applied to the switching transistor to effectively reduce the leakage of the capacitor, and combines the high carrier movement of the microcrystalline germanium film transistor. The rate and high reliability characteristics are applied to a driving TFT (Driving TFT) to increase the brightness of the organic light emitting diode and improve the lifetime of the display element. Compared with the prior art, the embodiment of the present invention does not need to rely on the circuit to fabricate a high-stability organic light-emitting diode panel with a simple crystal design of two transistors and a capacitor (2T-1C). 1A-1F are cross-sectional views showing respective steps of a method of fabricating an organic light emitting diode lower plate in accordance with an embodiment of the present invention. Referring to Figure 1A, a substrate 100 such as glass, quartz, a flexible polymeric transparent substrate or a thin metal plate is provided. A dielectric layer 112 can be formed on the substrate 100. Next, a patterned halogen element electrode 114 is formed on the first region of the substrate. The halogen electrode 114 is, for example, a metal electrode or an indium tin oxide electrode. Referring to FIG. 1B, a first dielectric layer 120 is formed to cover the pattern electrode 114 and the substrate 100. Next, a patterned first conductive layer 125 is formed of metal and heavily doped yttrium islands as a source/drain electrode of the top gate thin film transistor. Referring to Fig. 1C, a microcrystalline germanium island 130 or a low temperature polycrystalline germanium island is formed to cover the source/drain electrode 125 of the top gate thin film transistor as an active layer of a top gate thin film transistor. Referring to FIG. 1D, a second dielectric layer 140 is formed to cover the source/drain electrodes 125 of the top gate thin film transistor, and the microcrystalline island 130. The material of the second dielectric layer 140 may be a hafnium nitride layer, a hafnium oxide layer, or a hafnium oxynitride layer, or other suitable dielectric layer 201112414 material. Next, a contact hole opening 142 is formed to expose the pixel electrode 114 and the source/drain electrode 125 as shown in Fig. 1D. It should be noted that the use of a halogen electrode (ITO) and other materials has an etching selectivity ratio that is not destroyed when the contact hole 142 is opened. Referring to Fig. 1E, a patterned second conductive layer ι5 is formed to serve as a gate electrode of the top gate thin film transistor. The patterned second conductive layer further includes an electrical contact 150 connecting the halogen electrode ι14 and the source/drain electrode 125. Then, a third dielectric layer ι6 is formed to cover the top gate thin film and the first germanium electrode 114 is exposed, as shown in FIG. 1F. The choice of the second conductive layer (e.g., metal) material must be cost effective compared to the underlying dielectric layer. Fig. 2A is a circuit diagram showing a 2T-1C crystal structure 10a according to an embodiment of the present invention, and Fig. 2B is a schematic cross-sectional view showing a 2T-1C halogen structure i〇a in Fig. 2A. Referring to Fig. 2A, a display element 10a composed of an active element 2T-1C includes a pixel region composed of a scanning line 22 and a data line 24. The display unit 1〇a further includes a switching φ transistor (Switching TFT) 12 such as a bottom gate type amorphous germanium film transistor 'effectively reducing the leakage of the storage capacitor 16 and a driving transistor (Driving TFT) 14 For example, a top gated crystalline germanium thin film transistor is used to increase the brightness of the organic light emitting diode (OLED) 18 and to improve the lifetime of the display element. Referring to FIG. 2B, in this embodiment, the upper electrode 51 of the capacitor 50 is connected to the source/drain (S/D) of the bottom gate TFT 60 and is connected to the top. The gate terminal of a gate-type thin film transistor (t〇p gate TFT) 70. Furthermore, the lower electrode 53 of the capacitor 5 相 is connected to the GND, and is not connected to the source/drain r 201112414 (S/D) of the top gate TFT 70. Fig. 2C is a circuit diagram showing a 2T-1C crystal structure 10b according to another embodiment of the present invention, and Fig. 2D is a schematic cross-sectional view showing a 2T-1C halogen structure 10b in Fig. 2C. In this embodiment, the upper electrode 55 of the capacitor 50 is connected to the source/drain (S/D) of the bottom gate thin film transistor 60 and is connected to the gate terminal of the top gate thin film transistor 70. Further, the lower electrode 57 of the capacitor 50 is connected to VDD and is electrically connected to the source/drain (S/D) of the top gate thin film transistor 70. According to an embodiment of the present invention, the process for preparing the integrated microcrystalline germanium transistor and the amorphous germanium transistor in a 2T-1C display is also a seven-mask process, so that the number of process masks is not increased due to component integration. The reliability of the active component substrate circuit and the panel life can be improved. The 2T-1C process for displaying halogens includes forming a patterned halogen electrode, forming a patterned drain/source region (eg, a microcrystalline germanium transistor) and defining a patterned metal gate region (eg, an amorphous germanium transistor). , defining a first active layer (eg, a microcrystalline germanium transistor), defining a second active layer (eg, an amorphous germanium transistor), forming a contact hole, defining a gate region (eg, microcrystalline chopped transistor), and defining and pole/ A source region (for example, an amorphous germanium transistor) defines a protective layer. 3A-3H are cross-sectional views showing respective steps of a method of fabricating an organic light emitting diode display device according to an embodiment of the present invention. Referring to Figure 3A, a substrate 100 is provided having four regions, such as glass, quartz, a flexible polymeric transparent substrate or a thin metal plate. A dielectric layer 112 can be formed on the substrate 100. Next, a patterned halogen element electrode 114 is formed on the first region of the substrate. The pixel electrode 114 is, for example, a metal electrode or an indium tin oxide electrode. 201112414 Referring to FIG. 3B, a first dielectric layer 120 is formed to cover the pattern electrode 114 and the substrate 100. Next, a patterned first conductive layer 125a, 125b, and 125c are formed on the second, third, and fourth regions, respectively, as the source/drain electrodes and the bottom gate of the top gate thin film transistor. The gate electrode of a thin film transistor. Referring to FIG. 3C, a microcrystalline yttrium island 130 or a low temperature polysilicon island is formed on the second region, covering the source/drain electrodes 125a and 125b of the top gate thin film transistor as a top gate thin film The active layer of the crystal. Please refer to FIG. 3D to form a second dielectric layer 140 on the second, third and fourth regions covering the source/drain electrodes 125a and 125b of the top gate thin film transistor, the microcrystal The island 130 and the gate electrode 125c of the bottom gate thin film transistor. The material of the second dielectric layer 140 may be a tantalum nitride layer, a hafnium oxide layer, or a hafnium oxynitride layer, or other suitable dielectric layer material. Next, an amorphous germanium island 145 is formed on the second dielectric layer 140 of the fourth region, and the gate electrode 125c of the bottom gate thin film transistor is formed as an active layer of the bottom gate thin film transistor. For example, in one embodiment, after the definition step of the active layer of the top gate microcrystalline transistor is completed, three layers of SiN/a-Si/n+ a-Si are deposited directly by chemical weather deposition (CVD), wherein SiN is a common dielectric layer of a top gate transistor and a bottom gate transistor. Next, a contact hole opening H2 is formed to expose the halogen electrode 114 and the source/> and the electrode 12 5 a ' as shown in Fig. 3E. It should be noted that the use of the pixel electrode (ITO) and other materials has an etching selectivity ratio that is not destroyed when the contact hole 142 is opened. Referring to FIG. 3F, the patterned second conductive layers 150a, 150b, and 150c are formed on the second, third, and fourth regions to serve as the gate electrode of the top gate film r »7* 201112414 transistor and The source/drain electrode of the bottom gate thin film transistor. The patterned second conductive layer further includes an electrical contact 150d connecting the halogen electrode 114 and the source/drain electrode 125a. Next, a third dielectric layer 160 is formed on the second, third, and fourth regions to cover the top gate thin film transistor and the bottom gate thin film transistor, and expose the first region of the halogen Electrode 114 is shown in Figure 3G. The choice of the second conductive layer (e.g., metal) material must have an etch selectivity ratio to the underlying dielectric layer. Referring to FIG. 3H, an organic light-emitting layer 170 is formed on the third dielectric layer 160 and electrically connected to the halogen electrode 114 to form an organic light-emitting diode 180 on the organic light-emitting layer 170. The light emitting layer 170 may be a small molecule type OLED or a polymer type PLED. Furthermore, the organic light-emitting layer 170 of each element may be a corresponding color halogen (for example, red, green, blue) or a white light OLED element. Next, a protective layer 190 or a counter substrate is formed on the organic light emitting diode 180. The halogen electrode 114, the organic light-emitting layer 170, and the organic light-emitting diode electrode 180 constitute an organic light-emitting diode element. For example, the organic light emitting diode element can be an upper light emitting diode or a lower light emitting diode. 4 is a cross-sectional view showing an active device array substrate according to an embodiment of the present invention. In view of the above, according to the disclosure of the above embodiments, an active device array substrate 200 includes a pixel array having active components on a substrate. Each element includes a bottom gate amorphous amorphous thin film transistor (a-Si TFT), a storage capacitor Cs, and a top gate crystalline germanium thin film transistor (C-Si TFT), the bottom gate The gate of the amorphous germanium thin film transistor and the source/drain of the top gated crystalline germanium thin film transistor are composed of the same material layer and the source of the bottom gate amorphous cut film transistor / and pole 201112414 The gate of the top gated crystalline germanium thin film transistor is composed of the same material layer. Since the active device array substrate 200 includes a top gate microcrystalline germanium transistor and a bottom gate amorphous germanium transistor on the same pixel, and because it has both a microcrystalline germanium transistor and an amorphous germanium transistor, it can simultaneously Switching transistor with south drive transistor reliability and low leakage current. According to this crystal design, the organic light-emitting diode panel can have better panel characteristics. Furthermore, in the process of integrating the amorphous germanium transistor and the microcrystalline germanium transistor in a single element, the quality of the organic light-emitting Φ diode panel is improved without adding an additional process mask, such a halogen and process. The structural design meets the needs of both mass production and performance. The present invention has been disclosed in the above various embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 201112414 [Simplified Schematic] FIG. 1A-1F is a schematic cross-sectional view showing steps of a method for fabricating an organic light-emitting diode lower plate according to an embodiment of the present invention; FIG. 2A is a view showing a 2T-1C according to an embodiment of the present invention. The circuit of the halogen structure 10 a is not intended, and the second FIG. 2B shows a schematic cross-sectional view of the 2T-1C halogen structure 10a in FIG. 2A; the second FIG. 2C shows the 2T-1C according to another embodiment of the present invention. The circuit of the prime structure 1 Ob is not intended, and the 2D diagram shows a schematic cross-sectional view of the 2T-1C halogen structure 10b in FIG. 2C; FIGS. 3A-3H show the organic light emitting diode display device according to an embodiment of the present invention. A schematic cross-sectional view of each step of the manufacturing method; and FIG. 4 is a cross-sectional view showing the active device array substrate according to an embodiment of the present invention. [Main component symbol description] 10a, 10b~ display halogen; 12~ switching transistor; 14~ drive transistor (Driving TFT); 16~ storage capacitor; 18~ organic light-emitting diode; 22~ scan Line, 14 201112414 24~ data line; 50~capacitor; 51, 55~ upper electrode; 53, 57~ lower electrode; 60~ bottom gate type thin film transistor, 70~ top gate type thin film transistor; 100~ substrate 112~ dielectric layer; φ II4 ~ halogen electrode; 120~ first dielectric layer; 125, 125a, 125b, and 125c~ patterned first conductive layer; 130~ microcrystalline 矽 island; 140~ second Electrical layer; 145~ amorphous island, 142~ contact hole; 150, 150a-150d~ second conductive layer; • 160~ third dielectric layer; 170~ organic light emitting layer; 180~ organic light emitting diode electrode; 190~protective layer; 200~ active device array substrate. 15