TW201112002A - Data transmission device and method based on serial peripheral interface - Google Patents

Abstract

The present invention provides a data transmission method based on serial peripheral interface (SPI). The method generates a master clock for a master controller and a slave clock for a slave controller. Frequencies of the master clock and the slave clock are twice the frequency of a serial clock between the master controller and the slave controller. The master clock is counted to control data transmission of the master controller. The slave clock is counted to control data transmission of the slave controller.

Description

201112002 VI. Description of the invention: [Technical field to which the invention pertains] • _] The present invention relates to a method for data transmission of a serial data transmission, [0002], in particular, a device based on a serial peripheral interface bus and Its data transmission method. [Prior Art] The Serial Peripheral Interface (spi) is a serial synchronous communication interface. With this interface, the master device (i.e., the master) can perform data transfer in tandem with one or more slave devices (i.e., slaves). [0003] ❹ The conventional S PI bus system performs data transmission based on the serial clock signals provided by the master device to the slave devices, and transmits the bit data every serial clock cycle. By appropriately increasing the frequency of the serial clock signal, a higher data transfer rate can be obtained. For example, when the serial clock signal frequency is 8 MHz, the data transmission rate is 8 Mbps. When the frequency of the tfL 蜱 is increased to UMHz, the data transmission rate is increased to 1 bps. However, the frequency of the serial clock signal is limited. Can not be improved. For example, to ensure that the signal ' -, .4 %,, · integrity', the highest serial clock signal has a frequency of 32 MHz. Correspondingly, the data transmission rate of the traditional SPI bus system is also limited. For example, when the frequency of the highest serial clock signal is 32MHz, the maximum data transmission rate can only reach 32Mbps. [0004] On the other hand, the vast majority of current SPI bus systems use the traditional 51>1 busbars for data transmission with conventional SPI bus systems. The compatibility issue cannot be ignored. SUMMARY OF THE INVENTION 098133052 Form No. A0101 Page 3 of 37 0982056595-0 201112002 [0005] In view of the above, it is necessary to provide a device based on a serial peripheral interface (SPI) bus and its data transmission method, which can be realized High-speed data transmission, and compatible with the SPI bus system of the prior art. [0006] A host controller based on an SPI bus can perform data transmission with a slave controller based on an SPI bus, the host controller includes: a host clock generation unit for generating a host internal clock; and a slave selection a unit, configured to select a slave controller for data transmission with the host controller; a host clock divider unit, configured to divide the host internal clock by a frequency division to generate a serial clock signal, and send the serial clock signal to the selected one Slave controller; host clock counting unit for counting the internal clock of the host: host address buffer for buffering the destination address sent to the selected slave controller; host output data buffer for buffering and sending A valid data for the selected slave controller; a host output control logic unit for generating a read/write operation control character, reading a target address transmitted from the host address buffer to the selected slave controller, The host output data buffer reads the valid data sent to the selected slave controller and presses according to the internal clock of the host and the internal clock count value of the host. The specified sequence sends the read/write operation control character, the target address, and the valid data to the selected slave controller, and the read/write operation control character is used to control the selected slave controller to perform the corresponding read/write. And the host input control logic unit is configured to receive the valid data sent by the selected slave controller according to the internal clock of the host and the internal clock count value of the host, and buffer the received valid data into the host input data buffer. [0007] A data transmission method based on a serial peripheral interface (SPI) bus for data transmission between a host controller and a slave controller, the 098133052 Form No. A0101 Page 4 of 37 pp. -0 201112002

The method comprises the steps of: the host controller generates a host internal clock; the host control selects a slave controller for data transmission; the host controller divides the internal clock of the host to generate a serial clock signal, and sends the serial clock signal to the selection. The slave controller; the slave controller will serialize the clock signal - the multi-frequency raw machine internal clock; the domain (four) the internal of the host: know the number of pieces of material H to count from the oil clock; the host control inside the machine. The p-time value and the host internal clock transmit the 4/write operation control character and the target address in the specified order, and the slave controller receives the read/write operation control character according to the slave internal clock count value and the slave internal clock. And the target address; corresponding to the write operation control #, the host controller sends the valid data according to the clock value of the host (four) clock in the host, and the slave controller according to the internal clock count value of the slave and the internal clock of the slave Receiving valid data and writing the valid data to the storage unit specified by the destination address, or corresponding to the read operation control, the slave controller reads the valid data from the storage unit specified by the target address, and according to the slave The internal clock of the machine: and the internal clock count value of the slave, the valid data is sent to the host controller in the specified order, and the host controller receives the valid data according to the internal clock of the host and the internal clock count value of the host; and the host controller ends the pair The choice of slave controller. [0008] The present invention doubles the frequency of the internal clock of the master controller and the slave controller, and utilizes multiple control logic units to coordinate data transmission between the host controller and the slave controller, and transmits each half of the serial clock cycle. The round-bit data enables high-speed data transfer. Moreover, the present invention supports single-speed data transmission to accommodate conventional SPI bus systems. [Embodiment] 098133052 Form No. A0101 Page 5 of 37 0982056595-0 201112002 [_9] Referring to FIG. 1, a system architecture of a preferred embodiment of a Serial Peripheral Interface (SPI) bus system Figure. The SPI bus system 1 includes a host controller and one or more slave controllers, such as slave controllers 12A-12D. Data transfer between the host controller u and the slave controllers 12A-12D through the SPI bus 13 is performed. The SPI bus 13 includes a serial clock signal line 14, a master wheel/slave input data line 15, a master wheeling/slave output data line 16, and a slave select signal line 17A-17D. The serial clock signal line ι4 transmits a serial clock signal (SCLK), and the host output/slave input data line 15 transmits data (M0SI) sent by the host controller 11 to the slave controller 12A_12D, the host input The slave output data line 16 transmits the data (μ丨ς〇) sent from the slave controllers 12A-12D to the host controller η, and the slave selects the signal line 17A-17D to transmit the slave selection signal (/SSb) /SS4). The SPI bus system 10 operates in a manner that includes write operations and read operations. The host controller 11 has the initiative of the SPI bus control, and both the read and write operations are initiated by the host controller 11. When the write operation is performed, the host controller 11 transmits the target address and the valid data to the slave controllers 12A-12D, and the slave controllers 12A-12D write the valid data to the storage unit designated by the target address. During the read operation, the host controller u sends the target address to the slave controllers 12A-12D 'the slave controllers 12A-12D to read the valid data from the storage unit specified by the target address, and returns the valid data to the host. Controller 11. [0010] Referring to FIG. 2, it is a detailed architecture diagram of the host controller U in FIG. The host controller 11 includes a host clock generating unit 2, a slave selecting unit 210, a host clock dividing unit 220, a host clock counting unit 23〇098133052, a form number A0101, a sixth page, a total of 37 pages, 20, 925, 659, 550, a The address buffer 240, the host output data buffer 250, the host input-bedding buffer 260, the host output control logic unit 270, and the host wheeling control logic unit 280. [0011] The host clock generating unit 200 generates a host internal clock, and outputs the host internal clock to the slave selecting unit 21, the host clock dividing unit 220, the host clock counting unit 23, and the host output control logic unit. 270 and the host input control logic unit "o. The host internal clock is used for the slave selection unit 21, the host clock division unit 22, the host clock counting unit 230, the host output control logic unit 27, and the host input control logic unit. The signal outputted by 280 is synchronized. In this embodiment, the host clock generating unit generates a host internal clock according to a system clock provided by an external circuit (for example, an external crystal oscillator circuit). For example, a system provided by an external crystal oscillator circuit is assumed. The clock frequency is 16ΜΗζ, the host controller U needs a 64MHz host internal clock, then the host clock generation unit 2〇〇 quadruples the system clock to generate a 64MHz host internal clock.

Ud κ I

[0012] Ο The slave selection unit 210 generates a slave selection and is sent by the slave selection signal line 17A-17D to the slave control piano 12A-12D to indicate whether the slave controller 12A-12D is Data transmission is performed with the host controller 11. Specifically, 'when the host controller 11 and the slave controller 12A, 12B, 12C or 12D perform data transmission, the slave selection unit 210 sets the corresponding slave selection signal to be valid. When the data transmission is completed, the slave The machine selection unit 210 disables the corresponding slave selection signal. In the present embodiment, the slave selection signals transmitted from the host controller 11 to the slave controllers 12A, 12B, 12C, and 12D are /SSI, /SS2, /SS3, and /SS4, respectively. Assuming that the slave select signal is active low, if the host controller 11 selects to perform data transfer with the slave 098133052 Form No. A0101, page 7/37 page 0982056595-0 201112002, the slave select unit 210 will /SS2 Set low to set /SSI, /SS3, and /SS4 high. When the data transfer from the master controller 11 and the slave controller 12B is completed, the slave selecting unit 200 sets the slave select signal /SS2 to a high level. In the present embodiment, the slave selecting unit 200 generates the slave select signals /SSI, /SS2, /SS3, and /SS4 based on the selection control signals supplied from the external device (e.g., the processor).

[0013] The host clock frequency dividing unit 220 divides the internal clock of the host into a serial clock signal, and sends the serial clock signal from the serial clock signal line 14 to the slave controllers 12A-12D. Obviously, the frequency of the internal clock of the host is twice that of the serial clock signal. V

13⁄4 丨 II

[0014] The host clock counting unit 230 counts the internal clock of the host, and outputs the internal clock count value of the host to the slave selecting unit 2H), the host output controlling logic unit 270, and the host input controlling logic unit 280. The slave selection unit 210 determines whether or not the data transmission is completed based on the host internal clock count value of the host clock counting unit 230. For example, suppose that 32-bit data needs to be transferred between the host controller 11 and the slave controller 12, each host transmits 1 bit of data in the internal clock cycle, and the host internal clock count is incremented by 1 every one internal clock cycle. If the host clock counting unit 2 3 0 starts counting from 〇, then counting to 31 indicates that the data transmission is completed. The host clock counting unit 230 may be configured to increment the host internal clock count value by one every internal host clock cycle, or increase the host internal clock count value by one every two host internal clock cycles, thereby controlling the host controller 11 and The data transfer rate of the slave controller 12. Specifically, when it is required to transmit the data at twice the speed (that is, twice the frequency of the serial clock signal), 098133052 Form No. 1010101 Page 8/37 Page 0982056595-0 201112002 When the data is transmitted, the host clock counting unit 23 A host internal clock cycle increments the host internal clock count by one; when it is required to transfer data at a single rate (ie, at the same rate as the serial clock signal frequency), the host clock count unit 230 will pass each of the two host internal clock cycles. The internal clock count value of the host is incremented by 1. In this embodiment, the host clock counting unit 23 controls the operation mode of the signal according to the counting mode provided by the external device. For example, when the counting mode control signal is 丨, the host clock counting unit 230 increments the host internal clock count value Ο [0015] every two clock cycles in the host, and each time the counting mode control signal is 〇 The host internal clock cycle host clock counting unit 23 〇 provides the host internal clock count value plus j 〇 the host address buffer 24 〇 provides storage space, and the buffer is sent to the target address of the slave controller 12 Α -12D; The host output data buffer 250 provides storage space and caches valid beeps sent to the slave controller. In this embodiment, the # machine address buffer 24 receives the valid data provided by the external device, and the host output data buffers the destination address provided by the external device. further? The host address buffer uses two address buss to receive the target address provided by the external device, and the host output data buffer 250 uses two data buss to receive the valid data provided by the external device. [0016] The host rotation control logic unit 27G generates a read/write operation control character, reads a target address transmitted from the machine address buffer 240 to the slave controller 12^121), and outputs data from the host. The buffer 25Q reads the valid data sent to the slave controllers 12A, 12D, and according to the internal clock of the host and the main clock count value, the read/write operation control character, target 098133052 form number_1, ninth according to the specified order. Page / Total 37 pages 0982056595-0 201112002, X and active > are sent by the master output/slave input data line 15 to the slave controllers 12A-12D. For a write operation, the host rotates the control logic to generate a write operation control; for a read operation, the host output control unit 270 generates a 6 buy operation control. The host rotation control logic unit 270 transmits data on the edge of the host internal clock. For example, special data is sent on the rising edge of each host's internal clock. Alternatively, a 1-bit data is transmitted on the falling edge of each host's internal clock. [0018] 098133052, the host input control logic unit 28 receives the valid signals sent by the slave controller 12A_12D by the master input/slave wheel data line 16 according to the host internal_and the host internal clock count value, and The received valid data is cached to the host input data buffer 26G. The main state input control logic unit 280 is connected to the data on the transition edge of the internal clock of the host. For example, Ub#f^ ^ is received on the rising edge of each host's internal clock or 1-bit data is received on the falling edge of each host's internal clock. In the present embodiment, the host output control logic unit 27G and the host input control logic unit 280 perform read/write operations in accordance with the _device providing (four)/write control signals. When __view_, the host output (4) logic unit 270 generates a write operation control character, and sends the write operation_address destination address and valid data to (4)! i12A_12D; when receiving the read (four) signal, the host output control logic unit 27G generates a read operation control character, and sends the read operation control character and the target address to the slave controller i2A_m, and the host input control logic unit 28 receives the slave The valid data returned by the controller ^(10) is cached in the host input data buffer 26〇. Referring to Figure 3, a detailed architecture diagram of the slave controller of Figure 4 is shown. The slave controllers 12A-12D include a slave clock multiplier unit 3A, a slave form number Α0101, a 10th page, a total of 37 pages, and a [0019] 201112002 [0020] Ο [0021] 〇 [0022] 098133052 The number unit 310, the slave input control logic unit 320, the slave output control logic unit 330, the slave address buffer 340, the slave input data buffer 350, the slave output data buffer 36, and the slave operation control logic Unit 370 and slave target memory 380. The slave clock multiplying unit 3 receives the serial clock signal sent by the host controller by the serial clock signal line 丨4, and generates the slave internal clock by the double frequency of the serial clock signal' and the slave The internal clock is output to the slave clock counting unit 31, the slave input control logic unit 32, and the slave output control logic unit 330. Similarly to the internal clock of the master, the slave internal clock is used to synchronize the signals output from the slave clock counting unit 31, the slave input control logic unit 320, and the slave output control logic unit 33. The internal clock of the slave is twice the frequency of the serial clock signal. In the present embodiment, the slave clock multiplier unit 300 uses a phase locked loop circuit to double the serial clock signal. The phase-locked loop circuit receives the system clock provided by the external circuit as a reference clock e (jn, the slave clock counting unit 310 receives the slave signal sent by the host controller 11 by the slave select 1 signal line 17--171) The acoustic selection signal, when the slave select signal is valid, 'counts the internal clock of the slave, and outputs the slave internal clock count value to the slave input control logic unit 320 and the slave output control logic unit 330 » the slave input The control logic unit 320 receives the read/write operation control character, the target address and the valid data sent by the host controller 11 from the master output/slave input data line 15 according to the slave internal clock and the slave internal clock count value, and will receive the received data. The target address is buffered into the slave address buffer 340, and the received valid data is buffered to the slave input data buffer 350, and according to the read/write operation of the receiving form number A0101 page 11/37 page 〇982 201112002 The control character generates a corresponding read/write operation output to the slave operation control logic, and the right received write control symbol, then the slave input control logic unit 320 generates a read y3 if received. On the day, the input logic control unit Μ0 produces the Tr signal 1 machine input logic control unit 306 unit receives data from the edge of the = clock transition. For example, the rising edge of each slave is touched by a special request. Alternatively, receive 1 bit of data on the falling edge of each slave clock. . The slave operates the control logic unit 37. The corresponding operation is performed according to the received read/write operation control signal. Specifically, when the (four) write operation; the message is said, the target address buffered from the location area 340 and the valid data buffered by the slave input data buffer 350 are read from the display (4) transfer 37G, and will be valid. f is stored in the _# standard memory (10) target address missing _ memory unit; or when __ as a control signal 'slave operation control logic unit 370 reads the slave address buffer 340 cached target value address, The edge target bit reads the valid bee material in the specified storage unit and buffers the valid data into the slave output data buffer 360. In this embodiment, the slave operation control logic unit transmits the data through two addresses. The row is connected to the slave address buffer 34 (), connected to the slave input data buffer 350 through two input data buss, and connected to the slave output data buffer 36 through two output bus buffers. . If the data is transmitted at twice the speed, the slave operation control will use 7 address bus, two wheel data bus and two wheel data bus to transmit data. If the single-speed transmission m slave operation control logic unit 370 uses one of the address bus, one input data bus 098133052, the form number A0101, the 12th page, the total output page, the data transmission line for data transmission . [0024] The slave output control logic unit 330 reads the valid data buffered by the slave output data buffer 36, and outputs the data line 16 by the master input/slave according to the internal clock of the slave and the internal clock count value of the slave. The valid data read is sent to the host control in the specified order (4). The slave output control logic unit 330 transmits data on the edge of the slave internal clock. For example, the 丨 bit data is transmitted on the rising edge of each slave's internal clock. Alternatively, the 丨 bit data is transmitted on the falling edge of each slave's internal clock. [0025] Referring to FIG. 4, a flow chart of a preferred embodiment of a data transmission method based on a serial peripheral interface (spi) bus bar of the present invention is shown in the flowchart of the host controller 11 and the slave controller 12B in FIG. The data transmission is described as an example. [0026] Ο Step S4 (U, the host clock generates a single (four) Q to generate a host internal clock and outputs the internal clock of the host to the slave selection unit 21, the host clock is divided, and the unit 22G 'host clock turns Material 23 (}, host rotation control logic early 270 and host input (four) logic single, element 28 (^ host internal clock for slave_unit 2U), host time - frequency single, host clock counting unit 230, the host output control (4) unit 27 () and the signal output by the host input control logic unit 28 () are synchronized. In this embodiment, the host clock generates a single (four) Q according to an external circuit (such as an external crystal oscillator circuit) provided by the line The clock generates a host internal clock. For example, if the external crystal oscillator circuit provides a system clock frequency of 16 MHz and the host controller 11 requires a 64 MHz internal domain, the L-machine clock generating unit 200 quadruples the system clock, thereby Generating the internal clock of the host 2_2 098133052 Form No. A0101 Page 13 of 37 0982056595-0 201112002 闺Step S4〇2, the slave selecting unit 210 transmits the slave selected signal line i?B to the slave controller 12B. The machine selection signal /SS2 is asserted. Assuming that the slave select signal is active low, the slave select unit ... puts / speaks low. 阙Step S403, the master clock divider unit 22 〇 will host the internal clock two The serial clock signal is generated by frequency division and transmits the serial clock signal from the serial clock signal line 14 to the slave controller m. As described above, the frequency of the internal clock of the host is twice that of the serial clock signal. Step 0404, the slave clock multiplying unit 3 of the slave controller 12B double-frequency generates the slave internal clock, and outputs the slave internal clock to the slave clock counting unit 310. The slave wheel control logic unit 320 and the slave output control unit _, the frequency of the internal clock of the slave is the same as the internal clock of the master, which is twice the serial clock signal. In this embodiment, the slave Clock multiplier The unit 3〇〇 uses a phase-locked loop circuit to double the serial clock signal. When the phase-locked loop circuit receives the system clock provided by the external circuit as a reference, the clock.... _] step S405 'host stupid counting unit 23〇 Counting the internal clock of the host, and outputting the internal clock count value of the host to the slave selection unit 21, the host output control logic unit 270, and the host input control logic unit 28; the slave clock "ten number 310" to the slave internal The clock is counted and the slave internal clock count value is output to the slave input control logic unit 32 and the slave output control logic unit 330. The host clock counting unit 23〇 can be set to increment the host internal clock count value by one internal clock cycle, or the master internal clock count value is incremented by one after two host internal clock cycles, thereby controlling the host controller. 11 and slave controller 丨 2 098133052 Form No. A0101 Page 14 of 37 nC) Si 201112002 Data transfer rate. Specifically, the standby clock phase, the mysterious, and the field must be doubled (that is, the rate of the tandem unit = frequency twice). The value is added to the host internal clock cycle to the host internal clock count = value &quot When the material needs to be transmitted at a single speed (that is, the same frequency as the serial clock signal frequency = rate), the host clock counting unit adds the internal clock count value of the host every two internal clock cycles! . [0031] ❹ 098 098133052 Step S406 The host control passes the read/^ operation control character and the target address between the slave (4) device (10). Specifically, the host output control logic (four) generates a read/write operation control character, reads from the host address buffer 240 and sends it to the slave (4) target, the root clock internal clock and the host _^ clock count value will The read/write operation control character and the target address are transmitted from the master output/slave input data line 15 to the slave controller 12 in the order of (4); the slave wheel control logic unit is based on the slave internal clock and the slave internal The clock count value receives the read/write operation control character and the target address sent by the host controller, buffers the received target address to the slave address buffer 340, and stores the received east$ data g to the slave input. The data buffer 350' and based on the received; read/write operation control generates a read/write operation control signal and outputs it to the slave operation control logic unit 37A. For example, the host output control logic unit 27 sends a 1-bit read/write operation control character when the host internal clock count value is 〇 or 1, and transmits when the host internal clock count value is 2, 3, ..., or 15. 1-bit target address. The slave input control logic unit 320 receives a 1-bit read/write operation control when the slave internal clock count value is 〇 or 1, and receives when the slave internal clock count value is 2, 3..... or 15. 1 bit target address "And, the host output control logic unit 270 transmits data on the transition edge of the host internal clock, from the form number A0101 page 15 / 37 pages 0982056595-0 201112002 machine input control logic unit 3 in the slave The data is received on the edge of the skip. [0032] Step S407 'The effective data is transmitted between the host controller n and the slave controller m. In this step, for the write operation (at this time, the slave input control logic unit 320 transmits the write operation control slave slave operation control logic unit 37). The host wheel control logic unit 27 () outputs the data buffer 25G from the host. The valid data sent to the slave controller 12B is read, and the valid data is sent from the host output/slave input data line 15 to the slave according to the host clock count single cut (four) host internal clock and the host internal clock count value in a specified order. Machine control · 12 Β ; slave input control logic unit 320 receives valid data according to the value of the slave clock and the slave material. The slave operation control logic (10) 〇 root operation (4) signal writes the valid data received to the target position. The storage unit of the slave target memory class specified by the address is for the read operation (at this time, the slave input control logic unit 32 sends the read operation control signal to the slave operation control logic unit 37), and the slave operation control logic unit 37Q Read operation (4) The slave target memory 38_ storage unit specified by the source target address reads the valid data and buffers it into the slave output data buffer 36〇 The slave output control logic unit 330 reads the valid data, and sends the valid data to the host controller U according to the slave internal clock and the slave internal clock count value in the specified order from the host input/slave output data line 16. The host input control logic unit 280 receives the valid data sent by the slave output control logic unit 330 according to the host internal clock and the host internal clock count value and buffers the received valid data to the host input data buffer 260. The slave output control logic unit 330 transmits data on the edge of the slave internal clock. Main 098133052 Form No. A0101 Page 16/37 Page 0982056595-0 201112002 [0033] [0035] 〇[0036] The machine input control logic unit receives data on the edge of the internal clock of the host. 'From the money control briefing unit holding a single speed of the shell transfer wheel' also supports double-speed data transmission. Step S408 After the data transmission of the master controller u and the slave controller 12B is completed, the slave selecting unit 200 sets the slave select signal /SS2 to be invalid, for example, sets /SS2 to the level. In the present embodiment, the slave selecting unit 210 determines whether or not the data transmission of the host controller 11 and the slave controller 12B is completed based on the host internal clock count value of the host clock counting unit 23A. For example, 'assuming that 32-bit data needs to be transferred between the host controller 11 and the slave controller 12, each host transmits 1 bit of data in the internal clock cycle, and the host internal clock count is incremented by 1 every one internal clock cycle. If the host clock counting unit 230 starts counting from 0, counting to 31 indicates that the data transmission is completed. Figures 5 to 8 are schematic views of the data of the double-speed transfer wheel. 5(:1^ indicates the serial clock signal, 2xSCLK indicates the internal clock of the host, /SS2 indicates the slave selection signal +MOSI of the slave controller 12B indicates the data on the host output/slave input data line 15, MISO indicates In the example shown in Figure 5 to Figure 8 of the master input/slave output data line 1_6, data transmission is performed by means of interleaved transmission. 'Every valid data is transmitted each time. Each valid data is 8 bits, each The target address corresponding to the valid data is 7 bits, and each valid data corresponds to a 1-bit read/write operation control character, wherein the first valid data (hereinafter referred to as the first valid data) is D0, and the corresponding first target The address is 098133052 Form No. A0101 Page/Total 37 Page 0982056595-0 201112002 A0 'The number of bits of valid data from low to high is D〇〇, D〇i, D〇2, D03, D04, D05, D06, D07, each bit of the first target address is A00, A01, A02, A03, A04, A05, A06, A07 from low to high. The second valid data (hereinafter referred to as the second valid data) is D1, Corresponding second target address is A1, second The bits of the valid data are from low to high D10, Dll ' D12, D13, D14, D15, D16, D17 'The bits of the second target address are from 1 to 1, A11, A12, A13, A14. A15, A16, A17. As can be seen from FIG. 5 to FIG. 8, two read/write operation control symbols are first transmitted between the host controller 11 and the slave controller i2B, and then two target addresses are transmitted, and finally two transmissions are performed. Valid data, and in the order from low to present: the target address and the bits of the valid data are transmitted. The order of the address and address ▲ is: A, Α10, Α01, Ail, Α02, Α12, Α03, Α13 , Α〇4, Au ' Α05, Α15, Α06, Α16, the order of sending valid data is: D〇〇, DIO, D01 ' Dll, D02, D12, D03, D13, D04, D14, D05, D15, D06, D00, D06, D16. [0038] Specifically, FIG. 5 is a schematic diagram of performing two write operations in a continuous manner. First, the write operation control symbols /wo and /wi are transmitted, and then the target addresses A0 and A1 are transmitted. Finally, the valid data DO and D1 are transmitted, and the write operation controllers 1〇 and 〆W1, the target addresses A0 and A 1 and the valid data D〇 and m are both transmitted by the master output/slave input data line 15. Figure 6 is a schematic diagram of two consecutive read operations. The read operation control characters R0 and R1 are transmitted first, and then the target address is transmitted. ", the last valid data D0 and D1 are transmitted. Moreover, the read operation control symbols and the target addresses A0 and A1 are transmitted by the host output/slave input data line 15 as valid data 098133052 Form No. A0101 Page 18 of 37 0982056595-0 201112002 DO and D1 are transmitted by the master wheel/slave input data line 16. [_ Diagram of money execution - write operation and - read operation. First, the write operation control/W〇 and the read operation control are transmitted, then the target addresses A〇 and A1 are transmitted, and the valid data DO and D1 are finally transmitted. Moreover, the write operation control symbol /W, the read operation control symbol R1, the target address A0 and A1, and the valid data DO are transmitted by the host output/slave input data line 15, and the valid data D1 is input by the host input/slave data. Line 16 passes. [0040] 098 [0043] FIG. 8 is a schematic diagram of sequential execution - secondary read operation and - secondary write operation. First, transfer read operation control fine and write operation control (4) / W transfer destination address A0 and A1 ' last transmission of valid data (10) and ^. Moreover, the read operation control fine and write operation control, the target address _A1 and the valid data D1 are transmitted by the host output/slave input data line ι5, and the valid data (10) is transmitted by the host input/slave input data line 16. ~ Tian can understand that if the SPI bus system 1Q transmits data at a single speed, the write operation is performed as shown in Fig. 9, and the teaching operation is performed as shown in Fig. 9. With the present invention, the SPI, bus system 1Q can transmit 1 bit of data every half of the serial clock signal period. Compared with the conventional SPI bus system, it achieves a higher data transmission rate, for example, if the highest serial number The frequency of the clock signal is 32. The SPI bus system of the prior art can only reach the data transmission rate of ^(4)_8, and the bus system 10 of the present invention can achieve the data transmission rate of up to 64 Mbps. Moreover, the master controller 11 and the slave controller 12 _121) both support the single-speed carrier: the SPI bus system that is compatible with the conventional technology. In summary, the present invention meets the requirements of the invention patent, and the United States legally proposes a patent form bat spicy deletion 1 帛 I9 1 / a total of 37 pages 0982056595-0 201112002 application. The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0044] FIG. 1 is a system architecture diagram of a preferred embodiment of a serial peripheral interface bus system. [0045] FIG. 2 is a detailed architecture diagram of a host controller in FIG. 3 is a detailed architecture diagram of the slave controller of FIG. 1. 4 is a schematic diagram of a preferred embodiment of a data transmission method based on a tandem peripheral interface bus of the present invention. 5 is a schematic diagram of two consecutive write operations when data is transmitted at twice the speed. [0049] FIG. 6 is a schematic diagram of two consecutive read operations when data is transmitted at twice the speed. [0050] FIG. A schematic diagram of performing a write operation and a read operation successively when transferring data at a double speed. [0051] FIG. 8 is a schematic diagram of performing a read operation and a write operation successively when data is transmitted at twice the speed. [0052] FIG. 9 is a schematic diagram of a write operation performed when data is transmitted at a single speed. [0053] FIG. 10 is a schematic diagram of a read operation performed when data is transmitted at a single speed. [Main component symbol description] 098133052 Form No. A0101 Page 20 of 37 0982056595-0 201112002

SPI Bus System 10 [0055] Host Controller 11 [0056] Slave Controller 12A-12D [0057] SPI Bus 13 [0058] Serial Clock Signal Line 14 [0059] Master Output/Slave Input Data Line 15 [0060] Master Input/Slave Output Data Line 16 [0061] Slave Select Signal Line 17A-17D [0062] Master Clock Generation Unit 200 [0063] Slave Select Unit 210 [0064] Host Clock Divider Unit 220 [0065] Host clock counting unit 230: ; ; .丨;7 i| gas. [0066] Host address buffer 2 40 ! ii - , w *; [0067] Host output data buffer 250 [0068] Host Input Data Buffer 260 [0069] Host Output Control Logic Unit 270 [0070] Master Input Control Logic Unit 280 [0071] Slave Clock Multiplier Unit 300 [0072] Slave Clock Counting Unit 310 098133052 Form Number A0101 Page 21 / 37-201112002 [0073] Slave Input Control Logic Unit 320 [0074] Slave Output Control Logic Unit 330 [0075] Slave Address Buffer 340 [0076] Slave Input Data Buffer 350 [0077] Slave Output Data Buffer 360 [0078] Slave Operation Logic unit 370 [0079] Slave target memory 380 〇 [0080] Generate host internal clock S401 [0081] Slave select signal is asserted S402 [0082] Transmit serial clock signal S403 [0083] Generate slave internal clock S404 [0084] respectively transmit the read/write operation control character and the target address S406 to the internal clock of the master and the slave internal clock S405 [0085] [0086] Transfer valid data S407 [0087] The slave select signal is invalid S408 098133052 Form number Α0101 Page 22 of 37 0982056595-0

Claims (1)

201112002 VII. Patent application scope: 1. A host controller based on a serial peripheral interface (.SPI) bus, which can perform data transmission with a slave controller based on SPI bus. The host controller includes: host clock generation a unit for generating a host internal clock; a slave selecting unit for selecting a slave controller for data transmission with the host controller; and a host clock dividing unit for dividing the internal clock of the host to generate a serial clock signal And sending the serial clock signal to the selected slave controller 主机 the host clock counting unit for counting the internal clock of the host; the host address buffer for buffering the target bit sent to the selected slave controller The host output data buffer is used to buffer the valid data sent to the selected slave controller, and the host output control logic unit is configured to generate a read/write operation control character, which is read and sent from the Q host address buffer. The target address of the selected slave controller is read from the host output data buffer and sent to the selected slave controller. Valid data, and send the read/write operation control character, the target address, and the valid data to the selected slave controller according to the internal clock of the host and the internal clock count value of the host, wherein the read/write operation control character The slave controller for controlling the selection performs a corresponding read/write operation; and the host input control logic unit is configured to receive the valid data sent by the selected slave controller according to the internal clock of the host and the internal clock count value of the host, The received valid data is cached in the host input data buffer. The SPI bus-based host controller of claim 1, wherein the host clock counting unit transmits data at twice the speed, as described in claim 1 of the invention. The host internal clock count is incremented by one each time a host internal clock cycle is passed, and the host internal clock count is incremented by one every two host internal clock cycles when transmitting data at a single rate. 3. The SPI bus-based host controller of claim 1, wherein the host output control logic unit transmits the read/write operation control character, the target address, and the valid data in an interleaved manner. 4. The SPI bus-based host control device according to claim 1, wherein the slave selection unit determines whether the data transmission is completed according to a host internal clock count value of the host clock counting unit, and if the data transmission is completed. , then the selection of the slave controller is ended. 5. A slave controller based on a serial peripheral interface (SPI) bus, which can perform data transfer with a host controller based on an SPI bus, the slave controller comprising: a slave clock multiplier unit for Receiving the serial clock signal sent by the host controller, generating the slave internal clock by double the frequency of the serial clock signal; y the slave clock counting unit, configured to perform data transmission with the slave controller when the host controller selects The slave internal clock is counted; the slave input control logic unit is configured to receive the read/write operation control character, the target address, and the valid data sent by the host controller according to the slave internal clock and the slave internal clock count value. Cache the received target address into the slave address buffer, buffer the received valid data into the slave input data buffer, and generate a corresponding read/write operation control signal according to the received read/write operation control character; The slave operation control logic unit is used when receiving the write operation control signal, 098133052 Form No. A0101 Page 24/37 Page 0982056595-0 201112002 Read the valid data of the buffer buffer of the slave address buffer buffer, and π卩 and the library address data specified by the target address of the slave input data buffer: when storing to the slave target memory signal, read The slave 70 is taken, or when the storage unit specified by the read operation control address is received, the tagged address is read, and the data buffer is output from the target bit to the slave; and the valid data is buffered ο ο ===: :::, round __cache_valid _=::__value-based on the serial peripheral interface (s "machine control. Used in the main" bus data transfer method, used in the host controller and The slave controller method includes the steps of: resource transfer, the host controller generates a host internal clock; the host controller selects a slave controller for data transmission. The host internal clock is divided by two to generate a serial clock signal. The serial clock signal is sent to the __ controller. The slave controller doubles the serial clock signal to the slave internal clock. The host control n pairs the host (four) clock count, the slave control master slave clock count ; The host controller is based on the host The clock count value and the host internal clock send the read/write operation control character and the target address in the specified order, and the slave controller receives the read/write operation control character and the target bit according to the internal clock count value of the slave and the internal clock of the slave. Corresponding to the write operation control character, the host controller sends valid data according to the internal clock count value of the host and the internal clock of the host in the specified order, and the slave controller selects according to the internal clock count value of the slave and the internal clock of the slave. 098133052 Form No. A0101 Page 25 of 37 0982056595-0 201112002 Receive valid tribute and write the valid data to the storage early element specified by the destination address, or corresponding to the read operation control, the slave controller The storage unit specified by the target address reads the valid data, and sends the valid data to the host controller according to the internal clock of the slave and the internal clock count value of the slave, and the host controller according to the internal clock of the host and the internal clock of the host The count value receives the valid data; and the host controller ends the selection of the slave controller Choose. 7. The SPI bus-based data transmission method according to claim 6, wherein in the step of the host controller counting the internal clock of the host, the host controller passes each host when transmitting data at twice the speed The internal clock cycle increments the host's internal clock count by one, incrementing the host's internal clock count by one every two host internal clock cycles when transferring data at a single rate. 8. The SPI bus-based data transmission method according to claim 6, wherein the host controller transmits a read/write operation control character and a target according to a host internal clock count value and a host internal clock in a specified order. In the step of address, the host controller sends the read/write operation control character and the target address in an interleaved manner, and the host controller sends the valid data according to the internal clock count value of the host and the internal clock of the host in a specified order. The host controller sends valid data by means of interleaved transmission. 9. The SPI bus-based data transmission method according to claim 6, wherein in the step of the host controller ending the selection of the slave controller, the host controller determines whether the host internal clock count value is After the data transmission is completed, if the data transmission is completed, the selection of the slave controller is ended. 098133052 Form No. A0101 Page 26 of 37 201112002 10 . SPI bus-based data transmission method as described in claim 6 The slave controller generates a slave clock signal by a factor of two times to generate a slave internal clock, and the slave controller uses a phase locked loop circuit to double the serial clock signal. Ο 098133052 Form number Α0101 !3 Page 27 of 37 0982056595-0