TWI386813B - Method and apparatus for communicating a bit per half clock cycle over at least one pin of an spi bus - Google Patents

Description

Method and apparatus for transmitting one bit per half-clock cycle on at least one pin on a sequence peripheral interface bus [Related application materials]

U.S. Application No. 11/748,984, filed on Jun. Priority is claimed in U.S. Patent Application Serial No. 11/773,704, filed on Jan. No. No. No.

The invention relates to a method for data transmission in an integrated circuit, in particular to increase the peripheral interface bus in the sequence by transmitting one bit per half clock cycle on at least one pin on the sequence peripheral bus bar. The method of transferring data speed.

The present invention relates to a Sequence Peripheral Interface (SPI) bus with a data output pin and a data input pin. For example, the sequence interface of the sequence peripheral interface has an advantage over the parallel interface, that is, the sequence peripheral mask has a relatively simple connection. Furthermore, as clock speeds increase, the advantages of parallel interfaces in transmission speed become less and less important. However, in applications where speed and simplicity are important, it is still desirable to continue to use the standard Serial Peripheral Interface (SPI) bus, while at the same time increasing its transmission speed.

It is an object of the present invention to provide an integrated circuit comprising a busbar according to a sequence peripheral interface standard between the integrated circuit and another integrated circuit Data transfer. The bus bar has a plurality of pins, including: a first data transmission pin to perform the data transmission on the bus, and a second data transmission pin to perform the data transmission on the bus, a wafer selection The pin indicates whether the data transmission is being performed between the integrated circuit and another integrated circuit, and a clock signal provides a clock signal to the bus. Depending on the mode configuration settings, the bus can be operated in different modes, and the definition and function of the output/input pins are different. The first operation mode and the second operation mode are exemplified below. The sink may operate in at least one first mode of operation, wherein in the first mode, the first data transfer pin transmits data at a rate of one bit of a clock signal at a half cycle. In some embodiments, the second data transmission pin also transmits data at a rate of one-half cycle of one clock signal.

In some embodiments, the bus bar also has a second mode in which the first data communication transmission pin transmits data communication at a rate of one cycle of one clock signal. The circuit includes a mode control circuit to selectively operate in one of a plurality of modes of operation, such as a first mode or a second mode. In different embodiments, in at least one mode of operation (eg, the first mode of operation or the second mode of operation), the data transmission pin is transmitted from the integrated circuit to another integrated circuit, and/or Data is transferred from another integrated circuit to the integrated circuit.

In some embodiments, the bus bar uses a redundant period to compensate for a delay of another integrated circuit.

In some embodiments, a memory is further coupled to the bus.

In various embodiments, the integrated circuit can be a main integrated circuit or a redundant integrated circuit.

In some embodiments of the main integrated circuit, the plurality of pins includes a plurality of chip select pins, and each of the plurality of chip select pins is indicated by the main integrated circuit and a further servo circuit. Whether data transfer is in progress.

In some embodiments of the servant circuit, the wafer select pin indicates whether data transfer is in progress between the main body circuit and the servant circuit.

In some embodiments, the first data communication transmission pin and the second data communication transmission pin perform data transmission between the integrated circuit and another integrated circuit in the same direction.

Another object of the present invention is to provide a method for data transmission between integrated circuits, comprising the steps of: providing a clock via a clock pin to a bus according to a sequence peripheral interface standard, the bus bar being in the product Data is transferred between the body circuit and another integrated circuit.

A wafer select signal is transmitted to indicate whether the data transfer is in progress between the integrated circuit and another integrated circuit.

a first data transmission pin of the bus bar and a second data transmission pin for data transmission between the integrated circuit and another integrated circuit, wherein the first data communication transmission pin is at least at one In the first mode of operation, data is transmitted at a rate of one-half cycle of one clock signal.

Other embodiments are described later.

It is still another object of the present invention to provide an apparatus for data transmission between integrated circuits, comprising: a clock function means for providing a clock to a busbar according to a sequence peripheral interface standard, the busbar being arranged in the integrated body Data is transferred between the circuit and another integrated circuit.

The wafer selects a signal transfer function means to indicate whether the data transfer is in progress between the integrated circuit and another integrated circuit.

In a first mode of the bus, the data transmission function means to perform between the integrated circuit and the other integrated circuit on a first data transmission pin and a second data transmission pin of the bus The transmission of this data, including: The data transmission function on the transmission bit of the first data communication transmits data at a rate of one-half of one clock signal.

Figure 1 is a schematic diagram of a sequence peripheral interface (SPI) configuration with an embodiment of a master and servant circuit.

The sequence peripheral interface (SPI) bus is a sequence interface with the following signals: sequence clock (SCK); master data output or servant data input (MDO/SI); master data input or servant data output (MDI/SO) ); and wafer selection (CS#). Many sequential peripheral interface (SPI) embodiments have two configuration bits, clock polarity (CPOL) and pulse phase (CPHA). Because the sequence clock (SCK) transmits a separate clock signal, which is the exclusive clock for the peripheral interface (SPI) data of this sequence, the sequence peripheral interface (SPI) is a synchronous interface, ie it will not be timed. The pulse signal is contained in the data stream itself.

The clock polarity (CPOL) determines whether the shift clock idle state is low level (CPOL=0) or high level (CPOL=1). The clock phase (CPHA) determines which clock edge is shifted in and out of the data (when CPHA=0, the MO/SI data is shifted out at the falling edge, and when CPHA=1, the MO/SI data is shifted into the rising edge. ). Since each bit has two states, four different combinations can be allowed. Two Sequence Peripheral Interface (SPI) elements communicate with each other using the same clock polarity and phase settings.

Two of the four clock polarity and phase settings allow the sequence peripheral interface (SPI) to communicate with different microwire components and vice versa. The microwire is a subset of the Sequence Peripheral Interface (SPI) and is an embodiment of the Sequence Peripheral Interface (SPI). this The microwire protocol has the following fixed clock polarity and phase: SI (data shift entry) is locked at the rising edge of the sequence clock, and SO (data shift out) is changed at the falling edge of the sequence clock. The sequence clock is always at a low level if no data is transmitted.

An embodiment of the Sequence Peripheral Interface (SPI) modifies the SI and SO pins for higher speed access operations. The input SI pin is no longer exclusively used as the instruction/address input, and the output SO pin is no longer only used as the data/status output. Instead, both the SI and SO pins are used as inputs or both. Output. When the phase is input at the instruction/address, both the SI and SO pins are used as input pins and the autonomous component receives the input data. In the data/status output phase, both the SI and SO pins are used as output pins and the data is transferred to the main component. Because this SI and SO pin can be used as input and output pins, they are referred to herein as SI/SIO0 and SI/SIO1, respectively. In the case of the two input and output pins, the efficiency of this operation instruction is traditionally only using the input SI pin as the instruction/address input, and only the output SO pin is compared as the data/status output, which is efficient. Increase the advantage by twice.

Figure 1 shows a sequence of Peripheral Interface (SPI) configurations having a main integrated circuit component 110 electrically coupled to three servo integrated circuit components 100, 101 and 102. The wafer selection pins of the main component 110 are CS#0, CS#1, and CS#2, and are electrically connected to the wafer selection pins CS# of the respective servant components 100, 101, and 102, respectively. The sequence clock (SCK) pin of this master element 110 is electrically coupled to the sequence clock (SCK) pin of the servant elements 100, 101 and 102. The SI/SIO0 (MSI/SIO0) pin of this master element 110 is electrically coupled to the SI/SIO0 pin of the servant elements 100, 101 and 102. The SO/SIO1 (MSI/SIO1) pin of the main component 110 is electrically connected to the SO/SIO1 pin of the servant components 100, 101 and 102. In this configuration, the MSIO0 and MSIO1 pins of this main integrated circuit component and this The SI/SIO0 and SO/SIO1 pins of the servant circuit component are bidirectional input/output pins. When the input phase is commanded, the MSIO0 and MSIO1 pins are used as the main component output pins, and the SI/SIO0 and SO/SIO1 pins are the inputs to the specific servant. Conversely, at the data output phase, the SI/SIO0 and SO/SIO1 pins are the output pins for a particular servant component, while the MSIO0 and MSIO1 pins are the primary component inputs. In an embodiment, the bus bar can also have a mode control circuit.

Figure 2 is a schematic diagram of a read clock of a sequence of peripheral interface (SPI) integrated circuits with many redundant periods to compensate for the delay of the servo circuit.

After a wafer select signal (CS#) is asserted at a falling edge, an 8-bit instruction is transmitted and received by the SI pin to enable the two input/output pins to perform the same direction of input and output operations. This address is latched at the rising/falling edge of the sequence clock (SCK), and the address data is shifted by two bits at the rising/falling edge of each sequence clock (SCK), at the two input/output pins. Bits, that is, SI/SIO0 and SO/SIO1 are interleaved. The first and second bits of this address are transmitted by the MSIO0 and MSIO1 pins of the master element, and thus the SI/SIO0 and SO/SIO1 pins of the slave element are simultaneously received. Therefore, the address bit transfers 2 bits at a time via the SI/SIO0 and SO/SIO1 pins. The address bits are continuously transmitted and received until the 24-bit address transfer is completed. Depending on the frequency of the sequence clock (SCK), some specific number of redundant periods of N=0, 0.5, 1, 1.5, 2, 2.5, etc. may be between the last bit of the address and the first bit of the output data. Was inserted. This extra cycle is used for the internal operation of the servant component. For example, after a 4-bit redundant period is inserted, the data begins to shift out at the rising/falling edge of the sequence clock (SCK) after the end of the redundant period. This data is shifted by 2 bits each time by the SI/SIO0 and SO/SIO1 pins. This one-tuple data can be shifted out only with 4 clock rise/fall edges. This 2-bit output takes advantage of the high efficiency data output produced by the two peripherals of this sequence peripheral interface (SPI) bus. Compared to a simpler Serial Peripheral Interface (SPI) interface, this Serial Peripheral Interface (SPI) interface has twice the data output performance and a shorter address bit input time. A high-performance interface increases system access time efficiency and improves overall system performance while waiting for servant component operations.

Figure 3 is a read clock diagram of a sequence of peripheral interface (SPI) integrated circuits with more redundant periods than in Figure 2 to compensate for the longer delay of the servo circuit.

The figure shows a data transfer with an 8-bit redundant clock cycle. A larger number of extra cycles are needed to match the internal operation of the servant element, such as when the internal operation of the servant element is slow, or when the frequency of the sequence clock (SCK) is higher than the sequence clock that operates with fewer redundant cycles (SCK), for example, the four bit excess period shown in FIG. The number of redundant cycles depends on the frequency of the sequence clock (SCK).

Figure 4 is a flow chart of an operational mode of a sequence of peripheral interface (SPI) integrated circuits that uses a single pin to transmit data.

At step 402, the wafer select signal (CS#) is at a low level. At step 404, the read command code associated with the transfer of the data using the single sequence peripheral interface (SPI) pin is sent. At step 406, the 24-bit address is sent to a single pin to transfer the data. At step 408, an 8-bit redundant period is awaited. At step 410, the data is stored in the address specified by the single pin transmission data. At step 412, the wafer select signal (CS#) becomes a high level and this change can occur at any time in step 410.

Figure 5 is a flow chart of an operation mode of a sequence of peripheral interface (SPI) integrated circuits, which uses multiple pins to transmit data, and a certain number of redundant periods after the transmission address and data are stored at the address. Was inserted before.

At step 502, the wafer select signal (CS#) is at a low level. At step 504, the data associated read instruction code is transmitted using the two Sequence Peripheral Interface (SPI) pins. At step 506, the 24-bit address is interleaved to the two pins to transfer the data. At step 508, an 8-bit redundant period is awaited. At step 510, the data is stored in the address specified by the two pin transmission data. At step 512, the wafer select signal (CS#) becomes a high level and this change can occur at any time in step 510.

Figure 6 is a timing diagram of a transmitted data of a sequence of peripheral interface (SPI) integrated circuits that uses multiple pins and double speed (DDR) to transmit data.

Regardless of the address transmitted by the autonomous integrated circuit to the servo circuit, and the backhaul data stored by the address is returned from the servant circuit to the main integrated circuit, both are transmitted at twice speed (DDR). That is, data transmission is performed at a rate of one-half cycle of one clock signal. In both directions, two pins are used to interleave the data, thus increasing the transmission speed. In another embodiment, a single pin is used instead of two to transmit data.

Figure 7 is a clock diagram of a transmitted data of a sequence of peripheral interface (SPI) integrated circuits using multiple pins and transmitting data using double speed (DDR) in only one direction between the master and the servant.

The address transmitted by the autonomous integrated circuit to the servo circuit is not transmitted at twice the speed (DDR). The data stored in this address is transmitted back to the main integrated circuit from the servant circuit, and is transmitted at twice the speed (DDR). In both directions, two The pins are used to interleave the data, thus increasing the transmission speed. In another embodiment, a single pin is used instead of two to transmit data.

Figure 8 is a clock diagram of a sequence of peripheral interface (SPI) integrated circuits, which uses multiple pins and transmits data in double direction (DDR) in only one direction between the master and the servant. It is the opposite direction to Figure 7.

The address transmitted by the autonomous integrated circuit to the servant circuit is transmitted at twice the speed (DDR). The data stored in this address is transmitted back to the main integrated circuit from the servant circuit, and is not transmitted at twice the speed (DDR). In both directions, two pins are used to interleave the data, thus increasing the transmission speed. In another embodiment, a single pin is used instead of two to transmit data.

Figure 9 is a block diagram showing an example of a sequential peripheral interface (SPI) integrated circuit including a non-volatile memory array in accordance with an embodiment of the present invention.

The integrated circuit 950 includes a memory array 900 formed on a semiconductor substrate using a charge trapping structure non-volatile memory cell, such as a floating gate, a charge trap, or a resistive element (e.g., phase change). The memory cell array 900 can be a separate memory cell, interleaved into an array, or interleaved in multiple arrays. A column of decoders 901 is coupled to a plurality of word lines 902 arranged in columns in the memory array 900. The row of decoders 903 are coupled to a plurality of bit lines 904 arranged in a row in the memory array 900. An address to row decoder 903 and column decoder 901 are provided on bus 905. In block 906, the sense amplifier and data input structure is coupled to the row decoder 903 via data bus 907, through which data is provided from the input/output ports on the integrated circuit 950. Or a data entry structure that provides data to block 906 from other sources within or external to integrated circuit 950. Passed in block 906 The data output line 915 provides data from the sense amplifiers to the input/output ports on the integrated circuit 950, or provides data to other data destinations internal or external to the integrated circuit 950. A biasing arrangement state machine 909 controls the application of the biasing arrangement supply voltage 908, such as erase confirmation and stylization confirmation voltage, and the arrangement of programming, erasing, and reading the memory cell, for example, having a double speed clock and/or The two sequence peripheral interface (SPI) transmission pins are used in parallel or in parallel.

While the invention has been described herein with reference to the preferred embodiments, A variety of modifications and combinations can be readily made by those skilled in the art, and such modifications and combinations are intended to be within the scope of the invention and the scope of the invention.

110‧‧‧Main product circuit

100, 101, 102‧‧‧ servant circuit

CS#‧‧‧ wafer selection

SCK‧‧‧ sequence clock

MSI‧‧‧ Master Data Input

SI‧‧‧ servant data input

SO‧‧‧ servant data output

IO‧‧‧Input and output pins

900‧‧‧Non-volatile memory array

901‧‧‧ column decoder

902‧‧‧ character line

903‧‧ ‧ row decoder

904‧‧‧ bit line

905‧‧ ‧ busbar

907‧‧‧ data bus

906‧‧‧Sense amplifier/data input structure

908‧‧‧ bias supply voltage

909‧‧‧Pressure Arrangement State Machine

911‧‧‧ data input line

915‧‧‧ data output line

950‧‧‧Integrated circuit

Figure 1 is a diagram showing a sequence of Peripheral Interface (SPI) configurations with master and slave integrated circuits.

Figure 2 is a schematic diagram of a read clock for a sequence of peripheral interface (SPI) integrated circuits with many redundant periods to compensate for the delay of the servo circuit.

Figure 3 is a schematic diagram of a read clock for a sequence of peripheral interface (SPI) integrated circuits with more redundant periods than Fig. 2 to compensate for the longer delay of the servo circuit.

Figure 4 is a flow chart of an operational mode of a sequence of peripheral interface (SPI) integrated circuits that uses a single pin to transmit data.

Figure 5 is a flow chart of an operational mode of a sequence of peripheral interface (SPI) integrated circuits that uses multiple pins to transmit data.

Figure 6 is a timing diagram of a transmitted data of a sequence of peripheral interface (SPI) integrated circuits that uses multiple pins and double speed (DDR) to transmit data.

Figure 7 is a clock diagram of a transmitted data of a sequence of peripheral interface (SPI) integrated circuits using multiple pins and transmitting data using double speed (DDR) in only one direction between the master and the servant.

Figure 8 is a clock diagram of a sequence of peripheral interface (SPI) integrated circuits, which uses multiple pins and transmits data in double direction (DDR) in only one direction between the master and the servant. It is the opposite direction to Figure 7.

Figure 9 is a block diagram showing an example of a sequential peripheral interface (SPI) integrated circuit including a non-volatile memory array in accordance with an embodiment of the present invention.

110‧‧‧Main product circuit

100, 101, 102‧‧‧ servant circuit

CS#‧‧‧ wafer selection

SCK‧‧‧ sequence clock

MSI‧‧‧ Master Data Input

SI‧‧‧ servant data input

SO‧‧‧ servant data output

IO‧‧‧Input and output pins

Claims (23)

An integrated circuit includes: a bus bar according to a sequence peripheral interface standard, wherein the bus bar transmits data between the integrated circuit and another integrated circuit, and includes: a plurality of pins, including: a first data Transmitting a pin to perform the data transfer on the bus; a second data transfer pin to perform the data transfer on the bus; a chip select pin to indicate the integrated circuit and another integrated circuit Whether the data transmission is in progress; and a clock pin position; wherein the bus bar can operate in a first operation mode and a second operation mode, in the first operation mode, the first data transmission pin position Data transmission is performed at a rate of one-half cycle of one clock signal, and in the second operation mode, the first data transmission pin transmits data at a rate of one clock of one clock signal; and wherein the data is transmitted The second mode of operation is utilized for transmission, and the address and data are transmitted using the first mode of operation or the second mode of operation. The integrated circuit of claim 1, wherein the bus uses an excess period to compensate for a delay of the other integrated circuit. The integrated circuit of claim 1, further comprising: a memory coupled to the bus. The integrated circuit of claim 1, wherein the integrated circuit is a main integrated circuit. The integrated circuit of claim 1, wherein the integrated circuit is a main integrated circuit, and the plurality of pins comprises a plurality of chip select pins, and each of the plurality of wafers selects a pin indication. Whether or not the data transfer is in progress between the main integrated circuit and one of the other integrated circuits. The integrated circuit of claim 1, wherein the other integrated circuit is a servant circuit. The integrated circuit of claim 1, wherein the other integrated circuit is a servant circuit, and the chip select pin indicates whether between the main integrated circuit and the servant circuit This data transfer is in progress. The integrated circuit of claim 1, wherein in the first mode of operation, the first data transfer pin transmits data from the integrated circuit to the other integrated circuit. The integrated circuit of claim 1, wherein in the first mode of operation, the first data transfer pin transmits data from the other integrated circuit to the integrated circuit. The integrated circuit of claim 1, wherein in the first mode of operation, the second data transmission pin transmits data communication at a rate of one-half cycle of one clock signal. The integrated circuit of claim 1, wherein in the first mode of operation, the first data communication transmission pin and the second data transmission pin are in the same direction in the integrated circuit and Data transfer is performed between the other integrated circuits. A method for data transmission between integrated circuits, comprising: providing a clock via a clock pin to a bus according to a sequence peripheral interface standard, the bus bar being between the integrated circuit and another integrated circuit Transmitting data; transmitting a wafer selection signal to indicate whether the data transmission is in progress between the integrated circuit and the other integrated circuit; using a first mode in a first data transmission pin of the bus bar and a a second data transmission pin for performing command transmission between the integrated circuit and the other integrated circuit, wherein the first mode is performed at a rate of one cycle of one clock signal; and utilizing the first mode Or a second mode in the first data transmission pin of the bus bar and a second data transmission pin to perform address and data transmission between the integrated circuit and the other integrated circuit, wherein the In the second mode, one clock signal is transmitted at a rate of one-half cycle. The method of claim 12, wherein the bus bar uses a redundant period to compensate for a delay of the other integrated circuit. The method of claim 12, further comprising: transmitting data with a memory coupled to the bus. The method of claim 12, wherein the integrated circuit is a main integrated circuit. The method of claim 12, wherein the integrated circuit is a main integrated circuit, and the plurality of pins comprises a plurality of chip selection pins, and each of the plurality of chip selection pins indicates Whether the data transfer is in progress between the main integrated circuit and one of the other servo circuits. The method of claim 12, wherein the other integrated circuit is a servant circuit. The method of claim 12, wherein the integrated circuit is a servant circuit, and the chip selection pin indicates whether the data is being performed between the servant circuit and a main integrated circuit. transmission. The method of claim 12, wherein in the first mode, the first data transmission pin is transmitted from the integrated circuit to the other integrated circuit. The method of claim 12, wherein in the first mode, the first data transmission pin is transmitted from the other integrated circuit to the integrated circuit. The method of claim 12, wherein in the first mode, the second data transmission pin transmits data communication at a rate of one-half cycle of one clock signal. The method of claim 12, wherein in the first mode, the first data transmission pin and the second data transmission pin are in the same direction in the integrated circuit and the other product Data transfer between body circuits. A device for data transmission between integrated circuits, comprising: a clock function means for providing a clock to a bus according to a sequence peripheral interface standard, the bus bar being arranged in the integrated circuit and another integrated circuit Transmitting data; a chip selection signal transmission function means for indicating whether the data transmission is being performed between the integrated circuit and the other integrated circuit; and a data transmission function means for a first data in the bus bar And transmitting the data between the integrated circuit and the second integrated circuit, and the first data transmission pin is in a first operation mode. The signal is transmitted at a rate of one bit at a half cycle of the pulse signal, and in a second mode of operation, the first data transmission pin transmits data at a rate of one bit per clock of one clock signal; and wherein the command system utilizes The second mode of operation is transmitted, and the address and data are transmitted using the first mode of operation.