TW201108311A - Process for aligning nanoparticles - Google Patents

Process for aligning nanoparticles Download PDF

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TW201108311A
TW201108311A TW99118235A TW99118235A TW201108311A TW 201108311 A TW201108311 A TW 201108311A TW 99118235 A TW99118235 A TW 99118235A TW 99118235 A TW99118235 A TW 99118235A TW 201108311 A TW201108311 A TW 201108311A
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Taiwan
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electrode
substrate
semiconductor
electrodes
nanoparticles
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TW99118235A
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Chinese (zh)
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Lichun Chen
Michael Coelle
Miguel Carrasco-Orozco
Mark John Goulding
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Merck Patent Gmbh
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0673Nanowires or nanotubes oriented parallel to a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
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  • Thin Film Transistor (AREA)

Abstract

The invention relates to a process for aligning conducting or semiconducting nanoparticles, to a process for preparing electronic devices comprising such aligned nanoparticles, and to electronic devices prepared by these processes.

Description

201108311 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種配向導電或半導體奈米粒子之方法, 一種製備包含此經配向之奈米粒子之電子裝置之方法,及 藉由此等方法製得之電子裝置。 【先前技術】 將導電或半導體奈米粒子(如奈米線或奈米管)裝配至奈 米級裝置及電路中可實現各種奈米電子及光子應用。已將 個別的半導體奈米線配置成場效電晶體(FET)(Xiang等 人,Nature 441 (2006),489-493)、記憶裝置(Lee 等人, Nature Nanotechnology 2 (2007),626-630)、光檢測器及 太陽能電池(Tian 等人,Nature 449 (2007),885-889 ; Hayden等人,Nature Materials 5 (2006),352-356)、及感 應器(Han等人,Chemical Physics Letters 389 (2004),176-180)。已使用n-及p-型半導體奈米線或奈米管獲得更複雜 的發光二極體(LED)(Gudiksen等人,Nature 415 (2002), 617-620)及互補及二極體邏輯裝置(Bachtold等人,Science 9 (2001) , 294 , 1317-1320)。 先前技藝描述基於由下而上法裝配奈米線裝置或於預圖 案化之基板上裝配無規分佈之奈米線之方法。然而,就大 量生產而言,此等方法費時且過於昂貴,難以控制且一般 僅獲得極低良率。由於同時亦已有人發表大量生產奈米線 之方法(Wan等人,Applied Physics Letters 84 (1)(2004), 124-126),因此有需要配向及裝配藉由此等方法製得之奈 148004.doc 201108311 米線之技術。 於先前技藝中已揭示藉由電場輔助來配向及裝配奈米線 之數種方法。因此,Cao等人,Nanotechnology 17 (2006), 23 78-23 80描述一種藉由DC電場(DCEF)來控制銀奈米線之 配向之技術。其中,自與兩136 nm厚銀膜電極接觸之8〇 nm厚固體電解質RbAg4^膜,藉由於該等銀電極之間施加 DCEF來直接合成銀奈米線。此導致形成定向銀奈米線。 然而’儘管此方法經證實可直接製備配向奈米線,但其不 適用於電子裝置之大量生產期間之奈米線配向。201108311 VI. Description of the Invention: [Technical Field] The present invention relates to a method for aligning conductive or semiconductor nanoparticles, a method for preparing an electronic device comprising the aligned nanoparticles, and the like The electronic device produced. [Prior Art] Various nanoelectronic and photonic applications can be realized by assembling conductive or semiconductor nanoparticles (such as nanowires or nanotubes) into nanoscale devices and circuits. Individual semiconductor nanowires have been configured as field effect transistors (FETs) (Xiang et al, Nature 441 (2006), 489-493), memory devices (Lee et al, Nature Nanotechnology 2 (2007), 626-630 ), photodetectors and solar cells (Tian et al, Nature 449 (2007), 885-889; Hayden et al, Nature Materials 5 (2006), 352-356), and sensors (Han et al., Chemical Physics Letters) 389 (2004), 176-180). More complex light-emitting diodes (LEDs) have been obtained using n- and p-type semiconductor nanowires or nanotubes (Gudiksen et al, Nature 415 (2002), 617-620) and complementary and diode logic devices (Bachtold et al., Science 9 (2001), 294, 1317-1320). The prior art description is based on a method of assembling a nanowire device from a bottom-up method or assembling a randomly distributed nanowire on a pre-patterned substrate. However, in terms of mass production, such methods are time consuming and too expensive to control and generally only achieve very low yields. Since a method for mass production of nanowires has also been published (Wan et al., Applied Physics Letters 84 (1) (2004), 124-126), there is a need for alignment and assembly by using such methods. .doc 201108311 The technology of rice noodles. Several methods of aligning and assembling nanowires by electric field assistance have been disclosed in the prior art. Thus, Cao et al, Nanotechnology 17 (2006), 23 78-23 80 describe a technique for controlling the alignment of silver nanowires by a DC electric field (DCEF). Among them, from the 8 〇 nm thick solid electrolyte RbAg4 film which is in contact with two 136 nm thick silver film electrodes, the silver nanowire is directly synthesized by applying DCEF between the silver electrodes. This results in the formation of oriented silver nanowires. However, although this method has been confirmed to directly prepare aligned nanowires, it is not suitable for nanowire alignment during mass production of electronic devices.

Motayed等人 ’ Journai 〇f Applied Physics 1〇〇(2〇〇6), 114310,Smith 等人,Applied Physics Letters 77 (9) (2000),1399-1401 ’ 及 US 6,536,106描述一種配向預製備 之GaN或Au奈米線之方法,其中將該等奈米線分散於液體 中及沉積於覆蓋有圖案化及又指狀電極結構之基板上。當 對電極施加非均勻電場時,奈米線經介電泳動力 (dielectrophoretic force)配向。然而,此方法具有數個缺 點。例如’其需製造具有複雜及精細圖案之用於施加電場 之叉指狀電極結構,此不利於大量生產。此外,電極之尺 寸及距離係在與奈米線尺寸相同之範圍内,以致奈米線與 電極重疊。為防止電極指因金屬奈米線而直接接觸及進而 短路,需以(例如)藉由化學氣相沉積法沉積之氮化矽的保 護層覆蓋電極。再者’此令該方法不適宜於大量生產電子 裝置期間之奈米線配向。 因此,仍需求一種配向奈米粒子之經改良、簡單且有效 148004.doc 201108311 之方法,其不僅可用於製造諸如電晶體之電子裝 製造其他基於奈米粒子之電子裝置,如二極體(led、光; 極體)、⑤冑器、及互補及二極體邏輯裝置,纟其用於大 里生產此等裝置’且其不具有如上所述之先前技藝中所揭 不之方法之缺點。本發明之一目的係提供此一改 方法。本發明之另一目的係提供由此方法獲得之改良之電 子裝置’尤其係' 電晶體及太陽能電池。本發明之其他目的 係自以下詳細論述而為熟習本技藝者立即獲識。 頃發現此等目的可藉由提供本發明所主張之方法實現。 【發明内容】 本發明係關於一種配向導電或半導體奈米粒子之方法, 其包含步驟: 1) 將一對輔助電極置於基板上, 2) 將導電或半導體奈米粒子沉積於輔助電極之間之基板 上,及 3)對輔助電極施加電壓。 較佳地,令奈米粒子與一或多個裝置結構(較佳工作電 極而非輔助電極)接觸。於配向期間,較佳不對裝置或工 作電極施加電壓。 配向奈米粒子之先決條件係其等具有各向異性,較佳係 細長形狀,如奈米線、奈米管、奈米棒、奈米帶、奈米 鬚,或甚至板形,如奈米盤。 本發明進一步係關於藉由本發明之方法配向之奈米粒子 於電子、電光學、電致發光或光學裝置令作為電荷傳送、Motayed et al. 'Journai 〇f Applied Physics 1〇〇 (2〇〇6), 114310, Smith et al., Applied Physics Letters 77 (9) (2000), 1399-1401 ' and US 6,536,106 describe a pre-prepared GaN Or a method of Au nanowires, wherein the nanowires are dispersed in a liquid and deposited on a substrate covered with a patterned and finger-like electrode structure. When a non-uniform electric field is applied to the electrodes, the nanowires are aligned by a dielectrophoretic force. However, this method has several drawbacks. For example, it is required to manufacture an interdigitated electrode structure for applying an electric field having a complicated and fine pattern, which is disadvantageous for mass production. Further, the size and distance of the electrodes are in the same range as the size of the nanowires, so that the nanowires overlap the electrodes. In order to prevent the electrode fingers from directly contacting and thus short-circuiting due to the metal nanowire, it is necessary to cover the electrode with, for example, a protective layer of tantalum nitride deposited by chemical vapor deposition. Furthermore, this method is not suitable for nanowire alignment during mass production of electronic devices. Therefore, there is still a need for an improved, simple and effective method of aligning nanoparticles 148004.doc 201108311, which can be used not only for the manufacture of electronic devices such as transistors, but also for nanoparticle-based electronic devices such as diodes (led , light; polar body, 5 胄, and complementary and diode logic devices, which are used in Dali to produce such devices' and which do not have the disadvantages of the methods disclosed in the prior art as described above. It is an object of the present invention to provide such a modification. Another object of the present invention is to provide an improved electronic device 'particularly' a transistor and a solar cell obtained by the method. Other objects of the present invention are immediately apparent to those skilled in the art from the following detailed description. It is found that such objects can be achieved by providing a method as claimed in the present invention. SUMMARY OF THE INVENTION The present invention is directed to a method of orienting conductive or semiconductor nanoparticles comprising the steps of: 1) placing a pair of auxiliary electrodes on a substrate, and 2) depositing conductive or semiconductor nanoparticles between the auxiliary electrodes On the substrate, and 3) apply a voltage to the auxiliary electrode. Preferably, the nanoparticles are contacted with one or more device structures (preferably working electrodes rather than auxiliary electrodes). During the alignment, it is preferred not to apply a voltage to the device or the working electrode. Prerequisites for aligning nanoparticles are anisotropic, preferably elongated, such as nanowires, nanotubes, nanorods, nanoribbons, nanowhiskers, or even plate shapes, such as nano plate. The invention further relates to the use of nanoparticles aligned by the method of the invention in electron, electro-optical, electroluminescent or optical devices as charge transport,

[S 148004.doc 201108311 導電或半導體組件之用途。 本發明進一步係關於一種製備電子、光電子、電致發光 或光學裝置,較佳電子裝置之方法,其包含㈣: a) 將工作電極(較佳源及沒電極(4))佈置於絲 層(3)上, b) 將-對辅助電極置於基板⑴或介電層(3)上以使其等 不與工作電極(4)接觸, C)將視需要分散於液體中之導電或半導體奈米粒子層(5) 沉積於基板⑴或介電層(3)及工作電極⑷上’以使奈米 粒子位於輔助電極之間, d) 對輔助電極施加電壓, e) 視需要將液體自奈米粒子層(5)移除, f) 視需要移除辅助電極,及 g) 視需要於奈米粒子層上提供一或多個其他功能声, 其中亦可以不同次序實施步驟…十句及^較佳地, 此等^驟係以指定之次序實施。步驟…〇及d)之次序可 祆據實際因素(女全措施等)改變及調整。較佳地,此等粒 子係半導體。 較佳地’根據步驟e)移除液體,更佳同時維持根據步驟 d)之電壓。較佳地根據步驟十更佳地於移除液體後或句 中所提供之㈣已降低至零之後移除電極。 ,卜,佳地將輔助電極置於_位置中,以使工作電極中之至― 少-者(源極及/或汲極)’較僅兩者,至少部份或完全地位 於輔助電極之間。更佳地’令各輔助及工作電極周圍之電 148004.doc 201108311 場方向平行對準一般而言,此係藉由 電極之表面平行對準 ¾•極與工作 而貫現。因此,佈局較佳 子垂直於工作電極之# '、使不米粒 电枝之表面,及可最終於其等 形(半)導體結構。 間形成細長 或者,於本發明之_較佳實 位;^ r τ w卷極係由永久 、文裝有作電極之基板或裝置 此每浐y, 士 取次衮罝上之補充電極表示。於 =…中’辅助電極係固定電極。隨、 移除補充電極。其等伴留7 為根據步驟e) .A v 保留於基板上,但一旦經配向之太半 粒子永久固定於基板,彳 不未 夂雷“ * 貝]其4不再使用。當辅助電極係永 電極¥,步驟a)及b)可於-共同程序中實施。 本發明進一步係關於—種藉由如上下文 之包含經配向奈米粒子之裝置。 」製仔 ^明進-步係關於一種包含經配向奈米線及工作電極 =子、電光學'電致發光或光學裝置,其中該等經配向 丁只粒子連接工作電極。工作電極較佳於其等表面上不分 離’此係一優點。可無需將工作電極連接至用於配向之電 壓而製造該褒置。工作電極較佳係位於基板上,更佳係位 於平坦基板上。基板之表面可為平坦’即,無用於藉由除 根據本發明所施加之電塵外之方式進行奈米粒子配向之光 柵等。簡單平坦表面較任何其他表面改f更易獲得。 本發明之裝置較佳包含複數個奈米粒子。相對於較佳可 用於僅將單個或有限個奈米粒子定位至一定位置之其他方 法,本發明之方法尤其可用於配向複數個奈米粒子,。 本發明之裝置較佳包含場效電晶體FET,其包含: 148004.doc 201108311 -基板(1), -閘電極(2), -介電層(3), -源及汲電極(4),及 -包含藉由上下文所述之方法配向之奈米粒子之半導體層 ⑺。 一般而言,該半導體層(5)連接該源及汲電極(4)。 電子、電光學、電致發光或光學裝置包括,但非限於 (有機)場效電晶體((〇)FET)、積體電路(IC) (有機)薄膜電 晶體((o)tFT)、射頻識別(RFID)標籤、(有機)發光二極體 ’LED)、(有機)發光電晶體((〇)LET)、電致發光顯示哭、 (有機)光伏打((〇)PV)電池、(有機)太陽能電池((〇_)s^)、 可撓(〇)PV及(〇-)SC、(有機)雷射二極體((〇)雷射)、(有 機)積體電路((0-)IC)、照明裝置、感應裝置、電極材料、 光導體、光檢測器、電子照相記錄裝置、電容器、電荷注 射層、肖特基(Schottky)二極體、平面化層' 抗靜電:、 導電基板、導電㈣、光導體、電子照相裝置、有機記憶 裝置、生物感應器、生物晶片、光學偏振片、光學阻: 器、及光學補償器。 印 術語之定義 術語「辅助電極」意指用 極。輔助電極僅用於該目的 子之裝置之部分之任何其他 於配向本發明之奈米粒子之電 ,且與構成包含經配向奈米粒 電極不同。 裝置組件或裝置 術语「可移動電極」意指可置於基板 148004.doc 201108311 將其永久固定(較佳僅用於奈米粒子配 對於基板、裝置組件或裝置移動之輔助電)極且 件連接例如’错由諸如央具、螺釘等機械固定構 接至基板、裳置組件或裝置,但可 ^方法再次輕易移除,且不會破壞或損毅基板、= 件或裝置之電極。 凌置組 術語「工作電極」係指非輔助或可移動電極 電極尤其係指位於經配向奈米粒子之沉: 近或直接位於該位置上之任何裝置之電極。於_ 細例中,工作雪搞仫 一竿又仏貝 或沒電極。係,例如,電晶體狀裝置之源電極及/ 術語「奈米粒子」(於文獻中亦稱為「奈米材 二例::7,344,961中所定義之奈米線、奈米棒、奈 s、奈米四腳體、奈米帶及/或其等组合,該案全文係 以引用之方式併入本申請案中。其較佳係指奈米線。 術語「H族」、「IV族」等係指元素週期表。 ::「奈米線」意指包含至少一橫截面大小,〇咖, ^土<1()()邮,且具有縱橫比(長..寬)>1(),較佳>5〇,更 >刚之任何細長形,較佳導電或半導體顆粒 ”可具有可變的直徑或可具有實質上均—之直經。二 而S ’直徑係於遠離奈米線之末端處(例如,於又 :Γ%、观或叫)評估。就奈米線之整個:㈣度 度而言,奈米線可為直線或可為彎曲或曲折形。 就本發明而言’直奈米線較㈣者佳,其純螺旋形者 148004.doc 201108311 佳。本發明之奈米線可明確排除碳奈米#,及於特 施 例中排除具有大於15G nm之最小直徑之長形粒子。^米管&[S 148004.doc 201108311 Use of conductive or semiconductor components. The invention further relates to a method of preparing an electronic, optoelectronic, electroluminescent or optical device, preferably an electronic device, comprising (iv): a) arranging a working electrode (a preferred source and a non-electrode (4)) in the wire layer ( 3) upper, b) placing the auxiliary electrode on the substrate (1) or the dielectric layer (3) so as not to be in contact with the working electrode (4), C) conducting or dispersing the conductive or semiconductor neat in the liquid as needed The rice particle layer (5) is deposited on the substrate (1) or the dielectric layer (3) and the working electrode (4) so that the nanoparticles are located between the auxiliary electrodes, d) the voltage is applied to the auxiliary electrode, e) the liquid is supplied as needed The rice particle layer (5) is removed, f) the auxiliary electrode is removed as needed, and g) one or more other functional sounds are provided on the nanoparticle layer as needed, wherein the steps can also be performed in different orders... ten sentences and ^ Preferably, such implementations are carried out in the specified order. The order of steps...〇 and d) can be changed and adjusted according to actual factors (female measures, etc.). Preferably, such a particle semiconductor. Preferably, the liquid is removed according to step e), more preferably while maintaining the voltage according to step d). Preferably, the electrode is removed after the removal of the liquid or the (4) provided in the sentence has been reduced to zero, according to step ten. Preferably, the auxiliary electrode is placed in the _ position such that at least two of the working electrodes (source and/or drain) are located at least partially or completely at the auxiliary electrode. between. More preferably, the power around the auxiliary and working electrodes is 148004.doc 201108311 The parallel alignment of the field direction is generally achieved by the parallel alignment of the electrodes on the surface of the electrode. Therefore, the layout is preferably perpendicular to the #' of the working electrode, the surface of the non-grained branch, and may end up in its isomorphic (semi)conductor structure. Forming a slender shape or a preferred position in the present invention; ^ r τ w is a permanent substrate, or a substrate or device equipped with an electrode as a supplementary electrode on each of the 浐, 士. In the =... the auxiliary electrode is a fixed electrode. Follow, remove the supplemental electrode. The accompanying 7 is retained on the substrate according to step e). A v , but once the aligned semi-particles are permanently fixed to the substrate, the “ “ “ * * * * 其 其 其 。 。 。 。 。 。 。 。 辅助The permanent electrode ¥, steps a) and b) can be carried out in a common procedure. The invention further relates to a device comprising a aligned nanoparticle by the context of the invention. The invention comprises an aligned nanowire and a working electrode=sub, electro-optical electroluminescent or optical device, wherein the aligned particles are connected to the working electrode. The working electrode preferably has no advantage of being separated from its surface. The device can be fabricated without connecting the working electrode to the voltage for alignment. The working electrode is preferably located on the substrate, preferably on a flat substrate. The surface of the substrate may be flat', i.e., there is no grating or the like for performing nanoparticle alignment by means of electric dust applied according to the present invention. A simple flat surface is easier to obtain than any other surface. The apparatus of the present invention preferably comprises a plurality of nanoparticles. The method of the present invention is particularly useful for aligning a plurality of nanoparticles, relative to other methods which are preferably useful for positioning only a single or a limited number of nanoparticles to a certain location. The device of the present invention preferably comprises a field effect transistor FET comprising: 148004.doc 201108311 - substrate (1), - gate electrode (2), - dielectric layer (3), - source and germanium electrode (4), And - a semiconductor layer (7) comprising nanoparticles aligned by a method as described above and below. In general, the semiconductor layer (5) is connected to the source and the germanium electrode (4). Electron, electro-optical, electroluminescent or optical devices including, but not limited to, (organic) field effect transistors ((〇) FET), integrated circuit (IC) (organic) thin film transistors ((o)tFT), RF Identification (RFID) tag, (organic) light-emitting diode 'LED', (organic) light-emitting transistor ((〇) LET), electroluminescence display crying, (organic) photovoltaic ((〇) PV) battery, ( Organic) solar cells ((〇_)s^), flexible (〇) PV and (〇-)SC, (organic) laser diode ((〇) laser), (organic) integrated circuit (( 0-) IC), illuminating device, sensing device, electrode material, photoconductor, photodetector, electrophotographic recording device, capacitor, charge injection layer, Schottky diode, planarization layer 'antistatic: , conductive substrate, conductive (four), photoconductor, electrophotographic device, organic memory device, biosensor, biochip, optical polarizer, optical resistor, and optical compensator. Definition of the terminology The term "auxiliary electrode" means the electrode. The auxiliary electrode is used only for any of the other components of the device of the present purpose, and is different from the electrode comprising the aligned nanoparticle. DEVICE ASSEMBLY OR DEVICE The term "movable electrode" means that it can be permanently mounted on a substrate 148004.doc 201108311 (preferably only for nanoparticle with auxiliary circuitry for substrate, device assembly or device movement) and The connection, for example, is mechanically fixed to the substrate, the skirt assembly or the device by mechanical means such as a centering device, a screw, etc., but can be easily removed again without damaging or damaging the electrodes of the substrate, the device or the device. Alignment Group The term "working electrode" means a non-auxiliary or movable electrode. The electrode refers specifically to the electrode of any device that is located near or directly at the position of the aligned nanoparticle. In the _ example, the work snow is messed up with a mussel or no electrode. For example, the source electrode of the transistor-like device and/or the term "nanoparticles" (also referred to in the literature as "nano-wires, nano-bars, nanorods, s, as defined in 7,344,961" The combination of the four-legged body, the nano-belt and/or the like, is incorporated herein by reference in its entirety. It preferably refers to the nanowire. The term "H family", "IV family" The term “period” means “at least one cross-sectional size, 〇 ,, ^ 地<1()(), and has an aspect ratio (length..width)>1 (), preferably > 5 〇, more > just any of the elongated, preferably electrically conductive or semiconducting particles may have a variable diameter or may have substantially uniform - straight. The second 'S' diameter is Keep away from the end of the nanowire (for example, again: Γ%, view or call). For the whole of the nanowire: (4) degrees, the nanowire can be straight or curved or meandered. In the present invention, the 'straight nanowire is better than (four), and the pure spiral is 148004.doc 201108311. The nanowire of the present invention can clearly exclude carbon nano#, and in special cases ^ M & amp tube 15G nm greater than the smallest diameter of the other elongated particles;

之尺寸係如關於奈米線所定義。 不 B 【實施方式】 用於本發明之奈米粒子較佳具有各向異性形狀,即,其 等具有不同的長度及寬度/直徑,例如,奈米線或夺米 嘗。奈米線之直徑或寬度一般係於數十至數百奈米,較佳 5至⑽⑽之範圍内。奈米粒子之長度—般係超過5〇〇 ⑽,較佳u1〇〇微米㈣。縱橫比(長幻較佳係$至 此各向異性形狀令奈米粒子趨於沿電場定向。奈米 線及奈米管為尤佳。尤佳者係半導體奈米線。 ^發明之奈米粒子可於材料特性上實f上均句,或於一 二實施例中亦可不均勻(例如,奈米線異質結構)。其等可 自基本上任何習知材料製備’且可呈,例如,實質上晶 形、實質上單晶形、多晶形或非晶形。 般而5,可使用各種各樣的材料來製備奈米粒子,包 括仁非限於,選自由Iv族半導體、πι_ν族半導體、π_ 族半V體、過渡金屬 '或上述者之合金或混合物組成之 :之半導體材料。尤佳_族半導體係si、&、sn及其等 二金更佳者係ΠΙ·ν族半導體與其他丨〗〗族及/或v族元素之 。金及II-VI族半導體與其似】族及/或%族元素之合金。 I且及較佳的半導體材料包括,但非限於,si、Ge、 se、Te、B、C(包括金剛石)、p、B c、B_p(Bp6)、B- C Sl"Ge ' Sl'Sn^-Ge-Sn ' SiC ' BN ' BP ' BAs ' 148004.doc 201108311 AIN、A1P、AlAs、AlSb、GaN、GaP、GaAs、GaSbThe dimensions are as defined for the nanowire. Not B [Embodiment] The nanoparticles for use in the present invention preferably have an anisotropic shape, i.e., they have different lengths and widths/diameters, for example, a nanowire or a rice. The diameter or width of the nanowire is generally in the range of tens to hundreds of nanometers, preferably 5 to (10) (10). The length of the nanoparticle is generally more than 5 〇〇 (10), preferably u1 〇〇 micron (four). The aspect ratio (long illusion is better than the anisotropic shape so that the nanoparticle tends to be oriented along the electric field. The nanowire and the nanotube are particularly preferred. The better is the semiconductor nanowire. ^The nanoparticle of the invention can be It may be non-uniform in the material properties, or may be non-uniform in the two-two embodiment (for example, a nanowire heterostructure), etc. may be prepared from substantially any conventional material and may be, for example, substantially Crystal form, substantially monocrystalline, polymorphous or amorphous. Generally, a variety of materials can be used to prepare the nano particles, including the non-limiting, selected from the group consisting of Iv semiconductors, πι_ν semiconductors, π_ family half V Body, transition metal' or alloy or mixture of the above: semiconductor material. Youjia _ family semiconductor system si, &, sn and its two gold better system ΠΙ· ν semiconductor and other 丨〗 Metal and/or v-group elements. Alloys of gold and II-VI semiconductors and their likes and/or % group elements. I and preferred semiconductor materials include, but are not limited to, si, Ge, se, Te , B, C (including diamond), p, B c, B_p (Bp6), B-C Sl" Ge ' Sl'Sn^-Ge-Sn ' SiC ' BN ' BP ' BAs ' 148004.doc 201108311 AIN, A1P, AlAs, AlSb, GaN, GaP, GaAs, GaSb

InN、InP、InAs、InSb、ZnO、ZnS、ZnSe、ZnTe、CdS、 CdSe、CdTe、HgS、HgSe、HgTe、BeS、BeSe、BeTe、 MgS、MgSe、GeS、GeSe、GeTe、SnS、SnSe、SnTe、 PbO、PbS、PbSe、PbTe、CuF、CuCl、CuBr、Cul、 AgF、AgCl、AgBr、Agl、BeSiN2、CaCN2、ZnGeP2、InN, InP, InAs, InSb, ZnO, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, BeS, BeSe, BeTe, MgS, MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, Cul, AgF, AgCl, AgBr, Agl, BeSiN2, CaCN2, ZnGeP2

CdSnAs2、ZnSnSb2、CuGeP3、CuSi2P3、(Cu、Ag)(Al、 Ga、In、Ti、Fe)(S、Se ' Te)2、Si3N4、Ge3N4、Al2〇3、 (A卜Ga、In)2(S、Se、Te)3、Al2CO、及上述材料中之兩 或多者之任何適宜組合。 奈米粒子亦可由其他材料組成,或包含其他材料,包 括,但非限於,諸如 Au、Ni、Pd、ir、C〇、Cr、A1、Ti、CdSnAs2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag) (Al, Ga, In, Ti, Fe) (S, Se ' Te) 2, Si3N4, Ge3N4, Al2〇3, (A Bu Ga, In) 2 ( S, Se, Te) 3, Al 2 CO, and any suitable combination of two or more of the foregoing. Nanoparticles may also be composed of other materials or include other materials including, but not limited to, such as Au, Ni, Pd, ir, C〇, Cr, A1, Ti,

Fe、Sn等之金屬金屬合金、包括(半)導體聚合物之聚合 物、陶瓷、及/或其等組合。亦可採用其他導電或半 材料。 亦可將奈米粒子摻雜至卜型^型半導體中。例如,盆 等可含有選自由以下組成之群之摻雜物:冑自叫了 特定言之Β、Α1或1^•型摻雜物,選自W㈣,、特定一 之P、As及…型接雜物,選自π族元素,、定/ Ο,及叫型摻雜物,選自族元素,,特I: 之C及Si之p-型摻雜物,或選自、 '疋〇 兄、自由 Si、Ge、Sn、 組成之群之η-型摻雜物。亦 、e&Te m ^用其他已知之摻 奈米粒子可基本上由-種材料組成,但亦可雜材枓。 圍核之殼係由不同材料或 核/殼結構’其中該核及包阁^ 具有(例如) 不同 148004.doc -11. 201108311 材料組合物組成或包含不同材料或材料組合物。例如,核/ 殼奈米線可由包含,例如,獨立地選自由C、Si、Ge及Sn 組成之群之IV族元素之奈米線核及奈米線殼組成。殼亦可 由絕緣材料(例如IV族元素之氧化物)組成或包含絕緣材 料。 於核/殼奈米線之情況中,就P-型摻雜線而言,絕緣殼之 價帶可較核之價帶低,或就η-型摻雜線而言,殼之導電帶 可較核高。一般而言,核奈米結構可自任何金屬或半導體 材料製成,及殼可自相同或不同材料製成。例如,第一核 材料可包含選自由II-VI族半導體、III-V族半導體、IV族 半導體及其等合金組成之群之第一半導體。類似地,第二 殼材料可包含與第一半導體相同或不同,且(例如)選自由 II-VI族半導體、III-V族半導體、IV族半導體、及其等合 金組成之群之第二半導體。適宜半導體之實例包括,但非 限於,CdSe、CdTe、InP、InAs、CdS、ZnS、ZnSe、 ZnTe、HgTe、GaN、GaP、GaAs、GaSb、InSb、Si、Ge、 AlAs、AlSb、PbSe、PbS及PbTe。如上所述,可將諸如 Au、Cr、Sn、Ni、A1等及其等合金之金屬材料用作核材 料,且金屬核可由適宜殼材料(例如,Si02或其他絕緣材 料)包覆。 通常將一有機單層沉積於奈米線上。此層可具有以下數 種作用: -奈米線可更佳地分散於溶劑中。 -保護奈米線免受氧化。 148004.doc -12- 201108311 -改變奈米線之功函數。 該有機單層可為根據以上功能之許多類型,例如,烧 基、烷硫醇類型等,如j· Am chem s〇c(2〇〇4),126 (47),15466中所描述。 奈米線或奈米帶亦可包括碳奈米管,或自導電或半導體 有機材料(例如,稠五苯、有機聚合物)或過渡金屬氧化物 製成之奈米管。 奈米粒子可藉由各種不同方法製造。例如,已描述利用 基於溶液、界面活性劑介導之結晶生長來製造球狀無機奈 米粒子(例如,量子點)及細長形奈米粒子(例如,奈米棒及 奈米四腳體)。亦已採用其他方法來製造奈米粒子,包括 氣相方法。例如,已揭示藉由雷射熱解矽烷氣體來製備矽 奈米晶體。 用於製備奈米線之一適宜方法利用自適宜前驅體材料 (如,上述元素之金屬鹵化物或有機金屬化合物)之溶液生 長。此可藉由,例如,在適宜溫度下將奈米線前驅體曝露 於包含有機溶劑之奈米線生長溶液中之金屬奈米晶體來達 成。金屬奈米晶體充作催化半導體奈米線之生長的晶種粒 子。金屬奈米晶體可於原位於生長溶液中自金屬奈米晶體 前驅體形成,或者奈米晶體可經預製備並隨後添加至生長 溶液中。適宜的金屬奈米晶體係自先前技藝獲識。 奈米粒子之適宜材料及形狀及其等之製備方法一般係為 熟習本技藝者已知並揭示於文獻中,例如,以上引用之文Metal metal alloys of Fe, Sn, etc., polymers including (semi)conductor polymers, ceramics, and/or combinations thereof. Other conductive or semi-materials may also be used. Nanoparticles can also be doped into a semiconductor. For example, the pots and the like may contain a dopant selected from the group consisting of: 胄 特定 特定 特定 Β Α Α Α 或 或 或 , , , , , , , , , , , , , , , , , , , , , , The dopant is selected from the group consisting of a π-group element, a deuterium/deuterium, and a dopant, selected from the group consisting of a group element, a special type I: a p-type dopant of C and Si, or selected from the group consisting of Brother, free Si, Ge, Sn, η-type dopants of the group. Also, e&Te m ^ can be composed of other kinds of materials by other known nano-particles, but can also be used as a material. The shell of the core is composed of different materials or core/shell structures, wherein the core and the package have, for example, different compositions or materials comprising different materials or material compositions. For example, the core/shell nanowire may be composed of a nanowire core and a nanowire shell comprising, for example, a group IV element independently selected from the group consisting of C, Si, Ge, and Sn. The shell may also be composed of an insulating material (e.g., an oxide of a Group IV element) or an insulating material. In the case of a core/shell nanowire, in the case of a P-type doped line, the valence band of the insulating shell may be lower than the valence band of the core, or in the case of an η-type doping line, the conductive strip of the shell may be Higher than the nuclear. In general, the core nanostructure can be made from any metal or semiconductor material, and the shell can be made from the same or different materials. For example, the first core material may comprise a first semiconductor selected from the group consisting of a II-VI semiconductor, a III-V semiconductor, a Group IV semiconductor, and the like. Similarly, the second shell material may comprise the same or different first semiconductor and, for example, a second semiconductor selected from the group consisting of II-VI semiconductors, III-V semiconductors, Group IV semiconductors, and alloys thereof . Examples of suitable semiconductors include, but are not limited to, CdSe, CdTe, InP, InAs, CdS, ZnS, ZnSe, ZnTe, HgTe, GaN, GaP, GaAs, GaSb, InSb, Si, Ge, AlAs, AlSb, PbSe, PbS, and PbTe. As described above, a metal material such as Au, Cr, Sn, Ni, A1, or the like and the like can be used as the core material, and the metal core can be coated with a suitable shell material (e.g., SiO 2 or other insulating material). An organic monolayer is typically deposited on the nanowire. This layer can have several effects as follows: - The nanowire can be more preferably dispersed in a solvent. - Protect the nanowire from oxidation. 148004.doc -12- 201108311 - Change the work function of the nanowire. The organic monolayer may be of many types depending on the above functions, for example, an alkyl group, an alkanethiol type, etc., as described in j. Am chem s〇c (2〇〇4), 126 (47), 15466. The nanowire or nanobelt may also include a carbon nanotube or a nanotube made of a conductive or semiconductive organic material (e.g., pentacene, an organic polymer) or a transition metal oxide. Nanoparticles can be made by a variety of different methods. For example, the use of solution-based, surfactant-mediated crystal growth to produce spherical inorganic nanoparticles (e.g., quantum dots) and elongated nanoparticles (e.g., nanorods and nanotetrapods) has been described. Other methods have also been used to make nanoparticles, including gas phase processes. For example, it has been disclosed to prepare a ruthenium crystal by laser pyrolysis of a decane gas. One suitable method for preparing the nanowires utilizes a solution of a solution from a suitable precursor material (e.g., a metal halide or an organometallic compound of the above elements). This can be achieved, for example, by exposing the nanowire precursor to metal nanocrystals in a nanowire growth solution containing an organic solvent at a suitable temperature. Metal nanocrystals act as seed particles that catalyze the growth of semiconductor nanowires. The metal nanocrystals may be formed from the metal nanocrystal precursor in the original growth solution, or the nanocrystals may be pre-prepared and subsequently added to the growth solution. Suitable metal nanocrystal systems are known from prior art. Suitable materials and shapes of nanoparticles and methods for their preparation are generally known to those skilled in the art and are disclosed in the literature, for example, in the above cited text.

獻中,或於US 2005/0029678 Al ; A.T. Heitsch、D.D 1480Q4.doc -13- 201108311Contributed to, or in US 2005/0029678 Al; A.T. Heitsch, D.D 1480Q4.doc -13- 201108311

Fanfair、H.-Y. Tuan及 Β_Α· Korgel,J. Am. Chem. Soc. (2008),130,5346-7 ; T· Hanrath、Β·Α· Korgel,J. Am, Chem. Soc. 126 (2004),15466-72 ; D. Fanfair等人,Crystal Growth & Design 5 (2005),1971-6 ; A.M· Morales等人,Fanfair, H.-Y. Tuan and Β_Α·Korgel, J. Am. Chem. Soc. (2008), 130, 5346-7; T. Hanrath, Β·Α·Korgel, J. Am, Chem. Soc. 126 (2004), 15466-72; D. Fanfair et al., Crystal Growth & Design 5 (2005), 1971-6; AM· Morales et al.

Science (1998) &gt; 279 &gt; 208-1 1 ; WO 02/17362 ; WO 01/03208 及於US 7,344,961 B2及其中所引用之參考文獻中。將關於 製造奈米線之上述文獻之全文以引用之方式併入本申請案_ 中。 干又丨土 Ί本員 根據本發明配向奈米粒子 1) 將一對輔助電極置於基板上, 2) 將導電或半導體奈米粒子沉積於辅助電極之間之基板 上,及 3) 對該兩辅助電極施加電壓。 於具有導體或半㈣特性之奈米粒子巾,#將奈米粒子 置於電場中時’電子或電荷載子可輕易地移動…般將奈 米粒子分散於介電介f(—般係液體,例如溶劑)中,其; 個別的奈米粒子經分離以致其等之間無接觸。當跨過液體 施加外部電場時’於單個奈米粒子中之正或負電荷將相摩 地隨者電場移向各向異性奈米粒子之不同末端。由於奈米 粒子之間無接觸,故電荷將於個別奈綠子之末端積累直 至由移動電荷引起之内電場等於所施加之外電場。由於太 米粒子之各向里忖报灿 ..., &quot;τ' ,於奈米粒子兩端上 電荷會形成偶極子。芒太水次負 右不水粒子可於液體中自由移動, 所形成之偶極子將令其#沿外電場線配向。 ^ 148004.doc • 14 - 201108311 F = aELsin0cos9 施加至該偶極子之電力(F)係與奈米粒子長度(L)、電場強 度(E)及因子sinecose成比例,其中a係與溶劑之介電常數 及奈米線中之自由電荷密度有關之常數,及θ係奈米線之 縱軸與電場之間之角度。 此原理亦適用於AC場之情況,其中電荷將隨外場相應 地變化。施加至奈米粒子之電力將令其等以如上述相同的 方式沿電場線配向。交變場之頻率可極大範圍地變化。以 自下限至1 MHz之頻率為較佳。高於5〇 kHz之高頻率可能 較佳,係因於短路情況中其等對人體之作用低。以別Hz 至5 kHz之頻率為特佳。 較佳地,用於配向方法所施加之電壓係Ac電壓。 為配向奈米粒子’需使用電極對以形成電場。此可藉由 將電極沉積於基板上或藉由使用一或多個可移動電極(較 佳一對類似電極)來實現。 較佳地,辅助電極係可移動電極。因此,於用於奈米粒 子配向方法後,其等不會形成裝置之最終構架之-部分。 將可移動電極置於欲於其上配向奈米粒子之基板或裝置 或裴置組件上。電極可直接與基板接觸。電極亦可,例 如’藉由固定構件固$,以使其等直接與基板接觸,或不 接觸基板而係以短距離(接觸或數10微米距離)靠近基板。 將其等與電源連接,以致可施加電壓而建立所需強度(較 佳1至250 kV/m)之電場。 兩輔助或可移動電極之間之距離較佳應大於各向異性奈</ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The entire disclosure of the above-mentioned documents for the manufacture of nanowires is incorporated herein by reference. Dry and 丨 Ί 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配 配A voltage is applied to the two auxiliary electrodes. For nano-particle towels with conductor or semi-four characteristics, when the nano particles are placed in an electric field, 'electrons or charge carriers can be easily moved...the nano particles are dispersed in the dielectric f (the general liquid) In the case of, for example, a solvent), the individual nanoparticles are separated so that there is no contact between them. When an external electric field is applied across the liquid, the positive or negative charge in a single nanoparticle shifts the phase electric field to the different ends of the anisotropic nanoparticle. Since there is no contact between the nanoparticles, the charge will accumulate at the end of the individual nano-greens until the electric field caused by the moving charge is equal to the applied electric field. Because of the various directions of the rice particles, ..., &quot;τ', the charge on both ends of the nanoparticle will form a dipole. Mangtai water is negative. The right non-water particles can move freely in the liquid, and the formed dipole will make its # along the external electric field line. ^ 148004.doc • 14 - 201108311 F = aELsin0cos9 The power (F) applied to the dipole is proportional to the nanoparticle length (L), the electric field strength (E) and the factor sinecose, where a is the dielectric of the solvent. The constant and the constant of the free charge density in the nanowire, and the angle between the longitudinal axis of the θ-line nanowire and the electric field. This principle also applies to the case of an AC field where the charge will vary correspondingly with the external field. The power applied to the nanoparticles will cause them to align along the electric field lines in the same manner as described above. The frequency of the alternating field can vary greatly. It is preferred to use a frequency from the lower limit to 1 MHz. Higher frequencies above 5 kHz may be preferred due to their low effect on the human body due to short circuits. It is especially good at frequencies from Hz to 5 kHz. Preferably, the voltage applied to the alignment method is an Ac voltage. To align the nanoparticles, an electrode pair is used to form an electric field. This can be accomplished by depositing electrodes on the substrate or by using one or more movable electrodes (preferably a pair of similar electrodes). Preferably, the auxiliary electrode is a movable electrode. Therefore, after being used in the nanoparticle alignment method, they do not form part of the final framework of the device. The movable electrode is placed on a substrate or device or device assembly on which the nanoparticles are to be aligned. The electrodes can be in direct contact with the substrate. The electrodes may, for example, be fixed by a fixing member such that they are in direct contact with the substrate, or are in close proximity to the substrate at a short distance (contact or a distance of 10 microns) without contacting the substrate. They are connected to the power source so that a voltage can be applied to establish an electric field of a desired intensity (preferably 1 to 250 kV/m). The distance between the two auxiliary or movable electrodes should preferably be greater than the anisotropic

[S 148004.doc 201108311 米粒子之縱向尺寸β 通後藉由任何適宜方法將奈米粒子沉積於輔助電極、或 裝置或裝置組件之間之基板區域上成為一薄層,同時對電 極施加電壓。 與先前技術部分中所述之使用〇E裝置之圖案化S/D電極 來施加用於配向之電場之先前技藝之配向奈米粒子之方法 比車父,本發明之方法具有數個優點。因此,由於使用外部 電極,可輕易地改變距離及藉此改變電場強度,及亦可於 沒有損壞裝置電極或其等所連接之組件的風險下施加較高 電壓。此特別有利,係因所沉積之奈米粒子可直接與裝置 電極接觸,以致當對此等裝置電極施加良好配向所需之高 電壓時,會發生電短路,其隨後會破壞奈米粒子及裝置。 由於使用外部電極,可避免此風險。基於相同原因,於本 發明之方法中無需於裝置電極與奈米粒子之間提供如先前 技藝方法中所使用之保護性絕緣層。就此技術而言,亦可 利用柔性、凹板、喷霧、成捲式及喷墨印刷技術,以藉由 快速配向方法實施奈米粒子沉積。 以使用包含奈米粒子之液體之液體沉積技術為尤佳。較 佳沉積技術包括,但非限於,旋塗、浸塗、彎月面塗覆、 喷墨印刷、墨浸、凸版印刷、篩網印刷 '刮刀塗覆、輥輪 印刷、反轉輥輪印刷、平版光微影印刷、快乾印刷、凹版 印刷、捲同紙印刷、喷塗、刷塗或移印。以柔性印刷、凹 版印刷及喷墨印刷為特佳。 為藉由液體沉積技術塗覆’應首先將奈米粒子分散於適 148004.doc -16- 201108311 宜液體或溶劑中。 液體之介電特,丨生其為 甚為重要係因其係用作介電介質。夺 米粒子應充分分耑,丨中允a + &quot; 政 亦為电場下之NW定向提供自由 ,。液體介電介質可為溶劑或溶銭合物,較佳為有機溶 1較佳浴劑-般係取決於_表面之屬性。就非鈍化聽 而吕’若表^被氧化,則通常使用醇型溶劑。就表面經純 化之NWffij δ ’可使用許多有機溶劑。溶劑之極化亦可係 關於NW分散之重要問冑:若極性溶劑具有高介電常數, 則外電場可輕易地觸及奈米粒子而不致於液體中有過多損 失。一般以大於5(2(TC)之介電常數為較佳。 、 較佳的液體及溶劑係取決㈣於囊封奈米粒子之單層之 類型。就大部份烧基或烯烴類單層介質而言,良好溶劑係 ^心溶劑’如氯仿及二氯苯。較佳液體—般包含氯 本、1,2-二氯笨、丁酮或苯曱醚。以具有高偶極矩之溶劑 為車又佳,尤其係具有1,5 D(德拜)或更高之永久偶極矩之溶 劑。 溶劑可額外包含一或多種其他組分’例如,表面活性化 合物、潤滑劑、潤濕劑、分散劑、疏水劑、黏附劑、流動 改良劑、消泡劑' 除氣劑、反應性或非反應性稀釋劑、助 劑、著色劑、染料或顏料、增敏劑、穩定劑、其他奈米粒 子或抑制劑。 於沉積奈米粒子溶液並配向奈米粒子後,較佳(例如)藉 由於周圍溫度及氣壓下蒸發來移除溶劑。亦可施加熱及/ 或降低壓力來加速蒸發。 148004.doc •17· 201108311 二後可以另一襞置功能層或一或多個保護層覆蓋經配向 之奈米粒子層,例如將聚合物介電層沉積於頂閘型電晶體 之頂面,或u聚合物保護層來避免氧氣破壞奈米粒子。 可將藉由本發明之方法配向之奈米粒子用作電子'電光 學、電致發光、光致發光或光學組件或裝置中之電荷傳 輸、半導體、導電、光導或發光材料。 j佳裝置係、FET、TFT、IC、邏輯電路、電容器、汉㈣ 籤LED LET、PV、太陽能電池、雷射二極體、光導 體、光檢測器、電子照相裝置、電子照相記錄裝置、有機 a己憶裳置、感應裝置、電荷注射層、肖特基三極體、平面 化層、抗靜電膜,基板及導電圖案。於此等裝置中, -般將本發明之配向奈米粒子施用為薄層或膜。尤佳者係 FET及 TFT ° 較佳電子裝置包含以下組件: -視需要之一基板(1), -一或多個導體,較佳係電極(2,4), -包含介電質之絕緣層(3), -包含配向奈米粒子之半導體層(5)。 本發明之第一較佳實施例係關於一種底閘型(BQ)FET裝 置如圖1示例性顯示,其以以下所述次序包含以下組 件: -視需要之一基板(1), -閘電極(2), -包含介電質之絕緣層(3), 148004.doc •18· 201108311 -源及汲電極(4),及 -包含配向奈米粒子之導電(或較佳半導體)層(5)。 用於製備此BG電晶體裝置之方法較佳包含步驟: -將閘電極(2)施加於基板(1)上, -將介電層(3)施加於閘電極(2)及基板(1)之頂面上, -將源及汲電極(4)施加於介電層(3)之頂面上, -將一對輔助電極置於介電層(3)上,以使其等不與源及 汲電極(4)接觸, -將視需要分散於具有或無黏結劑之溶劑或溶劑混合物中 之半導體奈米粒子(5)之層沉積於介電層(3)及源及汲電 極(4)上,以使奈米粒子位於輔助電極之間, -對輔助電極施加電壓, -視需要將液體自奈米粒子層(5)移除, -視需要移除辅助電極,及 -視需要於奈米粒子層上提供一或多個其他功能層。 第二較佳實施例係關於一種頂閘型(TG)FET裝置,如圖 2中示例性顯示,其以以下描述之次序包含以下組分: -一基板(1), -源及汲電極(4), -包含配向奈米粒子之半導體層(5), -包含介電質之絕緣層(3),及 -閘電極(2)。 用於製備此TG電晶體裝置之方法較佳包含步驟: -將源及汲電極(4)施加於基板(1)上, 148004.doc -19· 201108311 -將一對輔助電極置於基板(1)上’以使其等不與源及沒 電極(4)接觸, -將視需要分散於具有或不具有黏結劑之溶劑或溶劑混合 物中之半導體奈米粒子層(5)沉積於基板(!)及源及汲電 極(4)上,以使奈米粒子位於輔助電極之間, -對輔助電極施加電壓, _視需要將液體自奈米粒子層(5)移除, -視需要移除輔助電極, -將介電層(3)施加於奈米粒子層(5)之頂面上,及 •將閘電極(2)施加於介電層之頂面上。 此等裝置結構及方法之變化可輕易地由熟習本技藝者利 用本技藝已知之習知方法及材料實施,例如,以提供頂接 觸(TG)或底接觸(BC)電晶體裝置。 可以任何次序佈置FET裝置中之閘、源及汲電極及絕緣 及半導體層’其限制條件係源與没電;^係、藉由絕緣層與問 電極分離’閘電極與半導體層均與絕緣層接觸,且源電極 及沒電極均與半導體層接觸。 於更普遍之方法中,製備電子裝置(較佳半透明電子裝 置)之方法係如下: )字作電極(較佳源及汲電極(4))施加於基板(1)上或介 電層(3)上, b)將-對輔助電極置於基板⑴或介電層⑴上,以使其 等不與源及汲電極(4)接觸, C)將視需要分散於液體中之導電或半導體奈米粒子層(5) 148004.doc •20- 201108311 沉積於基板(1)或介電層(3)及源&amp;沒電極⑷上,以使奈 米粒子位於輔助電極之間, d) 對辅助電極施加電壓, e) 視需要將液體自奈米粒子層(5)移除, f) 視需要移除辅助電極,及 g) 視需要於奈米粒子層上提供—或多個其他功能層, 其中可以不同次序實施步驟b)、〇、d)及奈二粒子 較佳係半導體。 較佳地’在輔助電極之間之電場仍然存在時,將液體部 :或完全地移除。一般藉由施加所需電壓來維持所需電 場。 裝置之其他組件及適宜材料及其等之製備方法係為熟習 本技藝者已知,且描述於文獻(例如,us 7,Q29,9叫中。 例如’可使用各種基板(例如,玻璃或塑膠)來製造本發 明之裝置。-般以塑膠材料為較佳,實例包括醇酸樹脂、 稀丙基醋、苯并環丁烯、丁二稀_苯乙稀、纖維素、乙酸 纖維素、環氧化物 '環氧聚合物、乙稀_氯三氟乙烯、乙 烯-四氟乙烯、纖維玻璃增強之塑膠、敗碳聚合物、六I 丙烯二敗亞乙烯共聚物、高密度聚乙烯、聚對二曱苯、聚 酿胺、聚醯亞胺、聚芳醯胺、聚二甲基石夕氧烧、聚醚硬、 聚乙烯、聚萘二曱酸乙二酯、聚對苯二曱酸乙二酯、聚 _、聚甲基丙稀酸甲酷、聚兩婦、聚苯^ 鼠乙烯、聚胺基甲酸醋、聚氯乙稀、聚石夕氧橡膠、聚石夕 氧。較佳的基板材料係聚對笨二甲酸乙二_、聚龜亞胺、 148004.doc -21 - 201108311 及聚萘二曱酸乙二酯。基板亦可包含塗覆有以上材料之任 何塑膠材料、金屬或玻璃。基板較佳應為均句以確保良好 的圖案清晰度。基板亦可藉由擠壓、拉伸、摩擦或藉由光 化學技術均勻地預對準,以定向有機半導體來增強載子移 動性。 '原及及閘電極可藉由諸如喷塗、浸塗、捲筒紙塗覆或 旋轉塗覆之液體塗覆’或藉由真空沉積或氣相沉積方法沉 積。適宜的電極材料及沉積方法係為熟習本技藝者已知。 適宜的電極材料包括,但非限於,無機或有機材料,或兩 者之複合物。適宜導體或電極材料之實例包括聚苯胺、聚 吼洛、PEDQT或摻雜共輛聚合物、其他石墨分散液或糊狀 物石反奈米官或石墨烯薄片或諸如Au、Ag、a、、犯 或其等混合物之金屬粒子,以及諸如(例如)Cu、Cr、 等之濺鍍塗覆或蒸鍍金屬,及如(例如)ITO之半導體。亦 可使用自液相沉積之有機金屬前驅體。 本發明之PV裝置較佳包含: •一低功函數電極(例如紹), -一高功函數電極(例如,ΙΤ0),其中一者係透明, -由電洞傳輸及電子傳輸材料及其等混合物組成之單一摻 合層或雙層;該雙層可作為兩不同層、或摻合混合物存 在(參見,例如,Coakley,Κ.Μ 及 McGehee,MD chem[S 148004.doc 201108311 The longitudinal dimension β of the rice particles is then deposited by any suitable method to deposit a nanoparticle on the substrate area between the auxiliary electrode, or the device or device assembly, while applying a voltage to the electrode. The method of prior art aligning nanoparticles for applying an electric field for alignment with the patterned S/D electrodes of the 〇E device described in the prior art section has several advantages over the method of the present invention. Therefore, since the external electrode is used, the distance can be easily changed and thereby the electric field strength can be changed, and a higher voltage can be applied without risk of damaging the device electrode or its connected components. This is particularly advantageous because the deposited nanoparticles can be in direct contact with the device electrodes such that when a high voltage is required for the electrodes of such devices to apply a good alignment, an electrical short can occur, which subsequently destroys the nanoparticles and the device. . This risk can be avoided due to the use of external electrodes. For the same reason, it is not necessary to provide a protective insulating layer between the device electrode and the nanoparticle as used in the prior art method in the method of the present invention. For this technique, flexible, gravure, spray, roll-to-roll, and inkjet printing techniques can also be utilized to effect nanoparticle deposition by a rapid alignment method. Liquid deposition techniques using liquids containing nanoparticles are preferred. Preferred deposition techniques include, but are not limited to, spin coating, dip coating, meniscus coating, ink jet printing, ink immersion, letterpress printing, screen printing 'blade coating, roller printing, reverse roller printing, Lithographic lithography, fast-drying, gravure, roll-to-paper, spray, brush or pad printing. It is particularly good for flexographic printing, gravure printing and inkjet printing. In order to be coated by liquid deposition techniques, the nanoparticles should first be dispersed in a liquid or solvent suitable for use in 148004.doc -16 - 201108311. The dielectric of the liquid is very important because it is used as a dielectric medium. The particles of the rice should be fully divided, and the a&quot; government also provides freedom for the NW orientation under the electric field. The liquid dielectric medium can be a solvent or a solvate, preferably an organic solvent. A preferred bath is generally dependent on the nature of the surface. In the case of non-passivation, if the surface is oxidized, an alcohol type solvent is usually used. Many organic solvents can be used in the case of surface-purified NWffij δ '. The polarization of the solvent can also be important for NW dispersion: if the polar solvent has a high dielectric constant, the external electric field can easily touch the nanoparticles without excessive loss in the liquid. Generally, a dielectric constant of more than 5 (2 (TC) is preferred. The preferred liquid and solvent depend on the type of the monolayer of the encapsulated nanoparticle. Most of the alkyl or olefinic monolayer For the medium, a good solvent is a solvent such as chloroform and dichlorobenzene. Preferably, the liquid generally contains a chlorine, 1,2-dichlorobenzene, methyl ethyl ketone or benzoin. A solvent having a high dipole moment. It is also good for cars, especially solvents with a permanent dipole moment of 1,5 D (Debye) or higher. Solvents may additionally contain one or more other components 'for example, surface active compounds, lubricants, wetting agents , dispersants, hydrophobic agents, adhesives, flow improvers, defoamers' degassing agents, reactive or non-reactive diluents, additives, colorants, dyes or pigments, sensitizers, stabilizers, other nemesis Rice particles or inhibitors. After depositing the nanoparticle solution and aligning the nanoparticles, it is preferred to remove the solvent, for example, by evaporation at ambient temperature and pressure. Heat may also be applied and/or pressure may be reduced to accelerate evaporation. 148004.doc •17· 201108311 Two additional functional layers or one Or a plurality of protective layers covering the aligned nanoparticle layer, for example, depositing a polymer dielectric layer on the top surface of the top gate type transistor, or a u polymer protective layer to prevent oxygen from damaging the nano particles. Aligned nanoparticles of the invention are used as charge transport, semiconductor, conductive, photoconductive or luminescent materials in electronic 'electro-optical, electroluminescent, photoluminescent or optical components or devices. j good device systems, FETs, TFTs, IC, logic circuit, capacitor, Han (four) sign LED LET, PV, solar cell, laser diode, photoconductor, photodetector, electrophotographic device, electrophotographic recording device, organic a memory board, sensing device, Charge injection layer, Schottky triode, planarization layer, antistatic film, substrate and conductive pattern. In such devices, the aligned nanoparticles of the present invention are generally applied as a thin layer or a film. FET and TFT ° The preferred electronic device comprises the following components: - one substrate (1) as needed, - one or more conductors, preferably a tie electrode (2, 4), - an insulating layer containing a dielectric (3) ), - containing aligned nanoparticle Semiconductor Layer (5). A first preferred embodiment of the present invention is directed to a bottom gate type (BQ) FET device as exemplarily shown in FIG. 1, which comprises the following components in the order described below: - one of the substrates as needed ( 1), - gate electrode (2), - dielectric layer containing dielectric (3), 148004.doc • 18· 201108311 - source and germanium electrode (4), and - conductive containing aligned nanoparticles (or Preferably, the method for preparing the BG transistor device comprises the steps of: - applying a gate electrode (2) to the substrate (1), - applying a dielectric layer (3) to the gate electrode (2) and the top surface of the substrate (1), - applying the source and the germanium electrode (4) to the top surface of the dielectric layer (3), - placing a pair of auxiliary electrodes on the dielectric layer (3) So that it does not contact the source and the ruthenium electrode (4), - deposit a layer of semiconductor nanoparticles (5) dispersed in a solvent or solvent mixture with or without a binder as needed on the dielectric layer (3) And the source and the ytterbium electrode (4) so that the nanoparticles are located between the auxiliary electrodes, - applying a voltage to the auxiliary electrode, - if necessary, the liquid is from the nanoparticle layer (5) ) removal, - removal of the auxiliary electrode as needed, and - providing one or more other functional layers on the nanoparticle layer as needed. The second preferred embodiment is directed to a top gate type (TG) FET device, as exemplarily shown in Fig. 2, which comprises the following components in the order described below: - a substrate (1), - source and germanium electrodes ( 4) - a semiconductor layer (5) comprising aligned nanoparticles, - an insulating layer (3) comprising a dielectric, and - a gate electrode (2). The method for preparing the TG transistor device preferably comprises the steps of: - applying a source and a germanium electrode (4) to the substrate (1), 148004.doc -19·201108311 - placing a pair of auxiliary electrodes on the substrate (1) On the 'substrate so that it does not contact the source and the electrode (4), the semiconductor nanoparticle layer (5) which is dispersed in a solvent or solvent mixture with or without a binder as needed is deposited on the substrate (! And the source and the yttrium electrode (4) so that the nanoparticles are located between the auxiliary electrodes, - applying a voltage to the auxiliary electrode, _ removing the liquid from the nanoparticle layer (5) as needed, - removing as needed An auxiliary electrode, - a dielectric layer (3) is applied to the top surface of the nanoparticle layer (5), and a gate electrode (2) is applied to the top surface of the dielectric layer. Variations in the structure and method of such devices can be readily implemented by those skilled in the art using conventional methods and materials known in the art, for example, to provide a top contact (TG) or bottom contact (BC) transistor device. The gate, source and drain electrodes and the insulating and semiconductor layers in the FET device can be arranged in any order. The limiting conditions are source and no power; the system is separated from the electrode by the insulating layer. The gate electrode and the semiconductor layer are both insulated and insulated. Contact, and both the source electrode and the non-electrode are in contact with the semiconductor layer. In a more general method, the method of preparing an electronic device (preferably a semi-transparent electronic device) is as follows: a word electrode (a preferred source and a germanium electrode (4)) is applied to the substrate (1) or a dielectric layer ( 3) upper, b) placing the auxiliary electrode on the substrate (1) or the dielectric layer (1) so as not to be in contact with the source and the germanium electrode (4), C) conducting or dispersing the conductive or semiconductor in the liquid as needed Nanoparticle layer (5) 148004.doc •20- 201108311 Deposited on substrate (1) or dielectric layer (3) and source &amp; no electrode (4) so that the nanoparticles are located between the auxiliary electrodes, d) Apply voltage to the auxiliary electrode, e) remove the liquid from the nanoparticle layer (5) as needed, f) remove the auxiliary electrode as needed, and g) provide on the nanoparticle layer as needed - or multiple other functional layers Wherein steps b), 〇, d) and nai particles may be carried out in a different order. Preferably, the liquid portion is: or completely removed when the electric field between the auxiliary electrodes is still present. The required electric field is typically maintained by applying the required voltage. Other components of the device, suitable materials, and methods of making the same are known to those skilled in the art and are described in the literature (eg, us 7, Q29, 9 for example. 'A variety of substrates can be used (eg, glass or plastic) To manufacture the device of the present invention. Generally, a plastic material is preferred. Examples include alkyd resin, propyl vinegar, benzocyclobutene, butyl benzene, cellulose, cellulose acetate, and rings. Oxide 'epoxy polymer, ethylene-chlorotrifluoroethylene, ethylene-tetrafluoroethylene, fiberglass reinforced plastic, carbon fiber polymer, hexa-propylene propylene propylene vinylene copolymer, high density polyethylene, poly pair Diphenylbenzene, polystyrene, polyamidiamine, polyarsenamide, polydimethyl oxalate, polyether hard, polyethylene, polyethylene naphthalate, polyethylene terephthalate Diester, poly-, polymethyl methacrylate, gemini, polystyrene, vinyl, polyurethane, polyvinyl chloride, polyoxet, polychlorite, preferably The substrate material is poly(p-dibenzoic acid), polyglycolide, 148004.doc -21 - 201108311 and polyethylene naphthalate The substrate may also comprise any plastic material, metal or glass coated with the above materials. The substrate should preferably be uniform to ensure good pattern definition. The substrate can also be extruded, stretched, rubbed or lighted by light. Chemical techniques are uniformly pre-aligned to direct organic semiconductors to enhance carrier mobility. 'Original and gate electrodes can be coated by liquids such as spray coating, dip coating, web coating or spin coating' or Deposition by vacuum deposition or vapor deposition methods. Suitable electrode materials and deposition methods are known to those skilled in the art. Suitable electrode materials include, but are not limited to, inorganic or organic materials, or a combination of the two. Examples of conductor or electrode materials include polyaniline, polypyroxene, PEDQT or doped co-polymers, other graphite dispersions or paste stone reverse-nano- or graphene sheets or such as Au, Ag, a, Metal particles of or a mixture thereof, and sputter coated or vapor-deposited metals such as, for example, Cu, Cr, etc., and semiconductors such as, for example, ITO. Organometallic precursors deposited from liquid phase may also be used.The PV device of the present invention preferably comprises: • a low work function electrode (eg, )), a high work function electrode (eg, ΙΤ0), one of which is transparent, - a hole transport and electron transport material, and the like A single blend or double layer of the mixture; the bilayer can exist as two distinct layers, or as a blending mixture (see, for example, Coakley, Κ.Μ and McGehee, MD chem

Mater. (2004),16, 4533), _ 一改變高功函數電極之功函數以為電洞提供歐姆接觸之 視耑要之導電聚合物層(如,例如,pED〇T:pSs), 148004.doc -22· 201108311 觸之視需要之 位於該高功函數電極上為電子提供歐姆接 塗層(諸如LiF), 包含本發明之配向奈米粒 其中該電洞及/或電子傳輸材料 子0 電子傳輸材料亦可為諸如氧化辞或硒化鎘之無機封料, 或諸如富勒烯(fullerene)衍生物之有機材料或η·推雜奈 米粒子及線(例如,PCBM, [(6,6)_苯基C61_ 丁酸甲醋]或聚 口物,參見,例如,Coakley,K.M. &amp;McGehee,M.D.Mater. (2004), 16, 4533), _ a conductive polymer layer that changes the work function of the high work function electrode to provide an ohmic contact for the hole (eg, for example, pED〇T:pSs), 148004. Doc -22· 201108311 It is desirable to provide an ohmic coating (such as LiF) for the electrons on the high work function electrode, comprising the aligned nanoparticle of the present invention, wherein the hole and/or electron transport material is 0 electron transport The material may also be an inorganic seal such as oxidized or cadmium selenide, or an organic material such as a fullerene derivative or an η·negative nanoparticle and a wire (for example, PCBM, [(6, 6) _phenyl C61_butyric acid methyl vinegar] or agglomerates, see, for example, Coakley, KM &amp; McGehee, MD

Chem. Mater. (2004),16, 4533)β電洞傳輸材料可為自p摻 雜奈米粒子及奈米線。 或者,可將本發明之配向奈米粒子用於(例如)顯示器應 用中之有機發光裝置或二極體(LED),或用作(例如)液晶 員示器之责光器。常見led係利用多層結構獲得。發射層 一般係夾合於一或多個電子傳輸及/或電洞傳輸層之間。 藉由施加電壓,作為電荷載子之電子及電洞移向發射層, 其等於此處再組合導致激發及進而令包含於發射層中之發 光體單元發光。根據其等電學及/或光學特性,可將配向 奈米粒子用於LED裝置之電荷傳輸層及/或發射層中之一或 多者中。例如,可將電致發光奈米線用作LED裝置中之發 射層’如 US 6,918,946及 US 6,846,565 中所述。 亦可將包含導電材料之配向奈米粒子用作包括,但非限 於’下列之應用中之金屬之替代物:LED應用中之電荷注 射層及ITO平面化層、平板顯示器及觸控螢幕之膜 '抗靜 電膜、印刷導電基板、諸如印刷電路板及電容器之電子應 148004.doc -23- · 201108311 用中之圖案或跡線。 由於藉由本發明方法配向之奈米粒子,尤其奈米線或奈 米管,具有高各向異性,故其等亦可單獨或與其他材料一 起用於如光學偏振片之光學組件或裝置中。 若令大區域内之線平行配向,則其等將會形成長個別線 之線柵型結構,該結構又可用作線柵偏振片(Wgp)。 概念上最簡單之偏振片係線栅偏振片,其係由佈置於與 入射光束垂直之平面中之細平行導線之規則陣列組成。其 電場之一分量平行於線配向之電磁波誘發電子沿線之長度 移動。由於電子可自由移動,當反射光時,偏振月以如金 屬表面之類似方式工作;一部份能量因線中之焦耳熱而損 失’及剩餘之波會沿入射光束反向反射。就電場垂直於線 之波而言’電子無法沿各線寬度移動過遠;因此,幾乎不 損失或反射能量,且入射波可傳播通過栅。由於平行於線 之電場分量被吸收或反射,故透射波具有僅沿與線垂直方 向之電場’並進而線性偏振。 就實際用途而言,線間之分隔距離應小於輻射波長,且 線寬應佔此距離之一小部份。此意味一般僅將線栅偏振片 用於微波及遠及中紅外光。利用本發明之技術,可製得偏 振光線之極窄間距柵格。由於偏振程度幾乎與入射波長及 角度無關,故可將WGP用於諸如投影之寬頻帶應用。 於本文通篇及本說明書之申請專利範圍中,詞語「包 含」及「含有」及此等詞語之變體,例如「包含有」及 「包括」意指「包括但非限於」,且非意欲(且不)排除其 148004.doc •24- 201108311 :組分。除非前後文另外明確說明,否則如本文所使用之 = 吾之複數形式於本文t應理解為包括單數形式且反之亦 將瞭解可對本料之以上實㈣奸變化 =之範圍内。除非另外說明,否則本說明書中丄: 各特徵可經用於相同、等效或類似目的之替代特徵替代。 因此,除非另外說明,否則所揭示之各特徵僅係等效咬類 似特徵之通用系列中之一實例。 於本說明書及申請專利範討所揭示之所有特徵可以任 何組合方式組合,除此等特徵及/或步驟中之至少一部份 係相互排斥之組合外。特定言之,本發明之較佳特徵可適 用於本發明之所有態樣且可以任何組合使用。類似地以 非必需組合描述之特徵可獨立(非組合)地使用。 本發明現將參照以下實例更詳細地描述,該等實例僅作 說明之用且不限制本發明之範圍。 縮寫 NW 奈米線 Au/Ge/Si/Al 金/鍺/矽/鋁 AC/DC 交流電’ a.c./直流電,d.c. (BG)FET (底閘式)場效電晶體 OE 有機電子元件 LB方法 利用朗谬爾-布洛傑特(Langmuir-Blodgett) 膜之方法 EFIA方法 電場配向方法 14S004.doc -25- 201108311 PV 光伏打 S/D 源極及汲極 WGP 線拇偏振片 實驗 藉由 A.T. Heitsch等人之J. Am. Chem. Soc. (2008) 130, 5436_7所例示之固-液-固(SLS)生長製造本申請案之實例中 所使用之奈米線。然而,本發明之實例並非限於藉由以上 及文獻 Adv. Mater. (2004) 7,646-649 ; J. Am. Chem. Soc. (2002) 124(7), 1424-1429,及 Chem. Mater. (2005) 17, 5 705-571 1中任一者所述之SLS方法製得之奈米線。例如, 亦可應用基於氣相生長奈米線之方法。 實例1 直接於玻璃基板上配向之Ge奈米線(NW) 用於此實驗之配向方法係示例性地描述於圖3中,其中 (1)係玻璃基板,(7)係輔助電極及(6)表示包含NW之液滴。 藉由使用HP 8111A脈衝/功能發電機20 MHz及Trek功率放 大器(Model 603)提供電場,該電場係由沉積於潔淨玻璃基 板(1)上之兩平行電極條(7)提供。電極(7)係以使用熱蒸鍍 方法沉積之A1薄膜應用,且其具有30 nm之厚度。兩電極 (7)之間之間隙為2 mm,且所施加之AC電壓為50至500 V 及0.9 kHz頻率。NW分散液係藉由將以異戊二烯鈍化之0.1 mg Ge NW分散於1 ml氯仿或1 ml丁酮中而製得,並作為液 滴(6)分配於電極(7)之間之基板(1)之頂面上。Chem. Mater. (2004), 16, 4533) The beta hole transport material can be self-p-doped nanoparticles and nanowires. Alternatively, the aligned nanoparticles of the present invention can be used, for example, as an organic light-emitting device or diode (LED) in a display application, or as a light-receiving device for, for example, a liquid crystal display. Common led systems are obtained using a multilayer structure. The emissive layer is typically sandwiched between one or more electron transport and/or hole transport layers. By applying a voltage, the electrons and holes that act as charge carriers move toward the emissive layer, which is equivalent to recombining here to cause excitation and, in turn, to cause the light emitting unit contained in the emissive layer to emit light. Depending on its isoelectric and/or optical properties, the aligned nanoparticles can be used in one or more of the charge transport layer and/or the emissive layer of the LED device. For example, an electroluminescent nanowire can be used as the emission layer in an LED device as described in US 6,918,946 and US 6,846,565. Aligned nanoparticles comprising a conductive material can also be used as a substitute for, but not limited to, metals in the following applications: charge injection layer and ITO planarization layer in LED applications, flat panel display and touch screen film 'Antistatic film, printed conductive substrate, electronics such as printed circuit boards and capacitors should be used in patterns or traces. 148004.doc -23- · 201108311 Since the nanoparticles, especially the nanowires or nanotubes, which are aligned by the method of the present invention have high anisotropy, they can be used alone or in combination with other materials in optical components or devices such as optical polarizers. If the lines in a large area are aligned in parallel, they will form a wire-grid structure of long individual lines, which in turn can be used as a wire grid polarizer (Wgp). The conceptually simplest polarizer is a wire grid polarizer consisting of a regular array of fine parallel wires arranged in a plane perpendicular to the incident beam. One of the electric fields is parallel to the line-aligned electromagnetic wave to induce electrons to move along the length of the line. Since the electrons are free to move, when reflecting light, the polarization month works in a similar manner as a metal surface; a portion of the energy is lost due to Joule heat in the line' and the remaining waves are reflected back along the incident beam. Insofar as the electric field is perpendicular to the wave of the line, electrons cannot move too far along the width of each line; therefore, energy is hardly lost or reflected, and the incident wave can propagate through the grid. Since the electric field component parallel to the line is absorbed or reflected, the transmitted wave has an electric field 'only in a direction perpendicular to the line' and is thus linearly polarized. For practical purposes, the separation distance between lines should be less than the wavelength of the radiation, and the line width should be a small part of this distance. This means that only wire grid polarizers are used for microwave and far and mid-infrared light. Using the technique of the present invention, an extremely narrow pitch grid of polarized light can be produced. Since the degree of polarization is almost independent of the incident wavelength and angle, WGP can be used for wideband applications such as projection. The words "including" and "including" and variations of such terms such as "including" and "including" means "including but not limited to" and are not intended to be used in the scope of the application. (and not) excludes 148004.doc •24-201108311: components. Unless otherwise expressly stated herein, the use of the plural <RTI ID=0.0>> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> is intended to include the singular and vice versa. In the present specification, unless otherwise stated, each feature may be replaced by alternative features for the same, equivalent or similar purpose. Thus, unless otherwise stated, the features disclosed are only one example of a generic series of equivalent bite-like features. All of the features disclosed in this specification and the patent specification can be combined in any combination, except that at least some of the features and/or steps are mutually exclusive combinations. In particular, preferred features of the invention are applicable to all aspects of the invention and can be used in any combination. Features described similarly in non-essential combinations can be used independently (non-combined). The invention will now be described in more detail with reference to the following examples, which are intended to be illustrative only and not limiting the scope of the invention. Abbreviation NW nanowire Au/Ge/Si/Al gold/锗/矽/aluminum AC/DC AC ac/dc, dc (BG) FET (bottom gate) field effect transistor OE organic electronic component LB method using lang Langmuir-Blodgett film method EFIA method electric field alignment method 14S004.doc -25- 201108311 PV photovoltaic S/D source and bungee WGP line thumb polarizer experiment by AT Heitsch et al The solid-liquid-solid (SLS) growth exemplified by J. Am. Chem. Soc. (2008) 130, 5436_7 produces the nanowires used in the examples of the present application. However, examples of the invention are not limited by the above and the literature Adv. Mater. (2004) 7, 646-649; J. Am. Chem. Soc. (2002) 124(7), 1424-1429, and Chem. Mater (2005) The nanowire prepared by the SLS method of any of the above, 5, 705-571. For example, a method based on vapor phase growth of nanowires can also be applied. Example 1 Ge nanowire (NW) aligned directly on a glass substrate. The alignment method used in this experiment is exemplarily described in Fig. 3, wherein (1) is a glass substrate, (7) is an auxiliary electrode, and (6) ) indicates a droplet containing NW. An electric field is provided by using an HP 8111A pulse/function generator 20 MHz and a Trek power amplifier (Model 603) provided by two parallel electrode strips (7) deposited on a clean glass substrate (1). The electrode (7) was applied as an A1 film deposited by a thermal evaporation method, and it had a thickness of 30 nm. The gap between the two electrodes (7) is 2 mm and the applied AC voltage is 50 to 500 V and 0.9 kHz. The NW dispersion is prepared by dispersing 0.1 mg Ge NW inactivated with isoprene in 1 ml of chloroform or 1 ml of methyl ethyl ketone, and is distributed as a droplet (6) between the electrodes (7). (1) on the top surface.

1A)自氯仿分配之NW 148004.doc • 26· 201108311 利用玻璃吸液管將Ge NW(均藉由異戊二烯鈍化)分散液 作為單一液滴分配於施加有電場之兩電極之間之基板上。 蒸發氣仿後,NW便沉積於基板上。圖4顯示完全蒸發溶劑 後所拍攝之光學圖像,其中(7)係其中一個A1電極。可觀察 到一部份NW已於電場中配向。據信此係由電場引發之NW 配向引起,如上文所述。然而,自圖4亦可見經配向NW之 數量較NW之總數低,此可歸因於所使用之溶劑。此處, 氯仿之蒸發速率極高,以致NW無充足時間來完成定向。 因此,建議使用具有較低蒸發速率之溶劑以延長NW於電 場作用下於液體中定向之時間,及/或使用較高電場強度 以增加NW之定向速度。1A) NW from chloroform distribution 148004.doc • 26· 201108311 A Ge NW (all passivated by isoprene) dispersion is dispensed as a single droplet from a substrate between two electrodes to which an electric field is applied, using a glass pipette on. After evaporation of the vapor, NW is deposited on the substrate. Figure 4 shows an optical image taken after completely evaporating the solvent, wherein (7) is one of the A1 electrodes. It can be observed that a portion of the NW has been aligned in the electric field. It is believed that this is caused by the NW alignment induced by the electric field, as described above. However, it can be seen from Figure 4 that the number of aligned NWs is lower than the total number of NWs, which can be attributed to the solvent used. Here, the evaporation rate of chloroform is so high that NW does not have enough time to complete the orientation. Therefore, it is recommended to use a solvent having a lower evaporation rate to extend the time during which the NW is oriented in the liquid under the action of the electric field, and/or to use a higher electric field strength to increase the directional velocity of the NW.

1B)自丁酮分配之NW 為降低溶劑蒸發速率,如上所述實施第二實驗,但其中 使用丁酮(ch3c(o)ch2ch3)替代氣仿。丁酮可如氯仿般良 好地分配經異戊二烯鈍化之Ge NW。然而,相比於氣仿, 丁酮蒸發較慢及因此可於完全蒸發前於基板上停留數秒; 此時間足以令NW於電極之間配向。圖5顯示溶劑完全蒸發 後所拍攝之光學圖像,其中(7)係其中一個A1電極。清晰可 見NW(2)於AC電場中配向。然而,存在沿電極向前或向後 之流動流,其較施加至NW之電力強,及因此可破壞溶液 中已形成之經配向NW。此亦可於圖5中觀察到:靠近電極 之NW(5)經配向及甚至分佈,遠離電極之NW經配向,但 未經均勻分佈且一部份亦經損壞,猜想此係由如使用光學 顯微鏡所觀察到之流動流引起。 148004.doc •27- 201108311 1C)單元中Ge NW之配向 以上實驗顯示溶劑之沸點對控制電場配向具有重要作 用》較低的溶劑蒸發速率令NW於電場下有更多時間再排 佈。然而,溶劑流動流仍可破壞經配向之NW束。 為解決此問題,於另一實驗中使用毛細管力來將NW分 散液引入至囊封單元中,隨後於此處施加電場。於此單元 中,藉由蒸鍍將具有2 mm間隙之電極沉積於一玻璃基板 上,於基板之邊緣上添加〇. 1 mm之間隔物,並隨後將另一 玻璃基板置於第一基板之頂面上。兩基板之間隙為〇. 1 mm 且其係用作毛細管通道。 將NW溶液滴於單元邊緣上,且其因毛細管力而立即進 入單元中。 當溶液覆蓋兩電極之間之通道或間隙時,對電極間隙施 加頻率0.9 kHz之75至750 V AC電壓。圖6顯示溶劑蒸發後 之經配向NW。清晰可見NW係沿電場線配向。總而言之, 證實可利用電場配向Ge NW。 於實例1中,證實NW配向之品質係取決於所使用之溶劑 及蒸發速率之控制。因此,良好配向可藉由選擇高沸點溶 劑或藉由將NW分散液囊封於單元内’並於此處實施電場 引發之配向而達成。 實例2 用於利用Ge NW製備FET之電場引發之配向(EFIA) 仍可改良上述方法以大規模生產OE裝置。例如,若需 將NW沉積於大量(&gt;l〇3)FET通道上,則需將特定電極沉積 148004.doc -28 - 201108311 於各通道並對其等施加電場。此外,經施加至個別區域之 電場可影響施加至其他區域之電場。此方法甚為複雜且不 適用於工業用途。 口此’亦可於工業規模上實現之更簡單及有用之方法係 不例性地描述於下文。就此目的而言,將一對枉電極用於 %加電場,該對柱電極可位於基板上之任何位置。圖7示 例丨生及示思性地描述一種於所選擇之單一 BG FET裝置之 頂面上配向Ge NW之方法,該BG FET裝置包含其上塗覆 有底閘電極及作為介電質之Si〇2層之矽基板(1)。於Si02層 之頂面上,提供Au源及汲電極(4)。將連接至AC電源(8)之 —對可移動柱電極(7)置於該裝置上。兩柱電極(7)之間之 間隙為1至2 mm。將施加至柱電極之電壓固定至75〇 v, 0. 9.kHz。 用於配向Ge NW之方法係實施如下: 1. 將柱電極(7)置於裝置之所需區域處。 2. 對柱電極(7)施加電壓,以確保於將Nw分散液置於基板 上之則存在所施加之電場。 3·自玻璃吸液管將!^…於丁酮中之分散液(6)分配於兩柱電 極之間。由於BG矽FET基板之表面經充分潤濕,故Nw 液滴不僅於兩電極間之區域擴散,並且亦會擴散至附 近區域。 4·於此條件下用於奈米線配向之時間小於丨分鐘。由於溶 劑仍可於蒸發期間移動奈米線,故需維持電場直至大 部份溶劑已蒸發。 148004.doc •29· 201108311 5.移除柱電極(7)。 圖8顯示移除溶劑後所拍攝之兩光學圖像。 圖8A顯示位於兩柱電極之間之完整2〇 bg ρΕτ裝 置’該兩柱電極之原始位i可自_中觀㈣。圖8B顯示圓 中所示之中央裝置區域之放大圖。可見Nw係沿與s/d電極 指垂直之方向配向。 圖9顯示BG FET裝置之傳輸特性,其中半導體層係藉由 如上所述之EFIA方法自經配向]^冒製得。Ge Nw之開關比 係高於102,具有6.55 V/十個單位(v/deeade)之極陡的次臨 界擺巾S。1B) NW partitioned from butanone To reduce the evaporation rate of the solvent, a second experiment was carried out as described above, except that butanone (ch3c(o)ch2ch3) was used instead of the gas imitation. Butanone can well distribute isoprene-passivated Ge NW like chloroform. However, butanone evaporates slowly compared to gas imitation and can therefore stay on the substrate for a few seconds before complete evaporation; this time is sufficient to align the NW between the electrodes. Figure 5 shows an optical image taken after the solvent has completely evaporated, wherein (7) is one of the A1 electrodes. Clearly visible NW (2) is aligned in the AC electric field. However, there is a flow forward or backward along the electrode that is stronger than the power applied to the NW, and thus can destroy the aligned NW that has formed in the solution. This can also be observed in Figure 5: NW (5) near the electrode is aligned and even distributed, NW away from the electrode is aligned, but not evenly distributed and some parts are also damaged, it is suspected that the use of optical Caused by the flow current observed by the microscope. 148004.doc •27- 201108311 1C) Orientation of Ge NW in the cell The above experiment shows that the boiling point of the solvent plays an important role in controlling the electric field alignment. The lower solvent evaporation rate allows the NW to have more time to be discharged under the electric field. However, the solvent flow stream can still destroy the aligned NW beam. To solve this problem, capillary force was used in another experiment to introduce the NW dispersion into the encapsulation unit, whereupon an electric field was applied. In this unit, an electrode having a gap of 2 mm is deposited on a glass substrate by evaporation, a spacer of 1 mm is added to the edge of the substrate, and then another glass substrate is placed on the first substrate. On the top. The gap between the two substrates is 〇. 1 mm and it is used as a capillary channel. The NW solution was dropped onto the edge of the unit and it immediately entered the unit due to capillary forces. When the solution covers the channel or gap between the two electrodes, a voltage of 75 to 750 V AC at a frequency of 0.9 kHz is applied to the electrode gap. Figure 6 shows the aligned NW after evaporation of the solvent. It is clearly visible that the NW system is aligned along the electric field line. In summary, it was confirmed that the electric field can be used to align Ge NW. In Example 1, it was confirmed that the quality of the NW alignment depends on the control of the solvent used and the evaporation rate. Thus, good alignment can be achieved by selecting a high boiling point solvent or by encapsulating the NW dispersion in the unit&apos; and performing an electric field induced alignment there. Example 2 Field-Initiated Orientation (EFIA) for Fabricating FETs Using Ge NW The above method can still be modified to produce OE devices on a large scale. For example, if NW is to be deposited on a large number of (&gt;l〇3) FET channels, a specific electrode is deposited 148004.doc -28 - 201108311 on each channel and an electric field is applied thereto. In addition, the electric field applied to the individual regions can affect the electric field applied to other regions. This method is very complicated and not suitable for industrial use. A simpler and more useful method that can be implemented on an industrial scale is described below. For this purpose, a pair of germanium electrodes are used for the % applied electric field, which can be located anywhere on the substrate. Figure 7 illustrates a method for twinning and imaginatively describing a Ge NW disposed on the top surface of a selected single BG FET device including a bottom gate electrode and a Si NMOS as a dielectric. 2 layers of germanium substrate (1). On the top surface of the SiO 2 layer, an Au source and a ruthenium electrode (4) are provided. Connected to the AC power source (8) - the movable column electrode (7) is placed on the device. The gap between the two column electrodes (7) is 1 to 2 mm. The voltage applied to the column electrode was fixed to 75 〇 v, 0.9 kHz. The method for aligning Ge NW is carried out as follows: 1. Place the column electrode (7) at the desired area of the device. 2. Apply a voltage to the column electrode (7) to ensure that the applied electric field is present when the Nw dispersion is placed on the substrate. 3. From the glass pipette will! ^... The dispersion (6) in butanone is partitioned between two columns of electrodes. Since the surface of the BG 矽FET substrate is sufficiently wetted, the Nw droplets diffuse not only in the region between the electrodes but also in the vicinity. 4. The time for the alignment of the nanowires under these conditions is less than 丨 minutes. Since the solvent can still move the nanowire during evaporation, the electric field needs to be maintained until most of the solvent has evaporated. 148004.doc •29· 201108311 5. Remove the post electrode (7). Figure 8 shows two optical images taken after solvent removal. Figure 8A shows the complete 2 〇 bg ρ Ε τ device located between the two column electrodes. The original position i of the two column electrodes can be viewed from the middle (4). Figure 8B shows an enlarged view of the central device area shown in the circle. It can be seen that the Nw system is aligned in a direction perpendicular to the s/d electrode fingers. Fig. 9 shows the transmission characteristics of the BG FET device in which the semiconductor layer is fabricated by the EFIA method as described above. Ge Nw has a switching ratio higher than 102 and has a very steep sub-critical wipe S of 6.55 V/ten units (v/deeade).

對照實例1 :利用藉由LB(朗繆爾·布洛傑特)技術配向之Ge NW製備FET BG FET裝置係製備如下: 基板係與實例1所述者相同,為於Si〇2介電層上具有圖 案化S/D電極之底閘式基板。將該等基板如標準矽基板清 潔方法般清潔。 藉由使用氯仿溶劑製備具有Oj mg/ml濃度之Ge Nw溶 液。 將兩至三滴以上溶液滴於燒杯中之水面上。溶液滴到達 表面後溶劑即迅速蒸發,留下奈米線於水面上形成1^~層 之一或多個間距。 令預先置於溶液中之以上基板緩慢地自表面下方移向奈 米線層’並隨後自水中移出。NW層附著並沉積於基板上。 乾燥底閘式奈米線FET及等待測試。 148004.doc •30- 201108311 圖10顯示20 μιη S/D通道BG FET(於石夕基板上)上之Ge NW(藉由LB法沈積)之光學圖像,及圖11顯示該裝置之傳 輸特性。其開關比較本發明之裝置低。 藉由對比利用實例2所述之EFIA方法製備之BG fet裝置 之傳輪特性與藉由LB技術沉積NW之TG FET之傳輸特性, 清晰可見利用EFIA方法獲得之裝置展現改良之性能。 【圖式簡單說明】 圖1示意性描繪本發明之底閘式FET裝置,其包含基板 (1) ’閘電極(2),介電層(3),源及汲電極(4),及包含藉由 如上下文所述之方法配向之奈米粒子之半導體層(5)。 圖2示意性描繪本發明之頂閘式FET裝置,其包含基板 (1) ’閘電極(2),介電層(3),源及汲電極(4),及包含藉由 如上下文所述之方法配向之奈米粒子之半導體層(5)。 圖3示意性描繪實例丨所使用之配向方法,其中將含有 N W之液滴(6 )置於一對電極(7 )之間之基板(丨)之頂部上。 圖4顯示藉由實例丨A之方法配向之奈米線之光學圖像。 於右手側顯示其中一個紹電極(7)。 圖5顯示藉由實例1B之方法配向之奈米線之光學圖像。 其描繪電極(7)及經沉積之奈米線(5)。 圖6顯示於一對電極(7)之間藉由實例丨c之方法配向之奈 米線之光學圖像。 圖7不思)·生地描繪實例2中所使用之配向方法。該圖顯示 &amp;額外層U閘電極、Si〇2介電層)覆蓋之基板⑴,於該基 板上形成之-對閉電極(4),一對柱電極⑺,連接至柱電 J48004.doc 201108311 Μ )之AC電源,及準備將奈米線分散液分配於電極⑺與 (4)之間之吸液管。妇 電極(7)係以閘電極(4)交匯處為中 〇 圖8顯示根據實例2剪供# a 士 I備之具有經配向奈米線之底閘式 、置之光學圖像。左側之梳狀電極交匯處之中心部分 以約倍放大顯示於右側。於放大圖中,彳見:: 米線橫跨電極之間之間I I二月冗奈 橫示根據實例2製得之底閘式阳裝置之傳輸特性。 下閘電壓(V) ’縱軸顯示汲極電流 3V下之測量值,下曲線表示1V下之測量值。曲線表不 圖=對照實例〗製傷之底閘式fet裝置之光學 結構)。 一’丁、木線(明亮 圖 1 1 §5 — 特性。Μ根據對照實例丨製備之底閘式FET裝置之傳輸 【主要元件符號說明】 1 基板 2 3 4 5 6 7 8 閘電極 介電層 源及汲電極 半導體層(圖1 NW液滴 輔助電極 AC電源 2) ; NW(圖 5) 148004.doc -32,Comparative Example 1: Preparation of a FET BG FET device using Ge NW aligned by LB (Langmuer Blodgett) technology was prepared as follows: The substrate system was the same as that described in Example 1, and was a Si〇2 dielectric layer. A bottom gate substrate having a patterned S/D electrode thereon. The substrates are cleaned as in the standard 矽 substrate cleaning method. A Ge Nw solution having a concentration of Oj mg/ml was prepared by using a chloroform solvent. Two to three drops of the solution are dropped onto the water in the beaker. After the solution droplet reaches the surface, the solvent evaporates rapidly, leaving the nanowire to form one or more layers of the layer on the water surface. The above substrate previously placed in the solution was slowly moved from the lower surface to the nanowire layer' and then removed from the water. The NW layer is attached and deposited on the substrate. Dry the bottom gate nanowire FET and wait for the test. 148004.doc •30- 201108311 Figure 10 shows an optical image of a Ge NW (deposited by LB method) on a 20 μιη S/D channel BG FET (on a Shih-hs substrate), and Figure 11 shows the transmission characteristics of the device. . Its switch is lower than the device of the present invention. By comparing the transfer characteristics of the BG fet device prepared by the EFIA method described in Example 2 with the transfer characteristics of the TG FET deposited by the LB technique, it is clear that the device obtained by the EFIA method exhibits improved performance. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 schematically depicts a bottom gate FET device of the present invention comprising a substrate (1) 'gate electrode (2), a dielectric layer (3), a source and a germanium electrode (4), and The semiconductor layer (5) of the nanoparticles is aligned by a method as described above and below. 2 schematically depicts a top gate FET device of the present invention comprising a substrate (1) 'gate electrode (2), a dielectric layer (3), a source and a drain electrode (4), and including by the context The method is to align the semiconductor layer of the nanoparticle (5). Fig. 3 schematically depicts an alignment method used in the example ,, in which a droplet (6) containing N W is placed on top of a substrate (丨) between a pair of electrodes (7). Figure 4 shows an optical image of a nanowire aligned by the method of Example A. One of the electrodes (7) is displayed on the right hand side. Figure 5 shows an optical image of the nanowires aligned by the method of Example 1B. It depicts the electrode (7) and the deposited nanowire (5). Figure 6 shows an optical image of a nanowire aligned between a pair of electrodes (7) by the method of Example c. Figure 7 is not a case). The method of aligning used in Example 2 is depicted. The figure shows a substrate (1) covered by an &amp; additional layer U gate electrode, Si〇2 dielectric layer, and a pair of column electrodes (7) formed on the substrate, and a pair of column electrodes (7) connected to the column J48004.doc 201108311 Μ) AC power supply, and a pipette ready to distribute the nanowire dispersion between the electrodes (7) and (4). The electrode (7) is centered at the intersection of the gate electrode (4). Figure 8 shows the optical image of the bottom gate with the aligned nanowire according to Example 2. The center portion of the intersection of the comb electrodes on the left side is shown on the right side in approximately magnification. In the enlarged view, see:: The rice ray spans between the electrodes. I I February. The transmission characteristics of the bottom gate type positive device made according to Example 2. The lower gate voltage (V) ’ vertical axis shows the measured value at the drain current of 3V, and the lower curve shows the measured value at 1V. The curve is not shown in Fig. = the comparative example of the optical structure of the bottom-fate device of the wound. A 'd, wood line (bright figure 1 1 § 5 - characteristics. Μ according to the comparative example 丨 prepared bottom gate FET device transmission [main symbol description] 1 substrate 2 3 4 5 6 7 8 gate electrode dielectric layer Source and germanium electrode semiconductor layers (Fig. 1 NW droplet auxiliary electrode AC power source 2); NW (Fig. 5) 148004.doc -32,

Claims (1)

201108311 七、申請專利範圍: 1. 一種配向導電或半導體奈米粒 驟: 《方去’其包含以下步 1) 將一對辅助電極置於一基板上, 2) 將導電或半導體奈米粒子 基H ㈣㈣辅助電極之間之 3) 對該對輔助電極施加電壓, 同時該視需要選用之步驟2及3可以相反 2. 如請求項丨之方法,其特 也 太丰妯, 你〜及寺奈未粒子係選自由 ;“棒、奈米管、奈米帶及/或其等組合組成之 3. =”丨或2之方法’其特徵在於該兩輔助電極之間之 距離係大於料所沉積之奈米粒子之縱向尺寸。 4. 2求項1或2之方法’其特徵在於該等奈米粒子包含選 =IV族半導體、ΠΙ-ν族半導體、ΐΜα族半導體、過渡 金屬、或上述者之合金或混合物組成之群之一或多種半 導體材料。 飞夕禋千 5. 如請求項1或2之方法,复特微力 将徵在於该荨奈米粒子係分散 於液體中。 6 ·如請求項1或2之方法,盆特 ,、特徵在於该兩輔助電極係於配 向完成後移除。 7. 如凊求項1或2之方法,盆姓他士 、 乃次其特徵在於該等奈米粒子係經配 向成與一或多個裝:f·雷#二1 ^•極而非該兩輔助電極接觸。 8. 一種藉由如請求項1至7中任-項之方法配向之奈米粒子 148004.doc 201108311 於電子、電光學、電致發光或光學裝置中作為電荷傳輸 或導電或半導體組件之用途。 1 9· 一種製備電子、電光學、電致發光或光學裝置之方法, 其包含以下步驟: 約將工作電極(4)施加於基板(1)上或介電層(3)上, b) 將一對辅助電極置於該基板(1)或該介電層(3)上,以 使其等不與該等工作電極(4)接觸, c) 將視需要分散於液體中之導電或半導體奈米粒子層 (5)&gt;儿積於該基板(1)或該介電層(3)及該等工作電極(4) 上,以使該等奈米粒子係位於該兩輔助電極之間, d) 對該兩輔助電極施加電壓, e) 視需要將該液體自該奈米粒子層(5)移除, 0視需要移除該兩辅助電極, g)視需要於該奈米粒子層上提供—或多個其他功能層, 其中可以不同次序實施步驟b)、c)、d)及f)。 10.如請求項9之方法, 久電極。201108311 VII. Patent application scope: 1. A kind of ortho-conducting or semiconductor nano-particles: "When going" includes the following steps: 1) A pair of auxiliary electrodes are placed on a substrate, 2) Conductive or semiconductor nanoparticle-based H (4) (4) 3) between the auxiliary electrodes, apply voltage to the pair of auxiliary electrodes, and the steps 2 and 3 may be reversed as needed. 2. If the method of requesting the item is too high, you and the a method selected from the group consisting of: "rods, nanotubes, nanoribbons, and/or combinations thereof, 3. "" or 2" characterized in that the distance between the two auxiliary electrodes is greater than the deposited The longitudinal dimension of the rice particles. 4. The method of claim 1 or 2 characterized in that the nanoparticles comprise a group consisting of a Group IV semiconductor, a ΠΙ-ν semiconductor, a ΐΜα semiconductor, a transition metal, or an alloy or mixture of the foregoing. One or more semiconductor materials. In the case of claim 1 or 2, the complex micro-force will be characterized in that the nano-particles are dispersed in the liquid. 6. The method of claim 1 or 2, wherein the two auxiliary electrodes are removed after the alignment is completed. 7. The method of claim 1 or 2, wherein the nano-particles are aligned with one or more devices: f·雷#二1•• pole instead of The two auxiliary electrodes are in contact. 8. Use of a nanoparticle 148004.doc 201108311 aligned by the method of any one of claims 1 to 7 as a charge transport or conductive or semiconductor component in an electronic, electrooptical, electroluminescent or optical device. A method of preparing an electronic, electro-optical, electroluminescent or optical device, comprising the steps of: applying a working electrode (4) to a substrate (1) or a dielectric layer (3), b) a pair of auxiliary electrodes are disposed on the substrate (1) or the dielectric layer (3) so as not to be in contact with the working electrodes (4), c) conductive or semiconductor neats to be dispersed in the liquid as needed a rice particle layer (5) is deposited on the substrate (1) or the dielectric layer (3) and the working electrodes (4) such that the nanoparticles are located between the auxiliary electrodes. d) applying a voltage to the two auxiliary electrodes, e) removing the liquid from the nanoparticle layer (5) as needed, 0 removing the auxiliary electrodes as needed, g) optionally on the nanoparticle layer Provided - or a plurality of other functional layers, wherein steps b), c), d) and f) can be implemented in a different order. 10. The method of claim 9, the permanent electrode. 如請求項9至11中任一項之方法製備。 其中該兩輔助電極係該基板上 其特徵在於其係藉由Prepared by the method of any one of claims 9 to 11. Wherein the two auxiliary electrodes are on the substrate, characterized in that they are 配向奈米粒子連接該等工作電極。 子及工作電極之電 其特徵在於該等經 14.如請求項12或13之裝置, 其特徵在於其係 一場效電晶 148004.doc 201108311 體,其包含 一基板(1), 一閘電極(2 ), 一介電層(3), 源及汲電極(4),及 一包含經配向奈米粒子之半導體層(5) 148004.docThe alignment nanoparticles are connected to the working electrodes. The device and the electrode of the working electrode are characterized by the device of claim 12 or 13, characterized in that it is a field effect transistor 148004.doc 201108311 body comprising a substrate (1), a gate electrode ( 2), a dielectric layer (3), a source and a germanium electrode (4), and a semiconductor layer comprising aligned nanoparticles (5) 148004.doc
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