201107979 六、發明說明： 【先前技術】 電子裝置通常具有可供其使用之某一類型之記憶體系 統，諸如一大容量儲存裝置。一常見實例係一硬碟驅動器 (HDD)。HDD能夠以相對低的成本實現大量儲存，其中當 刖消費者HDD可具有超過一太_位元組之容量。通常 在旋轉磁性媒體或磁帶上儲存資料。實際上，所得資料信 號其波峰及波谷係資料型樣之磁通量反向之一結一 比信號。 HDD因其機械性質而具有某些缺點。HDD因衝擊、振動 或強磁場而易遭受損壞或過度讀寫錯誤。另外，其係可攜 式電子裝置中相對大的功率使用|…大容量儲存裝置之 另-實例係-固態硬碟（S S D)。替代將資料儲存於旋轉媒 體上，SSD利用半導體記憶體裝置來儲存其資料，其通常 包含使其對其主機系統看起來仿佛其係—典型刪^之一入 面及形狀因數。SSD之記憶體裝置可包括非 ^ 憶體裝置。 门°己 【發明内容】 將阐通用於 仏7入示研·。在以下 閣述中’出於閣釋目的而閣明具有實例特有細節之眾多實 例以提供對實例性實施例之—理解。麸 ^ 夕貫 者將顯而易見，可在*具有此等實例特有^ ^ 項:: =具有不同於所給出組合之細節組合之情形下實踐該等 149414.doc 201107979 本文中所述之某些實例性實施例可包含監視 記憶體之間的一資料傳輸(例如，一資料寫入卜 ^傳輸規範並可提供—評估結果。可基於該評估結果來調 =將來資料傳輸。出於此文件之目I—資料傳輸規範 ⑽如)與(例如)資料傳輸之大小(例如，所傳輸位元組 之數目）、寫入放大值及寫入頻寬相關聯之—個或多個 值’如下文將更詳細地闡述。 【實施方式】 在隨附圖式之該等圖中以實例方式而非限制方式圖解說 明所揭示技術之某些實施例。 圖1係根據本發明之各種實施例圖解說明用於管理資料 寫入至-固態硬碟（SSD)11()之—系統⑽之—圖示。系統 100可包含與-記憶體存取裝置(諸如一處理器12〇)通信之 一 SSD 110。系統100可因其透過（例如）處理器12〇控制SSD ho之作業而被視為SSD 110之一主機系統。系統1〇〇可採 用一個或多個應用程式（主機應用程式）來存取SSD 110。 系統100之某些實例可包含個人電腦、膝上型電腦、個人 數位助理(PDA)、數位相機、電子遊戲機、數位媒體播放 器/記錄器及類似物。 處理器120可包括一磁碟驅動控制器或另一外部處理 器。處理器120可經由一通信匯流排丨3〇與SSD i丨〇通信。 通k匯流排130可採用一已知協定來將處理器12〇連接至 SSD 110。通k匯流排13〇之類型可相依於系統1〇〇中所利 用之驅動介面之類型。某些習用硬碟驅動介面匯流排協定 149414.doc 201107979 之實例為積體驅動電子器件（IDE)、先進技術附件（ΑΤΑ)、 串行ATA(S ΑΤΑ)、並行ΑΤΑ(ΡΑΤΑ)、光纖通道及小型電腦 系統介面（SCSI)。在此技術中存在且已知其他驅動介面。 SSD 110之記憶體裝置可包含非揮發性快閃記憶體裝置。 下文將給出如與資料寫入管理有關的SSD 110之特徵之一 更詳細闡述。 圖2係根據本發明之各種實施例圖解說明經組態以管理 資料寫入之SSD 110之一圖示。SSD 110可包含搞合至一介 面230之一控制器210，該介面允許經由通信匯流排丨3〇(圖 1)與一主機（例如，圖1之處理器120或一主機應用程式）之 通信。介面230可係熟習此項技術者通常所已知的許多連 接器中之一者。此等介面230連接器之某些實例可包含 IDE、增強型IDE、ATA、SATA、及個人電腦記憶體卡國 際協會（PCMCIA)連接器。 可將SSD 11 〇中之記憶體組織成各自包括一個或多個記 憶體裝置（諸如快閃記憶體裝置）之多個儲存單元22〇。可將 記憶體裝置中之記憶體位置分組成若干個區塊。在快閃記 憶體裝置中，具有128個千位元組（ΚΒ” 256 ΚΒ、5ΐ2 κβ 之儲存容量之區塊係常見的。主機可能不知曉哪些快閃記 憶體裝置當前正針對資料讀取/寫入作業而定址。換;^ 之，主機不知曉-實際資料傳輪（例如，讀取或寫入）中二 存取之任-實體區塊位址（ΡΒΑ) 4機僅處理被轉譯成一 脱之-邏輯區塊位址（LBA)。自LBa至ρΒΑ之此轉譯可 在SSD Η0接收到指定一邏輯位址之—資料傳輸請求之後 149414.doc 201107979 在S S D 110内發生〇 在快閃記憶體裝置中，在寫入新資料之前，抹除一記憶 體區塊u為新資料騰出$間。舉例而t，.當主機請求僅4 KB之一資料寫入時，將抹除一記憶體區塊（舉例，κΒ) 以容納該4KB之資料。若分配各自包括各自具有⑶⑶之 一儲存容量之若干個區塊之2個儲存單元來服務該請求， 則將抹除兩個區塊（一個來自該2個所分配之儲存單元中之 每一者）以容納該4 KB之資料。 抹除時間可構成減慢快閃記憶體裝置之存取時間中之一 主要因素。在習用記憶體裝置中，可有限次數地將資料寫 入至一快閃記憶體内之一記憶體位置。儘管可允許的寫入 數目頗大（通常10，100至100,000)，但反覆寫入至同一位置 亦可損耗彼位4。因此，要謹慎地跨越可用記憶體位置均 句地散佈資料寫人以使祕量均衡。損耗均衡被視為控制 益210(亦稱為SSD控制器）負貴管理之任務中之一者。 在資料被儲存於SSD 110中之多個位置中並使主機12〇看 不到的情形下’可實施大量操縱以寫入並自咖ιι〇操取 資料。隨著資料變得曰益被分成片斷，罝 有足夠大小以正 確地寫入資料的記憶體區塊可能變得稀 此日T，使用資 料回收（有時由熟習此項技術者稱為垃 μ队茱）程序來回收 記憶體區塊以允許至SDD U0之額外寫 貢枓在SSD 110 内之實體移動越頻繁，驅動器可因程式抹除循環而更快地 損耗。 在一實例性實施例中，當正服務—主拖·欠 主機身料傳輸請求 149414.doc 201107979 時’主機可指定將由控制器21()考量之—資料傳輸頻寬（例 如’諸如-最低可接受寫人頻寬之—寫人頻寬，或一讀取 頻寬）。術語「資料傳輸頻寬」應被視為包含每單位時間 傳輸之—貧料的數量，通常以千位元每秒（Kb/s)或百萬位 疋每秒（MWS)表*。可藉由分配更多儲存單元220來服務 一資料傳輸請求（例如，建立可具有用於服務該資料傳輸 。月求之一區塊之儲存單元之數目）來達成一較大資料傳輸 頻寬。 對控制器210有意義的另一變數係寫入放大（WA卜術語 「寫入放大」係指（例如）經分配以用於服務一資料寫入之 記憶體之大小與寫入至經分配以服務彼請求之記憶體之實 際資料之大小的比率。舉例而言，將4 KB之資料寫入至 SSD 110可導致控制器21〇藉助最低可用數目個儲存單元 (記憶體之一個儲存單元）服務一寫入作業，其可包含可儲 存（例如）128 KB之一區塊。在此情形下，儘管僅將構成寫 入請求之4 KB之實際資料寫入至彼區塊，但亦抹除一個經 分配儲存單元220之一 128 KB資料區塊中的記憶體位置。 此導致128/4(即，32)之一 WA，此可能不是期望的。 SSD 110在較低WA值情形下之運作可導致88〇 ι1〇中記 憶體裝置之一更有效使用。在較低WA值情形下之運作亦 可導致更均勻分佈之損耗均衡，但同時較低寫入頻寬。因 此，SSD Π0可面臨由主機指定之寫入頻寬與由資料寫入 產生之WA之間的一折衷。 SSD 110可經組態以解決此折衷問題。舉例而言，基於 149414.doc 201107979 下文中所闡述之實施例，SSD 110可藉由調整儲存單元22〇 之分配來採用控制器210解決該折衷問題。 圖3係根據本發明之各種實施例圖解說明用以管理資料 寫入之SSD控制器210之模組之一圖示。圖3中所示之 SSD控制器210可（例如）包括一個或多個微處理器。ssd控 制器210可包含一記憶體31〇、一監視模組32〇、一評估模 組330及-調整模組34〇。監視模組32〇、評估模組及調 整模組340可包括儲存於記憶體310或圖2中之儲存單元22〇 中之軟體模組。在-實例性實施例中，此等模組可實施為 SSD控制器210中之嵌入式硬體。 監視模組320可運作以監視一主機（例如，圖處理器 120或一主機應用程式）與一記憶體（諸如組織成圖2之儲存 單元220之記憶體）之間的一資料傳輸。舉例而言，監視模 組320可具有監視一資料傳輸之一個或多個特性之能力， 忒一個或多個特性諸如資料傳輸之大小（例如，所傳輸位 几組之數目）、寫入放大（與該資料傳輸相關聯之wa)及與 该資料傳輸相關聯之寫入頻寬（BW)。在實例性實施例中， 亦可監視其他特性，諸如回收頻寬（例如，針對垃圾收集 而保留之一處理器頻寬）及讀取頻寬。 監視模組320可儲存與記憶體31〇中之該（等）所監視特性 相關聯之一個或多個值。記憶體310可包含以一個或多個 、’且態暫存器形式使用之一靜態隨機存取記憶體（sram)。 在一實例性實施例中，監視模組320可將特性值儲存於組 織成圖2之儲存單元22〇之快閃記憶體裝置中。該等所儲存 149414.doc 201107979 之特性值可與主機相關聯。 在κ例性實施例中，評估模組330可包括一處理器（例 如，一微處理器）。纟某些實施财，監視模組32〇及/或調 • 整模組34G很可能亦包括相同處理器。評估模組則可運作 • 卩自記憶體31〇擷取在一時間週期内儲存之特性值。評估 模組330可至少部分地基於特性值來確定統計值。舉例而 言’評估模組330可確定在—時間週期内儲存之職或寫入 頻寬之一平均值。評估模組33〇亦可確定-時間週期内之 一記憶體請求大小之一平均值。 評估模組330可將該等特性值及/或該等統計值（在本文中 通稱及/或個別地稱為「資料傳輸規範」）中之一者或多者 與一個或多個目標值進行比較。評估模組33〇可（例如）將平 均魏與-目標·進行比較並將結果報告給調整模組 340。在一實例性實施例中’評估模組33〇可指示—特性值 (例如，WA)顯示勝於先前值之一改良。 調整模組340可實施一如下噹笪 統計值中之兩者或更多者之門 之間的關係之-個演算法，諸如 -周整、服務—將來資料傳輸之儲存單元之數目之一 演算法，如下文參考圖5更詳細地闡述。 如本技術所已知，可在SSD 21〇内實 組，而不背離本發明之範疇。然而，可在不呈5 :同模 模組之情形下理解本發明。 ”此等頜外 I工只w q S狂頁料寫入 SSD 110中所涉及之^ 181 之某些變數之-表_。表40”之該 149414.doc 201107979 變數係以KB表示之記憶體請求大小、WA及經分配以服務 -資料傳輸請求之儲存單元（即，Lu)之數目。行42〇列舉 由-主機做出之多個寫入請求之大小(例如，圖艸之處理 器120或-主機應用程式）。圖2中之控制器21〇可藉由為資 料寫入分配多個儲存單元來對每一請求做出回應。行 430 440 450及460分別表示與該等資料寫入請求相對應 之由2個、4個、6個及10個儲存單元（即，來自每2個、* 個、6個及切個1^11之一個區塊）之分配產生之WA值。在表 4〇〇中，假設每一儲存單元區塊具有128 ΚΒ之儲存容量。 亦可使用其他容量。表400中之資料亦表示於圖5中所示之 圖表中。 圖5係根據本發明之各種實施例圖解說明圖4中所示之表 400之變數之改變之一圖表5〇〇。圖表5〇〇顯示…八依據針對 經分配以服務該等資料寫入請求之儲存裝置之不同數目之 資料寫入請求大小之變化。曲線5 1〇、52〇、53〇及54〇中之 每一者之所分配儲存單元之對應數目係在該圖表之圖例中 顯不為LU=2、4、6及10。如圖表5〇〇所見，一般趨勢係隨 著所請求資料寫入之大小增加，WA減小。對於小的資料 寫入請求大小（例如，小於128 KB)，除分配一單個儲存單 元外（其中將來自一單個儲存單元之一單個區塊用於服務 該請求）’控制器210可能別無選項。然而，隨著所請求資 料寫入之大小的增加，控制器21〇可具有更多選項。 舉例而言’若一所請求資料寫入之大小等於5丨2 KB，則 圖2中之控制器210可分配4個儲存單元，在此情形下，寫 149414.doc -10- 201107979 入放大將達到一值1。若該控制器選擇為彼資料寫入請求 分配8個儲存單元’則其可達成一寫入放大2。在每一儲存 單元之128 KB之所假設儲存容量之情形下，顯示所期望 WA值1至2發生於大於128 KB之資料寫入請求大小處。 圖6係根據本發明之各種實施例圖解說明用於SSD資料 寫入管理之一演算法之實施方案之一狀態圖6〇〇。圖3中之 調整模組340可實施狀態圖600中所示之演算法。狀態圖 600顯示狀態之間的若干個狀態及轉變。該等狀態可由變 數（諸如與圖2之控制器21 0之資料寫入相關聯之寫入bw及 WA)界定至圖1之SSD 110。在所期望狀態610中，寫入頻 寬被視為大於B W0，且所期望寫入放大被視為小於WA1。 寫入頻寬BW0之下限或WA之一可接受範圍（例如，介於 WA 1與WA2之間）亦可由主機指定。舉例而言，該主機之 一使用者可指定一所期望寫入通量目標，諸如7〇%讀 取、30%之寫入及一 5〇〇 Mb/s之最小寫入BW。使用者可將 目標值儲存至SSD控制器21 0中（例如，儲存至圖3之記憶體 310中）。 在可接受狀態620中，寫入頻寬係大於BW0且WA係在一 可接受範圍内（例如’小於WA2且大於WA 1)。該演算法之 目的係進行所有其他狀態至所期望狀態6丨〇或可接受狀態 620之轉變。舉例而言’由圖3中之調整模組34〇考量之初 始狀態可被視為係一狀態630。在進入此狀態前，圖2中之 控制器210已藉由將圖1之SSD 11〇上之n0個儲存單元分配 至一資料寫入請求來服務一資料寫入請求。如圖3中之監 149414.doc 11 201107979 視模組320所監視，此分配之結果係小於BW〇之一寫入頻 寬，且WA小於WA1。基於此情形，調整模組34〇可調整該 情形。 調整模組340可嘗試藉由將更多儲存單元分配至該資料 寫入請求來調整該情形。此可致使至所期望狀態61〇、可 接爻狀態620或另一狀態（諸如狀態64〇)之一轉變。在狀態 640處，WA係在可接受範圍内，然❿，寫入頻寬係小於 BW0。為增加寫入頻寬，調整模組34〇可嘗試藉由分配仍 更多個儲存單元來補救該情形。分配更多個儲存單元可導 致進入所期望狀態610、可接受狀態62〇或狀態65〇。 狀態650看似分配多於一足夠數目個儲存單元之結果， 乃因當頻寬已增加至一可接受值時，…八在該可接受範圍 外。該情形可致使圖3中之調整模組34〇減小所分配之儲存 單元之數目，此又可導致進入所期望狀態61〇或可接受狀 態620中之任一者。此亦可導致進入可係不可接受之狀態 660，乃因寫入頻寬及寫入放大兩者皆不在狀態62〇所指定 之可接受範圍内。因此，自狀態660之下一轉變將係返回 至狀態650且針對欲分配之儲存單元之數目嘗試另一值（例 如’大於先前所嘗試之值）。 在實例性實施例中，在圖3之記憶體31〇之每一轉變後， 調整模組340可儲存轉變資訊，諸如對儲存單元之數目進 行的調整次數及所監視結果（例如，寫入BW及WA)。調整 模組340可藉由嘗試避免中間狀態及分別直接轉變至圖6中 之所期望或可接受狀態610及620來使用該轉變資訊改良其 149414.doc 12 201107979 效率。在其中不可能分別轉變至所期望或可接受狀態51〇 及520之情形下，調整模組340可嘗試將WA值降低至一甚 至更大範圍。 圖7係根據本發明之各種實施例圖解說明sSD資料寫入 管理之一方法700之一流程圖。在作業71〇處，圖3之監視 模組320可監視主機與一記憶體（諸如組織成圖iissD ιι〇 之儲存單元220之一記憶體）之間的—資料傳輸。監視模組 320可監視一時間週期内之資料傳輸。該時間週期相依於 與该資料傳輸相關聯之訊務量。在作業72〇處，圖3之評估 模組3 3 0可評估該資料傳輸以提供一評估結果。 該評估結果可包括包含_ WA、一 t料傳輸Bw、及/或 儲存單元之一數目之一特性值。在某些實例性實施例中， 該特性值亦可或另-選擇為包含1收頻寬及—讀取頻 寬。評估模組330可至少部分地基於一所監視特性值（諸如 该特性值之一平均值，例如一時間週期内之平均寫入放 大）來確定一統計值。 »平估模組330可提供—評估結果，該評估結果指示該等 ::值及/或該等統計值中之至少一者是否滿足由該主機 &疋之-個或多個目標值。在—決策區塊㈣處，若該評 估結果係令人滿意的’則將控制傳遞至作業71〇。否則， 在作業740處’圖3之調整模組34〇(例如)可用於基於該評估 結果來調整一資料傳輪之—姓# 、 寻％之特性。如上文所論述，該演算 法可由圖3之調整模组34〇眘 、40貫施。舉例而言，調整模組340 可運作以調整一特性，諸如宜 士寫入頻寬、寫入放大及儲存單 149414.doc •13· 201107979 元之數目。 >圖3之調整模組340可實施此作業。如上文所論述，調整 模且340可運作以基於該評估結果來改變一資料傳輸之一 個或夕個#性或保持該特性不冑。舉例而t，當經分配以 服務資料寫入請求之儲存單元之數目適當時（在所進入 狀態分別係所期望或可接受狀態61〇或62〇中之一者時確 定），調整模組340可保持所分配儲存單元之彼數目不變。 在其中刀配至該資料寫人請求之儲存單元之數目不適當之 情形下，舉例而言’如小於彼BW0之-寫入BW所指示， 調整模組340可藉由分配一較大數目個儲存單元以改良寫 入B W來補救該情形。 圖8係根據本發明之各種實施例圖解說明用於管理SSD 資料寫入之一實例性系統8〇〇之一圖示。系統8〇〇可包含一 處理器81 〇、一汜僥體820、一記憶體控制器830, 一圖形控 制器840以及一輸入及輸出（1/〇)控制器85〇、一顯示器 852、一鍵盤854、一指向裝置856及一週邊裝置858 〇 一匯 流排860將所有此等裝置耦合在一起。一時脈產生器87〇經 由匯流排860將一時脈信號提供至系統8〇〇之該等裝置中之 至少一者。時脈產生器87〇之一實例可包含諸如一母板之 一電路板中之一振盪器。系統800中所示之兩個或多個裝 置可形成於一單個晶片中。 記憶體820可包括靜態隨機存取記憶體（sram)、動態 RAM，或包含快閃記憶體之非揮發性記憶體。匯流排％^ 可係一電路板上之互連跡線或可係一個或多個電纜。匯流 149414.doc •14· 201107979 排860亦可藉由 合系統_之掌晋電磁輪射（例如無線電波）等無線手段叙 . 、置。週邊裝置858可包括一印表機、 驅動單元（例如，諸如P表機、一磁碟 之一光學裝置，諸知 及一卿讀取器/寫入器 如—軟碟驅動器之一磁性裝置靖® 寫入器），或諸如一夫古π 衮置嗔取益及 麥克風之一聲訊裝置^ 圖所表不之系统8⑽可包含電 膝上型電腦、手^带 果上$電腦、 等）'益線通腦、㈣器、Weblf具、路由器 器m 如’蜂巢式電話、無線電話、啤叫 盗、個人數位助理笙 丁 1 電腦相關週邊裝置（例如，印表 機知描儀、監視器等）、 電、立體聲系統、磁帶及Γ播放 電視機、無線 器、攝錄機、數位_ M 、磁帶錄影機/播放 5|/^if5§ P3(動畫專家群，音訊層3)播放 器“己錄益、視訊軸 '鐘銀等）及類似物。 在實例性實施例中’週邊 k遭裝置858可包含其上儲存有一 組或多組指令（例如，軟 换的π # ^ +t入 孕人體）之一機益可讀媒體，該一組或 多組指令體現本文中所關 斤闡述之方法或功能中之任一者或多 腦系統8〇0執行該等指令期間，該等指令亦可全 部或至少部分地駐存於記憶體82〇内及/或處理器81〇内， 其中，己憶體820及處理器8_構成機器可讀媒體。 “遠機，可讀媒體在一實例性實施例中顯示為一單個 媒體’但術語「機器可讀媒體」應視為包含儲存該一組或 多t指令之一單個媒體或多個媒體（例如，一集中式或分 佈式資料庫’及/或相關聯快取及飼服器）。術語「機器可 3賣媒體」亦應視為包含能夠儲存、編碼或栽送供由機器執 149414.doc 201107979 灯且致使機ϋ實施本發明之方法中之任—者或多者之一組 指令的任—媒體。術語「機器可讀媒體」應相應地視為包 含（但不限於）固態記憶體以及光學及磁性媒體。 /盡管已闡述了用於管理SSD資料寫入作業之具體方法及 系統’但顯而易見’可對該等實施例做出各種修改及改 變。因此’應將說明書及圖式視為僅具有說明性而非限制 性意義。 k供發明摘要以符合37 CFR κι 丁 口 HR. § 1.72(b)，此需要允許讀 者快速弄清該技純發明之性質之—摘要1述發明摘要 係在理解其不將用於解釋或限制巾請專利範圍之情形下提 交的。另夕卜在前述實施方式中可見，出於簡化本發明之 目的而將各種特徵集合於—單個實施例中。不應將本發明 之此方法解释為限制申請專利範圍。因此，藉此將以下申 請專利範圍併人至實施方式中，纟中每—請求項獨立地作 為一單獨實施例。 【圖式簡單說明】 圖1係根據本發明之各種實施例圖解說明用於管理資料 寫入至一固態硬碟（SSD)之一系統之一圖示； 圖2係根據本發明之各種實施例圖解說明經組態以管理 資料寫入之一 SSD之一圖示； 圖3係根據本發明之各種實施例圖解說明經組態以管理 資料寫入之一 SSD控制器之模組之一圖示； 圖4係根據本發明之各種實施例圖解說明管理資_胃^ 至一 SSD中所涉及之某些變數之列表之一表； 149414.doc •16· 201107979 圖5係根據本發明之各種實施例圖解說明圖*中所示 之該等變數之改變之一圖表； 之表 圖6係根據本發明之各種實施例圖解說明用於ssd資料 寫入管理之一演算法之實施方案之—狀態圖； 圖7係根據本發明之各種實施例圖解說明SSD資料寫入 管理之一方法之一流程圖；及 圖8係根據本發明之各種實施例圖解說明用於管理SSD 資料寫入之一實例性系統之一圖示。 【主要元件符號說明】 110 儲存裝置（SSD) 120 主機（處理器） 130 通信匯流排 210 控制器 220 儲存單元 230 介面 310 記憶體 320 監視模組 330 評估模組 340 調整模組 810 處理器 820 記憶體 830 記憶體控制器 840 圖形控制器 850 I/O控制器 149414.doc •1*7· 201107979 852 顯示器 854 鍵盤 856 指向裝置 858 週邊裝置 860 匯流排 870 時脈產生器 149414.doc - 18 -201107979 VI. Description of the Invention: [Prior Art] Electronic devices typically have a type of memory system available for their use, such as a large capacity storage device. A common example is a hard disk drive (HDD). HDDs enable mass storage at relatively low cost, where a consumer HDD can have more than one terabyte of capacity. Data is usually stored on rotating magnetic media or on tape. In fact, the obtained data signal has one of the peaks of the magnetic flux of the peak and trough data types. HDD has certain drawbacks due to its mechanical properties. HDDs are subject to damage or excessive read and write errors due to shock, vibration or strong magnetic fields. In addition, it is a relatively large power use in portable electronic devices |... another example of a mass storage device - a solid state hard disk (S S D). Instead of storing the data on a rotating medium, the SSD uses a semiconductor memory device to store its data, which typically includes what it appears to its host system as if it were a typical one. The memory device of the SSD may include a non-memory device. Door °self [Summary] The explanation is used for 仏7 into the research. In the following, a number of examples of specific details are given to provide an understanding of the exemplary embodiments. The bran will be obvious, and can be practiced in cases where * have such instance-specific ^ ^ items:: = have a different combination of combinations than the given combination. 149414.doc 201107979 Some examples described in this article An embodiment may include monitoring a data transfer between memory (eg, a data write specification and may provide - an evaluation result. The data transfer may be based on the evaluation result. For the purpose of this document) I - the data transmission specification (10), for example, and/or the value of the data transmission (eg, the number of transmitted bytes), the write amplification value, and the write bandwidth - as follows Explain in more detail. [Embodiment] Some embodiments of the disclosed technology are illustrated by way of example and not limitation in the drawings. 1 is a diagram illustrating a system (10) for managing data writes to a Solid State Drive (SSD) 11() in accordance with various embodiments of the present invention. System 100 can include an SSD 110 in communication with a memory access device, such as a processor 12A. System 100 can be considered a host system of SSD 110 for its operation of controlling SSD ho through, for example, processor 12 . The system 1 can access the SSD 110 using one or more applications (host applications). Some examples of system 100 may include personal computers, laptops, personal digital assistants (PDAs), digital cameras, electronic gaming machines, digital media players/recorders, and the like. Processor 120 can include a disk drive controller or another external processor. The processor 120 can communicate with the SSD i丨〇 via a communication bus. The k-bus bar 130 can employ a known protocol to connect the processor 12 to the SSD 110. The type of the bus bar 13 can depend on the type of drive interface used in the system. Some examples of conventional hard disk drive interface bus protocol 149414.doc 201107979 are integrated drive electronics (IDE), advanced technology accessories (ΑΤΑ), serial ATA (S ΑΤΑ), parallel ΑΤΑ (ΡΑΤΑ), Fibre Channel and Small computer system interface (SCSI). Other drive interfaces are present and known in the art. The memory device of SSD 110 can include a non-volatile flash memory device. A more detailed description of the features of the SSD 110 associated with data write management will be given below. 2 is a diagram illustrating one of SSDs 110 configured to manage data writes in accordance with various embodiments of the present invention. The SSD 110 can include a controller 210 that interfaces to an interface 230 that allows communication with a host (e.g., the processor 120 of FIG. 1 or a host application) via the communication bus 3 (FIG. 1). . Interface 230 can be one of many connectors commonly known to those skilled in the art. Some examples of such interface 230 connectors may include IDE, Enhanced IDE, ATA, SATA, and Personal Computer Memory Card International Association (PCMCIA) connectors. The memory in the SSD 11 can be organized into a plurality of storage units 22 each including one or more memory devices, such as flash memory devices. The memory locations in the memory device can be grouped into several blocks. In a flash memory device, a block having a storage capacity of 128 kilobytes (ΚΒ" 256 ΚΒ, 5 ΐ 2 κβ is common. The host may not know which flash memory devices are currently reading for data/ Write to the job and address. Change; ^, the host does not know - the actual data transfer (for example, read or write) in the second access - physical block address (ΡΒΑ) 4 machine only processed into one Off-Logic Block Address (LBA). This translation from LBa to ρΒΑ can be received in SSD Η0 after receiving a data address request - 149414.doc 201107979 occurs in SSD 110 flash memory In the device, before writing new data, erase a memory block u to make a new data for $. For example, t, when the host requests only one of the 4 KB data to be written, a memory will be erased. a block (for example, κΒ) to accommodate the 4 KB of data. If two storage units each including a plurality of blocks each having a storage capacity of (3)(3) are allocated to serve the request, the two blocks are erased ( One from the two allocated storage units One) to accommodate the 4 KB of data. The erase time can constitute one of the main factors in slowing down the access time of the flash memory device. In the conventional memory device, the data can be written to a limited number of times. One of the memory locations in the flash memory. Although the number of writes allowed is quite large (usually 10,100 to 100,000), writing to the same location repeatedly can also deplete the bit 4. Therefore, be careful to cross the available The memory location is uniformly distributed to write the person to balance the secret. Loss equalization is regarded as one of the tasks of controlling the benefit 210 (also known as SSD controller). The data is stored in the SSD 110. In the case of multiple locations and the host 12 is not visible, 'a large number of manipulations can be implemented to write and retrieve data from the coffee. As the data becomes beneficial, it is divided into pieces, and the size is correct enough. The memory block in which the data is written may become thinner on this day, using data recovery (sometimes referred to by those skilled in the art) to reclaim the memory block to allow for additional to SDD U0. Write the entity of Gongga in SSD 110 The more frequent the move, the faster the driver can be lost due to the program erase cycle. In an exemplary embodiment, when the service is being serviced - the main drag and owe the host body transfer request 149414.doc 201107979 'the host can be specified by the controller 21 () consideration - data transmission bandwidth (such as 'such as - the minimum acceptable write bandwidth - write bandwidth, or a read bandwidth". The term "data transmission bandwidth" should be considered to contain each The amount of poor material transferred per unit time, usually in kilobits per second (Kb/s) or millions of bits per second (MWS) table*. A data transfer request can be served by allocating more storage units 220. (For example, the establishment may have the data transmission for service. The number of storage units in a block is calculated monthly to achieve a large data transmission bandwidth. Another variable that is meaningful to the controller 210 is write amplification (WA terminology "write amplification" refers to, for example, the size of the memory allocated for servicing a data write and the write to the service for distribution. The ratio of the size of the actual data of the memory requested by the user. For example, writing 4 KB of data to the SSD 110 may cause the controller 21 to service one of the lowest available number of storage units (one storage unit of memory). A write job, which may contain one block of 128 KB, for example. In this case, although only the actual data of 4 KB constituting the write request is written to the block, one is erased. Allocating a memory location in one of the 128 KB data blocks of the storage unit 220. This results in one of 128/4 (i.e., 32) WA, which may not be desirable. Operation of the SSD 110 at lower WA values may result in One of the 88 〇ι1 memory devices is more efficient to use. Operation at lower WA values can also result in a more evenly distributed loss balance, but at the same time lower write bandwidth. Therefore, SSD Π0 can be faced by the host Specified write bandwidth and A compromise between the data writes to the generated WA. The SSD 110 can be configured to address this tradeoff problem. For example, based on the embodiment set forth below in 149414.doc 201107979, the SSD 110 can be adjusted by the storage unit 22 The distribution is used to solve the tradeoff problem with controller 210. Figure 3 is a diagram illustrating one of the modules of SSD controller 210 for managing data writes in accordance with various embodiments of the present invention. The SSD controller 210 can, for example, include one or more microprocessors. The ssd controller 210 can include a memory 31, a monitoring module 32, an evaluation module 330, and an adjustment module 34. The module 32, the evaluation module and the adjustment module 340 can include software modules stored in the memory 310 or the storage unit 22A of FIG. 2. In an exemplary embodiment, the modules can be implemented as Embedded hardware in the SSD controller 210. The monitoring module 320 is operable to monitor a host (eg, the graphics processor 120 or a host application) and a memory (such as the memory organized into the storage unit 220 of FIG. 2) Data transmission between the body) For example, the monitoring module 320 can have the ability to monitor one or more characteristics of a data transmission, such as the size of the data transmission (eg, the number of groups of transmitted bits), write amplification ( Wa) associated with the data transfer and the write bandwidth (BW) associated with the data transfer. In an exemplary embodiment, other characteristics, such as reclaimed bandwidth (eg, reserved for garbage collection), may also be monitored. One of the processor bandwidths) and the read bandwidth. The monitoring module 320 can store one or more values associated with the (or other) monitored characteristics in the memory 31. Memory 310 can include a static random access memory (sram) in the form of one or more, state registers. In an exemplary embodiment, the monitoring module 320 can store the characteristic values in a flash memory device organized into the storage unit 22 of FIG. The attribute values stored in 149414.doc 201107979 can be associated with the host. In an exemplary embodiment, evaluation module 330 can include a processor (e.g., a microprocessor). For some implementations, the monitoring module 32 and/or the tuning module 34G are likely to include the same processor as well. The evaluation module is operational. • The memory 31 captures the characteristic values stored over a period of time. The evaluation module 330 can determine the statistical value based at least in part on the characteristic values. For example, the evaluation module 330 can determine an average of one of the jobs or write bandwidths stored during the time period. The evaluation module 33 can also determine an average of one of the memory request sizes over a time period. The evaluation module 330 can perform one or more of the characteristic values and/or the statistical values (referred to herein and/or individually as "data transmission specifications") with one or more target values. Comparison. The evaluation module 33 can, for example, compare the average Wei to the - target and report the result to the adjustment module 340. In an exemplary embodiment, the evaluation module 33 may indicate that the characteristic value (e.g., WA) display is better than one of the previous values. The adjustment module 340 can implement a calculation of the relationship between the gates of two or more of the statistical values, such as - weekly, service - the number of storage units for future data transmission The method is explained in more detail below with reference to Figure 5. As is known in the art, it can be implemented within the SSD 21 without departing from the scope of the invention. However, the present invention can be understood without the 5: same mode module. "These jaws are only written into the SSD 110. Some of the variables of 181 are listed in Table _. Table 40" of the 149414.doc 201107979 variable is a memory request in KB. Size, WA, and the number of storage units (ie, Lu) that are assigned a service-data transfer request. Line 42 lists the size of multiple write requests made by the -host (e.g., processor 120 or host application). The controller 21 in Figure 2 can respond to each request by allocating a plurality of storage units for the data write. Lines 430 440 450 and 460 represent 2, 4, 6 and 10 storage units respectively corresponding to the data write requests (ie, from every 2, *, 6 and 1^) The WA value generated by the allocation of a block of 11). In Table 4, it is assumed that each storage unit block has a storage capacity of 128 。. Other capacities can also be used. The data in Table 400 is also shown in the chart shown in Figure 5. Figure 5 is a diagram 5 of one of the variations of the variables of the table 400 shown in Figure 4, in accordance with various embodiments of the present invention. Figure 5 〇〇 shows ... eight based on the change in the size of the write request for a different number of data allocated to the storage device that is requesting the data write request. The corresponding number of allocated storage units for each of the curves 5 1〇, 52〇, 53〇, and 54〇 is not LU=2, 4, 6, and 10 in the legend of the graph. As seen in Figure 5, the general trend is as the size of the requested data is increased and WA is reduced. For small data write request sizes (eg, less than 128 KB), in addition to allocating a single storage unit (where a single block from a single storage unit will be used to service the request) 'controller 210 may have no options . However, as the size of the requested data write increases, the controller 21 may have more options. For example, if the size of a requested data write is equal to 5 丨 2 KB, the controller 210 in FIG. 2 can allocate 4 storage units. In this case, write 149414.doc -10- 201107979 into the enlargement A value of 1 is reached. If the controller chooses to allocate 8 storage units for its data write request, it can achieve a write amplification of 2. In the case of a assumed storage capacity of 128 KB per storage unit, it is shown that the expected WA values of 1 to 2 occur at a data write request size greater than 128 KB. Figure 6 is a diagram of one state of an embodiment of an algorithm for SSD data write management in accordance with various embodiments of the present invention. The adjustment module 340 of FIG. 3 can implement the algorithm shown in the state diagram 600. State diagram 600 shows several states and transitions between states. These states may be defined to the SSD 110 of Figure 1 by variables such as writes bw and WA associated with the data write of the controller 210 of Figure 2. In the desired state 610, the write bandwidth is considered to be greater than B W0 and the desired write amplification is considered to be less than WA1. The lower limit of the write bandwidth BW0 or one of the WA acceptable ranges (eg, between WA 1 and WA2) may also be specified by the host. For example, a user of the host can specify a desired write flux target, such as 7〇% read, 30% write, and a minimum write BW of 5〇〇 Mb/s. The user can store the target value in the SSD controller 210 (e.g., stored in the memory 310 of Figure 3). In the acceptable state 620, the write bandwidth is greater than BW0 and the WA is within an acceptable range (e.g., ' less than WA2 and greater than WA1). The purpose of the algorithm is to perform a transition from all other states to a desired state 6 or acceptable state 620. For example, the initial state considered by the adjustment module 34 in FIG. 3 can be considered to be a state 630. Before entering this state, the controller 210 of Fig. 2 has served a data write request by allocating n0 storage units on the SSD 11 of Fig. 1 to a data write request. As shown in Figure 3, 149414.doc 11 201107979 The result of this allocation is less than one of the write bandwidths of BW〇, and WA is less than WA1, as monitored by module 320. Based on this situation, the adjustment module 34 can adjust the situation. Adjustment module 340 can attempt to adjust the situation by allocating more storage units to the data write request. This may cause a transition to one of the desired state 61 〇, the connectable state 620, or another state (such as state 64 〇). At state 640, the WA is within an acceptable range, and then the write bandwidth is less than BW0. To increase the write bandwidth, the adjustment module 34 can attempt to remedy the situation by allocating more storage units. Allocating more storage units may result in entering a desired state 610, an acceptable state 62, or a state 65 。. State 650 appears to distribute more than one sufficient number of storage units because when the bandwidth has increased to an acceptable value, ... eight is outside the acceptable range. This situation may cause the adjustment module 34 in Figure 3 to reduce the number of allocated storage units, which in turn may result in entering either the desired state 61 or the acceptable state 620. This can also result in an unacceptable state of entry 660, since both the write bandwidth and the write amplification are not within the acceptable range specified by state 62. Thus, a transition from state 660 will return to state 650 and another value (e.g., greater than the previously attempted value) is attempted for the number of storage units to be allocated. In an exemplary embodiment, after each transition of the memory 31 of FIG. 3, the adjustment module 340 can store transition information, such as the number of adjustments to the number of storage units and the monitored results (eg, writing BW) And WA). The adjustment module 340 can improve the efficiency of the 149414.doc 12 201107979 by attempting to avoid intermediate states and directly transitioning to the desired or acceptable states 610 and 620 of FIG. 6, respectively. In the event that it is not possible to transition to the desired or acceptable states 51 and 520, respectively, the adjustment module 340 may attempt to reduce the WA value to a much larger range. Figure 7 is a flow diagram of one method 700 of illustrating sSD data write management in accordance with various embodiments of the present invention. At job 71, the monitoring module 320 of Figure 3 can monitor the data transfer between the host and a memory, such as the memory of a storage unit 220 organized into a picture iissD. The monitoring module 320 can monitor the transmission of data over a period of time. This time period is dependent on the amount of traffic associated with the data transmission. At job 72, the evaluation module 320 of Figure 3 can evaluate the data transfer to provide an evaluation result. The evaluation result may include a characteristic value including one of _WA, a t-transport Bw, and/or one of the storage units. In some exemplary embodiments, the characteristic value may alternatively or additionally be selected to include 1 receive bandwidth and - read bandwidth. The evaluation module 330 can determine a statistical value based at least in part on a monitored characteristic value, such as an average of one of the characteristic values, such as an average write amplification over a period of time. The rating module 330 can provide an evaluation result indicating whether at least one of the :: values and/or the statistical values meets one or more target values by the host & At the decision block (4), if the result of the evaluation is satisfactory, control is passed to job 71. Otherwise, at job 740, the adjustment module 34 of FIG. 3, for example, can be used to adjust the characteristics of a data transfer wheel, last name #, and % based on the evaluation result. As discussed above, the algorithm can be implemented by the adjustment module 34 of Figure 3. For example, the adjustment module 340 can operate to adjust a characteristic such as the number of write bandwidths, write amplification, and storage sheets 149414.doc •13·201107979. > The adjustment module 340 of Figure 3 can perform this operation. As discussed above, the modulo mode 340 and 340 can operate to change one of the data transmissions or to maintain the characteristics based on the evaluation results. For example, t, when the number of storage units allocated for the service data write request is appropriate (determined when the entered state is one of the desired or acceptable states 61 or 62, respectively), the adjustment module 340 The number of allocated storage units can be kept constant. In the case where the number of storage units in which the knife is assigned to the data writer request is inappropriate, for example, as indicated by the write BW less than the BW0, the adjustment module 340 can allocate a larger number by The storage unit remedies the situation by improving the write BW. 8 is a diagram illustrating one example system 8 for managing SSD data writes in accordance with various embodiments of the present invention. The system 8A can include a processor 81, a body 820, a memory controller 830, a graphics controller 840, and an input and output (1/〇) controller 85A, a display 852, and a A keyboard 854, a pointing device 856, and a peripheral device 858, a bus bar 860, couple all of these devices together. A clock generator 87 provides at least one of the clock signals to the system 8 via the bus 860. An example of the clock generator 87 can include an oscillator such as one of the boards of a motherboard. Two or more of the devices shown in system 800 can be formed in a single wafer. Memory 820 can include static random access memory (sram), dynamic RAM, or non-volatile memory containing flash memory. The bus bar %^ can be an interconnect trace on a board or can be one or more cables. Confluence 149414.doc •14· 201107979 Row 860 can also be described by wireless means such as the palm of the system (such as radio waves). The peripheral device 858 can include a printer, a driving unit (for example, a magnetic device such as a P-table, a magnetic disk, a know-how and a reader/writer such as a floppy disk drive) ® Writer), or a system such as a Fu π 衮 嗔 及 及 及 麦克风 麦克风 麦克风 麦克风 麦克风 麦克风 麦克风 麦克风 麦克风 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Line Tongnao, (4), Weblf, router m such as 'cellular phone, wireless phone, beer pirate, personal digital assistant Kenting 1 computer-related peripheral devices (for example, printers, monitors, etc.), Electric, stereo system, tape and video playback TV, wireless, camcorder, digital _ M, tape recorder / playback 5 | / ^ if5 § P3 (animated expert group, audio layer 3) player "received , video axis 'clock silver, etc., and the like. In an exemplary embodiment, the 'peripheral device 858 can include one or more sets of instructions stored thereon (eg, soft-switched π #^ +t into the pregnant human body) One machine readable medium, the one or more sets of instructions are embodied in this article The instructions may also reside wholly or at least partially within the memory 82's and/or the processor 81 during execution of the instructions or any of the methods or functions illustrated by the system or the multi-brain system. Wherein, the memory 820 and the processor 8_ constitute a machine readable medium. "The remote, readable medium is shown as a single medium in an exemplary embodiment," but the term "machine readable medium" shall be considered A single medium or a plurality of media (eg, a centralized or distributed repository) and/or associated cache and feeders for storing one or more of the one or more instructions. The term "machine 3 selling media" shall also be taken to include a set of instructions capable of being stored, encoded or planted by the machine for the execution of the 149414.doc 201107979 lamp and causing the machine to implement the invention. Ren-media. The term "machine readable medium" shall accordingly be taken to include, without limitation, solid state memory as well as optical and magnetic media. / Although the specific methods and systems for managing SSD data writing operations have been described, it is obvious that various modifications and changes can be made to the embodiments. Therefore, the specification and drawings are to be regarded as illustrative only and not limiting. k for the abstract of the invention to comply with 37 CFR κι □ HR. § 1.72(b), this requirement is to allow the reader to quickly ascertain the nature of the invention. The summary of the invention is not understood to be construed or limited. The towel is submitted under the circumstances of the patent. Further, in the foregoing embodiments, various features are grouped together in a single embodiment for the purpose of simplifying the invention. This method of the invention should not be construed as limiting the scope of the patent application. Therefore, the scope of the following patent application is hereby incorporated by reference in its entirety to the extent that the claims are individually and individually BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating one of systems for managing data writing to a solid state drive (SSD) in accordance with various embodiments of the present invention; FIG. 2 is a diagram of various embodiments in accordance with the present invention. An illustration of one of the SSDs configured to manage data writes is illustrated; FIG. 3 is a diagram illustrating one of the modules configured to manage data writes to an SSD controller in accordance with various embodiments of the present invention. Figure 4 is a table illustrating a list of certain variables involved in managing a resource to an SSD in accordance with various embodiments of the present invention; 149414.doc • 16· 201107979 Figure 5 is a representation of various implementations in accordance with the present invention A diagram illustrating one of the changes in the variables shown in FIG. *; FIG. 6 is a diagram illustrating an embodiment of an algorithm for ssd data write management in accordance with various embodiments of the present invention. Figure 7 is a flow diagram illustrating one of the methods of SSD data write management in accordance with various embodiments of the present invention; and Figure 8 illustrates an example of managing SSD data writes in accordance with various embodiments of the present invention. Systematic An illustration. [Main component symbol description] 110 Storage device (SSD) 120 Host (processor) 130 Communication bus 210 Controller 220 Storage unit 230 Interface 310 Memory 320 Monitoring module 330 Evaluation module 340 Adjustment module 810 Processor 820 Memory Body 830 Memory Controller 840 Graphics Controller 850 I/O Controller 149414.doc • 1*7· 201107979 852 Display 854 Keyboard 856 Pointing Device 858 Peripheral Device 860 Bus Bar 870 Clock Generator 149414.doc - 18 -