TW200823667A - Single-serial-port-to-multiple-parallel-port high-speed data transmission device with SATA interface - Google Patents

Abstract

The present invention relates to a single-serial-port-to-multiple-parallel-port high-speed data transmission device with SATA interface. The present invention comprises a SATA interface controller, parallel port interface controllers and flash memories. The SATA interface controller controls a plurality of parallel port interface controllers, in which each parallel port interface controller corresponds to at least one flash memory. Therefore, when a predetermined host issues a command, the command can be transmitted to the SATA interface controller via a serial bus connection port. Then, the command controls and dispenses data into a plurality of parallel port interface controllers connected with the SATA interface controller, and performs control to the flash memories correspondingly connected with the parallel port interface controllers. As a result, if the serial bus connection port has enough band width, an overall data transmission speed can be multiplied.

Description

200823667 IX. Description of the Invention: [Technical Field] The present invention provides a single-column-to-multiple parallel 珲-speed data transmission device with an SAΤA interface, especially a Wei s Ατ A interface controller for controlling a complex number (4) Remember, the transmission device does not have to reduce the speed due to the faster transmission speed of the flash memory. Furthermore, the sA interface controller is used to control the number of flash memory, which will enable the money to be stored at the same time. #取—一—一社快快记赖' thus the material _ overall performance [previous technology], according to the recent advancement of the S material solution (four) (four) transmission technology, thus developing such as USB 2 · 〇, IEEE 1 394, IDE Ui tra DMA mQde • The emergence of the high-speed interface of the section of the company's (four) transmission speed has been greatly improved, but unfortunately, the data transmission speed of the flash memory class storage components is close to the money, and far below the high speed The serial transmission speed of the serial and the parallel, and = (a) and IEE (1) is difficult, the definition of the data two (10) (10) ^ delete (10) ^ ^ parallel interface: then ha DMA mGde as an example, its silk = rate up to 133MB /S, again, the market is more The transmission speed is sata&Sata I with the transmission interface. The transmission speed can be as high as _川150 ΜΒρ^ and 5 200823667 3 G bps (3(10) ps), but the flash memory storage component is limited by its Physical hiding _ system, the current average transmission speed of up to 5mb

/s or so, so the data transmission speed has a bottleneck here, in order to solve the problem of poor transmission speed of the flash memory_memory component interface, and improve the overall performance of the product for the factory to guess the product _ re-transfer problem; for example, need to have High-speed data transmission Wei's flash drive, MP 3, PD a (personal digital assistant), Pocket PC (σ bag type personal _) machine. Furthermore, in the current data transmission and storage device, it is connected to a computer high-speed serial port (such as USB2 port), (4) __, please refer to the figure - shown as a conventional storage device and personal computer. The block diagram of the connection is as follows: the whole is a string of downstream devices of the device_埠B connected to the high-speed serial bus bar connection A1 of the personal computer A, and the tribute is transferred to the flash memory via the USB 2·0 interface. The body interface controller c, and stored in the flash memory D's miscellaneous USB2. ◦ is a high-speed serial port, but when the data is stored in pure flash memory _, it is expected to be in a busy state of flash memory 8 The swaying of the wheel, the real New Zealand to play the high-speed tandem ship, _, if the lack of good use of the lack of wealth, it is the direction of the industry to pursue improvement. Therefore, the above-mentioned deficiencies in the conventional technology have made it necessary for the people in this industry to improve their problems. SUMMARY OF THE INVENTION Nowadays, the inventors have succeeded in developing and designing a kind of experience and experience of the industry through continuous improvement and experimentation, in view of the fact that the above-mentioned conventional technology cannot realize the lack and deficiency of high-speed serial efficiency. The invention of the new high-speed data transmission device with single-column and multi-parallel connection of the SA interface has been extended to increase the user's convenience in operation. The main purpose of the present invention is to provide a high-speed "(4) transmission device with a SATA interface, a high-speed data transmission device, a SATA interface controller, a parallel interface controller, and a flash memory. In particular, a flash memory is used in conjunction with a parallel interface control state and a SATA interface controller to control the allocation. Therefore, when the storage is stored in the storage and storage data, as long as the interface is controlled to have sufficient bandwidth, It can increase the speed at which the host writes data to the flash memory, and can increase the overall data transmission speed by several times. Therefore, the high-speed data transmission device is no longer limited by the fast flash memory and the high speed. (4) The problem of misunderstanding. The secondary object of the present invention is to connect the second-time flash memory through the s A τ A interface controller and form a surface flash memory, and when the flash memory is read, written or backed up, Do a simple cut without complicated algorithms to calculate the address to be written, so you can easily rely on the flash memory __, Ke f to write a complex calculation 7 200823667 method is applied This kind of single string is more effective than the side effect. [Embodiment] In order to achieve the above object and structure, and in order to enable the member to have a further understanding of the object and the present invention, the technical means of the present invention is preferred. The embodiment is described in detail below, and the profit is fully understood. 70. Referring to the second figure, it is a schematic diagram of a high-speed data transmission device with a single-column-to-multiple parallel SAT of the SAT^ surface of the present invention. It can be clearly seen from the figure that the present invention provides Connected to the high-speed serial interface device and specially connected to the high-speed serial bus connection bee 11 connected to the host end, and the data is transmitted to the SATA interface controller 2 via the string ship connection 埠 ii and control distribution Data to a plurality of parallel interface control benefits 3, and then according to the flash memory 4 connected to the interface controller 3 for data age, Wei or command τ; domain, that is, the storage device through The transmission of this hair is not necessary to reduce the speed of the physical characteristics of the memory 4 to read the data in the flash memory 4 or read from the flash memory 4, and then The frequency of the bus bar connection 璋11 is sufficient enough to increase the overall data transmission speed for each additional side-by-side itch interface controller 3. 〈 However, please refer to the third figure. The difference between this figure and the second figure is that the / S A ΤΑ interface controller 2 can be directly connected to the flash memory 4 8 200823667

And when the data or the command is transmitted to the sA D interface controller 2 via the serial bus connection, the SATA interface controller 2 can store the data with the corresponding connected flash memory 4, Read or release of the command. Please refer to the fourth figure, which is a flow chart of the high-speed data transmission of the SAT^ surface of the SAT^ surface. It can be clearly seen from the figure. The loading step of the material system is performed: (10 0) starts; (101) the state of the flash memory 4 is read by the host terminal 1 or the temporary storage value of the state is changed; (1 0 2 ) 〇, if it is not 0, execute (1 0 i ); 0 3 ) Command parameters specified by the main 1 writer to function (F eatures), block count (sect 〇: C 0 unt), number of blocks ( Sector

Numb e r), magnetic column high position (

Cyiinder tiigh), magnetic column low-order element (C y I . 1 n d e r L ow) and device (

DeVi ce) or header (Tad); 4) Snapshot command and logical block address (LBA) for processing flash memory 4 through SATA interface; 5) H2 receive flash via SAT interface Memory 4 of 9 200823667 Data to SATA interface controller 2 buffer (

Buffer); (1〇6) confirm whether the buffer is full, if not, then • v 1 〇5), (1〇7) transfer the buffer data to the host end; (1〇8) confirm whether there is Other #料, if yes, ▲) . u〇5 • The factory (10 9) ends.

Referring to the fifth figure, it is a readout flow chart of the high-speed data transmission device with the SAT serial-to-multiple parallel port of the present invention, and it can be clearly seen that the invention is based on the following steps. (Fig. (2 0 〇) starts; (2 〇1) reads the status of the flash memory 4 or the temporary value of the state by the host terminal 1; (20 2) whether the working flag is 〇1 or not 〇, execute); U 1 (2 0 3) Host 1 writes the specified instruction parameters to function (F eatures), block count (sect 〇r U nt), block number (sector

Number, e r), magnetic column to bit (

Cyiinder High), magnetic column low position ( 200823667

Cylinder Low) and the device (D evice ) or header (H ead) register; (2 0 4) through the s ATA interface controller 2 to receive the data of the host 1 to the buffer of the SATA interface controller 2; 1 〇 5 ) Confirm that the buffer is full, if not, execute (2.0 4)

(1 〇 6) through the SATA interface controller 2 to process the read command of the flash memory 4 and the logical block address (L ba); (2 〇 7) transfer the buffer data to the flash memory 4; (2 〇8) Confirm whether the transmission is completed. If not, execute (2 0 7); (2 0 9 ) to confirm whether there is any other data to be written, and if so, execute (2 0 4); (11〇) . The series::::1=is shown as the flow chart of the transmission instruction of the data transmission device in the S ATA plane of the invention, and the following steps are carried out: 1 The temporary value of the status state of the flash memory is read by the host terminal; the ruler is eight 11 1 and the flag is Q, if not 0, the execution is performed (3 0 1 200823667 (3 0 3 ) host side 1 Write the specified command parameters to function (F eatures), block count (sect 〇r C ount), block number (sector N umber), cylinder high position (Cylinder High), magnetic column low position (Cylinder Low) and shock (

D evice ) or a header (head); (3 0 4) The SATA interface controller 2 can perform state setting or state reading processing on the flash memory 4 according to instructions of the host terminal; (3 0 5 ) The status of the flash memory 4 is read by the host terminal 1 or the temporary value of the state is changed; μ ); (3 〇 7) ends. However, (4) SATA interface is deleted 2 is a flash memory 4 that can control one or more flash memories 4, so the P+ of the trajectory ~ 転, the Wei __ SA TA interface The test SA, the form of multiple fast-acting bodies 4 should be subject to this creation. ΤΑ 秘 秘 2 2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ For one interface, it can also be: / EEE 1 3 9 4 series bus bar connection; in addition, the above flash memory 4 can be a flash drive, SD (Secure

Digital Memory CarcO M CSma r t Media Ca " S (10)_ry Stl / 2) memory card, HMct...C ::d) memory card, XD (

Lard), MSpR〇 (

Memory Stirir ^ ^ ^ , 1 Ck pR〇), MMC ( MUl t 1C...), "SD memory card, miniSD memory card or SATA memory hard disk and other forms of memory card's simple modification and equivalent structural changes The patent is fine. It should also be included in this creation. In addition, the above-mentioned counter 4 can be directly and electrically connected to the parallel interface controller 3 or the interface controller 2, thereby forming a storage device, and f is an independent external connection. The form is such that the patent pillow of the present invention is limited to Chen Ming. However, 'Please refer to the seventh figure _, which is a block diagram of the invention using a single memory. The lang ΑΤΑ fine control (5) is only connected with the - (4) memory 4, when (4) wants to write the human flash memory by the host end 1 4:13 200823667, the data is written into the flash memory 4 in different blocks (S ect 〇r ), however, as shown in the eighth figure, the invention uses two flash § The block diagram of the memory, when the data is to be written by the host terminal 1 to the two flash memory 4A and 4 B respectively, the flash memory 4a and 4 B data blocks are divided into a product number and an even number, so The written data can be written in the flash memory 4A and 4B according to the block to which it belongs; further, please refer to the ninth φ figure, which is the block of the invention using four flash memories. Schematic diagram, when the data is to be written into the four flash memory 4a, 4b, 4C and 4D by the host terminal, the data blocks of the flash memory 4A, 4B, 4〇 and 4〇 are divided into 4 Multiples, so the data to be written can be written to the flash memory 4 4A, 4B, 4C and 4D according to the block to which they belong. It is based on the fact that the present invention has the following advantages in comparison with the conventional technology. (-) The present invention controls a plurality of quick-hearted (four) memory layers 4 through the SA τ A interface controller 2, because the lining has a higher bandwidth. The interface is faster than the flash memory 4 because of the speed at which the item is written or written. Therefore, by combining the majority of the flash memory 4 in such a single series, the combination of the majority of the flash memory 4 will be possible. The SATA interface has the advantages of high frequency width and high read/write speed, so that the flash memory 4 can be used to accelerate the reading, writing or backup of the data. The SATA interface controller 2 controls a plurality of flash memories. Body 4 'Whether it is _ _ yan 4 manufacturer, software industry 妓 phase 200823667 Guanye can use the SATA interface controller 2 to complete the flash memory 4 data management, so the phase can be on the flash memory 4 management development cost. (3) When the present invention is connected to the flash memory 4 of the second power through the SATA interface controller 2 and constitutes a disk array, the read/write or backup of the flash memory 4 At the time, because the data can be made - simple cutting The required algorithm is used to calculate the bite to read the address, so it is easy to apply the flash memory 4 to the disk_ without having to write a complicated algorithm to apply to the single string. However, the above disclosure is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent of the present invention. Therefore, the use of the patent model of the sample is used. The invention is included in the scope of the patents covered by the present invention. In summary, the south speed data transmission device of the single serial train and multi-parallel 具 with SATA interface of the present invention can achieve its efficacy and purpose, so the present invention Sincerely - the invention of excellent secrets, in order to meet the requirements of the invention patents, in line with the money, new brewing and progressive, New Zealand proposed Shen 'green, hope that the trial committee will grant this case as soon as possible to protect the inventor's hard work. Invented, if there is any inspection of the singularity, please do not show it purely, the inventor will try his best to match the 5' sensation. 200823667 [Simplified explanation] The first picture is the storage device and personal intention of the conventional technology. Computer connection The second diagram is a schematic diagram of a high-speed data transmission device with a single-serial-to-multiple parallel port of the SATA interface of the present invention.

The third drawing is a block diagram of another preferred embodiment of the invention. The fourth figure is a flow chart of the single-column-to-multiple parallel _ high-speed data transmission device with the SATA interface of the present invention. The fifth figure is a flow chart for reading out the single-column-to-multi-parallel high-speed transmission t-station of the SATA interface of the present invention. The sixth figure is a transmission age flow chart of the high-speed dragon transmission device of the single-serial-to-multi-parallel SATA interface of the present invention.

The seventh figure is a block diagram of the present invention using a single flash memory. The figure is a block diagram of the use of two flash memories for this meal. The ninth figure is a block diagram showing the use of four flash memories in the present invention. [Main component description] 1. Host end 1 1 , Serial bus connection 埠 16 200823667 2, SATA interface controller 3, parallel interface controller 4, flash memory 4 A, flash memory 4 C , flash memory 4 B, flash memory 4 D, flash memory A, computer A 1, serial bus bar connection 埠 B, tandem bus bar connection 埠 C, flash memory interface controller D, Flash memory 17

Claims (1)

200823667 X. Patent application scope: 1 =/, = single interface of the interface, high-speed data transmission of multiple parallels, 'one or more devices' including SATA interface control and - a series of interface control , in which the pre-a and host-side serial bus connections are connected to the 5 ur SATA interface controller, and • ̄H or more than one parallel interface controller can be connected with the SATA interface controller Electrically connected' and the parallel interface controller can be separately connected to one: more than one flash memory is electrically connected; by the way, when the preset host end gives an instruction, the instruction continues The serial port, the port connection is transmitted to the SATM_ controller, and the control data is distributed to kill a number of parallel interface controllers connected with the SAT^ face control (4), and then the flash memory card for the parallel connection control connection is performed. control. • 2) The high-speed material transmission device with the SATA interface of the SATA interface as described in the first paragraph of the patent application, wherein the preset host-side command to control the s A ΤΑ interface can be data Setting/reading of the read/write person or flash memory status. 3. For the high-speed (four) service device with the SATA interface and the multi-parallel connection as described in item i of the patent scope, the ATAy^ controller can control one parallel side-by-side interface controller. 4. If the application of the patent range χ 之 具 τ 之 之 之 转 多 多 多 多 多 多 多 多 多 多 多 ' ' ' 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Memory. 5. If the high-speed data transmission device with the SA Τ A interface of the SA Τ A interface as described in the first paragraph of the patent application is applied, the SATA interface controller can write the data to the _ memory. The human dragon is cut and written into the corresponding flash memory. 6. Single-row bee turn with s A τ A interface as described in the application for patent lang i At the same time, the A-speed data of the side-by-side 置 is set, and the _ memory can be built in the transmission device. 7. A high-speed data transmission device with a single-column-to-multiple parallel port of the s Aτ eight interface as described in the scope of the patent application, wherein the smear can be externally connected to the transmission device. 8. A high-speed data transmission device with a SATA interface of a single serial-to-multiple parallel port as described in claim i, wherein the SATA interface controller can be set directly or through a preset domain material. The serial bus connection port. 9, such as the cap patent Gu Di i s A τ A interface of the single string 淳 多 multi-parallel 埠 high-speed # _ fresh, the injection downstream row 珲 can be a USB interface or iEEEl394 interface. Body, SD memory card, SM memory card, MS memory card, XD card 19 200823667 SPR〇, MMC memory card, MSD memory card,...n丨SD memory card or SATA memory hard disk flash memory. 1 1. A single-line, multi-parallel, high-speed data transmission device with a SATA interface, including a SAT^_ controller, wherein: the SATA interface controller can be connected to a preset bus terminal. The connection and connection of the SATA interface controller are respectively electrically connected to one or more flash memories; by the way, when the preset host end issues an instruction, the instruction is connected through the serial bus珲 Transfer to the sΑτA interface controller, and control through the sA A interface control and the corresponding connected flash memory. 12. The high-speed data transmission device of the single-serial-to-multiple parallel port with the sΑΤΑ interface as described in the scope of the patent scope ii, wherein the preset host-side command to the SAT system can be Read/write of data or setting/reading of flash memory status. 1 3. A high-speed data transmission device with a sATA interface and a single-serial-to-multiple parallel port as described in the i-th aspect of the patent scope, wherein the SATa interface controller can control two flash memorys of the second power . 14. A high-speed data transmission device with a sata interface as described in the patent application 帛n item, wherein the SATa interface controller can write when writing data to the flash memory. The entered data is cut into the corresponding flash memory. 20 200823667 15. A high-speed data transmission device with a SATA interface of a single serial-to-multiple parallel port as described in the above-mentioned patent scope, wherein the flash memory can be built in the transmission device. 16. A high-speed data transmission device with a SATA interface and a multi-parallel parallel port as described in the patent scope, wherein the flash memory can be externally connected to the transmission device. Lu 17, such as the single-column 2-to-multi-speed high-speed transmission device with SATA interface as described in the patent scope, the SATA interface controller can be connected to the preset host directly or through a transmission line. The serial bus connection port set in . 18. The high-speed transmission device of the single-column 埠 多 多 并 多 或 或 或 或 或 或 或 或 或 或 或 或 或 或 或 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 高速 高速 高速 高速 高速 高速 高速 高速 高速 高速 高速 高速 高速 高速 高速• 19. The high-speed data transmission device of the single-column bee-to-multiple parallel port with the s A τ A interface as described in the patent application scope!i, wherein the flash memory can be a flash drive, an SD memory card, S·Resume card, Ms memory card, χ〇111 1 ni SD memory card or SATA memory hard disk flash memory. twenty one