201107977 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種重置電路，且特別是有關於一種 可避免電子裝置中之快閃記憶體資料流失之重置電路。 【先前技術】201107977 VI. Description of the Invention: [Technical Field] The present invention relates to a reset circuit, and more particularly to a reset circuit that can avoid loss of flash memory data in an electronic device. [Prior Art]
一般電腦皆有設置重置開關或重置按鍵，用來進行系 、·先的查置，當電細當機或發生錯誤時，使用者可按下重置 開關來使系統重新開機以恢復正常狀態。 然而 糸、'死甲的快閃記憶體通常必須以區塊方式進行 寫入所以在快閃§己憶體正在進行寫入資料的同時，若使 用者按下重置開關，則目前正在進行寫人的資料會因為系 統重置而流失。為解決上關題，目翁採㈣方式有下 列成種.⑴將重置彳§號導d統中，然後再由系、统來控制 重置的時間，此方式是直翻料、統本身的倾撰寫，系 統判定重置按鍵是否有動作，並執行使用者的需求。利用 軟體控制可以輕易達到使用者的需求，但如果系統本已經 當機’則會造成重置按鍵也跟著失效。⑺増加重置尊語在 機器或說明書上告知使用者，重置後可能產生祕險以規 避相關責任’同時教導使用者必須時常進行資料備份處 理’此方式雖可避免責任流失的責任’但卻會誠使用者 的使用負擔，責任轉嫁使用者。 (3)當在進行f料讀取時，㈣、统失能4置按鍵，此方 式需要外加—些電路來達成重置失能的效果，系統只要不 201107977 是在資料寫入時當機，都可以讓使用者自由的進行重置， 所以大大的降低因系統當機無法重置的機會，但是還是有 機會造成重置失效’且失能重置時也是要告知使用者疋避 免使用者認為重置是無效的。（4)使用可程式邏輯積體電路 來達成此目的’但價格較高’且需要再耗費人力開發，電 路也不是純硬體設計。（5)不于理會，如設計的產品較為低 階或無重要資料可以保存’不予以理會資料是否有丟失， 這樣的做法價格最便宜，但使用者對產品與廠牌觀感會較 差。 【發明内容】 本發明提供一種重置電路’會將重置信號延遲一段時 間後再進行重置，並利用此延遲的時間完成快閃記憶體的 資料存取程序，避免因系統重置而造成資料流失的問題。 承上述，本發明提出一種重置電路，適用一電子裝 置，上述電子裝置具有一快閃記憶體，上述重置電路包括 一重置開關、一重置信號產生單元、一延遲單元、.一處理 單元。其中，重置開關用以重置上述電子裝置；重置信號 產生單元耦接於重置開關’當重置開關致能時產生第一重 置信號。延遲單元耦接於重置信號產生單元，用以延遲第 一重置信號一預設時間以產生一第二重置信號。處理單元 耦接重置信號產生單元、延遲單元與快閃記憶體之間。當 第一重置信號致能時，處理單元根據第一重置信號偵測快 閃記憶體是否正在進行寫入程序。若快閃記憶體正在進行 201107977 5之寫:處Γ早凡在預設時間中完成或終結快閃記憶 = 據第二重置信號進行系統重置。 -電壓源:―第—::种:士逑重置信信號產生單元包括 一™〇s電晶體Λ一電阻、一第—NPN電晶體、 垃於μ、+、去 弟二電阻以及—第二電容。電壓源耦 W的-端’·第―電容祕於上述重置開 關的：C之間；第—電_接於上述重置 與—第二電阻之間，上述第二電阻的另 述第-電阻與上述第一二曰，的基極耦接於上 曰曰體的射軸接於上述接地端；: 耦接上述第一ΝΡΝ電曰轉 、日日脰的閘極 汲極輪於上述電壓源，2、才、^，上述PM0S電晶體的 述第一重置传號M0S電晶體的源極輸出上 晶體:;極之；Γί且搞二:上糊源與上魂 晶體的源極與上述接地』之;:電谷轉接於上述PMOS電 在本發明一實施例中， 阻、一重置積體電路、—第五雷阳遲單元包括一第四電 阻與-第三電容串聯轉接於上第六電阻。第四電 之間；上述重置積體電路的重置信號與一接地螭 信號，上述重置積體電路的—輸=輪接於上述第-重t 與上述第三電容的共用節點，耦接於上述第四電陡 上述第一重置信號並於上述重置置積體電路用以延遲 出延遲後之上述第一重置信=體電路的上述輸出端％ “儿。弟五電阻輕接於上述第四 201107977 述第三電容的共用節點與-第二顧電晶體的 土 a，上述第二ΝΡΝ電晶體的射極耦接姑、 端；第六電阻触爾砂上接地 重置信號/、中上述弟二㈣電晶體的集極輸出上述第二 〜其中上述延遲單元更包括一第四電容盥— ΐ置Γ電容軸接於上述延遲單元，上】 上=::;rf容與上述第五電容之電容值決定 τΐΐπ—實施财，上述電子裝置為電腦、筆記型 述快閃記憶體為反及閘快閃記憶體（Ν屢 置方ί另上度來看’本發明另提出-種電子裝置的重 重置Ϊ法^ 置具有—邮記憶體與—重置開關， 第下列m先’ #重置開關致能時產生一 置:f紐’延遲第-重置信號以產生-第二重 正"宜上达第—重置信號谓測上述快閃記憶體是否 序序二若上述快閃記憶體正在進行寫入程 r容:姐*~理單員完成或終結上述快閃記憶體之寫入 接 ^ 在几成或終結上述快閃記憶體之寫入程序 便，根據上述第二重置信號進行％統重置。 在、隹基本發㈣用延遲重作的方式，讓系統 進完成快閃記憶體的資料寫入動作，然後再 丁糸置H避免重置而發生資料流失的 201107977 問題。 為讓本發明之上述特徵和優減更鶴易懂 舉貫施例，並配合所附圖式作詳細說明如下。 【實施方式】Generally, the computer has a reset switch or a reset button for system and first check. When the battery is down or an error occurs, the user can press the reset switch to restart the system to restore normal. status. However, 快, 'dead flash memory usually has to be written in block mode. So while the flash § 己 体 memory is writing data, if the user presses the reset switch, it is currently writing. People's data will be lost due to system reset. In order to solve the above-mentioned problems, the following four types of methods are found: (1) The 彳§号 will be reset, and then the system will control the reset time. This method is straightforward, the system itself. The author writes, the system determines whether the reset button has an action, and performs the user's needs. Software control can easily meet the user's needs, but if the system is already down, the reset button will also fail. (7) In addition to resetting the slogan, the user or the instruction manual informs the user that after resetting, a secret insurance may be generated to circumvent the relevant responsibilities. At the same time, the user must be taught to perform data backup processing frequently. This method can avoid the responsibility of loss of responsibility. The willingness of users to use, the responsibility is passed on to users. (3) When reading the f material, (4), the system can disable the 4 button, this method needs to add some circuits to achieve the effect of resetting the disability. As long as the system does not 201107977, it will crash when the data is written. Both allow the user to reset freely, so the chances of the system being unable to reset due to the system are greatly reduced, but there is still a chance to cause the reset to fail. And the user is notified when the disability is reset. The reset is invalid. (4) Using a programmable logic integrated circuit to achieve this goal 'but at a higher price' and requiring labor-intensive development, the circuit is not a pure hardware design. (5) If you don't pay attention to it, if the designed product is low-level or has no important information, you can save it. If you don't pay attention to whether the data is lost, the price is the cheapest, but the user will have a poor perception of the product and the brand. SUMMARY OF THE INVENTION The present invention provides a reset circuit that delays a reset signal for a period of time and then resets, and uses the delayed time to complete a data access procedure of the flash memory to avoid system reset. The problem of data loss. In view of the above, the present invention provides a reset circuit for an electronic device, the electronic device having a flash memory, the reset circuit including a reset switch, a reset signal generating unit, a delay unit, and a processing unit. The reset switch is used to reset the electronic device; the reset signal generating unit is coupled to the reset switch and generates a first reset signal when the reset switch is enabled. The delay unit is coupled to the reset signal generating unit for delaying the first reset signal for a predetermined time to generate a second reset signal. The processing unit is coupled between the reset signal generating unit, the delay unit, and the flash memory. When the first reset signal is enabled, the processing unit detects whether the flash memory is in the writing process according to the first reset signal. If the flash memory is in progress 201107977 5 Write: In the preset time to complete or terminate the flash memory = According to the second reset signal for system reset. - Voltage source: -第::: Kind: Gentry reset signal generation unit includes a TM〇s transistor, a resistor, a first-NPN transistor, a μ, a +, a second resistor, and a Two capacitors. The voltage source coupling W's - terminal '· the first capacitance is secreted between the C: C; the first electrical connection is between the reset and the second resistance, and the other of the second resistor is - The first and second bases of the resistor are coupled to the grounding end of the upper body; the first and second bases are coupled to the grounding terminal; Source, 2, ^, ^, the first reset signal of the above-mentioned PM0S transistor, the source output of the M0S transistor is crystal: extremely; Γί and engage two: the source of the upper paste source and the upper soul crystal In the embodiment of the present invention, the resistor is connected to the PMOS. The resistor and the reset integrated circuit comprise a fourth resistor and a third capacitor. Connected to the sixth resistor. Between the fourth power; the reset signal of the reset integrated circuit and a ground 螭 signal, the reset circuit of the reset integrated circuit is connected to the common node of the first-th weight t and the third capacitor, coupled And the outputting terminal of the first reset signal=body circuit after the delay of the resetting body circuit is used to delay the delay of the first reset signal; In the above-mentioned fourth 201107977, the common node of the third capacitor and the soil a of the second transistor, the emitter of the second transistor is coupled to the terminal, and the grounding reset signal of the sixth resistor ball is/ The collector of the second (four) transistor outputs the second to the second portion, wherein the delay unit further includes a fourth capacitor 盥 - the tantalum capacitor is connected to the delay unit, upper] =::; rf capacity and the above The capacitance value of the five capacitors determines τΐΐπ—the implementation of the above-mentioned electronic device is a computer, the notebook type is described as a flash memory, and the flash memory is the anti-gate flash memory (the other is to look at the other side of the invention) The resetting method of the electronic device has a postal memory And - reset switch, the following m first '# reset switch enable when generating a set: f button 'delay the first - reset signal to generate - second positive" " should be up to the first - reset signal Whether the flash memory is in sequence or not, if the above flash memory is in the process of writing the r: the sister*~ the manager completes or terminates the writing of the flash memory in the above or at the end of the above flash In the memory writing process, the % reset is performed according to the second reset signal. In the basic transmission (4), the system is used to complete the data writing operation of the flash memory, and then The problem of 201107977 in which data loss occurs due to resetting is avoided. In order to make the above-mentioned features and advantages of the present invention easier to understand, the following description will be made in detail with reference to the accompanying drawings.
键明參考附圖詳細闡述本發明的實施例’附圖舉例 似的元件料範實施例，其巾相同標號指示同樣或相 第一實施例 月 > 圖1，圖1為根據本發明第一實施例之首I電 生ί塊重置電„路100包括重置開關110、重置信號產 單元an延遲單兀130與處理單元140,重置信號產生 D。 耦接於重置開關11〇與延遲單元130之間，處理 窨帝 耗接於延遲單元130與快閃記憶體150之間。重 /龟路1〇〇可5又置於—電子裝置中，並用於對電子裝置進 竹系統重置。 t带重置開關U〇例如是按鍵，當使用者按下時，用以重 春屯子裝置。重置信號產生單元12〇耦接於重置開關11〇, !重置開_ 110致能時產生第-重置信I虎RET1，延遲單 ^ 12〇接收第一重置信號RET1並延遲該第一重置信號 1HT1的致能時間以產生第二重置信號RET2。處理單元 例如是中央微處理器，接收第一重置信號RET1與第 ^重置信號RET2 ’當重置開關uo致能時，第一重置信 竣RET1會隨之致能以通知處理單元14〇，使用者已經按 201107977DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention are described in detail with reference to the accompanying drawings, in which FIG. 1 is the same as the first embodiment of the present invention. FIG. 1 is a first embodiment according to the present invention. In the first embodiment of the embodiment, the circuit reset circuit 110 includes a reset switch 110, a reset signal generating unit an delay unit 130 and a processing unit 140, and a reset signal generating D. The reset switch 11 is coupled to the reset switch 11 Between the delay unit 130 and the processing unit, the processing unit is connected between the delay unit 130 and the flash memory 150. The heavy/turd road unit 5 is placed in the electronic device and used to enter the electronic device. The reset switch U 〇 is, for example, a button, and is used to restart the scorpion device when the user presses it. The reset signal generating unit 12 〇 is coupled to the reset switch 11 〇, ! The first reset signal I RET1 is generated, and the delay signal RET1 is received and the enable time of the first reset signal 1HT1 is delayed to generate the second reset signal RET2. The processing unit is, for example, The central microprocessor receives the first reset signal RET1 and the second reset signal RET2 'When When the switch is set enabled uo, Jun RET1 first reset channel will follow 14〇 enabled to notify the processing unit, the user has press 201,107,977
下重置開關。此時，處理單元14Q RET1偵測快閃記憶體15〇是:板據弟二：置= 閃記憶體150正在進行寫入程戽 仃寫入程序’右,κ 第-重置信號RET1·完成或 序，然後再根據第二重置靜憶體150之寫入程 由於延遲單㈣會系統重置。 _ 曰、避弟—重置信號RET1 —預設 在此㈣士月^第一重置㈣’因此處理單元140可 成快閃記憶體150的寫入程序，避免資 或U 140可增力σ操作頻率以加速寫入程序， 閃記龍15G的寫^知避免㈣流失。在 完成快閃記憶體150寫入程序的方式並不受 理。。疋置電路100會先延遲重置信f虎RET1，讓處 有時間完成快閃記憶體⑽的寫入程序，然後 声理f弟—重置f號RET2進行系統的重置。換句話說， =早π* 1=疋根據第二重置信號啦2來進行系統重 而根據第-重置錢RET1進行快閃記憶體—的資 胃完成或終結快閃記憶體15G的寫人程序表示 ::丨/如目如的寫入程序並紀錄目前的寫入資料。然 《動作當系統完成重置並請啟動時再重新進行寫入資料的 在先前技術中，當使用者按下重置按鍵後，系統便會 馬上進㈣統重置，並不會紐通知處理單元14〇以及預 曰留時間讓系騎行資料紐。因此，她於本發明，本發 明具有改善在先前技術中H㈣置而產生的資料流失^ 201107977 題。 一接下來，進—步說明重置信號產生單元120與延遲單 兀^30的細部電路圖，請參照圖2，圖2為根據本發明第 一貫施例之重置電路之硬體電路圖_。重置開關n〇例如一 身又包腦機忒上的重置按鍵(Reset b〇tt〇n)，當使用者按下重 置按鍵時，重置開關11〇會導通。Reset the switch. At this time, the processing unit 14Q RET1 detects the flash memory 15〇: the board is the second brother: the set = the flash memory 150 is writing the program 戽仃 the program 'right, κ the first - reset signal RET1 · completion or preface Then, according to the second reset, the write process of the memory block 150 will be reset due to the delay of the single (four). _ 曰, 避 brother - reset signal RET1 - preset here (four) 士月 ^ first reset (four) 'so the processing unit 140 can be written into the flash memory 150, avoid capital or U 140 can increase force σ The operating frequency is used to speed up the writing process, and the writing of the flashing dragon 15G avoids (4) loss. The way to complete the flash memory 150 write process is not reasonable. . The device circuit 100 first delays the reset signal f RET1, so that there is time to complete the writing process of the flash memory (10), and then the sound of the dynasty - reset the f RET2 for system reset. In other words, = early π * 1 = 疋 according to the second reset signal 2 to perform system weighting, according to the first-replacement money RET1 for flash memory - to complete or terminate the writing of the flash memory 15G The human program indicates: 丨 / Write the program as expected and record the current write data. However, in the prior art, when the system completes the reset and starts up, it is re-written. In the prior art, when the user presses the reset button, the system will immediately enter (4) reset, and will not process the notification. Unit 14〇 and pre-retention time allow the ride to be used. Therefore, in the present invention, the present invention has the problem of improving the data loss caused by H(4) in the prior art. Next, a detailed circuit diagram of the reset signal generating unit 120 and the delay unit 30 will be described. Referring to FIG. 2, FIG. 2 is a hardware circuit diagram of the reset circuit according to the first embodiment of the present invention. The reset switch n〇, for example, has a reset button (Reset b〇tt〇n) on the brain, and when the user presses the reset button, the reset switch 11 turns on.
重置信號產生單元12〇包括第一電容C1、第二電容 C2、第一電阻1^、第二電阻R2與第三電阻R3、PMOS 笔日日體（P channel metal oxide semiconductor transistor，簡 稱 PM0S)M1 與 NPN 電晶體（NpN bip〇lar juncti〇n transistor ’簡稱BJT))Q1。重置開關u〇的第一端耦接於 電壓源VDD，第一電容Cl耦接於重置開關11〇的第二端 與接地端GND之間。第一電阻R1耦接於重置開關11〇的 第二端與第二電阻R2之間，第二電阻R2的另一端耦接於 接地端GND。第一 NPN電晶體Q1的基極耦接於第一電 阻R1與第二電阻R2的共用節點，第一 npn電晶體Q1 • 的射極耦接於接地端GND°PMOS電晶體M1的閘極耦接 第一 NPN電晶體Q1的集極，pMOS電晶體奶的源極輕 接於笔壓源VDD ’而》及極則輸出第—重置信號RgTi。第 二電阻R3耦接於電壓源VDD與PM0S電晶體M1的閘極 之間。第二電容C2減於刚0S電晶體⑽的没極與接 地端GND之間。 冨重置開關100因使用者按下而致能時，電容ci會 開始充電，然後第-NPN電晶體Qi會隨之導通，然後使 201107977 ΡΜΟ^電晶體Ml導通’此時pM〇s電晶體Μι的 輸出南電位的第-重置信號ΜΤ1以表示使用者按下重▲ 開關100。 延遲單元130包括第三電阻R3、第四電阻反4、 電^5、第六電阻R6、第三電容C3、第四電容C4、第 五電容C5、重置積體電路m與第二刪電晶體Q2。第 三電阻R3,第三電阻幻與第三電容C3串聯她於第一 重置信號RET1與接地端GND之間。重置積體電路订丨例 ^疋PST9229NR 〇r FP6801(天钰科技股份有限公司的電源 管理晶片），重置積體電路U1的輸入端VCC耦接於第— 重置彳5旒RET1，重置積體電路U1的輸出端VOUT耦接 於第四電阻R4與第三電容C3的共用節點，重置積體電路 U1以第一重置信號RET1做為工作電源並延遲—預設時間 後’經由輸出端V0UT輸出對應於第一重置信號RET1 ^ 輸出信號。 第五電阻R5耦接於第四電阻&4與第三電容C3的共 用節點與第二NPN電晶體Q2的基極之間 ，第二NPN電 晶體Q2的射極耦接於接地端GND。第五電阻R5耦接於 電壓源VDD與第二NPN電晶體Q2的集極之間，其中第 二NPN電晶體Q2的集極輪出第二重置信號RET2。 重置積體電路U1可利用現成的延遲晶片來實現，主 要功用在於延遲第一重置信號RET1，然後經由其輸出哺 VOUT輸出延遲後的第一重置信號RET1。重置積體電略 U1的延遲時間可由電容C4、C5(耦接於重置積體電路 201107977 ^’不同的晶片有不同的延遲時間電路鱼 週^倾置方式，圖2僅林發 加贅述。重置積體電路111在筮一 Λ 在此不 會延遲-職時崎再致能日彳 彳s#uRET1致能後’ NPN電晶體Q2。第二‘匕^端V〇^以導通第二 出電壓即為第二重置信f#uRET2:Q2的:極所產生的輸 第二刪電晶體Q2導通而轉離^置㈣咖2會因 和〜、為低電位，缺德太楚—^The reset signal generating unit 12A includes a first capacitor C1, a second capacitor C2, a first resistor 1^, a second resistor R2 and a third resistor R3, and a P channel metal oxide semiconductor transistor (PM0S). M1 and NPN transistor (NpN bip〇lar juncti〇n transistor 'BJT for short) Q1. The first end of the reset switch u is coupled to the voltage source VDD, and the first capacitor C1 is coupled between the second end of the reset switch 11A and the ground GND. The first resistor R1 is coupled between the second end of the reset switch 11A and the second resistor R2, and the other end of the second resistor R2 is coupled to the ground GND. The base of the first NPN transistor Q1 is coupled to the common node of the first resistor R1 and the second resistor R2. The emitter of the first npn transistor Q1 is coupled to the ground GND. The gate coupling of the PMOS transistor M1. Connected to the collector of the first NPN transistor Q1, the source of the pMOS transistor milk is lightly connected to the pen voltage source VDD' and the pole outputs the first reset signal RgTi. The second resistor R3 is coupled between the voltage source VDD and the gate of the PMOS transistor M1. The second capacitor C2 is subtracted from the between the pole of the 0S transistor (10) and the ground GND.冨 When the reset switch 100 is enabled by the user pressing, the capacitor ci will start to charge, and then the first-NPN transistor Qi will be turned on, and then the 201107977 电^ transistor M1 will be turned on' at this time pM〇s transistor The first reset signal ΜΤ1 of the south potential is outputted to indicate that the user presses the heavy ▲ switch 100. The delay unit 130 includes a third resistor R3, a fourth resistor inverse 4, an electric 5, a sixth resistor R6, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a reset integrated circuit m, and a second power cut. Crystal Q2. The third resistor R3, the third resistor phantom and the third capacitor C3 are connected in series between the first reset signal RET1 and the ground GND. Reset the integrated circuit. Example: 疋PST9229NR 〇r FP6801 (Power Management Chip of Tianyi Technology Co., Ltd.), reset the input terminal VCC of the integrated circuit U1 to the first - reset 彳5旒RET1, heavy The output terminal VOUT of the integrated circuit U1 is coupled to the common node of the fourth resistor R4 and the third capacitor C3, and the reset integrated circuit U1 uses the first reset signal RET1 as the operating power source and is delayed - after the preset time. The output signal corresponding to the first reset signal RET1 ^ is output via the output terminal VOUT. The fifth resistor R5 is coupled between the common node of the fourth resistor & 4 and the third capacitor C3 and the base of the second NPN transistor Q2, and the emitter of the second NPN transistor Q2 is coupled to the ground GND. The fifth resistor R5 is coupled between the voltage source VDD and the collector of the second NPN transistor Q2, wherein the collector of the second NPN transistor Q2 rotates the second reset signal RET2. The reset integrated circuit U1 can be implemented by using an off-the-shelf delay chip, the main function of which is to delay the first reset signal RET1, and then output the delayed first reset signal RET1 via its output VOUT. The delay time of resetting the integrated circuit U1 can be determined by capacitors C4 and C5 (coupled to the reset integrated circuit 201107977 ^' different wafers have different delay time circuit fish ^ tilting mode, Figure 2 only Lin Fajia The reset integrated circuit 111 is not delayed here - the time is after the 彳彳 u u u u u u u u u u u u N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N The second output voltage is the second reset signal f#uRET2: Q2: the second generated transistor Q2 generated by the pole is turned on and turned away from the ^4 (4) coffee 2 will be due to ~ and low potential, lacking morality - ^
置#號尺£1[1降為低電位時轉態為高電位。當第 號RET1降為低電位時，重置積體電路⑺合失 ^ ^/f^V()UT會降輕電麵使第二θ咖電: 處理=兀Μ0會根據第二重置錢勘 „重置信號騰2恢復至高電位時開始丁重^ 之’弟二重置信號RET2是直她接於處理單 = 腳位’以直接重置系統。此外，值得注意的是，本〜= 的弟二重置信號RET2是以低電位作為致能準位，^ =:此為限’只要改變電路設計，便可以高電位: 接下來，進一步說明上述圖2中各電路節點的電 化，請參照圖3，目3為根據本發明第—實施例之戶 形圖。使用者按下重置開關110時，重置開關11〇合導=， 使得第一電容ci的偏壓VC1拉高為高電位，當使a用者放 開後，偏壓VC1會因第一電容α放電而下降，苴中期間 D1為使用者按下重置開關110的時間。在時間丁'丨，第二 11 201107977 腦電晶體φ會因傾VC1上升而導通，立华 W會因導通而下降，而第—PM0S電晶體組則會因第 :酬電晶體Q1的集極電壓VQ1下降而導通，此時， 二f能’即轉態為高電位。重置積體電 尸1山使第-重置信號咖延遲—預設時間⑽後致能】 輸出VOUT的電壓，並且在第—曹〆、 柄雷彷η士甘认， 重置仏旒RET1轉態為 付八輸出端νουτ的電壓也會隨之轉態為低電 二重置積體電路U1是以第—重置信號拙T1 做為工作電壓所造成。 重置積體電路U1的輪出端ν〇υτ =電的r:使第二重置™ 的輸出端V0UT電壓上升而上升， R=i出，V〇〜下降而下降。第二重置= 腿2的致能時間D3即為主系統重置的時間。由圖3可 = 按下重置_ UG時，第—重置信號虹η 二=ί能（两電位)以告知處理元14〇使用者 後延遲1設時_後，第二重置信I m仏之致能(錢位)使祕麟重置。處理單元 士D2令完成或終結目前正在進行的快閃 第:ϊ:〗程序以避免資料流失。 署的述貫施例的說明，本發明可歸納出—種電子裝 二實施例4子圖4 ’圖4為根據本發明第 、置的重置方法流程圖。其中電子裝置具 201107977 有一快閃記憶體150與一重置開關110，重置方法包括下 列步驟：首先’當重置開關110致能時，產生第—重置作 號RET1(步驟S410)’然後延遲第一重置信號reti以產生 一第二重置信號RET2(步驟S420)。接下來，根據第—重 置信號RET1偵測快閃記憶體150是否正在進行寫入程序 (步驟S430)，若快閃記憶體150正在進行寫入程序，則經 由處理單元140完成或終結快閃記憶體15〇之寫入程序（步 驟S440)。然後，在完成或終結快閃記憶體15〇之寫入程 • 序後’根據第二重置信號RET2進行系統重置。其中，= 快閃記憶體150沒有正在進行寫入程序，處理單元14〇同 樣會在第二重置信號RET2致能時才進行系統重置。本重 置方法之其餘操作細節請參照上述第一實施例之說明，在 此不加累述 綜合上述，本發明利用純硬體電路設計重置積體電 路，將重置信號延遲後再輸出至系統以進行重置，並預先 告知系統準備進行重置。系統可於重置信號的延遲期間中 • 預先完成快閃記憶體的寫入程序，避免因使用者突發式的 按下重置開關而造成資料流失的問題。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，故本 兔明之保遵範圍當視後附之申請專利範圍所界定者為準。 13 201107977 【圖式簡單說明】 圖1為根據本發明第一實施例之重置電路方塊圖。 圖2為根據本發明第一實施例之重置電路之硬體電路 圖。 - . 圖3為根據本發明第一實施例之信號波形圖。 圖4為根據本發明第二實施例之電子裝置的重置方法 流程圖。 【主要元件符號說明】 100 :重置電路 VDD :電壓源 110 :重置開關 GND :接地端 120 :重置信號產生單元 VCC :輸入端 130 :延遲單元 VOUT :輸出端 140 :處理單元 TC、SUB :重置積體電路 150 :快閃記憶體 U1的接腳 RET1 :第一重置信號 S410〜S450 :流程圖步驟 RET2 :第二重置信號 D1:重置開關被按下的期間 R1〜R6 :電阻 D2 :預設時間 C1〜C5 :電容 D3 :第二重置信號RET2的 Ml : PMOS電晶體 致能時間 Ql、Q2 : NPN電晶體 U1 :重置積體電路 T1 :時間 14Set the #尺尺£1[1 when the low level is low, the transition state is high. When the first RET1 falls to a low potential, reset the integrated circuit (7) and lose ^ ^ / f ^ V () UT will lower the light electric surface to make the second θ coffee: Processing = 兀Μ 0 will be based on the second replacement money Survey „Reset signal Teng 2 resumes to high potential when Ding heavy ^ The second brother reset signal RET2 is straight she is connected to the processing single = pin position to directly reset the system. In addition, it is worth noting that this ~= The second reset signal RET2 is based on the low potential as the enable level, ^ =: This is the limit 'As long as the circuit design is changed, the potential can be high: Next, further explain the electrification of each circuit node in Figure 2 above, please refer to Figure 3 is a diagram showing a floor plan according to the first embodiment of the present invention. When the user presses the reset switch 110, the reset switch 11 is turned on, so that the bias voltage VC1 of the first capacitor ci is raised high. The potential, when a user is released, the bias voltage VC1 will drop due to the discharge of the first capacitor α, and the period D1 is the time for the user to press the reset switch 110. At the time D', the second 11 201107977 The brain crystal φ will be turned on due to the rise of the tilt VC1, and the Lihua W will fall due to conduction, while the first-PM0S transistor group will be due to the first: The collector voltage VQ1 of the crystal Q1 falls and is turned on. At this time, the two f can't turn into a high potential. The reset of the integrated body of the corpse is delayed by the first-reset signal - the preset time (10) is enabled. Output the voltage of VOUT, and in the first - Cao 〆, 柄 仿 甘 甘 甘 ,, reset 仏旒 RET1 转 为 为 付 付 付 付 付 付 付 付 付 付 付 付 付 付 付 付 付 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压 电压U1 is caused by the first reset signal 拙T1 as the operating voltage. The reset terminal ν 〇υ τ of the integrated circuit U1 = electrical r: the voltage of the output terminal VOUT of the second reset TM rises and rises, R = i out, V 〇 ~ drop and fall. Second reset = leg 2's enable time D3 is the time of reset for the main system. From Figure 3 can be = press reset _ UG, first - reset The signal rainbow η 2 = ί can (two potentials) to inform the processing unit 14 〇 user delay 1 set _, after the second reset letter I m 仏 enable (money bit) to reset the secret lin. The D2 order completes or terminates the flashing that is currently in progress: ϊ: 〗 program to avoid data loss. The description of the application of the Department, the invention can be summarized - the implementation of electronic equipment 4 sub-figure 4' Figure 4 is a flow chart of a reset method according to the present invention. The electronic device has a flash memory 150 and a reset switch 110. The reset method includes the following steps: When the switch 110 is enabled, the first reset signal RET1 is generated (step S410)' and then the first reset signal reti is delayed to generate a second reset signal RET2 (step S420). Next, according to the first reset The signal RET1 detects whether the flash memory 150 is performing a writing process (step S430). If the flash memory 150 is performing a writing process, the writing process of the flash memory 15 is completed or terminated via the processing unit 140. (Step S440). Then, after completing or terminating the write process of the flash memory 15', the system reset is performed according to the second reset signal RET2. Wherein, the flash memory 150 is not in the process of writing, and the processing unit 14 will perform the system reset only when the second reset signal RET2 is enabled. For the rest of the operation of the resetting method, please refer to the description of the first embodiment. The above description does not add to the above. The present invention uses a pure hardware circuit design to reset the integrated circuit, delays the reset signal, and then outputs the reset signal to The system is reset and the system is pre-announced to be ready for reset. The system can complete the writing process of the flash memory in advance during the delay period of the reset signal to avoid the problem of data loss caused by the user pressing the reset switch in a sudden manner. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of this rabbit's warranty is subject to the definition of the patent application scope attached. 13 201107977 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a reset circuit in accordance with a first embodiment of the present invention. Fig. 2 is a hardware circuit diagram of a reset circuit in accordance with a first embodiment of the present invention. - Figure 3 is a signal waveform diagram in accordance with a first embodiment of the present invention. 4 is a flow chart showing a reset method of an electronic device according to a second embodiment of the present invention. [Main component symbol description] 100: Reset circuit VDD: Voltage source 110: Reset switch GND: Ground terminal 120: Reset signal generating unit VCC: Input terminal 130: Delay unit VOUT: Output terminal 140: Processing unit TC, SUB : reset integrated circuit 150 : pin RET1 of flash memory U1 : first reset signal S410 ~ S450 : flow chart step RET2 : second reset signal D1 : period during which reset switch is pressed R1 R R6 : Resistor D2 : Preset time C1 to C5 : Capacitor D3 : Ml of second reset signal RET2 : PMOS transistor enable time Ql, Q2 : NPN transistor U1 : Reset integrated circuit T1 : Time 14