201106809 六、發明說明： 【發明所屬之技術領域】 本發明係關於透過導電性金屬層將導電性金屬電沉積 於絕緣基板的表面而形成配線圖案之印刷電路板及其製造 方法。詳細而言，本發明係關於使用具備包含Ni、Cr等導 電性金屬層之附有導電性金屬層的絕緣基板（CCL)，將使用 光阻所形成之圖案用作為遮罩材，選擇性地將導電性金屬 電沉積於此導電性金屬的表面而形成配線圖案之印刷電路 板，且為因所形成之配線圖案的線寬而產生之導電性金屬 厚度的變動幅度甚小之印刷電路板，以及製造出此印刷電 路板之方法。 【先前技術】 為了安裝電子零件，係使用印刷電路板。此種印刷電 路板，係由：由聚醯亞胺膜等所構成之絕緣薄膜；以及形 成於其上方之銅等導電性金屬所構成之配線圖案所形成。 以往，此種印刷電路板，係將銅箔配置在絕緣薄膜的表面， 將光阻層形成於此銅箔的表面，並將光阻層進行曝光、顯 影以形成期望的圖案，然後將此圖案用作為遮罩材，選擇 性地將銅箔進行蝕刻來形成期望的配線圖案（減成法， subtractive process)，但在此方法中，非常難以將線寬 形成為35/zm以下，而逐漸難以因應近來電子零件的高積 體化。 以取代上述之方法而言，近來受矚目者有半加成法。 此方法係將導電性的基材金屬層形成於絕緣基板的表面， 6 322068 201106809 將光阻層形成於此基材金屬層的表面，然 成為期望的®& 曼將該光阻層形 μ @ p π的圖案，並在從如此形成的圖案暴露+ > + 屬層上電汾^ ^ 略出之基材金 匕積導電性金屬，來形成配線圖案者 法，亦可劁Λ 彔音。根據此方 灰乂出線寬為ΙΟ/im左右的配線圖宠 ,-λ- -Γ 因應高密声π 口素，因此亦可 度化之電子零件的安裝。 關曰此種半加成法之印刷電路板，係有種種提案 258411 ^ 2〇〇3-〇37137 ^-^^^#P, 2003-&報、日本特開 2002-215059 號公 問4 °亦即，本發明人係針對採用此半加歧所製造之印 刷電路板的穩定性缺失進行種難討，結果發現在採用半 加成法所製造之印刷電路板中，因線路寬度與間距寬度而 於析出之導電性金屬的厚度具有參差變動。 (先前技術文獻） (專利文獻） (專利文獻1)日本特開·3_G37137號公報 (專利文獻2)日本特開·3_258411號公報 (專利文獻3)日本特開2GG2-215G59號公報 【發明内容】 (發明所欲解決之課題） 本發明之目的’係提供一種不會因配線圖案之線寬或 間距的不同而於電沉積之導電性金屬層的厚度產生差異之 印刷電路板、以及製造具有此種均句性高的配線厚度之印 刷電路板之方法。 322068 7 201106809 (用以解決課題之手段） 本發明之印刷電路板係經過於絕緣基板的表面隔著基 材金屬層，而在含有基材金屬層之導電性層的表面配置使 圖案成形為期望形狀之感光性樹脂層，並選擇性地析出導 電性金屬層之工序，而形成有由基材金屬層及導電性金屬 層所構成之配線寬度不同且具所期望形狀之複數個配線圖 案者；該印刷電路板係滿足下列（1)至（3)所述之條件中的 任一條件。 (1) 所有配線之間距寬度為50# m以下的窄間距寬度。 (2) 所有配線之間距寬度係超過50 μ m且為100/zm以 下。 (3) 上述印刷電路板中，當配線的間距寬度為50#m以 下之配線與配線的間距寬度超過50//m且為100# m以下之 配線混合存在時，以形成於該印刷電路板之配線寬度中間 距寬度超過50#m且為100//m以下之配線的配線寬度為 a，以形成於該印刷電路板之虛設配線的虛設配線寬度為 a’，以忽略形成於該印刷電路板之虛設配線時之與鄰接配 線的距離之配線空隙寬度為b，以形成於該印刷電路板之 配線與鄰接虛設配線的距離之空隙寬度為b’，以忽略形成 於該印刷電路板之虛設配線時之配線的間距寬度為P時， 係滿足 (A) a//m^P/z mxO. 5 ' b // P ^ mxO. 5 ' 25//m^a//m ^ 95 // m ； (B) 該印刷電路板具有虛設配線，a+a’ # m 2 P a mx 8 322068 201106809 0.5 ' bf β\Ά^? β mxO. 25' S/zra^a^m^SS/zni' 5/cim^a, # m S 85//m中之任一項。 本發明中，印刷電路板係經過於上述絕緣基板的表面 隔著基材金屬層，在含有基材金屬層之導電性層的表面配 置使圖案成形為期望形狀之感光性樹脂層，並選擇性地析 出導電性金屬層之工序，形成有由基材金屬層及導電性金 屬層所構成之配線寬度不同的複數個配線圖案而成； 該印刷電路板較佳係滿足下列關係，亦即（3)上述印刷 電路板中，當配線的間距寬度為50#m以下之配線與配線 的間距寬度超過50/im且為100/zm以下之配線混合存在， 且以形成於該印刷電路板之配線中之間距寬度超過5 0 # m 且為100//m以下之配線的配線寬度為a，以形成於該印刷 電路板之虛設配線的虛設配線寬度為a’，以忽略形成於該 印刷電路板之虛設配線時之與鄰接之配線的距離之配線空 隙寬度為b，以形成於該印刷電路板之配線與鄰接之虛設 配線的距離之空隙寬度為b’，以忽略形成於該印刷電路板 之虛設配線時之配線的間距寬度為P時，係滿足 (A)a//m^P/z mxO. 5 ' b β\Ά^? β mxO. 5 ' 25//m^a//m ^ 95 // m ； (Β)該印刷電路板具有虛設配線，a+a’ 0. 5、b’ // mS PxO. 25、5/zmSa#mS85/zm、5#mSa’ /zm S 85 // m中之任一項。 再者，本發明之印刷電路板中，在上述配線圖案内， 當間距寬度P由配線圖案的線寬與空隙寬度之合計所構成 9 322068 201106809 時’較佳係在間距寬度P成為50//m<PS 100//m之配線圖 案之間配置虛設電極，並於8. 5至9. 2/zm的範圍内將形成 該印刷電路板之配線圖案的導電性金屬的厚度進行均一化 而成。 亦即，本發明之印刷電路板中，在藉由半加成法所形 成之窄配線間距的印刷電路板中，當窄配線寬度的配線圖 案與較此還寬的配線圖案混合存在時，不論所形成之配線 圖案寬度的寬窄’均可提供配線圖案厚度均一之印刷電路 板。 此外，如上所述地藉由半加成法形成配線圖案時，將 光阻層進行曝光、顯影並析出導電性金屬時，由光阻層所 限制之導電性金屬的析出部分，會有沿著配線圖案兩旁的 長度方向未析出導電性金屬之凹入部。此可得知為在將光 阻層曝光為期望形狀後，進行顯影時，光阻殘留於底部所 產生者。 由於此光阻的殘留，使導電性金屬無法析出於該殘留 的部位，在由析出之導電性金屬所構成之配線圖案的底 部，會沿著配線圖案的長度方向而產生未析出導電性金屬 之凹入部。 關於如此種凹入部產生原因之光阻殘留的因素，其詳 細内容仍未明瞭，但將絲層進行曝光、顯影時，有㈣ 殘潰殘留於絕緣基板上之基材導電性金屬層(鋼層）上則為 事實’由此即可得知形成凹人部之原因。為了防止此 顯影殘㈣產生，在將導電性金屬層（銅層）進行化學研磨 322068 10 201106809 並將新顯現之導電性金屬層（銅層）的表面進行脫 後，於3小時内形成光阻層，並且將經脫脂 :處理 阻層進行曝光，然後進行顯影，如此即不會=之光 邊’所以在絕緣薄膜上之導電性金屬層（銅層）上‘肩衫殘 成往配_案的寬度方向_侵人之凹人部，而能=會形 具有大致垂直於絕緣薄膜的表面之側面之配線圖案。°成 再者，本發明之印刷電路板之配線圖案的厚度中， 線彼此的比較之標準差(STDE)(導電性金屬層之严 ： 準差（STDE) ’較佳為 0. 15/ζιη以下。 又的才不 此外，本發明之印刷電路板，上述配線圖案之厚度的 標準差（STDE)相對於上述配線圖案的平均厚度⑽^比 (STDE/AVE)較佳係位於 0· 005至0. 018的範圍内。 本發明中，上述配線一般為形成於印刷電路板之内引 線或外引線。 本發明之導電性金屬，較佳為電沉積於基材金屬層的 表面之銅或鋼合金，此外，形成印刷電路板之絕緣基板的 表面上所形成之基材金屬層，較佳係使用隔著包含Ni及BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board in which a wiring pattern is formed by electrodepositing a conductive metal on a surface of an insulating substrate through a conductive metal layer, and a method of manufacturing the same. More specifically, the present invention relates to an insulating substrate (CCL) having a conductive metal layer including a conductive metal layer such as Ni or Cr, and a pattern formed using a photoresist as a mask, optionally A printed circuit board in which a conductive metal is electrodeposited on the surface of the conductive metal to form a wiring pattern, and the printed circuit board having a small variation in thickness of the conductive metal due to the line width of the formed wiring pattern is used. And a method of manufacturing the printed circuit board. [Prior Art] In order to mount an electronic component, a printed circuit board is used. Such a printed circuit board is formed by an insulating film made of a polyimide film or the like and a wiring pattern formed of a conductive metal such as copper formed thereon. Conventionally, such a printed circuit board has a copper foil disposed on a surface of an insulating film, a photoresist layer formed on a surface of the copper foil, and a photoresist layer is exposed and developed to form a desired pattern, and then the pattern is formed. As a masking material, the copper foil is selectively etched to form a desired wiring pattern (reduction process), but in this method, it is very difficult to form the line width to be 35/zm or less, which is gradually difficult In response to the recent high integration of electronic components. In order to replace the above method, recently, the subject has a semi-additive method. In this method, a conductive base metal layer is formed on the surface of the insulating substrate, and 6 322068 201106809 forms a photoresist layer on the surface of the base metal layer, thereby becoming a desired ® & @ p π pattern, and exposed from the pattern thus formed + > + genus layer 上 ^ ^ 之 之 之 基材 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略 略. According to this, the ash line width of the ash line is about ΙΟ/im, and the -λ- - Γ can be used for the installation of electronic parts due to the high-density sound π mouth. Regarding the printed circuit board of such a semi-additive method, there are various proposals 258411 ^ 2〇〇3-〇37137 ^-^^^#P, 2003-& newspaper, and JP-A-2002-215059. That is, the inventors of the present invention have difficulty in stabilizing the stability of a printed circuit board manufactured by using this semi-aliasing, and as a result, found that in the printed circuit board manufactured by the semi-additive method, the line width and pitch are The thickness of the deposited conductive metal has a variation in variation. (Patent Document) (Patent Document 1) Japanese Patent Laid-Open Publication No. Hei. No. 3-258411 (Patent Document 3). (Problems to be Solved by the Invention) The object of the present invention is to provide a printed circuit board which does not differ in the thickness of the electrodeposited conductive metal layer due to the difference in line width or pitch of the wiring pattern, and the manufacture thereof. A method of printing a printed circuit board having a high degree of wiring thickness. 322068 7 201106809 (Means for Solving the Problem) The printed circuit board of the present invention is disposed on the surface of the conductive layer containing the base metal layer via the base metal layer via the surface of the insulating substrate, so that the pattern is formed into a desired shape. a step of selectively depositing a conductive metal layer in a shape of a photosensitive resin layer, and forming a plurality of wiring patterns having a different wiring width and having a desired shape by a base metal layer and a conductive metal layer; The printed circuit board satisfies any of the conditions described in the following (1) to (3). (1) A narrow pitch width of 50# m or less between all wirings. (2) The width between all wirings is more than 50 μm and is less than 100/zm. (3) In the printed circuit board, when the pitch of the wiring having a pitch width of 50#m or less and the pitch of the wiring and the wiring are more than 50/m and the wiring of 100# m or less is mixed, the printed circuit board is formed on the printed circuit board. In the wiring width, the wiring width of the wiring having a pitch width of more than 50 #m and 100//m or less is a, and the dummy wiring width of the dummy wiring formed on the printed circuit board is a', ignoring the formation of the printed circuit. The width of the wiring gap of the distance from the adjacent wiring when the dummy wiring of the board is b, the width of the gap formed between the wiring of the printed circuit board and the adjacent dummy wiring is b', so as to ignore the dummy formed on the printed circuit board. When the pitch width of the wiring during wiring is P, it satisfies (A) a//m^P/z mxO. 5 ' b // P ^ mxO. 5 ' 25//m^a//m ^ 95 // m; (B) The printed circuit board has dummy wiring, a+a' # m 2 P a mx 8 322068 201106809 0.5 ' bf β\Ά^? β mxO. 25' S/zra^a^m^SS/zni '5/cim^a, # m S 85//m. In the present invention, the printed circuit board is placed on the surface of the insulating substrate via a base metal layer, and a photosensitive resin layer which is patterned into a desired shape is disposed on the surface of the conductive layer containing the base metal layer, and is selectively In the step of depositing the conductive metal layer, a plurality of wiring patterns having different wiring widths composed of the base metal layer and the conductive metal layer are formed; and the printed circuit board preferably satisfies the following relationship, that is, (3) In the above printed circuit board, wirings having a pitch width of 50#m or less and wirings having a pitch width of more than 50/im and 100/zm or less are mixed and formed in the wiring of the printed circuit board. The wiring width of the wiring having a width exceeding 5 0 #m and being 100//m or less is a, so that the dummy wiring width of the dummy wiring formed on the printed circuit board is a', ignoring the formation on the printed circuit board. The wiring gap width of the distance from the adjacent wiring at the time of the dummy wiring is b, so that the gap width between the wiring formed on the printed circuit board and the adjacent dummy wiring is b', When the pitch width of the wiring formed in the dummy wiring of the printed circuit board is P, it satisfies (A) a//m^P/z mxO. 5 ' b β\Ά^? β mxO. 5 ' 25// m^a//m ^ 95 // m ; (Β) The printed circuit board has dummy wiring, a+a' 0. 5, b' // mS PxO. 25, 5/zmSa#mS85/zm, 5# mSa' /zm S 85 // m of any of them. Further, in the printed circuit board of the present invention, in the wiring pattern, when the pitch width P is composed of the total of the line width and the gap width of the wiring pattern, 9 322068 201106809 is preferable, and the pitch width P is preferably 50//. A dummy electrode is disposed between the wiring patterns of the m < PS 100 / / m, and the thickness of the conductive metal forming the wiring pattern of the printed circuit board is uniformized in the range of 8.5 to 9. 2 / zm. . That is, in the printed circuit board of the present invention, in the printed circuit board having a narrow wiring pitch formed by the semi-additive method, when the wiring pattern of the narrow wiring width is mixed with the wiring pattern which is wider than this, regardless of The width and width of the formed wiring pattern width can provide a printed circuit board having a uniform wiring pattern thickness. Further, when the wiring pattern is formed by the semi-additive method as described above, when the photoresist layer is exposed, developed, and the conductive metal is deposited, the deposited portion of the conductive metal which is restricted by the photoresist layer may be along The concave portion of the conductive metal is not deposited in the longitudinal direction on both sides of the wiring pattern. This is known to be the case where the photoresist remains on the bottom when the photoresist layer is exposed to a desired shape and developed. Due to the residual of the photoresist, the conductive metal cannot be deposited on the remaining portion, and at the bottom of the wiring pattern composed of the deposited conductive metal, the conductive metal is not deposited along the longitudinal direction of the wiring pattern. Concave part. The details of the photoresist residue caused by such a recessed portion are still unclear. However, when the silk layer is exposed and developed, there are (4) residual conductive metal layers (steel layer) remaining on the insulating substrate. The above is the fact 'therefore, the reason for forming the concave part can be known. In order to prevent the occurrence of the development residue (4), the conductive metal layer (copper layer) is chemically polished 322068 10 201106809 and the surface of the newly formed conductive metal layer (copper layer) is removed, and a photoresist is formed in 3 hours. The layer, and will be degreased: the resist layer is exposed for exposure, and then developed, so that it does not have a light edge', so the conductive metal layer (copper layer) on the insulating film is replaced by a shoulder shirt. The width direction _ invades the human part, and can = form a wiring pattern having a side substantially perpendicular to the surface of the insulating film. Further, in the thickness of the wiring pattern of the printed circuit board of the present invention, the standard deviation (STDE) of the comparison between the wires (the thickness of the conductive metal layer: the quasi-difference (STDE)' is preferably 0.15/ζιη Further, in addition, in the printed circuit board of the present invention, the standard deviation (STDE) of the thickness of the wiring pattern relative to the average thickness (10) of the wiring pattern (STDE/AVE) is preferably at 0·005 to In the range of 0. 018, in the present invention, the wiring is generally formed as a lead or an outer lead in a printed circuit board. The conductive metal of the present invention is preferably copper or steel electrodeposited on the surface of the base metal layer. The alloy, in addition, the base metal layer formed on the surface of the insulating substrate forming the printed circuit board, preferably using Ni and
Cr之基材金屬而具有銅層讀有導電性金屬層的絕緣基板 所形成》 此外，本發明之印刷電路板可藉由下列方法製造出。 亦即’該印刷電路板係經由在含有基材金屬層之導電性層 的表面配置使圖案成形為期望形狀之感光性樹脂層，並選 擇性地析出導電性金屬層之工序，而形成有由基材金屬層 及導電性金屬層所構成之配線寬度不同且具有期望形狀的 322068 11 201106809 複數個配線圖案；並且於絕緣基板的表面隔著基材金屬 層，形成有由導電性金屬層所構成之配線寬度不同的複數 個配線圖案之印刷電路板，當製造該印刷電路板時 於該配線圖案内， 當線寬為5至85/zm，空隙寬度為15至95//m時，係 以使虛設配線形成於該配線與鄰接之配線之間的空隙之方 式形成光阻層； 以使該配線與鄰接之虛設配線的空隙位於5至25#m 的範圍内之方式形成光阻層，並析出導電性金屬。 上述製造方法中，在形成光阻層前，將導電性金屬層 的表面進行脫脂處理後，於3小時以内形成光阻層，藉此 可有效地防止凹入部的產生。 (發明之效果） 根據本發明，在附有導電性金屬層的絕緣基板之導電 性金屬層的表面上，藉由塗佈光阻層並將其進行曝光、顯 影來形成期望形狀的圖案，將此圖案用作為遮罩材，並將 新的導電性金屬電沉積於導電性金屬層的表面來形成期望 的配線圖案時，由於可藉由配線圖案的線寬或間距寬度來 控制電沉積之導電性金屬的量，所以析出之導電性金屬的 厚度為不同者較少。因此，根據本發明，可製得均一性高 之印刷電路板。 尤其根據本發明，藉由在將導電性金屬層的表面進行 脫脂處理後，於3小時以内形成光阻層，當將此光阻層進 行曝光並進行顯影時，理應經顯影去除之光阻不會殘存於 12 322068 201106809 導電h生金屬層的表面，因此，即使藉由半加成法析出新的 導電! 生金屬（銅）來形成配線圖案，亦不會在此配線圖案的 側土底。p，形成沿著長度方向之凹入部，而能夠形成具有 大致垂直於絕緣薄膜表面之側壁之配線圖案。 • —尤其疋，本發明較佳可運用在將配線圖案形成於不具 有疋件孔之厚度丨2至50/zm之絕緣基板的表面之薄膜覆晶 封裝（C0F)。 【實施方式】 接著參照圖式更詳細地說明本發明之印刷電路板。 第1圖係顯示藉由用以製造本發明之印刷電路板時的 製造工序所製得之基板的剖面例之剖面圖。 、如第1圖所示，在製造本發明之印刷電路板時，首先 準備於喊基板1丨的表面上隔著基材金制13配置有導 '電性金屬層15之附有導電性金屬層的絕緣基板（CCL)IO。 在此絕緣基板較佳為聚醯亞胺薄膜或聚酿胺酿亞胺 樹脂薄臈。此絕緣基板特佳為聚醯亞胺薄膜，此情形時， 聚醯亞胺薄财’較耗㈣'蜜錢4與芳㈣二胺所 合成之全芳香族《賴、以及㈣笨四賴二酐盘芳香. 族一胺所合成之具有聯苯骨架之全芳麵魏亞胺。 上述CCL之絕緣薄膜的厚度一般為5幻〇〇_ 為12至75_的範圍内。尤其當本發明之印刷電 =膜裝_時，由於不具有元件孔，並藉由 牙透絕緣_之光量的差來界定形成於 二田 形狀及位置，故特佳係以可確保充分的 量，、圖案的 322068 13 201106809 將絕緣薄膜的厚度設為12至50# m的範圍内。此外，藉由 將具有上述厚度的絕緣薄膜用作為絕緣基板u，在從 CCL10的责面側將搭接工具往絕緣基板11按壓以進行接合 時，可將充分的熱及超音波傳達至連接的引線部分。 上述CCL10的基材金屬層13，一般係運用例如濺鍍 法、真空蒸鍍法等方法，將鎳、鉻等導電性基材金屬形成 於絕緣基板11的表面。 再者，較佳係在上述所形成之基材金屬層13的表面， 形成有由導電性金屬所構成之導電性金屬層15。在此，形 成導電性金屬層15之金屬，較佳為使用鋼或銅合金。 此導電性金屬層15，可藉由將基材金屬層13作為電 極使之電沉積來形成，亦可採用無電解電鍍法來形成。此 外’亦可藉由真空蒸鍍等氣相方法來形成。 第1圖（a)係顯示此種CCL10的典型剖面例。 在此種CCL10中，基材金屬層13的厚度，一般為〇· 〇〇5 至0.04yin，較佳為0.007至0.025以m的範圍内。此外， 形成於此基材金屬層13的表面之導電性金屬層15的厚 度，一般為0. 1至8/zm，較佳為〇. 1至的範圍内。 本發明中，可直接將配線圖案形成於具有此厚度之導電性 金屬層15上，但為了形成精度更佳之配線圖案，較佳係藉 由酸洗等將導電性金屬層15的至少一部分予以去除後，^ 擇性地析出新的導電性金屬來形成配線圖案。本發明中， 以形成導電性金屬層15之金屬而言，若考量到在後續工序 中形成配線圖案時，較佳為銅或銅合金。 322068 14 201106809 當將預先形成於CCL10之導電性金屬層15的至少一部 分予以去除時，形成於CCL10之導電性金屬層15的厚度， 一般係以成為最初所形成之導電性金屬層的0. 1至100%， 較佳為6至100%，特佳為6至99%之方式來去除導電性金 屬。如此將預先形成之導電性金屬層15的一部分予以去除 後，藉由半加成法來形成配線圖案，藉此可形成更鮮明的 配線圖案。第1圖（b)係顯示將導電性金屬層15的一部分 予以去除之狀態的CCL之剖面圖。蝕刻導電性金屬層15時 所用之蝕刻液，只要可均一地溶解導電性金屬者，並無特 別限定，一般較佳係使用以鹽酸等礦物酸為基質並含有氯 化鐵、氣化銅、過水硫酸系化合物等之独刻液。 如上所述，因應必要而將導電性金屬層15的一部分予 以去除後，或是不進行此種導電性金屬層15的去除，即如 第1圖（c)所示，將光阻層20形成於導電性金屬層15的表 面。 以往，當直接將光阻層（感光性樹脂層）20形成於新露 出的導電性金屬層（銅層）15的表面，並將此光阻層20進 行曝光、顯影時，如第7圖所示，於導電性金屬層15與光 阻層20的交界部分，會殘存光阻。如此當光阻殘存時，在 析出導電性金屬之後續工序中，由於在此殘存之光阻部分 使導電性金屬無法析出，所以如第7圖所示，會於析出之 導電性金屬產生側凹（undercut)。如此當產生側凹時，配 線圖案與形成底層之金屬的密著面積將減少，而成為配線 圖案剝離之原因。 15 322068 201106809 本發明中，為了防止此種光阻的殘留而進行種種檢 討，結果，係在前述工序中將導電性金屬進行钱刻以去除 其一部分，將由導電性金屬所構成之層的表面進行整面處 理’並將經整面處理之導電性金屬層的表面進行脫脂處理 後，於3· 5小時内，較佳為3小時内形成光阻層。如此藉 由脫脂處理’可去除位於導電性金屬層表面之氧化物^ 等，將光阻層進行曝光、顯影時所顯影之光阻殘潰不會^ 存於導電性金屬層表面，而形成對於絕緣膜垂直陡立之 阻層側壁。 因此’依循本發明之方法，將導電性金屬層表面進行 脫脂處理後，於3. 5㈣内，較佳為3小時内形成光阻層， 並在進行曝光、㈣後析出導電性金相形成之配線曰圖 案，係具有從絕緣薄膜的表面垂直豎立之陡Λ肖形狀，不會 產生側凹等。因此’㈣以高接著·來接合底層之導電 性金屬與析出之導電性金屬層，#由析出所形成之配線圖 案’不會從基材的導電性金屬剝離。 就上述脫脂工序中所使用之溶劑而言，·一般係使用酸 性清潔劑或有機溶卜在此所用之有機溶劑，係使用可去 除新顯露出之無機酸或形成於導電性金屬層的表面之氧化 膜等雜質之H以此種有機溶劑的例子而言，可列舉出 甲醇、乙醇、異丙醇、正丁醇、乙基溶纖劑等醇類；丙酮、 綱類、嶋。此外，本發日种所狀紐清潔劑，例如可 使用含有3至7容量％硫酸之清潔劑。此等溶劑可單獨使用 或組合使用。可將此種溶劑浸入至布、不織布等，來擦拭 322068 16 201106809 = = = ::表一潰於溶劑中並擦 迷新顯露出之導電性金屬面限:將==往單向擦拭上 面之導電性金屬以外者予以才：字：於導電性金屬層的表 . 聣脂。 拭除，或是浸潰於溶劑中進行 般 將稅===:\序可在常溫下進行’但較佳係 =至㈣秒，較佳為2〇至9()4=溫度，並使溶液接觸 /与潔新顯露出之導電姓冬愿y藉由進仃此種脫脂，可 可維:3.5小時，較佳為維::::。’此表面狀態， 此方式進行脫脂處理 之 小時内將光阻層舖於3. 5小時内，較佳為 面。亦即，藉由在羞脂處理的導電性金屬層表 導電性金屬i的表面匕物或其他成分未附著於新顯露出 光後，於形成光阻層，在進行感光、_ 先阻的殘留膜腳*>屬 橫切面的兩端緣不會產」 地賢立之側壁之配線=形成具有對於絕緣薄膜大致^ C用:=，可使用藉由曝光使曝先部分硬^ 陡。=本Γ由曝光使曝先部分可溶於顯影液之； …光阻層可藉由塗佈光阻墨來形成，亦 4為薄片狀之触薄片予㈣著來形成。 、 圖案==阻層2°的厚度’較佳係與欲形成· u m -尽度大致相同…般為5至、m，較佳為8至i 322068 17 201106809 如此地形成光阻層20後，將形成有期望圖案之遮罩 22配置在光阻層20上，從光源24照射光線，如第1圖（e) 所示，藉此形成由將光阻層20進行曝光、顯影所殘存之光 阻所構成之圖案28。 本發明中，如上所述形成由光阻所構成之圖案後，如 第1圖（f)所示，將電力供應至顯露出於上述圖案28間之 導電性金屬層15，而將再新析出之導電性金屬層15’電沉 積於位在表面之導電性金屬層15的表面。 一般形成於印刷電路板之配線圖案中，如第2圖所 示，由於圖案28寬度的不同，使所形成之配線圖案中，混 合存在有線寬較窄的配線圖案30與線寬較寬的配線圖案 31。線寬較窄的配線圖案30容易形成相對較厚的配線圖 案，而在配線寬度較寬的部分，如第2圖所示，容易形成 相對較薄的配線圖案。如此配線圖案之導電性金屬層的厚 度，當間距（P)寬度較寬時僅有些許差異，不會產生特別問 題。然而，隨著電子零件之安裝密度的提高使間距寬度（P) 變窄，即使是些許之配線圖案的厚度差，亦可能產生問題。 具體而言，在1.個電子零件安裝用的印刷電路板中，線寬 較寬的配線圖案與線寬較窄的配線圖案共存時，由於配線 圖案的厚度不同，使配線圖案的電阻值等亦產生差異，可 能導致電子零件的錯誤動作，此外，當藉由搭接等來確保 與其他裝置的電極間之電性連接時，會有產生造成連接不 良等問題。 因此，本發明中，藉由例如形成虛設配線等，來防止 18 322068 201106809 電解液的集中以及電流密度的上升，而形成均質的配線。 亦即，於本發明，在配線圖案中，間距寬度p係由配 線圖案的線寬與空隙寬度之合計所構成，在間距寬度P成 為50 // m < PS 100 /z m之配線圖案之間配置虛設電極，並將 形成該印刷電路板之配線圖案的導電性金屬的厚度，於8. 5 ·» 至9. 2//m的範圍内進行均一化，而在該導電性金屬之厚度 的範圍内，將構成配線圖案之導電性金屬的厚度進行均一 化。 例如，在間距寬度較寬之處，如第3圖（a)所示，於配 線間形成虛設配線41，藉此可抑制各配線之電流密度的上 升，而獲得均一性高之印刷電路板。 本發明之印刷電路板，係利用上述間距寬度與配線寬 度與析出金屬厚度之關係，於絕緣基板的表面上，隔著基 材金屬層，形成有由導電性金屬所構成之配線寬度不同的 複數個配線圖案。 如第6圖所示，於本發明中，將形成於本發明之印刷 電路板之配線寬度中間距寬度超過50//m且為100//m以下 之配線的配線寬度設為a，將形成於此印刷電路板之虛設 配線的虛設配線寬度設為a’，將忽略形成於此印刷電路板 之虛設配線時之與鄰接配線的距離之配線空隙寬度設為 b，將形成於此印刷電路板之配線與鄰接之虛設配線的距離 之空隙寬度設為b’，將忽略形成於此印刷電路板之虛設配 線時之配線的間距寬度設為P時，藉由使本發明之印刷電 路板滿足下列（1)至（3)所述之條件中的任一條件，可形成 19 322068 201106809 均質的配線圖案。 (1) 所有配線之間距寬度為50//m以下的窄間距寬度。 (2) 所有配線之間距寬度係超過50//in且為1〇〇/zm以 下之寬間距寬度。 (3) 上述印刷電路板中，當配線的間距寬度為50 以 下之配線與配線的間距寬度超過50 // m且為1 〇〇 // m以下之 配線混合存在時，以形成於該印刷電路板之配線寬度中間 距寬度超過50//m且為100/ζιη以下之配線的配線寬度為 a，以形成於該印刷電路板之虛設配線的虛設配線寬度為 a’，以忽略形成於該印刷電路板之虛設配線時之與鄰接之 配線的距離之配線空隙寬度為b’以形成於該印刷電路板 之配線與鄰接之虛設配線的距離之空隙寬度為b，，以忽略 形成於該印刷電路板之虛設配線時之配線的間距寬度為p 時’只要滿足 (A) a/zm^P/z raxO. 5 ' b // P // mxO. 5 ' 25^m^a//m ^ 95 ^ m ； (B) 該印刷電路板具有虛設配線，a+a，" 0. 5 > b ^ mxO. 25 ' 5/zm^a//m^85/zm'5/zin^a, // 85 /z m中之A或B的任一項即可。 尤其在本發明之印刷電路板中，藉由管理線寬與空隙 之比（線寬/空隙），可將導電性金屬的厚度，於8. 5至9. 2 的範圍内進行均一化。 例如，當線寬/空隙寬度為〗.〇以上，較佳為1〇至 1· 2時，導電性金屬的厚度一般為& 6至9 較佳為 20 322068 201106809 8. 6至8· 7 e m的範圍内， 此外，當線寬與空隙之比（線寬/空隙）未it U且為 0.5以上時’導電性金屬的厚度一般為8·6至8 ，較 佳為8.6至8·8/ζιη的範圍内，當線寬與空隙之比（線寬/ .空隙）未達0. 5 ’較佳為0.4/zm以上且未達0 5#m時，導 電性金屬的厚度-般為8. 9至9· 2⑽，較佳為8 9至9. i # m的範圍内。 本發明中，虛設配線為在此印刷電路板中不會形成電 性連接之配線。 本發明中，配線間雖多少會產生些許變動度，但上述 導電性金屬層之厚度的標準差（STDE) 一般為〇15//m以 下，特佳為0.13至0.05em的範圍内。 此外，在上述形成之印刷電路板中，將該配線圖案之 厚度的標準差（STDE)相對於上述配線圖案的平均厚度（AVE；) 之比（STDE/AVE)較佳地調整於〇· 〇〇5至〇. 〇18的範圍内之 配線’該均質性極高，於搭接時可確保穩定的連接，並且 可使配線本身的電阻值穩定地達到一定值。 如此’藉由調整配線寬度與空隙寬度之關係，可消除 被視為半加成法的問題點之析出導電性金屬的厚度不均， 而獲得均一性高的配線圖案。 如此形成之配線，一般為直線地形成於印刷電路板之 内引線或外引線。形成於此種内引線或外引線之配線（引 線）’有時不具有同一線寬，有時配線寬度或間距寬度為不 同之引線相互鄰接而形成。 21 322068 201106809 斤述，第1圖（f)係顯示由形成於此絕緣基板Η 志而^導電性金屬層15，形成於此導電性金屬層15的 有期望形狀的圖案28，以及析出於未形成此圖案 金屬層15的表面之導電性金屬層15，戶斤構成之積 此’導電性金屬層15與析出之導電性金屬層15,， π 鋼或銅合金之同一金屬所形成’導電性金屬層 之導電性金屬層15,呈一體化，所以在本發明 不需特別區分時’係、記載為導電性金屬層15。 藉由將如此形成之積層體進行例如驗洗淨，可去除由 Ζ所構成之圖案28。第1圖⑷係顯示圖案28被去除之 狀態。 上所述，當去除圖案28時，形成有圖案28之部分， 15係顯露出’於其下部則存在有基材金屬層 13 ° *位於形成有圖案28之部分的導電性金屬層，由於非常 的薄所以可藉由與一般的姓刻液進行短時間接觸來去 除此外，此時可將形成基材金屬層13之金屬的一部分， 例如鍊等亦料去除。然而形成基材金屬層U之鉻等金 屬，難以藉由與上述蝕刻液的接觸來完全地去除。此情形 時，經過上述蝕刻工序後，可藉由將此基板與過錳酸鉀之 類的氧化性蝕刻劑進行接觸，來去除鉻等形成基材金屬層 13之金屬，或是進行電性鈍化。 此外，由於可藉由使用氧化性處理液稍微地溶解絕緣 基板表面，所以當例如藉由濺鍍法等來形成基材金屬層 22 322068 201106809 時，可將浸入於絕緣基板表面之基材金屬與絕緣基板表面 一同去除。再者，含有藉由濺鍍法或真空蒸鍍法等來形成 絕緣基板之樹脂中所產生的羥基、醯胺基等之極性基之表 面部分，亦可同時被溶解去除，所以可製得不易產生離子 遷移等所造成的短路之印刷電路板。 Λ 如上所述形成配線圖案後，一般係以使與電子零件連 接之内引線以及連接此配線基板與外部的配線之外引線顯 露出之方式形成防焊層。防焊層，可藉由使用開口成期望 形狀之網版，並塗佈防焊油墨而形成，或是將形成防焊層 之薄膜鑿穿為期望形狀，並貼著於預定位置而形成。 如此形成防焊層後，在從防焊層顯露出之内引線及外 引線的表面，形成錫鍵敷層、焊錫鍍敷層、金鍍敷層、錄 金鍍敷層等鍍敷層。此種鍍敷層的厚度，一般為0. 1至1 /zm，較佳為0.2至0.6/t/in的範圍内。上述說明係關於在 形成防焊層後形成鍍敷層之方法，但鍍敷層可在形成防焊 層前來形成，或是可在形成防焊層前，於配線圖案全體上 形成較薄的鍍敷層，在形成防焊層後，再將鐘敷層形成於 從防焊層顯露出之引線部分上。 如此，本發明之印刷電路板，係將藉由半加成法來形 成配線圖案時所析出之導電性金屬層的厚度，不論配線圖 案的線寬為何，均可調整於一定範圍内。如此，藉由將導 電性金屬層的厚度進行均一化，可將電流流通於配線圖案 時所產生之電阻值控制為一定，而將安定的電力或電性訊 號供應至電子零件，因此可防止電子零件的錯誤動作等。 23 322068 201106809 再者，可藉由半加成法來 減成法（subtractive)相比二性更高的配線圖案。與 線圖案，卻同時也具有所形成之°=形成線寬較細的配 問題，但根據本發明，可 、、圖案的厚度非一定之 電路板。 了$成具有均質性高的細線之印刷 同：：=::，間距寬度或線寬為不 的厚度產生變動之特性度ΐ不同使配線 件之高積體化的進一步發展，乃^者所文裝之電子零 7赞展乃逐漸變得更為重要。 之導路板，係將形成於絕緣薄膜上 層表面之㈣地綱’在形成於該導電性金屬 面之配線圖案的下端部不會形成側凹，配線圖 固地接合於導電性金屬層表面， ^ 生剝離。 I表面戶斤形成之配線圖案不會產 (實施例） 接著顯示本發明之實施例來更詳細地說明本發明，作 本發明並不限定於此等實施例。 一 [實施例1] 首先準備下列CCL，亦即於厚声叩 膜的表面形成有厚度—之“、聚酿亞胺薄 屬層，於此基材金屬層的表面形成 構成之基材金 CCL。 序又丨.m的銅層之 將此CCL的導電性金屬接觸扒 的厚度調整為0.3， 、餘刻液，將導電性金屬 322068 24 201106809 如此將位於表面之導電性金屬予以蝕刻去除後，將新 顯露出之金屬層的表面，含浸於用水將上村工業公司製的 Through Copper ACL-067 稀釋為 13%之液體（30°C)為時 40 秒，以進行脫脂。如此經脫脂後，於1小時後將光阻予以 層合。 a 於如此調整後之CCL的導電性金屬的表面，以使乾燥 厚度成為15/zm之方式將光阻予以層合，並且以使線寬/ 空隙成為第1表所示之方式進行曝光·顯影。 以電子顯微鏡觀察上述經曝光的光阻層，如第9圖的 lh所示，並未產生光阻的殘留膜腳。 在此所形成之配線圖案，為間距寬度50μπι以下之窄 間距的印刷電路板，並未形成虛設電極。 依循一般方法，使用上述圖案，並藉由半加成法來製 造出印刷電路板。 對如此形成之配線圖案的厚度，使用Nikon DigiMicro MD-5C(Nikon公司製）的接觸式膜厚計，對3片的同一處進 行2次的測定。 求取藉由上述方法所形成之印刷電路板之配線圖案的 平均厚度（AVE)、配線圖案之厚度的標準差（STDE)、以及配 線圖案之厚度的標準差（STDE)相對於上述配線圖案的平均 厚度（AVE)之比（STDE/AVE)。 結果如第1表及第5圖所示。 此外，如上所述，由於未產生光阻的殘留膜腳，所以 未產生因殘留膜腳所產生之側凹。 25 322068 201106809 [實施例2] 實施例1中，除了將間距寬度構成如第丨表所示之超 過50# m且為1〇〇以m以下之外，其他以相同方式藉由半力2 成法來製造出印刷電路板。 該實施例2中，亦與實施例丄相同，將位於表面之導 電性金屬予以蝕刻去除後，將新顯露出之金屬層的表面， 含浸於用水將上村工業公司製的Through Copper ACl-067 稀=為13%之液體（30。〇為時40秒，以進行脫脂。如此經 脫脂後’於1小時後將光阻予以層合。 如此形成光阻層後，將光阻進行曝光、顯影並以電子 顯微鏡進行觀察，與第9圖相同，並未產生殘留膜腳。 對所得之印刷電路板，以與實施例1相同之方式測定 配線圖案的厚度。 與貫施例1相同，求取藉由上述方法所测量之印刷電 路板之配線圖案的平均厚度（Ave)、配線圖案之厚度的標準 差（STDE)、以及該配線圖案之厚度的標準差（STDE)相對於 上述配線圖案的平均厚度（AVE)之比（STDE/AVE)。 結果如第.1表及第5圖所示。 此外’使用電子顯微鏡來觀察上述方法所形成之配線 圖案，可得知並未產生側凹。 [實施例3] 除了將間距寬度構成如第1表所示之使5〇以m以下的 窄間距與超過50# m且為100# m以下的寬間距混合存在之 外’其他與實施例1相同，以滿足下列條件之方式來形成。 26 322068 201106809 « a μ, P β mxO. 5 ' b/z mSP/z mxO. 5、 25 // a/i 95// m 此實施例3中’亦與實施例i相同，將位於表面之導 電性金屬予以蝕刻去除後，將新顯露出之金屬層的表面， 含浸於用水將上村工業公司製的Thr〇ugh copper ACL-067 稀釋為13%之液體（30。〇為時40秒，以進行脫脂。如此經 脫月旨後，於1小時後將光阻予以層合。 對所得之印刷電路板，以與實施例1相同之方式測定 配線圖案之導電性金屬的鍍敷厚度。 與實施例1相同’求取藉由上述方法所測定之印刷電 路板之配線圖案的平均厚度（AVE)、配線圖案之厚度的標準 差（STDE)、以及該配線圖案之厚度的標準差（STDE)相對於 上述配線圖案的平均厚度（AVE)之比（STDE/AVE)。 結果如第1表及第5圖所示。 此外，使用電子顯微鏡來觀察上述方法所形成之配線 圖案，可得知並未產生側凹。 [實施例4] 將間距寬度構成如第1表所示之使50 /z m以下的窄間 距與50//Π1以上l〇〇#m以下的寬間距混合存在時，在超過 5〇#m且為100//Π1以下之寬間距的部分（間距寬度i〇〇# m) ’以滿足下列條件之方式來形成虛設圖案。其他條件與 實施例1相同。 如此形成光阻層後’將光阻進行曝光、顯影並以電子 322068 27 201106809 顯微鏡進行觀察，與第9圖相同，並未產生殘留膜腳。 a+ a* β Ρ β mxO. 5 ' bJ β P β mxO. 25 ' 5 /z a // 85 β m ' 5 // mS a’ // mS 85 // m 對所得之印刷電路板，以與實施例1相同之方式測定 配線圖案之導電性金屬的鍍敷厚度。 與實施例1相同，求取藉由上述方法所測定之印刷電 路板之配線圖案的平均厚度（AVE)、配線圖案之厚度的標準 差（STDE)、以及該配線圖案之厚度的標準差（STDE)相對於 上述配線圖案的平均厚度（AVE)之比（STDE/AVE)。 結果如第1表及第5圖所示。 此外，使用電子顯微鏡來觀察上述方法所形成之配線 圖案，可得知並未產生側凹。 [比較例1 ] 除了如第1表所示使20ΑΠ1、30//m、100/zm的間距混 合存在之外，其他與實施例1相同地製造出印刷電路板。 對所得之印刷電路板，以與實施例1相同之方式測定 配線圖案之導電性金屬的鍍敷厚度。 與實施例1相同，求取藉由上述方法所測定之印刷電 路板之配線圖案的平均厚度（AVE)、配線圖案之厚度的標準 差（STDE)、以及該配線圖案之厚度的標準差（STDE)相對於 上述配線圖案的平均厚度（AVE)之比（STDE/AVE)。 結果如第1表及第5圖所示。 28 322068 201106809 [比較例2] 除了如第1表所示，使20 // m、40 // m、75 /z m的間距 混合存在之外，其他與實施例1相同地製造出印刷電路板。 對所得之印刷電路板，以與實施例1相同之方式測定 配線圖案之導電性金屬的鍍敷厚度。 與實施例1相同，求取藉由上述方法所測定之印刷電 路板之配線圖案的平均厚度（AVE)、配線圖案之厚度的標準 差（STDE)、以及該配線圖案之厚度的標準差（STDE)相對於 上述配線圖案的平均厚度（AVE)之比（STDE/AVE)。 結果如第1表所示。 第1表 間距P (//m) 線寬(a) (^m) 空隙(b) (//m) 虚設配線 寬度(a。 (//m) 虛設配線形 成後之空隙 寬度(b’） (㈣） 鍍敷厚度 (㈣） AVE (//m) STDEV (jum) STDEV/AVE 實施例1 20 10 10 無虛設配線 無虛設配線 8.6 8.7 0. 06 0.01 30 15 15 8.7 50 10 40 8.7 實施例2 75 15 60 無虛設配線 無虛設配線 9.0 9. 1 0.12 0.01 100 40 60 9.2 100 20 80 9.2 實施例3 30 15 15 無虛設配線 無虛設配線 8.7 8.8 0.12 0.01 50 20 30 8.9 80 40 40 8.9 實施例4 30 15 15 無虛設配線 無虛設配線 8.7 8.8 0. 12 0.01 50 20 30 8.9 100 40 60 10 25 8.9 比較例1 20 10 10 無虛設配線 無虛設配線 8.6 8.8 0.32 0. 04 30 15 15 8.7 100 40 60 9.2 比較例2 20 10 10 無虛設配線 無虛設配線 8.6 8.8 0.21 0.02 40 20 20 8.7 75 15 60 9.0 29 322068 201106809 從上述第1表所示之結果中，可得知本發明之印刷電 路板所形成之配線圖案的厚度（鍍敷層的厚度）無參差變 化，而形成有均質性高的配線圖案。尤其當並列形成多數 條配線且該配線的間距寬度不同時，以間距寬度50//m為 界而大幅地不同時’根據本發明之印刷電路板，即使間距 寬度大幅地不同，亦可形成具有高均質性的配線圖案。 [實施例5] 除了在實施例1中之脫脂工序後1〇分鐘内貼著光阻薄 片之外，其他以相同方式來形成印刷電路板，該結果係未 觀察到光阻的側凹。 [實施例6] 除了在實施例1中之脫脂工序後2小時貼著光阻薄片 之外，其他以相同方式來形成印刷電路板，該結果幾乎未 觀察到光阻的殘留膜腳。 [實施例7] 除了在實施例1中之脫脂工序後3小時貼著光阻薄片 之外，其他以相同方式來形成印刷電路板，該結果係僅觀 察到些許光阻的殘留膜腳。 [實施例8] 除了在實施例1中之脫脂工序後3小時15分鐘貼著光 阻薄片之外，其他以相同方式來形成印刷電路板，該結果 係雖僅觀察到些許光阻的殘留膜腳，但並未產生足以導致 配線圖案剝離強度降低之程度的較大殘留膜腳。 [比較例3至7] 322068 30 201106809 於實施例1中之脫脂工序後經過4小時（4h、比較例 3)，7小時（7h、比較例4)，18小時（18h、比較例5)，20 小時（20h、比較例6) ’ 24小時（24h、比較例7)後，於貼 著光阻薄片後進行曝光、顯影，並以與實施例1相同之方 式來觀察此時的殘留膜腳狀態。 脫脂後經過4小時後，殘留膜腳的殘留較顯著，即使 超過4小時，殘留膜腳的產生程度亦未大幅增加。 然而，在處理後經過1小時後貼著光阻薄片之實施例 中’光阻_諸腳極少，因此..，可得知藉由利用半加成 法’在所形成之配線圖案的側壁底部不易形成侧凹部。尤 其田在3. 5小時内，較佳為3小時内形成光阻膜時，幾乎 不會產生側凹，相對於此，t在脫脂後超過4小時後形成 光阻膜時’隨著時間的經過，側凹會增大，大約至Μ小時 為止’側凹會隨著時間的經過而增大，但當超㉟Μ 時，側凹的增大變得不怎麼顯著。 【圖式簡單說明】 之印刷電路板時之各工 第1圖（a)至（g)為製造本發明 序的剖面圖。 第2圖係示意性誠圖魏敷之電流的獅狀態之 第3圖（a)及⑻係顯示藉由半加成法 金屬厚度進行均-化之.具體方法例。 以之導電性 第4圖係顯示線寬/空隙寬與導電 之關係的曲線圖。 I屬的析出厚度 322068 31 201106809 第5圖係顯示第4表所示之間距、線寬、空隙、鍍敷 厚度之關係的曲線圖。 第6圖係顯示本發明所規定之配線寬度a、虛設配線 寬度a’、配線空隙寬度b、空隙寬度b’、間距寬度P之關 係的圖。 第7圖係顯示藉由以往的方法將感光性樹脂層（乾膜） 鋪設於導電性金屬層的表面，並經由曝光、顯影工序使導 電性金屬析出而得之配線圖案的剖面例之工序圖，其為顯 示形成有產生側凹（Undercut)之配線圖案之工序。 第8圖係顯示依循本發明之方法，將導電性金屬層（銅 層）的表面進行脫脂後，於3小時内將感光性樹脂層（乾膜） 鋪設於導電性金屬層的表面，經由曝光、顯影後，使導電 性金屬析出而得之未產生側凹之本發明工序例之工序圖。 第9圖係顯示依循本發明之方法將導電性金屬層的表 面進行脫脂後至形成感光性樹脂層為止的時間改變時之側 凹（殘留膜腳）的產生狀況之電子顯微鏡照片。 【主要元件符號說明】. 10 CCL 11 絕緣基板 13 基材金屬層 15 導電性金屬層 15， 析出之導電性金屬層 22 遮罩 24 光源 28 圖案 30 線寬較窄的配線圖案 31 線寬較寬的配線圖案 41 虛設配線 42 粗配線 43 細配線 32 322068 201106809 a 形成於印刷電路板之間距寬度超過50//m且為100 以下之配線的配線寬度 a’ 形成於印刷電路板之虛設配線的虛設配線寬度 b 忽略形成於印刷電路板之虛設配線時之與鄰接之配 線的距離之配線空隙寬度 b’ 形成於印刷電路板之配線與鄰接之虛設配線的距離 之空隙寬度 P 忽略形成於印刷電路板之虛設配線時之配線的間距 寬度 33 322068The base metal of Cr is formed of an insulating substrate having a copper layer and a conductive metal layer. Further, the printed circuit board of the present invention can be produced by the following method. In other words, the printed circuit board is formed by disposing a photosensitive resin layer having a pattern into a desired shape on a surface of a conductive layer containing a base metal layer, and selectively depositing a conductive metal layer. a plurality of wiring patterns of a substrate metal layer and a conductive metal layer having different wiring widths and having a desired shape, and having a desired shape, and a conductive metal layer formed on the surface of the insulating substrate via a base metal layer a printed circuit board having a plurality of wiring patterns having different wiring widths, when the printed circuit board is manufactured, when the line width is 5 to 85/zm and the gap width is 15 to 95/m, Forming a photoresist layer in such a manner that a dummy wiring is formed in a gap between the wiring and the adjacent wiring; forming a photoresist layer such that the gap between the wiring and the adjacent dummy wiring is in a range of 5 to 25 #m, and A conductive metal is precipitated. In the above production method, the surface of the conductive metal layer is subjected to degreasing treatment before the formation of the photoresist layer, and then the photoresist layer is formed within 3 hours, whereby the generation of the concave portion can be effectively prevented. (Effect of the Invention) According to the present invention, a pattern of a desired shape is formed by applying a photoresist layer on a surface of a conductive metal layer of an insulating substrate with a conductive metal layer, and exposing and developing the photoresist layer. When the pattern is used as a masking material and a new conductive metal is electrodeposited on the surface of the conductive metal layer to form a desired wiring pattern, the conductivity of the electrodeposition can be controlled by the line width or the pitch width of the wiring pattern. The amount of the metallic metal is such that the thickness of the deposited conductive metal is less. Therefore, according to the present invention, a printed circuit board having high uniformity can be obtained. In particular, according to the present invention, the photoresist layer is formed within 3 hours after the surface of the conductive metal layer is degreased, and when the photoresist layer is exposed and developed, the photoresist which is supposed to be removed by development is not It will remain on the surface of the conductive metal layer of 12 322068 201106809. Therefore, even if a new conductive metal (copper) is formed by semi-addition to form a wiring pattern, it will not be on the side of the wiring pattern. p, forming a concave portion along the longitudinal direction, and forming a wiring pattern having a side wall substantially perpendicular to the surface of the insulating film. • In particular, the present invention is preferably applied to a film flip chip package (C0F) in which a wiring pattern is formed on the surface of an insulating substrate having a thickness of 丨2 to 50/zm which does not have a mesh hole. [Embodiment] Next, a printed circuit board of the present invention will be described in more detail with reference to the drawings. Fig. 1 is a cross-sectional view showing a cross-sectional view of a substrate obtained by a manufacturing process for producing a printed circuit board of the present invention. As shown in FIG. 1, when manufacturing the printed circuit board of the present invention, first, a conductive metal having a conductive metal layer 15 disposed on the surface of the substrate 1 is placed on the surface of the substrate 1 . Layer of insulating substrate (CCL) IO. The insulating substrate is preferably a polyimide film or a polyacrylamide resin. The insulating substrate is particularly preferably a polyimide film. In this case, the polythenemine is less expensive (four) 'miney money 4 and the aromatic (tetra) diamine is synthesized as a wholly aromatic "Lai, and (four) stupid four Aromatic scent of aromatic anhydride. A wholly aromatic flavonoid having a biphenyl skeleton synthesized by a monoamine. The thickness of the insulating film of the above CCL is generally in the range of 5 〇〇 _ of 12 to 75 Å. In particular, when the printed circuit of the present invention is a film package, since it has no element holes and is defined by the difference in the amount of light of the toothed insulation, it is formed in the shape and position of the second field, so that a sufficient amount can be secured. , 322068 13 201106809 The thickness of the insulating film is set in the range of 12 to 50 # m. Further, by using the insulating film having the above-described thickness as the insulating substrate u, when the bonding tool is pressed from the surface of the CCL 10 to the insulating substrate 11 to be bonded, sufficient heat and ultrasonic waves can be transmitted to the connected. Lead part. The base metal layer 13 of the CCL 10 is generally formed of a conductive base material such as nickel or chromium on the surface of the insulating substrate 11 by a method such as a sputtering method or a vacuum deposition method. Further, it is preferable that the conductive metal layer 15 made of a conductive metal is formed on the surface of the base metal layer 13 formed as described above. Here, the metal forming the conductive metal layer 15 is preferably steel or a copper alloy. The conductive metal layer 15 can be formed by electrodepositing the base metal layer 13 as an electrode, or can be formed by electroless plating. Further, it can also be formed by a vapor phase method such as vacuum evaporation. Fig. 1(a) shows an example of a typical cross section of such a CCL 10. In such a CCL 10, the thickness of the base metal layer 13 is generally in the range of 〇·5 to 0.04 yin, preferably 0.007 to 0.025 in the range of m. The thickness of the conductive metal layer 15 formed on the surface of the base metal layer 13 is generally from 0.1 to 8/zm, preferably from 0.1 to 1. In the present invention, the wiring pattern can be directly formed on the conductive metal layer 15 having the thickness. However, in order to form a wiring pattern having higher precision, it is preferable to remove at least a portion of the conductive metal layer 15 by pickling or the like. Thereafter, a new conductive metal is selectively deposited to form a wiring pattern. In the present invention, in the case of forming the wiring pattern in the subsequent step, the metal forming the conductive metal layer 15 is preferably copper or a copper alloy. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The conductive metal is removed to 100%, preferably 6 to 100%, particularly preferably 6 to 99%. By removing a part of the conductive metal layer 15 which is formed in advance, the wiring pattern is formed by a semi-additive method, whereby a sharper wiring pattern can be formed. Fig. 1(b) is a cross-sectional view showing the CCL in a state in which a part of the conductive metal layer 15 is removed. The etching liquid used for etching the conductive metal layer 15 is not particularly limited as long as it can uniformly dissolve the conductive metal, and it is generally preferred to use a mineral acid such as hydrochloric acid as a matrix and contain ferric chloride, vaporized copper, and An exclusive liquid such as a water sulfuric acid compound. As described above, if a part of the conductive metal layer 15 is removed as necessary, or the removal of the conductive metal layer 15 is not performed, the photoresist layer 20 is formed as shown in FIG. 1(c). On the surface of the conductive metal layer 15. Conventionally, when a photoresist layer (photosensitive resin layer) 20 is directly formed on the surface of a newly exposed conductive metal layer (copper layer) 15, and the photoresist layer 20 is exposed and developed, as shown in FIG. It is shown that a photoresist remains in the boundary portion between the conductive metal layer 15 and the photoresist layer 20. When the photoresist remains in this manner, in the subsequent step of depositing the conductive metal, the conductive metal cannot be deposited in the remaining photoresist portion. Therefore, as shown in Fig. 7, the conductive metal is deposited on the deposited side. (undercut). When the undercut is generated in this way, the adhesion area between the wiring pattern and the metal forming the underlayer is reduced, which causes the wiring pattern to peel off. In the present invention, in order to prevent the residual of such a photoresist, various investigations are performed. As a result, in the step, the conductive metal is burned to remove a part thereof, and the surface of the layer made of the conductive metal is subjected to a surface. After the entire surface treatment is performed and the surface of the conductive metal layer which has been subjected to the entire surface is subjected to degreasing treatment, the photoresist layer is formed within 3 hours, preferably within 3 hours. Thus, by removing the oxides on the surface of the conductive metal layer by the degreasing treatment, the photoresist residue developed when the photoresist layer is exposed and developed is not deposited on the surface of the conductive metal layer, thereby forming a The insulating film is vertically staggered to the side wall of the barrier layer. Therefore, according to the method of the present invention, after the surface of the conductive metal layer is degreased, a photoresist layer is formed in 3.5 (4), preferably within 3 hours, and after exposure, (4), a conductive metal phase is formed. The wiring pattern has a steep shape which is vertically erected from the surface of the insulating film, and does not cause undercut or the like. Therefore, (4) the conductive metal of the underlayer and the deposited conductive metal layer are joined with high adhesion, and the wiring pattern formed by the precipitation is not peeled off from the conductive metal of the substrate. In the solvent used in the degreasing step, generally, an acidic detergent or an organic solvent used in the organic solvent is used, and the newly exposed inorganic acid or the surface of the conductive metal layer can be removed. Examples of such an organic solvent as H of an impurity such as an oxide film include alcohols such as methanol, ethanol, isopropanol, n-butanol, and ethyl cellosolve; acetone, a class, and an anthracene. Further, as the detergent of the present invention, for example, a detergent containing 3 to 7 % by volume of sulfuric acid can be used. These solvents may be used singly or in combination. This solvent can be immersed in cloth, non-woven fabric, etc., to wipe 322068 16 201106809 = = = :: Table 1 collapsed in the solvent and rubbed the exposed conductive metal surface limit: == wipe in one direction Other than conductive metal: word: on the surface of the conductive metal layer. Rouge. Erasing, or immersing in a solvent, the tax ===:\ sequence can be carried out at room temperature 'but preferably = to (four) seconds, preferably 2 to 9 () 4 = temperature, and Solution contact / with the new conductivity revealed by the new name winter wish y by entering this degreasing, cocoa dimension: 3.5 hours, preferably dimension::::. 5小时内优选优选面。 In this surface state, in this manner, the photoresist layer is placed within 3.5 hours, preferably the surface. That is, the surface of the conductive metal i on the conductive metal layer treated with the shame is not adhered to the newly exposed light, and then the photoresist layer is formed, and the residual film is exposed. The foot*> is not produced at both ends of the cross section. The wiring of the side wall of the ground is formed with the use of the insulating film: =, the exposure portion can be hardened by exposure. = The exposure is such that the exposed portion is soluble in the developer; the photoresist layer can be formed by coating a photoresist ink, and 4 is a sheet-like contact sheet (4). The pattern == the thickness of the resist layer 2° is preferably substantially the same as the thickness to be formed. um - the degree is generally 5 to m, preferably 8 to i 322068 17 201106809 After the photoresist layer 20 is thus formed, The mask 22 having the desired pattern is disposed on the photoresist layer 20, and the light is irradiated from the light source 24, as shown in FIG. 1(e), thereby forming light remaining by exposure and development of the photoresist layer 20. The pattern 28 formed by the resistance. In the present invention, after the pattern formed of the photoresist is formed as described above, as shown in Fig. 1(f), electric power is supplied to the conductive metal layer 15 exposed between the patterns 28, and the precipitate is newly deposited. The conductive metal layer 15' is electrodeposited on the surface of the conductive metal layer 15 located on the surface. Generally, it is formed in the wiring pattern of the printed circuit board. As shown in FIG. 2, due to the difference in the width of the pattern 28, the wiring pattern 30 having a narrow line width and the wiring having a wide line width are mixed in the formed wiring pattern. Pattern 31. The wiring pattern 30 having a narrow line width tends to form a relatively thick wiring pattern, and in the portion where the wiring width is wide, as shown in Fig. 2, a relatively thin wiring pattern is easily formed. The thickness of the conductive metal layer of such a wiring pattern is only slightly different when the pitch (P) width is wide, and no particular problem occurs. However, as the mounting density of the electronic component is increased, the pitch width (P) is narrowed, and even a slight difference in the thickness of the wiring pattern may cause a problem. Specifically, in a printed circuit board for mounting an electronic component, when a wiring pattern having a wide line width and a wiring pattern having a narrow line width coexist, the resistance value of the wiring pattern is changed depending on the thickness of the wiring pattern. There is also a difference, which may cause malfunction of the electronic component. Further, when the electrical connection with the electrodes of other devices is ensured by lapping or the like, there is a problem that connection failure occurs. Therefore, in the present invention, by forming a dummy wiring or the like, for example, the concentration of the electrolyte and the increase in the current density of 18 322068 201106809 are prevented, and a uniform wiring is formed. That is, in the present invention, in the wiring pattern, the pitch width p is composed of the total of the line width and the gap width of the wiring pattern, and the pitch width P becomes 50 // m. < The thickness of the conductive metal of the wiring pattern of the printed circuit board is arranged between the wiring patterns of the PS 100 /zm, and the thickness of the conductive metal forming the wiring pattern of the printed circuit board is uniform in the range of 8.5 ·» to 9. 2 / / m The thickness of the conductive metal constituting the wiring pattern is made uniform in the range of the thickness of the conductive metal. For example, in the case where the pitch width is wide, as shown in Fig. 3(a), the dummy wiring 41 is formed between the wiring lines, whereby the increase in current density of each wiring can be suppressed, and a printed circuit board having high uniformity can be obtained. In the printed circuit board of the present invention, the relationship between the pitch width and the wiring width and the thickness of the deposited metal is formed on the surface of the insulating substrate via a base metal layer, and a plurality of wiring widths composed of conductive metals are formed. Wiring patterns. As shown in Fig. 6, in the wiring width of the printed circuit board of the present invention, the wiring width of the wiring having a pitch width of more than 50 / / m and 100 / / m or less is set to a, and will be formed. The dummy wiring width of the dummy wiring of the printed circuit board is set to a', and the wiring gap width of the distance from the adjacent wiring when the dummy wiring formed on the printed circuit board is ignored is set to b, which will be formed on the printed circuit board. When the width of the gap between the wiring and the adjacent dummy wiring is b', and the pitch width of the wiring when the dummy wiring formed on the printed circuit board is neglected is P, the printed circuit board of the present invention satisfies the following Any of the conditions described in (1) to (3) can form a uniform wiring pattern of 19 322068 201106809. (1) A narrow pitch width between all wirings with a width of 50//m or less. (2) The width between all wirings is more than 50//in and the width is wider than 1〇〇/zm. (3) In the above printed circuit board, when wirings having a pitch width of 50 or less and a pitch width of wirings of more than 50 // m and less than 1 〇〇//m are mixed, the printed circuit is formed in the printed circuit In the wiring width of the board, the wiring width of the wiring having a pitch width of more than 50/m and being 100/inch or less is a, and the dummy wiring width of the dummy wiring formed on the printed circuit board is a', ignoring the printing. The wiring gap width of the distance from the adjacent wiring when the dummy wiring of the circuit board is b' is such that the gap width between the wiring formed on the printed circuit board and the adjacent dummy wiring is b, and is omitted from being formed on the printed circuit When the pitch width of the wiring of the dummy wiring of the board is p, 'as long as it satisfies (A) a/zm^P/z raxO. 5 ' b // P // mxO. 5 ' 25^m^a//m ^ 95 ^ m ; (B) The printed circuit board has dummy wiring, a+a, " 0. 5 > b ^ mxO. 25 ' 5/zm^a//m^85/zm'5/zin^a, // Any of A or B in 85 /zm.至范围内的范围内。 In the range of 8.5 to 9. 2, the thickness of the conductive metal is uniform. For example, when the line width/void width is 〇.〇 or more, preferably 1〇 to 1-2, the thickness of the conductive metal is generally & 6 to 9 and preferably 20 322068 201106809 8. 6 to 8·7 In the range of em, in addition, when the ratio of line width to void (line width/void) is not it U and is 0.5 or more, the thickness of the conductive metal is generally from 8.6 to 8, preferably from 8.6 to 8. 8 In the range of /ζιη, when the ratio of line width to void (line width / gap) is less than 0.5. 5' is preferably 0.4/zm or more and less than 0 5#m, the thickness of the conductive metal is generally 8. 9 to 9 · 2 (10), preferably in the range of 8 9 to 9. i # m. In the present invention, the dummy wiring is a wiring in which the electrical connection is not formed in the printed circuit board. In the present invention, although some variation occurs in the wiring compartment, the standard deviation (STDE) of the thickness of the above-mentioned conductive metal layer is generally 〇15//m or less, and particularly preferably in the range of 0.13 to 0.05 em. Further, in the printed circuit board formed as described above, the ratio (STDE/AVE) of the standard deviation (STDE) of the thickness of the wiring pattern to the average thickness (AVE;) of the wiring pattern is preferably adjusted to 〇·〇 〇5 to 〇. Wiring within the range of 〇18' is extremely high in homogeneity, ensuring a stable connection when lapped, and allowing the resistance value of the wiring itself to stably reach a certain value. By adjusting the relationship between the wiring width and the gap width, the thickness unevenness of the deposited conductive metal, which is considered to be a problem of the semi-additive method, can be eliminated, and a wiring pattern having high uniformity can be obtained. The wiring thus formed is generally formed in a straight line or an outer lead in a printed circuit board. The wiring (lead) formed in such an inner lead or outer lead may not have the same line width, and the wiring width or the pitch width may be formed by making the lead adjacent to each other. 21 322068 201106809 Φ, Fig. 1(f) shows a pattern 28 having a desired shape formed on the conductive metal layer 15 by the insulating substrate layer formed thereon, and the pattern 28 having a desired shape The conductive metal layer 15 forming the surface of the patterned metal layer 15 is formed by the 'electroconductive metal layer 15 and the deposited conductive metal layer 15, the same metal of the π steel or the copper alloy. Since the conductive metal layer 15 of the metal layer is integrated, it is described as the conductive metal layer 15 when the present invention is not particularly distinguished. The pattern 28 composed of ruthenium can be removed by, for example, performing the cleaning of the layered body thus formed. Fig. 1 (4) shows the state in which the pattern 28 is removed. As described above, when the pattern 28 is removed, a portion of the pattern 28 is formed, and the 15 series reveals that there is a base metal layer 13 ° at the lower portion thereof * a conductive metal layer located at a portion where the pattern 28 is formed, since The thinness can be removed by short-time contact with a general surname engraving, and at this time, a part of the metal forming the base metal layer 13, such as a chain, can be removed. However, a metal such as chromium which forms the base metal layer U is difficult to be completely removed by contact with the above etching liquid. In this case, after the etching step, the substrate may be brought into contact with an oxidizing etchant such as potassium permanganate to remove the metal forming the base metal layer 13 such as chromium, or be electrically passivated. . Further, since the surface of the insulating substrate can be slightly dissolved by using the oxidizing treatment liquid, when the base metal layer 22 322068 201106809 is formed by, for example, sputtering, the base metal immersed in the surface of the insulating substrate can be The surface of the insulating substrate is removed together. Further, the surface portion of the polar group such as a hydroxyl group or a mercapto group which is formed in the resin which forms the insulating substrate by a sputtering method or a vacuum deposition method can be dissolved and removed at the same time, so that it can be easily produced. A printed circuit board that generates a short circuit caused by ion migration or the like.形成 After forming the wiring pattern as described above, the solder resist layer is generally formed so that the inner leads connected to the electronic components and the leads outside the wiring connecting the wiring board and the outside are exposed. The solder resist layer can be formed by using a screen which is opened to a desired shape and coated with a solder resist ink, or by cutting a film forming the solder resist layer into a desired shape and adhering to a predetermined position. After the solder resist layer is formed in this manner, a plating layer such as a tin bond layer, a solder plating layer, a gold plating layer, or a gold plating layer is formed on the surface of the inner lead and the outer lead which are exposed from the solder resist layer. The thickness of such a plating layer is generally from 0.1 to 1 /zm, preferably from 0.2 to 0.6 / t / in. The above description relates to a method of forming a plating layer after forming a solder resist layer, but the plating layer may be formed before the solder resist layer is formed, or may be formed thin on the entire wiring pattern before forming the solder resist layer. After forming the solder resist layer, the plating layer is formed on the lead portion exposed from the solder resist layer. As described above, in the printed circuit board of the present invention, the thickness of the conductive metal layer deposited when the wiring pattern is formed by the semi-additive method can be adjusted within a certain range regardless of the line width of the wiring pattern. By uniformizing the thickness of the conductive metal layer, the resistance value generated when the current flows through the wiring pattern can be controlled to be constant, and the stable electric power or electrical signal can be supplied to the electronic component, thereby preventing the electrons. Wrong action of the part, etc. 23 322068 201106809 Furthermore, a semi-additive method can be used to reduce the number of wiring patterns that are higher than the two. At the same time, the line pattern has the problem of forming a thin line with a smaller line width. However, according to the present invention, the thickness of the pattern is not constant. The printing of the thin line with high homogeneity is the same as::=::, the width of the pitch or the width of the line is not the thickness of the characteristic change, the further development of the high integration of the wiring member is The electronic zero 7 praise exhibition of the text is gradually becoming more important. The guide plate is formed on the surface of the upper surface of the insulating film, and the underside of the wiring pattern formed on the conductive metal surface does not form an undercut, and the wiring pattern is fixedly bonded to the surface of the conductive metal layer. ^ Raw stripping. The wiring pattern formed by the surface of the present invention is not produced. (Embodiment) The present invention will be described in more detail by showing the embodiments of the present invention, and the present invention is not limited to the embodiments. [Example 1] First, the following CCL was prepared, that is, a thickness of the thickened enamel film was formed on the surface of the thick enamel film, and the surface of the base metal layer was formed into a substrate gold CCL. The thickness of the conductive metal contact C of the CCL is adjusted to 0.3, and the remaining liquid, the conductive metal 322068 24 201106809, after etching the conductive metal on the surface, The surface of the newly exposed metal layer was immersed in water to dilute the Thorough Copper ACL-067 manufactured by Shangcun Industrial Co., Ltd. into a 13% liquid (30 ° C) for 40 seconds for degreasing. After one hour, the photoresist was laminated. a The surface of the conductive metal of the CCL thus adjusted was laminated so that the dry thickness became 15/zm, and the line width/void became the first Exposure and development were carried out in the manner shown in Table 1. The exposed photoresist layer was observed under an electron microscope, and the residual film leg of the photoresist was not formed as shown by lh in Fig. 9. The wiring pattern formed here was For a pitch width of 50 μπι or less A printed circuit board having a pitch does not form a dummy electrode. According to a general method, the above pattern is used, and a printed circuit board is manufactured by a semi-additive method. For the thickness of the wiring pattern thus formed, a Nikon DigiMicro MD-5C ( The contact-type film thickness meter manufactured by Nikon Co., Ltd. measured the same place of three sheets twice. The average thickness (AVE) of the wiring pattern of the printed circuit board formed by the above method and the thickness of the wiring pattern were determined. The standard deviation (STDE) and the ratio of the standard deviation (STDE) of the thickness of the wiring pattern to the average thickness (AVE) of the wiring pattern (STDE/AVE). The results are shown in Tables 1 and 5. As described above, since the residual film leg of the photoresist is not generated, the undercut due to the residual film leg is not generated. 25 322068 201106809 [Embodiment 2] In the embodiment 1, except that the pitch width is constituted as in the table The printed circuit board is manufactured by the half force 2 method in the same manner except that it is more than 50 # m and is 1 〇〇 or less. In the second embodiment, it is also the same as the embodiment , Surface conduction After the metal was etched and removed, the surface of the newly exposed metal layer was impregnated with a liquid of 13% by weight of the After Copper ACl-067 manufactured by Uemura Kogyo Co., Ltd. for 30 seconds for degreasing. After the degreasing, the photoresist was laminated after 1 hour. After the photoresist layer was formed, the photoresist was exposed, developed, and observed under an electron microscope. As in Fig. 9, no residual film leg was produced. The thickness of the wiring pattern was measured in the same manner as in Example 1 on the obtained printed circuit board. The average thickness (Ave) of the wiring pattern of the printed circuit board measured by the above method, the standard deviation (STDE) of the thickness of the wiring pattern, and the standard deviation of the thickness of the wiring pattern were determined in the same manner as in Example 1. STDE) The ratio of the average thickness (AVE) of the above wiring pattern (STDE/AVE). The results are shown in Tables 1 and 5. Further, it was found that the undercut was not produced by observing the wiring pattern formed by the above method using an electron microscope. [Embodiment 3] Other than Embodiment 1 except that the pitch width configuration is such that the narrow pitch of 5 〇 or less and the wide pitch of more than 50 # m and 100 # m or less are mixed as shown in Table 1 The same is formed in such a manner as to satisfy the following conditions. 26 322068 201106809 « a μ, P β mxO. 5 ' b/z mSP/z mxO. 5, 25 // a/i 95// m In this embodiment 3 'is also the same as in example i, will be located on the surface After the conductive metal was etched and removed, the surface of the newly exposed metal layer was immersed in water to dilute the Thr〇ugh copper ACL-067 manufactured by Uemura Kogyo Co., Ltd. into a liquid of 13% (30 〇 for 40 seconds). After degreasing, the photoresist was laminated after 1 hour. The printed circuit board was measured for the plating thickness of the conductive metal of the wiring pattern in the same manner as in Example 1. Example 1 is the same 'determining the average thickness (AVE) of the wiring pattern of the printed circuit board measured by the above method, the standard deviation (STDE) of the thickness of the wiring pattern, and the standard deviation (STDE) of the thickness of the wiring pattern. The ratio of the average thickness (AVE) of the wiring pattern (STDE/AVE). The results are shown in Tables 1 and 5. In addition, the wiring pattern formed by the above method was observed using an electron microscope, and it was found that The undercut is generated. [Embodiment 4] The pitch width is composed as in the first When the narrow pitch of 50 /zm or less is mixed with a wide pitch of 50 / / Π 1 or more and l 〇〇 #m or less as shown in Table 1, the portion having a wide pitch of more than 5 〇 #m and 100//Π1 or less is present. (Pitch width i 〇〇 # m) 'The dummy pattern is formed in such a manner as to satisfy the following conditions. Other conditions are the same as in Embodiment 1. After the photoresist layer is formed, the photoresist is exposed, developed, and electron-converted 322068 27 201106809 microscope Observed, as in Figure 9, no residual film legs were produced. a+ a* β Ρ β mxO. 5 ' bJ β P β mxO. 25 ' 5 /za // 85 β m ' 5 // mS a' / / mS 85 // m The plating thickness of the conductive metal of the wiring pattern was measured in the same manner as in Example 1 on the obtained printed circuit board. The printed circuit measured by the above method was obtained in the same manner as in Example 1. The average thickness (AVE) of the wiring pattern of the board, the standard deviation of the thickness of the wiring pattern (STDE), and the ratio of the standard deviation (STDE) of the thickness of the wiring pattern to the average thickness (AVE) of the wiring pattern (STDE/ AVE). The results are shown in Tables 1 and 5. In addition, using an electron microscope When the wiring pattern formed by the above method was observed, it was found that no undercut was generated. [Comparative Example 1] Except that the pitches of 20ΑΠ1, 30//m, and 100/zm were mixed as shown in the first table, A printed wiring board was produced in the same manner as in Example 1. The plating thickness of the conductive metal of the wiring pattern was measured in the same manner as in Example 1 on the obtained printed circuit board. In the same manner as in the first embodiment, the average thickness (AVE) of the wiring pattern of the printed circuit board measured by the above method, the standard deviation (STDE) of the thickness of the wiring pattern, and the standard deviation of the thickness of the wiring pattern (STDE) were obtained. The ratio (STDE/AVE) of the average thickness (AVE) with respect to the above wiring pattern. The results are shown in Tables 1 and 5. 28 322068 201106809 [Comparative Example 2] A printed circuit board was produced in the same manner as in Example 1 except that the pitches of 20 // m, 40 // m, and 75 /z m were mixed as shown in the first table. With respect to the obtained printed circuit board, the plating thickness of the conductive metal of the wiring pattern was measured in the same manner as in the first embodiment. In the same manner as in the first embodiment, the average thickness (AVE) of the wiring pattern of the printed circuit board measured by the above method, the standard deviation (STDE) of the thickness of the wiring pattern, and the standard deviation of the thickness of the wiring pattern (STDE) were obtained. The ratio (STDE/AVE) of the average thickness (AVE) with respect to the above wiring pattern. The results are shown in Table 1. 1st table pitch P (//m) Line width (a) (^m) Void (b) (//m) Dummy wiring width (a. (//m) Void width after formation of dummy wiring (b' ((4)) Plating thickness ((4)) AVE (//m) STDEV (jum) STDEV/AVE Example 1 20 10 10 No dummy wiring without dummy wiring 8.6 8.7 0. 06 0.01 30 15 15 8.7 50 10 40 8.7 Implementation Example 2 75 15 60 No dummy wiring without dummy wiring 9.0 9. 1 0.12 0.01 100 40 60 9.2 100 20 80 9.2 Example 3 30 15 15 No dummy wiring without dummy wiring 8.7 8.8 0.12 0.01 50 20 30 8.9 80 40 40 8.9 Implementation Example 4 30 15 15 No dummy wiring without dummy wiring 8.7 8.8 0. 12 0.01 50 20 30 8.9 100 40 60 10 25 8.9 Comparative example 1 20 10 10 No dummy wiring without dummy wiring 8.6 8.8 0.32 0. 04 30 15 15 8.7 100 40 60 9.2 Comparative Example 2 20 10 10 No dummy wiring without dummy wiring 8.6 8.8 0.21 0.02 40 20 20 8.7 75 15 60 9.0 29 322068 201106809 From the results shown in Table 1 above, the printed circuit board of the present invention is known. The thickness of the formed wiring pattern (thickness of the plating layer) is not changed unevenly, and a high homogeneity is formed. In particular, when a plurality of wirings are formed in parallel and the pitch width of the wirings is different, and the pitch width is 50//m as a boundary, the printed circuit board according to the present invention has a large difference in pitch width. A wiring pattern having high homogeneity can be formed. [Example 5] A printed circuit board was formed in the same manner except that the photoresist sheet was attached within 1 minute after the degreasing step in Example 1. No undercut of the photoresist was observed. [Example 6] A printed circuit board was formed in the same manner except that the photoresist sheet was attached 2 hours after the degreasing step in Example 1, and the result was hardly observed. Residual film leg of photoresist. [Example 7] A printed circuit board was formed in the same manner except that the photoresist sheet was attached 3 hours after the degreasing step in Example 1, and only a slight light was observed. Residual film leg of the resist. [Example 8] A printed circuit board was formed in the same manner except that the photoresist sheet was attached 3 hours and 15 minutes after the degreasing step in Example 1, and the result was observed only. A small amount of residual film leg of the photoresist, but does not produce a large residual film leg sufficient to cause a decrease in the peeling strength of the wiring pattern. [Comparative Examples 3 to 7] 322068 30 201106809 After 4 hours (4 hours, Comparative Example 3), 7 hours (7 hours, Comparative Example 4), 18 hours (18 hours, Comparative Example 5), after the degreasing step in Example 1, 20 hours (20h, Comparative Example 6) After 24 hours (24h, Comparative Example 7), exposure and development were carried out after the photoresist sheet was attached, and the residual film foot at this time was observed in the same manner as in Example 1. status. After 4 hours from the degreasing, the residual film residue remained remarkable, and even if it exceeded 4 hours, the degree of residual film leg did not increase significantly. However, in the embodiment in which the photoresist sheet is attached one hour after the treatment, the photoresist is extremely small, and therefore, it can be known that the semi-additive method is used at the bottom of the side wall of the formed wiring pattern. It is difficult to form an undercut. In particular, when the photoresist film is formed within 3.5 hours, preferably within 3 hours, the undercut is hardly generated. In contrast, t forms a photoresist film more than 4 hours after degreasing. After that, the undercuts will increase, and the undercut will increase with time until about Μ hours, but when over 35 ,, the increase in undercuts becomes less noticeable. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1(a) to (g) are cross-sectional views showing the order of the present invention. Fig. 2 is a schematic view of the lion state of the current of Wei Wei. Fig. 3 (a) and (8) show the specific method of homogenization by semi-additive metal thickness. Conductivity is shown in Figure 4 as a graph showing the relationship between line width/void width and conductivity. Precipitation thickness of I genus 322068 31 201106809 Fig. 5 is a graph showing the relationship between the distance, the line width, the void, and the plating thickness shown in Table 4. Fig. 6 is a view showing the relationship between the wiring width a, the dummy wiring width a', the wiring gap width b, the gap width b', and the pitch width P defined by the present invention. Fig. 7 is a view showing a cross-sectional view of a wiring pattern obtained by depositing a photosensitive resin layer (dry film) on the surface of a conductive metal layer by a conventional method and depositing a conductive metal through exposure and development steps. This is a process of displaying a wiring pattern in which an undercut is formed. Fig. 8 is a view showing the method of the present invention, after the surface of the conductive metal layer (copper layer) is degreased, the photosensitive resin layer (dry film) is applied to the surface of the conductive metal layer within 3 hours, and exposed. After the development, the conductive metal is deposited to obtain a process diagram of the process example of the present invention in which no undercut is generated. Fig. 9 is an electron micrograph showing the state of occurrence of the undercut (residual film leg) when the surface of the conductive metal layer is degreased to the time when the photosensitive resin layer is formed in accordance with the method of the present invention. [Main component symbol description]. 10 CCL 11 Insulating substrate 13 Substrate metal layer 15 Conductive metal layer 15, Precipitated conductive metal layer 22 Mask 24 Light source 28 Pattern 30 Line pattern with narrow line width 31 Wide line width Wiring pattern 41 dummy wiring 42 thick wiring 43 fine wiring 32 322068 201106809 a The wiring width a' of the wiring formed between the printed circuit boards with a width exceeding 50//m and being 100 or less is formed in the dummy wiring of the printed circuit board. Wiring width b ignoring the gap width b' of the distance from the adjacent wiring when the dummy wiring of the printed circuit board is omitted. The gap width P formed at the distance between the wiring of the printed circuit board and the adjacent dummy wiring is neglected on the printed circuit board. Wiring width of wiring for dummy wiring 33 322068