201105044 六、發明說明： 【發明所屬之技術領域】 本發明為一種數位類比轉換器，特別是一種可以減少 開關數目的數位類比轉換器。 【先前技術】 數位類比轉換器被廣泛的應用在混合模式的系統，其 中類比數位轉換器的作用如同混合模式系統内的數位信號 處理元件與類比信號處理元件之間的介面。 第1圖為傳統的23對2的數位類比轉換器。第1圖的 類比數位轉換器受控於3位元的輸入信號，且輸出電壓V0 與VI是由該輸入信號所決定。傳統的23對2的數位類比 轉換器需要3x23+23 ( 32)個開關元件才能實現。换言之， 一個傳統的2N對2的數位類比轉換器Nx2n+2n個開關元件 才能實現。如果N為10的話，對於數位類比轉換器所需 的開關元件就非常的多，而且電路佈局所要佔用的面積也 隨之增加。 第7圖為一習知的兩級式的N對1的數位類比轉換 器。第7圖所示的數位類比轉換器包括第一數位類比轉換 器（digital-to-analog converter，DAC) 71，受控於輸入信 號的中最南的（n-2 )個位兀’以及一弟二級’該弟二級包 括4個開關，由輸入信號中最低的2個位元。輸入信號中 最低的2個位元用來控制數位類比轉換器的輸出電壓 Vout。雖然傳統的兩級式數位類比轉換器需要較少的開關 元件，但是數位類比轉換器71所需的開關元件還是很多， 201105044 較大的電路佈局面積。因此本發賴供一種數位 =比轉換w的架構，可以使用較少的開關元件就可以實 現0 、 【發明内容】 μ絲^發明的實施例為—種數位類比轉換器，該數位類 具有兩個輸出，且受控於- η位元的輸入信號。 比轉換器包括一參考電壓電路、-第-開關陣 田J、第—開關陣列以及—切換電路。該參考電壓電路， ::=Γ)個參考電壓。該第一開，列，根據該 . . _ _ 電壓該第一開關陣列，接收該等2n Μ ’並根據除該輸人信號中除該第__位元外的複 數個位το、’選擇該等2^個參考電壓中的—第—電壓與 透過：第一輸出端與一第二輸出端輸出， 1+個電壓被直接傳送到第二開關陣列，且 兮笛φ、G 2中的所有奇數。該切換電路，用以輪出 該第一電壓與該第二電壓。 類比實施例為—種數位類比轉換器，該數位 :比轉，具有兩個輸出’且受控於一 η位元的 m位類比轉換器包括n出m : 路、一第一數位類比轉換單元以及一第二數 來老^早^。該參考電壓電路’用以產生（2n+1)個 >電查。該第一數位類比轉換單元，接收第（2i+1)個 201105044 參考電壓’並輸出一第一電摩， 的所有奇數°該第二數位類比轉換單元^為/到2n中 參考電Μ，並輸出-第二電摩，其收第（2n〇個 所有偶數。該第一數位類比轉換單元受控於 入信號中除了-第-位元外的所有位心…讀几的輸 貫施方式】 下文所討論者為本發明所揭露之較佳 說明書在基於本發明之精神以 a ^ ’、、'、 田、^眼座丨士 下列實^例說明，彳曰是並非 用以限制本發明為該等實施 仁疋工 以為本說明書之舉例說明使用，^月所舉之實施例僅用 點。 並非用以限制本發明之觀 第2圖為根據本發明的一 的干音圓^ 數位類比轉換器的一實施例 的不思圖。數位類比轉換器包 21、一 匕括第一數位類比轉換單元 >電1電路24、一第二數位類比轉換單元22以 及一切換電路（ switch circuit) 23。第一數位類比轉換單元 21與第二數位類比轉換單元22受控於一輸入信號si。第2 圖的實施例係以一 23對2的數位類比轉換器為例說明，但 非用以將本發明限於此。 第一數位類比轉換單元21接收參考電壓Vrl、Vr3、 Vr5以及Vr7 ’並根據一輸入信號Sc輸出一電壓γχ。第二 數位類比轉換單元22接收參考電壓Vr2、Vr4、vr6以及 Vr8，並根據輸入信號Sc輸出一電壓Vy。輪入信號Sc包 括位元b0、bl與b2。切換電路23序以輸出電壓V0與VI。 當輸入信號Sc的第一位元b0 (也就是最低位元）為1時， 201105044 電塗 為W ’電壓Vl為Vy。當輸入信號Sc的第一位· 元b〇 (也就是最低位元）為〇時，電壓V0為νγ，電壓— VI 為 Vx。 在第2圖中，所有的奇數電壓，如Vrl、Vr3、Vr5以 及Vr7，被直接傳送到第一數位類比轉換單元21，且第一 數位類比轉換單元21僅受控於輸入信號&的兩個位元， Μ與b2 °所有的偶數電壓VrO、Vr2、Vr4、Vr6以及Vr8， 被傳送到第二數位類比轉換單元22，且第二數位類比轉換 單元22 X控於輪入信號Sc的所有位元。 第3圖為根據本發明的一數位類比轉換器的另一實施 例的不意圖。為了說明書簡潔，第3圖中的詳細電路連接 在此不贅述’但習知技藝者當可了解其運作。第3圖所示 的開關元件係受控於一輪入信號，該輸入信號包括了位元 b0、bl與b2。在第3圖中，所有的奇數電壓，如Vrl、Vr3、 Vr5以及Vr7 ,僅由輸入信號中的兩個位元所決定是否輸 出’因此開關的數目便可以減少。 當輸入信號的第一個位元b0 (也就是最低位元）為0 時，開關SW4、SW8、SW12與SW16被導通。當輸入信 號的第一個位元b0為1時，開關SW1、SW5、SW9與SW13 被導通。當輸入信號的第二個位元bl為1時，開關SW2、 SW17、SW10與SW21被導通。當輸入信號的第二個位元 bl為0時，開關SW6、SW9、SW14與SW23被導通。當 輸入信號的第三個位元b2 (也就是最高位元）為1時， SW3、SW18、SW7與SW20被導通。當輸入信號的第三個 位元b2為0時，SW11、SW22、SW15與SW24被導通。 201105044 當輸入信號的第一個位元b0為0時，切換電路31引導電 壓Vx為電壓VI，且引導電壓VY為電壓V0。··當輸入信號 的第一個位元b0為1時，切換電路31引導電壓Vx為電壓 V0，且引導電壓VY為電壓VI。 表1為第3 .圖的數位類比轉換器的真值表。 輸入信號 切換電路切換前 切換電路切換後 b0 bl b2 Vx VY VO VI 0 0 0 Vrl VrO VrO Vrl 1 0 0 Vrl Vr2 Vrl Vr2 0 1 1 Vr7 Vr6 Vr6 Vr7 1 1 1 Vr7 Yr8 Vr7 Vr8 0 0 1 Vr5 Vr4 Vr4 Vr5 1 0 1 Vr5 Vr6 Vr5 Vr6 0 1 0 Vr3 Vr2 Vr2 Vr3 1 1 0 Vr3 Vr4 Vr3 Vr4 表1 第4圖為根據本發明之一切換電路的一實施例的示意 圖。切換電路包含兩個輸出端N1與N2，分別用以輸出電 壓V0與VI。第一開關S1耦接在端點N1與N3之間。第 二開關S2耦接在端點N2與N4之間。第三開關S3耦接在 端點N2與N3之間。第四開關S4耦接在端點N1與N4之 間。當輸入信號，如第2圖與第3圖中的輸入信號，的第 一個位元b0為0時，第一開關S1與第二開關S2被關閉， 第三.開關S3與第四開關S4被導通。當輸入信號，如第2 圖與第3圖中的輸入信號，的第一個位元b0為1時，第一 201105044 開關S3與第四開關 開關S1與弟一開關S2被導通，·第-三. S4 被關閉。 -201105044 VI. Description of the Invention: [Technical Field] The present invention is a digital analog converter, and more particularly, a digital analog converter capable of reducing the number of switches. [Prior Art] Digital analog converters are widely used in mixed mode systems in which an analog digital converter functions as an interface between a digital signal processing element and an analog signal processing element in a mixed mode system. Figure 1 shows a conventional 23-to-2 digital-to-digital converter. The analog-to-digital converter of Figure 1 is controlled by a 3-bit input signal, and the output voltages V0 and VI are determined by the input signal. The traditional 23-to-2 binary analog converter requires 3x23+23 (32) switching elements. In other words, a conventional 2N to 2 digital analog converter Nx2n + 2n switching elements can be implemented. If N is 10, the number of switching elements required for a digital analog converter is very large, and the area occupied by the circuit layout is also increased. Figure 7 is a conventional two-stage N-to-1 digital-to-analog converter. The digital analog converter shown in FIG. 7 includes a first digital-to-analog converter (DAC) 71 controlled by the southernmost (n-2) bits of the input signal and a The second level of the second grade consists of 4 switches, the lowest 2 bits of the input signal. The lowest 2 bits of the input signal are used to control the output voltage Vout of the digital analog converter. Although the conventional two-stage digital analog converter requires fewer switching elements, the digital analog converter 71 requires a large number of switching elements, and the 201105044 has a large circuit layout area. Therefore, the architecture for a digital=ratio conversion w can be implemented using fewer switching elements. [Invention] The embodiment of the invention is a digital analog converter having two digital analog converters. Outputs, controlled by an input signal of -n bits. The ratio converter includes a reference voltage circuit, a -th switch field J, a first switch array, and a - switching circuit. The reference voltage circuit, ::=Γ) reference voltage. The first open, column, according to the . . _ _ voltage, the first switch array receives the 2n Μ ' and selects according to a plurality of bits το, ' except for the __ bit in the input signal -1 - voltage and transmission of the 2^ reference voltages: the first output terminal and the second output terminal output, 1 + voltages are directly transmitted to the second switch array, and in the flute φ, G 2 All odd numbers. The switching circuit is configured to rotate the first voltage and the second voltage. The analog embodiment is a digital analog converter, the digit: ratio conversion, having two outputs ' and controlled by an n-bit m-bit analog converter including n out m: way, a first digital analog conversion unit And a second number to come to the old ^ early ^. The reference voltage circuit ' is used to generate (2n + 1) > The first digital analog conversion unit receives the (2i+1)th 201105044 reference voltage 'and outputs a first electric motor, and all the odd numbers of the second digital analog conversion unit ^ are /to 2n reference power, and Output - the second electric motor, which receives the second (2n〇 all even numbers. The first digital analog conversion unit is controlled by all the bits except the - the first bit in the incoming signal... The following description of the preferred embodiments of the present invention is illustrated by the following examples in the spirit of the present invention, which is not intended to limit the present invention. The implementations of the present invention are used for the purpose of illustration of the present specification, and the embodiment of the present invention is only for the purpose of limiting the present invention. FIG. 2 is a dry-tone circular analog conversion according to one of the present invention. An embodiment of the apparatus is not to be considered. The digital analog converter package 21, the first digital analog conversion unit > the electrical 1 circuit 24, the second digital analog conversion unit 22, and a switch circuit 23 First digital analog conversion unit 21 The second digital analog conversion unit 22 is controlled by an input signal si. The embodiment of Fig. 2 illustrates a 23 to 2 digital analog converter as an example, but is not intended to limit the invention to this. The first digital analogy The conversion unit 21 receives the reference voltages Vrl, Vr3, Vr5, and Vr7' and outputs a voltage γχ according to an input signal Sc. The second digital analog conversion unit 22 receives the reference voltages Vr2, Vr4, vr6, and Vr8, and outputs a signal according to the input signal Sc. The voltage Vy. The rounding signal Sc includes the bits b0, bl and b2. The switching circuit 23 sequentially outputs the voltages V0 and VI. When the first bit b0 (ie, the lowest bit) of the input signal Sc is 1, 201105044 The voltage V1 is applied as Vy. When the first bit of the input signal Sc, the element b〇 (that is, the lowest bit) is 〇, the voltage V0 is νγ, and the voltage - VI is Vx. In Fig. 2, all The odd voltages, such as Vrl, Vr3, Vr5, and Vr7, are directly transferred to the first digital analog conversion unit 21, and the first digital analog conversion unit 21 is controlled only by the two bits of the input signal & °All even voltages VrO, Vr2, Vr4, Vr6 And Vr8, is transmitted to the second digital analog conversion unit 22, and the second digital analog conversion unit 22 is controlled by all the bits of the round signal Sc. Fig. 3 is another example of a digital analog converter according to the present invention. For the sake of brevity of the description, the detailed circuit connections in FIG. 3 are not described herein again, but the operation of the art can be understood by those skilled in the art. The switching elements shown in FIG. 3 are controlled by a round-in signal. The input signal includes bits b0, bl, and b2. In Figure 3, all odd voltages, such as Vrl, Vr3, Vr5, and Vr7, are determined only by two bits in the input signal. The number can be reduced. When the first bit b0 (ie, the lowest bit) of the input signal is 0, the switches SW4, SW8, SW12, and SW16 are turned on. When the first bit b0 of the input signal is 1, the switches SW1, SW5, SW9, and SW13 are turned on. When the second bit bl of the input signal is 1, the switches SW2, SW17, SW10, and SW21 are turned on. When the second bit bl of the input signal is 0, the switches SW6, SW9, SW14, and SW23 are turned on. When the third bit b2 (i.e., the highest bit) of the input signal is 1, SW3, SW18, SW7, and SW20 are turned on. When the third bit b2 of the input signal is 0, SW11, SW22, SW15, and SW24 are turned on. 201105044 When the first bit b0 of the input signal is 0, the switching circuit 31 directs the voltage Vx to the voltage VI, and the pilot voltage VY is the voltage V0. When the first bit b0 of the input signal is 1, the switching circuit 31 directs the voltage Vx to the voltage V0, and the pilot voltage VY is the voltage VI. Table 1 is the truth table of the digital analog converter of Figure 3. Input signal switching circuit Switching circuit switching before switching b0 bl b2 Vx VY VO VI 0 0 0 Vrl VrO VrO Vrl 1 0 0 Vrl Vr2 Vrl Vr2 0 1 1 Vr7 Vr6 Vr6 Vr7 1 1 1 Vr7 Yr8 Vr7 Vr8 0 0 1 Vr5 Vr4 Vr4 Vr5 1 0 1 Vr5 Vr6 Vr5 Vr6 0 1 0 Vr3 Vr2 Vr2 Vr3 1 1 0 Vr3 Vr4 Vr3 Vr4 Table 1 FIG. 4 is a schematic diagram of an embodiment of a switching circuit according to the present invention. The switching circuit includes two output terminals N1 and N2 for outputting voltages V0 and VI, respectively. The first switch S1 is coupled between the terminals N1 and N3. The second switch S2 is coupled between the terminals N2 and N4. The third switch S3 is coupled between the terminals N2 and N3. The fourth switch S4 is coupled between the terminals N1 and N4. When the input signal, such as the input signal in FIGS. 2 and 3, the first bit b0 is 0, the first switch S1 and the second switch S2 are turned off, and the third switch S3 and the fourth switch S4 Being turned on. When the input signal, such as the input signal in FIGS. 2 and 3, the first bit b0 is 1, the first 201105044 switch S3 and the fourth switch S1 and the second switch S2 are turned on, · - 3. S4 is closed. -
根據第3圖與第4圖所示的電路，本發明所提出的2: 對2的數位類比轉換器只須要2 8個開關元件即可實現，而 傳統的23對2的數位類比轉換器則需$ % <固開J元件。 如果依本發明所提出的架構被應用到-個21。對2的數位類 比轉換II ’則可以節省下（2h)_4)個開關元件。這樣不只 可以簡化2N對2的數位類比轉換器的架構，而且也可以因' 為開關元件的數量減少而節省電路佈局的面積。 第5圖為根據本發明的一數位類比轉換器的另一實施 例的示意圖。為了說明書簡潔，帛5圖中的詳細電路連接 在此不贅述，但習知技藝者當可了解其運作。參考電壓電 路51產生（2n+l)個參考電壓。第一開關陣列％接收並 輸出該尊（2Π+1)個參考電壓巾的2n個參考電壓。第二開 關陣列接收該等2n個參考電壓’根據該n位元的輸入信According to the circuits shown in Figs. 3 and 4, the 2:2 to 2 digital analog converter of the present invention requires only 28 switching elements, and the conventional 23 to 2 digital analog converter Need $ % < to open the J component. If the architecture proposed in accordance with the present invention is applied to -21. The digital analog conversion of II can save (2h)_4) switching elements. This not only simplifies the architecture of the 2N to 2 digital analog converter, but also saves the area of the circuit layout by reducing the number of switching elements. Figure 5 is a schematic illustration of another embodiment of a digital analog converter in accordance with the present invention. For the sake of brevity of the description, the detailed circuit connections in Fig. 5 are not described here, but those skilled in the art can understand the operation thereof. The reference voltage circuit 51 generates (2n + 1) reference voltages. The first switch array % receives and outputs 2n reference voltages of the (2Π+1) reference voltage pads. The second switch array receives the 2n reference voltages according to the n-bit input signal
號’透過一第-輸出端犯輸出一第一電壓〜，以及透過 第一輸出端Ν4輸出一第二電壓νγβ _要注意的是，該等第（21+1)個電壓是直接傳送到第 一開關陣打列’毋需經過第一開關陣列中的開關，其中（^ ) 為〇到2中的所有奇數。更進—步來說，根據輪入信號中 的第一位70 b〇的狀態，第一參考電壓Vr〇與第九參考電壓 中只有—個會被傳送到第二開關陣列53。換言之，當 輸入信號中的第-個位元M)為G時，只有第-參考電壓 VrO被傳达到第二開關陣列幻。當輸入信號中的第一個位 一為1蛉，只有第九參考電壓Vr8被傳送到第二開關陣 201105044 列 53。 一 切換電路54會根據輸入信號中的第一個位元七0"的狀 態，決定將電壓Vx與VY分別傳送到端點N1與N2。當輸 入信號中的第一個位元b0為0時，電壓Vx被傳送到端點 N2且電壓VY被傳送到端點N1。當輸入信號中的第一個位 元b0為1時，電壓Vx被傳送到端點N1且電壓VY被傳送 到端點N2。 第6圖為根據本發明的一數位類比轉換器的另一實施 例的示意圖。與第5圖所示的數位類比轉換器相比，其不 同在於第二開關陣列被換成一二元開關陣列（binary switch array )。為了說明書簡潔，第6 .圖中的詳細電路連接在此 不贅述，但習知技藝者當可了解其運作。第6圖所示的數 位類比轉換器所需的開關元件的數量又較第5圖所示的數 位類比轉換器所需的開關元件的數量來得少。請參考表2。 表2為傳統的2N對2的數位類比轉換器所需的開關元件數 目與本發明所提供的2~對2的數位類比轉換器所需.的開關 元件數目的比較表。 控制信號位元數(η) 所需的開關元件數量 傳統的數位類比轉 第5圖所示的數位 第6圖所示的數位 換器 類比轉換器 類比轉換器 3 32 28 26 4 80 68 50 6 448 388 194 8 2304 2052 770 , 201105044 10 11264 10244 3074 η (η+1)*2η η*2η+4 3*2η+2 表2 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。The number 'outputs a first voltage ~ through a first-output terminal, and outputs a second voltage νγβ through the first output terminal Ν4. It should be noted that the (21+1)th voltage is directly transmitted to the first A switch array is not required to pass through the switches in the first switch array, where (^) is all odds of 〇2. Further, in accordance with the state of the first bit 70b of the rounding signal, only one of the first reference voltage Vr〇 and the ninth reference voltage is transmitted to the second switch array 53. In other words, when the first bit M) of the input signal is G, only the first reference voltage VrO is communicated to the second switch array. When the first bit in the input signal is 1 蛉, only the ninth reference voltage Vr8 is transmitted to the second switch matrix 201105044 column 53. A switching circuit 54 determines to transmit voltages Vx and VY to endpoints N1 and N2, respectively, based on the state of the first bit in the input signal. When the first bit b0 of the input signal is 0, the voltage Vx is transferred to the terminal N2 and the voltage VY is transmitted to the terminal N1. When the first bit b0 of the input signal is 1, the voltage Vx is transferred to the terminal N1 and the voltage VY is transmitted to the terminal N2. Figure 6 is a schematic illustration of another embodiment of a digital analog converter in accordance with the present invention. This differs from the digital analog converter shown in Figure 5 in that the second switch array is replaced by a binary switch array. For the sake of brevity of the description, the detailed circuit connections in Fig. 6 are not described here, but those skilled in the art can understand the operation thereof. The number of switching elements required for the digital analog converter shown in Fig. 6 is smaller than the number of switching elements required for the digital analog converter shown in Fig. 5. Please refer to Table 2. Table 2 is a comparison table of the number of switching elements required for the conventional 2N to 2 digital analog converter and the number of switching elements required for the 2 to 2 digital analog converter provided by the present invention. Number of control signal bits (η) Number of switching elements required Traditional digital analogy to digital display shown in Figure 5 Digital converter analog converter analog converter shown in Figure 6 3 32 28 26 4 80 68 50 6 448 388 194 8 2304 2052 770 , 201105044 10 11264 10244 3074 η (η+1)*2η η*2η+4 3*2η+2 Table 2 Although the present invention has been disclosed above in the preferred embodiment, it is not used The invention is intended to be limited to the scope of the invention, and the scope of the invention is defined by the scope of the appended claims.
11 201105044 【圖式簡單說明】 第1圖為傳統的_23對2的數位類比轉換器。 -.. 第2圖為根據本發明的一數位類比轉換器的一實施例 的不意圖。 第3圖為根據本發明的一數位類比轉換器的另一實施 例的示意圖。 第4圖為根據本發明之一切換電路的一實施例的示意 圖。 第5圖為根據本發明的一數位類比轉換器的另一實施 鲁 例的示意圖。 第6圖為根據本發明的一數位類比轉換器的另一實施 例的示意圖。 第7圖為一習知的兩級式的N對1的數位類比轉換器。 【主要元件符號說明】 21〜第一數位類比轉換單元 22〜第二數位類比轉換單元 籲 23、31〜切換電路 24〜參考電壓電路 51〜參考電壓電路 52〜第一開關陣列 53〜第二開關陣列 54〜切換電路 71〜數位類比轉換器 1211 201105044 [Simple description of the diagram] Figure 1 shows the traditional _23 to 2 digital analog converter. - Figure 2 is a schematic diagram of an embodiment of a digital analog converter in accordance with the present invention. Figure 3 is a schematic illustration of another embodiment of a digital analog converter in accordance with the present invention. Fig. 4 is a schematic view showing an embodiment of a switching circuit according to the present invention. Figure 5 is a schematic illustration of another embodiment of a digital analog converter in accordance with the present invention. Figure 6 is a schematic illustration of another embodiment of a digital analog converter in accordance with the present invention. Figure 7 is a conventional two-stage N-to-1 digital-to-digital converter. [Major component symbol description] 21 to first digital analog conversion unit 22 to second digital analog conversion unit 23, 31 to switching circuit 24 to reference voltage circuit 51 to reference voltage circuit 52 to first switch array 53 to second switch Array 54 to switching circuit 71 to digital analog converter 12