TW201105038A - Static latch - Google Patents

Abstract

A static latch includes a clock-based driver, an actuation circuit, and a weak latched unit. The clock-based driver includes first node, second node, a driving unit, first pass switch, and second pass switch. The driving unit drives the first node corresponding to first voltage in response to first level of an input signal and drives the second node having second voltage in response to second level of the input signal. The first pass switch drives an output node having a latched signal corresponding to the first voltage in response to the clock signal. The second pass switch drives the output node corresponding to the second voltage in response to the inverted clock signal. The actuation circuit drives the output node corresponding to the second voltage in response to the clock signal. The weak latch unit keeps the level of the latched signal when the static latch is disabled.

Description

201105038

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a latch, and more particularly to a static latch applied to a memory. [Prior Art] Referring to Fig. 1 which is a circuit diagram in accordance with a conventional shackle. Conventionally, the latch 1 includes a node N, an inverter iv, a switch pg, and a latching single LL. The inverter IV is responsive to the clock signal CK to generate the inverted clock signal CKB. The switch PG receives the input signal SIN and responds to the high signal level of the clock signal CK and the low signal level of the inverted clock signal CKB to provide the input signal SIN to the node N to establish the voltage signal SV. The pickup unit LL includes a drive inverter DI' for providing a shackle signal QB in response to the voltage signal. The latch unit LL further includes a feedback inverter FBI for inverting the pickup signal QB to the node N, so as to maintain the voltage level of the voltage signal SV and the shackle signal qb. • Both the switch PG and the drive inverter DI require a delay to provide a stable output signal. In other words, when the clock signal CK reaches its high level, the shackle 1 requires an additional two circuit delay times to establish its turn signal (ie, the shackle signal QB). The demand for high speed clock-based operation in existing circuits is increasing. Therefore, in the case where the frequency of the clock signal is increased, the period of the clock signal and the level maintaining time thereof are shortened, and the latching device 1 cannot be caused to generate the pickup signal QB. 201105038

TW5321 PA [Summary of the article j, f too two = 1 is a static lock, used to pick up the lock - signal. rkrdDdver), in response to the input signal, the second actuator is controlled by the clock signal and the inverted clock signal to provide the pickup signal. The static shackle associated with the present invention applies an activation circuit (Actuation~ Circuit) to drive the pickup signal together with the pulse drive type driver. Compared with the conventional shackle, the static occlusion device related to the present invention can shorten the delay time required to drive the shackle signal (from the time when the clock signal is triggered to the time when the data is correct). According to an aspect of the present invention, A static shackle is proposed, which comprises a clock-based driver, an first trigger circuit and an atch lock unit (Latch Uni 〇. The clock-driven driver includes a first node and a second node a driving unit, the first and second switches, the driving unit is configured to provide the first voltage to the first node in response to the first level of the input signal, and provide the second voltage to the second level in response to the second level of the input signal The first switch is configured to provide a first voltage on the first node to the output node in response to the clock signal, so that the level of the latch signal on the output node corresponds to the first voltage. The second switch is responsive to the reverse The phase clock signal provides a second voltage on the second node to the output node, and the level of the shackle signal corresponds to the first voltage. The first trigger circuit is configured to provide a second response to the clock signal Pointing the second voltage to the output node. The latching unit is configured to maintain the level of the pick-up signal when the clock signal is disabled. According to another aspect of the present invention, a static latch is provided, including a driver, a first trigger circuit and a shackle unit. The driver is responsive to the input

201105038 ..TW5321PA ;Electric ^P-Node' and responds (4) Responding to the second driver of the turn-in signal, the pulse signal is provided to the second electrical calendar on the second node to the output of the flute (four) transmitting circuit for responding to the clock signal Providing the ==: quasi-pick-up unit on the second node - for non-enabling, in order to make the above content of the present invention more apparent, the following is a detailed description of the preferred embodiment' The description is as follows: [Embodiment] The static lock device according to the embodiment of the present invention applies a clock-driven driver (Clock-based Driver) to respond to the round-in signal, and the pulse-driven driver is controlled by the clock signal and the reverse phase. The clock is reduced to provide the pickup signal. The static locker is further applied with a trigger circuit (Actuati〇n, which drives the latch signal together with the pulse drive driver. The first embodiment refers to FIG. 2, and the The circuit diagram of the static lock detector of the first embodiment of the invention is controlled by the clock signal Clk and the phase clock signal CLKB, and is used for storing the shackles on the output node NDO in response to the input signal & Signal SQB. Example In other words, the static lock device 2 includes an inverted HIIW for generating an inverted clock signal CLKB according to the clock signal. The static lock device 2 includes a clock drive driver (a〇ck_based Driver) 22, a trigger circuit or a trigger. 24 and low driving force lock unit 201105038

TW5321PA (WeaklatChUnit) 26. The clock drive type driver 22, the drive circuit 24' and the low drive force lock unit 26 are both coupled to the output node ND. The clock drive type drive 22 includes nodes Nm, ND2, drive unit 22a, and open M 22b and 22c. The drive unit melon and the switch are uncoupled to the defect ND1. The drive unit 22a and the switch 22c are lightly connected to the node ND2. The driving unit 22a supplies the voltage VI to the node nDi in response to the first level of the rounding signal SI (for example, a high signal level). For example, the voltage vi is the ground voltage. The driving unit 22a supplies the voltage V2 to the node in response to the second level of the input signal si (e.g., the low signal level). For example, the voltage V2 is the power supply voltage of the static snubber 2 having a high voltage level. For example, the drive unit 22a includes an N-type metal.

Oxide Semiconductor ' NMOS ) transistor T1 and P_type Metal Oxide Semiconductor ' PMOS transistor T2. The electric day and body T1 includes a gate, a source, and a drain, and receives an input signal SI, a receiving voltage VI, and a node ND1, respectively. The transistor T1 supplies a voltage V1 (ie, a ground voltage) to the node ND1 according to the first level of the input signal SI (ie, the high signal level). The transistor T2 includes a signal pole, a source and a drain, and receives the input signal SI, the receiving voltage V2, and the node ND2, respectively. The transistor T2 supplies a voltage V2 (i.e., a power supply voltage) to the node ND2 according to the second level of the input signal SI (i.e., the low signal level). Since the input signal SI can only be one of the high signal level or the low signal level in the operation of the static lock device 2, only one of the transistors T1 and T2 is turned on, and the transistors T1 and T2 are among them. The other is to close 'so that the corresponding node (ie ND1 or ND2) is floating 201105038

. :TW5321PA (Floating). The switch 22b drives the output terminal ND〇 in response to the clock signal CLK providing a voltage substantially equal to the voltage VI on the node nd 1 such that the level of the 拴 lock = number SQB corresponds to the voltage VI. For example, the switch 22b includes an NMOS transistor, and the gate, the source, and the drain receive the clock signal CLK, the node ND1, and the output terminal nD0, respectively. The switch 22b is turned on in response to the high signal level of the clock signal CLK to provide the voltage on the node ND1 to the output node ND〇. If the input signal is audibly high, the voltage on node ND1 (i.e., the ground voltage) is supplied to the wheel: NDO ’ so the pickup signal SQB is driven to the ground voltage. The switch 22c drives the output terminal ND〇 in response to the inverted clock signal CLKB providing a voltage on the node ND2 substantially equal to the voltage V2, so that the level of the latch signal SQB corresponds to the voltage V2. For example, the switch 2 包括 includes a PMOS transistor, and the gate, the source and the drain thereof receive the inverted clock signal CLKB, the node ND2, and the output node ND 分别 respectively. Switch 22c is turned on in response to the low level of inverted clock signal CLKB to provide the voltage on node ND2 to output ND0. If the input signal si is at a low level at this time, the voltage on the node ND2 (i.e., the power supply voltage) is supplied to the output terminal NDO, so that the latch signal SQB is driven to the power supply voltage. Since the inverted clock signal CLKB is generated by the inverter Inv according to the clock signal CLK, the inverted clock signal is compared with the ideal clock signal of the clock signal CLK, and the inverted clock signal CKLB is delayed by one inverter lnv. Circuit delay time. Thus, the switch 22c performs the operation corresponding to the operation of the switch 22b being turned on and supplying the voltage on the node ND1 to the output terminal ND0.

The TW5321PA will delay the delay of this circuit. Thus, the time required for the pickup signal SqB to be charged to the voltage V2 will be greater than the time required for the shackle signal sqb to be discharged to the voltage VI. To make matters worse, the 'switch 22c is implemented by a pm 〇 transistor, which typically has a lower current drive capability than the NMOS transistor. Thus, since the PMOS transistor in the switch 22c lacks the current driving capability, the time required for the latch signal SQB to be charged to the voltage V2 will be more severely delayed. In one example, the trigger circuit 24 is applied to the static latch 2. The trigger circuit 24 is responsive to the clock signal CLK, and the switch 22c provides the voltage on the node ND2 to the output terminal NDO. Thus, the time required for the shackle signal SQB to be charged to the voltage V2 can be effectively shortened. For example, the flip-flop circuit 24 includes an NMOS transistor whose gate, the gate and the source receive the clock signal CLK, the node ND2, and the output terminal NDO, respectively. The NMOS transistor in the flip-flop circuit 24 is turned on in response to the high level of the clock signal CLK to provide the voltage on the node ND2 to the output terminal NDO. Thus, the operation of driving the shackle signal SQB to the voltage V2 will not delay the circuit delay time of the inverter inverter Inv, and the trigger circuit 24 can also effectively improve the current driving capability of driving the shackle signal SQB to the voltage V2. Thus, the time required to charge the shackle signal SQB to the voltage V2 can be effectively shortened. The low drive shackle unit 26 maintains the level of the pickup signal SQB when the clock signal CLK is disabled. For example, the low drive latch unit 26 includes a set of Feedback Inverter Loops for maintaining the level of the shackle signal SQB. In one example, two inverters are applied to this set of feedback inverters, both of which are smaller in size.

.TW5321PA and the component with low drive capability of the shackle signal SQB. In one example, the input signal SI has a stable high level or a stable low level, for example, before the rising edge of the clock signal clk and the falling edge of the inverted clock signal CLKB. Thus, the voltages on the nodes ND1 and ND2 can be driven to voltages VI and V2, respectively, before the clock signal CLK is raised to a high level. In this way, the voltages on the nodes ND1 and ND2 can be immediately applied to drive the level setting completion state of the output terminal NDO when the clock signal CLK is raised to a high level. _ Referring to Fig. 3A, the % shows the delay time simulation result of the conventional shackle 1. The operation of the conventional shackle i and the static shackle 2 is simulated under the same simulation conditions (for example, the circuit condition condition (w〇rse Case Circuit Condition)) to obtain a simulation result as shown in Fig. 3A. For example, the input signal SIN reaches a stable signal level before the level of the clock signal CK changes. The time interval Tcq' is defined as the time delay from the time point when the clock signal cK level changes to the time when the pickup signal QB level changes. For &, the time interval Tcq, indicating the total delay time of the level change required for the shackle signal qb. When the signal is rounded, corresponding to the high signal level (that is, corresponding to the logic value 1), the interval time Tcq, (that is, the delay time when the pickup signal qb is converted from the high signal level to the low signal level) is equal to 〇. 8 6 7 seconds (Nanosecond ' ns). When the round signal SIN corresponds to the low signal level (that is, corresponds to the logic value 0), the time interval Tcq, (that is, the delay time of the latch signal qb from the low signal level to the high signal level) is equal to 1112. like. Referring to Fig. 3B, green shows the simulation result of the delay time of the static pickup 2 of the embodiment of the present invention. According to the same circuit simulation conditions, the time interval is defined as the time point from the clock signal CLK level change to 拴 201105038

TW5321PA «·. The time delay between the time when the lock signal SQB level changes. When the round signal SI corresponds to the high signal level and the shackle signal SQB corresponds to the low signal level, the time interval Tcq is equal to 346.346 ns. When the input signal SI corresponds to the low signal level and the pickup signal SQB corresponds to the high signal level, the time interval Tcq is equal to 〇.3l2ns. According to the results shown in FIGS. 3A and 3B, the static lock device 2 related to the conventional locker 1' can effectively reduce the delay time required for the change of the lock signal level. . In addition, by comparing the time interval Tcq equal to 1.112 ns, (corresponding to the circuit structure of the trigger circuit not applied to the latch) and the time interval Tcq equal to 0.312 ns (corresponding to the circuit structure of the latch application trigger circuit), the application The trigger circuit 24 can effectively shorten the delay time required for the latch signal to be switched from the low signal level to the 鬲 signal level in the latch. SECOND EMBODIMENT Referring to Figure 4, there is shown a circuit diagram of a static latch H in accordance with a second embodiment of the present invention. The static latch 3 shown in FIG. 4 is different from the static latch 2 shown in FIG. 2 in that the static lock 3 further includes a trigger circuit 34'' transmitting circuit 34, including a pM〇s transistor. In response to the inverted clock signal CLKB', together with the switching milk, provides the voltage on the node brain to the output terminal NDO. Thus, since the flip-flop circuit 34 and the switch 32b are provided in parallel, the equivalent resistance between the node ND1 and the output terminal ND can be effectively reduced. As a result, the time required for the shackle signal SQB to be discharged to the voltage VI can be shortened. 201105038

• TW5321PA Third Embodiment Referring to Figure 5, there is shown a circuit diagram of a first lock in accordance with the present invention. The eclipse shown in Fig. 5 is also picked up. The static shackle 4 is different from the static shackle 3 shown in Fig. 4 in that the static shackle 4 only includes the trigger circuit 34. There is substantially the same circuit connection _ and Wei's trigger circuit 44, the trigger circuit 44 responds to the inverted clock signal clkb, and the switch 42b provides the voltage on the node ND1 to the output terminal nd〇. in

The trigger circuit corresponding to the flip-flop circuits 24 and 34 in the static latchers 2 and 3 is omitted in the static latch 4. Since the flip-flop circuit 44' and the switch 42b connected in parallel are provided, the equivalent resistance between the node ND1 and the wheel terminal ND can be effectively reduced. In this way, the time required for the shackle signal SQB to be energized to the voltage Vi can also be effectively shortened. According to the above description, the static shackle of the above embodiment of the present invention includes a clock-driven driver for controlling the shackle signal according to the input signal controlled by the clock signal and the inverted clock signal. The static shackle associated with the present invention further employs a trigger circuit for driving the shackle signal together with the pulse drive driver. Thus, the static latch of the above embodiment of the present invention can effectively shorten the delay time required to drive the latch signal from the initial voltage to the termination voltage as compared to the conventional latch. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. A person skilled in the art having the knowledge of the present invention can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

201105038 TW5321PA [Simple description of the drawing] ‘ ” Figure 1 shows the circuit diagram of the conventional locker. Figure 2. The figure shows the static lock of the static locker according to the first embodiment of the present invention. The delay time of the non-conventional locker = = 2 will show the static lock 2 of the embodiment of the present invention. Delayed fruit delay time ^ Figure 4. Fig. 5 shows the electric power of the second real lock of the present invention. The figure shows the electric component of the static locker according to the third embodiment of the present invention. [Main component symbol description] 1 : 拴 locker Ν, ND1, ND2: node IV, Inv: inverters PG, 22b, 22c, 32b, 32c, 42b, 42c: switch LL: 拴 lock unit DI: inverter FBI: feedback inverters 2, 3, 4: static shackles 22, 32, 42: clock drive type drivers 22a, 32a, 42a : drive unit 24, 34, 34', 44': trigger circuit 26, 36, 46: low drive force 拴 lock unit NDO: output node ΤΙ, T2: transistor 12

Claims (1)

201105038 TW5321PA VII. Patent Application Range: L A static Latch, comprising: a clock-based driver, comprising: a first node and a second node; a driving unit, Providing a first voltage to the first node in response to a first level of an input signal, and providing a second voltage to the second node in response to a second level of the input signal; a first switch Providing the first voltage on the first node to an output node in response to a clock signal, such that one of the latching signals on the output node corresponds to the first voltage; and a second The switch is configured to provide the second voltage on the second node to the output node in response to an inverted clock signal, and the level of the shackle signal corresponds to the second voltage; a first trigger circuit (Actuation Circuit) for responding to the clock signal: the second voltage on the second node is sent to the output node; and • a Latch Unit for the clock signal is Non-energy Maintain the level of the shackle signal. 2. The static locker according to claim 1, comprising: a second trigger circuit for providing the first voltage on the first node to the output node in response to the inverted clock signal . 3. The static latch as claimed in claim 2, wherein the second trigger circuit comprises: a transistor comprising a gate, a first end and a second end, respectively receiving the inverted clock signal, Receiving the first voltage and coupling to the rounding node. 13 201105038 TW5321PA 4. If the scope of the patent application is 丨', the first trigger circuit includes: the static shackle, wherein the transistor includes a drain, a clock signal, and receives the second voltage and the second end, Receiving the 5. respectively, as in the patent application: the second is connected to the output node. The driving unit includes: the static shackle of the item, wherein the first transistor includes a gate, receives the input signal, receives the first terminal, and the second terminal is respectively connected to the second transistor , including opening the pole, to the first: node; and receiving the input signal, receiving the first & and the first end, respectively, 6. If the application of the fainting is electro-coated and coupled to the second node. The first switch includes: the static lock device according to Item 1, wherein the transistor includes a gate _ clock signal, and the second and the second ends are respectively received by the sister Defects and coupling to the output node. The second switch includes the static latch of claim 1, wherein the first end and the second end respectively receive the node and are coupled to the output node. The static shackle of the present invention, wherein the transistor includes a gate, an inverted clock signal, and is coupled to the eighth. The first lock unit of the patent application scope includes: a set of feedback inverters (Feedback Inverter Loop) to maintain the level of the shackle signal. 9. The static shackle of claim 1, wherein: an inverter is configured to generate the inverted pulse according to the clock signal. 201105038 . . . TW5321PA 10. - Static Pickup (Static Latch), including: * A driver 'speaks on the - the input signal - the first level provides a voltage to the first node, and in response to the - the clock signal provides the first: the point a first-to-output node, the second-level voltage is provided in response to the second-level input signal, and the material on the second node is provided to the output node in response to the -clock signal; a circuit (ActuatiGnCircuit) for responding to the time: the signal provides the second voltage on the second node to the output node; and the Latchh unit nx is reduced to the non-energy supply The level of the shackle signal. The static shackle of claim 10, wherein the driver comprises: a first node and a second node; the driving unit is configured to respond to the first bit of the input signal, and s voltage to the first node, and respond to the second bit of the input signal The second (four) residual m is over the first switch, and is configured to provide the first voltage of the first node to the output end in response to the clock signal, so that one of the pickup signals on the output terminal is at a level Corresponding to the first voltage; and a second switch for providing the second voltage to the output terminal in response to the inverted clock signal to cause the latch on the output end 5 This level corresponds to the second voltage. 15 201105038 TW5321PA · ♦ 12. The static shackle of claim 11, further comprising: a second trigger circuit for providing the first node on the first node in response to the inverted clock signal A voltage to the output node. 13. The static latching device of claim 12, wherein the second trigger circuit comprises: a transistor, including a gate, a first end, and a second end, respectively receiving the inverted clock signal, Receiving the first voltage and coupling to the output node. 14. The static shackle of claim 11, wherein the driving unit comprises: a first transistor, comprising a gate, a first end and a second end, respectively receiving the input signal, receiving the first a voltage is coupled to the first node; and a second transistor includes a gate, a first end, and a second end, respectively receiving the input signal, receiving the second voltage, and coupling to the second node. 15. The static shackle of claim 11, wherein the first switch comprises: a transistor, comprising a gate, a first end and a second end, respectively receiving the clock signal and coupled to The first node is coupled to the output node. 16. The static shackle of claim 11, wherein the second switch comprises: a transistor, comprising a gate, a first end and a second end, respectively receiving the inverted clock signal, coupled Connected to the second node and coupled to the output node. 17. The static shackle of claim 11, further comprising: an inverting Is ′ for generating the inverted clock based on the clock signal 201105038 ^ . TW5321PA number. 18. The static shackle of claim 10, wherein the first trigger circuit comprises: a transistor, including a gate, a first end, and a second end, respectively receiving the clock signal, receiving the The second voltage is coupled to the output node. 19. The static shackle of claim 10, wherein the latching unit comprises: a feedback inverter loop for maintaining the level of the shackle_signal. 17