201104768 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置。 【先前技術】 半導體裝置通常見於現代電子產品中。半導體裝置之 電組件的數目及密度可變化^離散半導體裝置一般含有一 種類型之電組件，例如發光二極體（LED)、小信號電晶體、 電阻器、電容器、電感器及功率金屬氧化物半導體場效電 晶體（MOSFET ) ^積體半導體裝置典型地含有數百個至數 百萬個電組件。積體半導體裝置之實例包括微控制器、微 處理器電荷耦合裝置（CCD )、太陽能電池及數位微鏡裝 置（DMD)。 半導體裝置執行許多功能，諸如高速計算、收發電磁 信號、控制電子裝置、冑日光轉化成電及建立電視顯示器 之視像投射。半導體裝置見於娛樂、通信、功率轉換、網 路、電腦及消費型產品之領域中。半導體裝置亦見於軍事 應用、航空 '汽車、工業控制器及辦公設備中。 半導體裝置係利用半導體材料之電特性。半導體材料 之原子結構允許藉由施加電場或經由摻雜製程而操縱其電 導率摻雜係將雜質引人半導體材料中以操縱及控 體裝置之電導率。 半導體裝置含有主動及被動電結構。主動結構（包括 雙極電，體及場效電晶體）#制電流流動。藉由改變推雜 私度及施加電場或基極電流，電晶體促進或限制電流流 4 201104768 動。被動結構（包括電阻器、電容器及電感器）在電壓與 電流之間建立為執行多種電功能所必需的關係。被動結構 與主動結構係電連接以形成電路，從而使半導體裝置能夠 執行高速計算及其他有用功能。 半導體裝置一般使用兩個複雜製造製程（亦即，前端 製造與後端製造）來製造，各製程潛在地包括數百個步驟。 前端製造包括在半導體晶圓之表面上形成多個晶粒。各晶 粒典型地相同且含有藉由電連接主動組件與被動組件所形 成之電路。後端製造包括將成品晶圓單切成個別晶粒且封 裝該晶粒以提供結構支撐及環境隔離。 半導體製造之-目的在於生產較小半導體裝置。較小 裝置典型地消耗較少功率、具有較高效能且可較高效地生 產另卜較j、半導體裝置具有較小佔據面積，此為較小 終產品所需°較小晶粒尺寸可藉由改良前端製程達成，從 而產生具有較小、較高密度之主動及被動組件的晶粒。後 端製程可藉由改良電互、表 电互連及封裝材料來產生具有較小佔據 面積之半導體裝置封裝。 圖1說明3有多個半導體晶粒12之習知半導體晶圓 10。晶圓1G可由諸如⑦、鍺、耗鎵、魏銦或碳化石夕之 半導體基材製成。各半導體晶粒12在其主動表面中具有根 據曰曰粒之電相形成之主動及被動裝置、導電層及介電 層。在-實施例中’半導體晶粒含有基賴比電路或數位 =，諸如數位信號處理器（DSp) '記憶體或其他信號處 路。+導體晶粒12亦可含有用於射頻（RF)信號處理 [S] 5 201104768 之積體被動裝置（IPD)，諸如電感器、電容器及電阻器。 半導體晶粒12係具有凸塊墊14形成於主動表面上之 覆晶型半導體裝置。凸塊墊14提供半導體晶粒12内中導 電層及主動及被動電路組件之電互連。谭料凸塊典型地形 成於凸塊墊14上以在晶圓單切之後使半導體晶粒丨2與印 刷電路板（PCB)及其他電裝置電互連。 晶圓測試為製造製程之一重要部分以確認半導體晶粒 12之連續性 '電參數及功能操作。在晶圓級鑑別不良晶粒 且自製造製程中移除以免至較高級系統時（例如多晶粒封 裝及PCB )發生故障，此故障代價更高昂。 圖2展不半導體晶圓10之習知晶圓探針測試組態。晶 圓1〇固定於晶圓操控器16上，其提供晶圓在乂、7及2方 向上之移動以達成測試目的。操控晶圓1〇以使具有觸指或 觸針20之測試探頭18電接觸凸塊墊14。電腦測試系統a 經由測試探頭18及觸指20對凸塊墊14收發電信號。電腦 測試系統22經由凸塊墊14測試半導體晶粒12之連續性、 電參數及功能操H若電腦測試“ 22制到測試故障， 則鑑別為不良半導體晶粒且隨後自製造製程中移除。 凸塊墊14具有小面積，直徑約50-500微米（μιη)。 觸心20典型地具有尖頭以使得可靠地電連接至凸塊塾μ。 在晶圓探針測言式過程+，觸# 2〇已知會穿透表面且損壞凸 塊塾14。實際上’晶圓探針測試可包括牵引觸指20橫越凸 塊墊14 ’導致凸塊塾表面上留下擦痕。晶圓探針測試在凸 塊墊中留下觸指標記’導致隨後焊料凸塊不易形成。為避 6 201104768 免相壞凸塊墊14,已在焊料凸塊24形成之後進行晶圓探針 測試，如圖3所示。 在大多數商務合同中’晶圓代工廠（waferf〇undry)被 其消費者要求保持對晶圓負責直至完成晶圓分類測試以確 保足夠良率。因凸塊墊損壞之潛在性’許多晶圓代工廠在 凸塊墊上形成焊料凸塊之後執行晶圓探測。晶圓代工廠直 至晶圓分類測試之後方可出售晶圓或以其他方式轉移晶圓 貝任，且代工廠直至凸塊形成之後方可進行晶圓分類測 試。然而，要求晶圓探測在凸塊形成之後進行限制了第三 方凸塊形成服務供應商之競爭。若晶圓探測可在凸塊形成 之前進行而不損壞凸塊墊，則晶圓代工廠可出售無凸塊之 晶圓且其他公司可參與提供凸塊形成服務。 【發明内容】 需要在凸塊形成之前執行晶圓探針測試而不損壞互連 凸塊墊。因此，在一實施例中，本發明為一種製造半導體 裝置之方法，其包含以下步驟：提供一含有多個半導體晶 粒之半導體晶圓，在半導體晶粒上形成多個互連凸塊墊， 在互連凸塊塾鄰近處形成多個犧牲凸塊塾，在各互連凸塊 塾與鄰近犧牲凸塊墊之間形成一導電鏈路以及在互連凸塊 墊上形成凸塊之如藉由電接觸犧牲凸塊墊進行晶圓探測。 在另一實施例中，本發明為一種製造半導體裝置之方 法，其包含以下步驟：提供一含有多個半導體晶粒之半導 體晶圓以及在半導體晶粒上同時地形成多個互連凸塊墊、 多個犧牲凸塊墊以及導電鏈路。犧牲凸塊墊安置於互連凸 201104768 塊墊鄰近處。一導電鏈路使各互連凸塊墊與鄰近犧牲凸塊 墊之間電連接。該方法進一步包括藉由電接觸犧牲凸塊墊 進行晶圓探測之步驟。 在另一實施例中，本發明為一種製造半導體裝置之方 法’其包含以下步驟：提供一含有多個半導體晶粒之半導 體晶圓，在半導體晶粒上'於一凸塊墊陣列内形成一互連 凸塊墊’於該凸塊墊陣列内形成一犧牲凸塊墊，在該互連 凸塊墊與該犧牲凸塊墊之間形成一導電鏈路以及藉由電接 觸該犧牲凸塊塾進行晶圓探測。 在另一實施例中，本發明為一種含有多個半導體晶粒 之半導體晶圓，該等晶粒包含一在該等半導體晶粒上於一 凸塊墊陣列内形成之互連凸塊墊。一犧牲凸塊墊形成於該 凸塊墊陣列内。一導電鏈路形成於該互連凸塊墊與該犧牲 凸塊墊之間。 【實施方式】 本發明在以下說明令以一或多個實施例參考圖式加以描述其 中相同數字代表相同或類似元件。儘管本發明依據達成本發明目的 之最佳方式描述，但熟習此項技術者應瞭解本發明欲涵蓋如隨附申 請專利範圍所限定之可包括於本發明之精神及範_内的替代物修 改及等效物以及如以下揭示内容及圖式所支持之其等效物。 半導體裝置-般使用兩個複雜製造製程來製造：前端 製造與後端製造。前端製造包括在半導體晶圓表面上形成 多個晶粒。該晶圓上之各晶粒含有主動及被動電組件，其 經電連接而形成功能電路"堵如電晶體及二極體之主動電 201104768 組件具有控制電流流動之能力》諸如電容器、電感器、電 阻器及變壓器之被動電組件在電壓與電流之間建立為執行 電路功能所必需的關係。 被動及主動組件藉由一系列製程步驟形成於半導體晶 圓表面上，包括摻雜、沈積、光微影、蝕刻及平坦化。摻 雜係藉由諸如離子植入或熱擴散之技術將雜質引入半導體 材料中。摻雜製程改變主動裝置中半導體材料之電導率， 從而使該半導體材料轉變成絕緣體、導體，或回應電場或 基極電流而動態地改變該半導體材料之電導率。電晶體含 有摻雜類型及程度不同之區域，其視需要配置以使該電晶 體能夠在施加電場或基極電流時促進或限制電流流動。 主動及被動組件係由具有不同電特性之材料層形成。 該等層可藉由多種沈積技術形成（部分由所沈積之材料類 型決定）。舉例而言，薄膜沈積可包括化學氣相沈積 (CVD)、物理氣相沈積（PVD)、電解電鍍及無電電鍍製 程。各層一般經圖案化以形成主動組件、被動組件或各組 件間電連接的部分。 可使用光微影對層進行圖案化，包括使光敏材料（例 如光阻）沈積於待圖案化之層上。使用光將圖案自光罩轉 印於光阻上。使用溶劑移除曝光之光阻圖案部分，暴露待 圖案化之下層部分。移除光阻之其餘部分，得到其下之圖 案化層。或者’有些類型之材料係使用諸如無電電鍍及電 解電鍍之技術藉由使材料直接沈積於先前沈積/蝕刻製程所 形成的區域或空隙中而加以圖案化。 201104768 在現有目案上沈積材料薄膜會放大下面的@案且產生 非均勻平坦表面。生產較小且較密集堆積之主動及被動組 件需要均勻平坦表面。可使用平坦化自晶圓表面移除材料 且產生均勻平坦表面。平坦化包括用拋光墊拋光晶圓表 面。在拋光期間將研磨材料及腐钱性化學品添加至晶圓表 面中。研磨劑機械作用與化學品腐蝕作用組合可移除任何 不規則表面構形，從而產生均勻平坦表面。 後端製造係指將成品晶圓切割或單切成個別晶粒且接 著^裝該晶粒以供結構支樓及環境隔離。致使單切晶粒， 七者曰曰圓非功此區（稱為切割道或劃線）冑晶圓劃痕並切 斷。使用雷射切割工1 5¾ 1 β 八戈鑛條早切日日圓。單切之後，將個 別曰曰粒固疋於封裝基板上，該封裝基板包括接腳或接觸 塾以供與其他系統組件互連。接著使羊導體晶粒上所形成 之接觸塾連接^裝内之接觸墊。電連接可由焊料凸塊、 柱形凸塊、導電膏吱煤蟪裕& 一 、 T ^焊線形成。使密封劑或其他成型材料 沈積於封裴上以提供物拽古嫂 权供物理支撐及電絕緣。接著將成品封裝 f入電系統中且半導體裝置之功能可供其他系統組件利 用0 圖4 ”充明具有多個黏著於其表面上之半導體封裴的晶 片載體基板或PCB 52電 <电于褒置5〇。視應用而定，電子裝 :5〇可具有一種類型之半導體封裝或多種類型之半導體封 、不同類型之半導體封装展示於圖4中以用於說明之目 的。 電子裝置5〇可為-使用半導體封裝執行-或多種電功 10 201104768 月巨之举獨系統。或者，雷子梦番ς fk -r认 X有4于衷置5〇可為一較大系統之子組 件。舉例而言，電子梦署-Γ , 于褒置50 了為一可插入電腦中之圖形卡、 ㈣介面卡或其他信號處理卡。半導體封裳可包括微處理 器、記憶體、特殊應用積體電路（ASIC)、邏輯電路、類 電路RF電路、離散裝置或其他半導體晶粒或電組件。 —在圖4中，PCB52提供—用於結構支撐之通用基板及 固疋於PCB上之半導體封裝的電互連。使用蒸鍵、電解電 鍍、無電電鍍、網版印刷或其他適合之金屬沈積製程在PCB 52之一表面上或層内形成導電信號跡線…信號跡線μ 在半導體封裝、固定組件及其他外部系統組件之每一者之 間提供電通信。跡線54亦向各半導體封裝提供電力及接地。 在-些實施例中，一半導體裝置具有兩級封裝。第一 級封裝為使半導體晶粒機械附著及電附著至一中間載體之 技術。第一級封裝包括使該中間載體機械附著及電附著至 PCB。在其他實施例中，—半導體裝置可能僅具有第一級封 裝，其中晶粒直接機械黏著及電黏著於pcB上。 出於說明之目的’在PCB 52上展示數種類型之第一級 封裝’包括焊線封裝56及覆晶58。另夕卜，展*固定於PM 52上之數種類型之第二級封裝，包括球狀柵格陣列（BGA) 6〇、凸塊晶片載體（BCC) 62、雙排型封裝（Dip) 64、平 台栅格陣列（LGA) 66、多晶片模組（mcm) 68、四邊扁 平=引腳封裝（QFN) 7〇及四邊扁平封裝72。視系統要求 而疋，半導體封裝之任何組合、第一級與第二級封裝類型 4何、‘且σ以及其他電子組件的組態可連接至PM Μ。在 11 201104768 一些實施例中，電子裝置50包括單個附著之半導體封裝； 而其他實施例需要多個互連封裝。藉由在單個基板上組合 一或多個半導體封裝，製造商可將預製組件合併於電子裝 置及系統中。由於半導體封裝包括複雜功能，因此可使用 較便宜組件及流線化製造製程來製造電子裝置。所得裝置 不太可能發生故障且製造費用較少，從而降低消費者成本。 圖5a-5C展示示例性半導體封裝。圖&進一步詳細說 明固定於PCB 52上之DIp 64。半導體晶粒Μ包括含有類 ST:::電路之主動區’該等類比電路或數位電路形 行作為主動裝置、被動裳置、導電層及介電 層，並且以根據晶粒之電設 电 -γ A, 1^.,, 電互連。舉例而言，電路 〇 ”個電晶體、二極體、電感器、電容、電阻 器及在半導體晶粒74之主動區内 ^益電阻 接觸墊76為諸如铭（A1) = ”他電路凡件。 金（Au)或銀、道 锡（Sn)、錄（Ni)、 至半導體晶粒74内所形成之電路的元件^個^’且電連接 間，使用金-矽共晶層或諸如埶 64組裝期 體晶粒74固定於中間載體心樹脂之黏合材料將半導 材料，諸如聚合物或H 。封裂主體包括絕緣封裝 粒74與PCB 5 及焊線82在半導體晶 以I間梃供電互遠。 以防止環境洚洛选、封劑84沈積於封裝上 衣兄濕軋及顆粒進入封梦 衣上 圖5b進一 + % 々扣晶粒74或焊線82。 步坪細說明固定於Prt5 r 用底膠或環氧樹脂點合材料92將C=52上之败62。使 體9〇上。焊線94在接觸塾心.導體晶f Μ固定於載 〃 8之間提供第一級封裝 12 201104768 互連。成型化合物或密封劑100沈積於半導體晶粒88及焊 線94上以向裝置提供物理支撐及電絕緣。使用諸如電解電 鑛或無電電鍍之適合金屬沈積法在PCB 52之一表面上形成 接觸墊102以防止氧化。接觸墊102電連接至PCB 52中之 一或多個導電信號跡線54。凸塊104形成於BCC 62之接觸 墊98與PCB 52之接觸墊102之間。 在圖5c中，半導體晶粒58依覆晶型第一級封裝方式面 向下固定於中間載體106上。半導體晶粒58之主動區1〇8 含有類比電路或數位電路，其以根據晶粒之電設計所形成 之主動裝置、被動裝置、導電層及介電層的形式執行。舉 例而言’電路可包括一或多個電晶體、二極體、電感器、 電容器、電阻器及主動區108内之其他電路元件。半導體 晶粒58經由凸塊11〇電連接及機械連接至載體1〇6。 BGA 60係使用凸塊112依BGA型第二級封裝方式電 連接及機械連接至PCB 52。半導體晶粒58經由凸塊11〇、 信號線114及凸塊112電連接至PCB 52中之導電信號跡線 54。成型化合物或密封劑丨16沈積於半導體晶粒58及載體 106上以向裝置提供物理支撐及電絕緣。覆晶半導體裝置提 供半導體晶粒58上之主動裝置至pCB 52上之導電跡線的 短導電路徑以縮短信號傳播距離，降低 路效能。在另-實施例中，在無中間載體心=電 可使用覆晶型第-級封裝方式將半導體晶粒以直接機械連 接及電連接至PCB 52。 圆 &坑明含有多個半導體晶粒 I牛導體晶圓201104768 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device. [Prior Art] Semiconductor devices are commonly found in modern electronic products. The number and density of electrical components of a semiconductor device can vary. Discrete semiconductor devices typically contain one type of electrical component, such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor. Field Effect Transistor (MOSFET) ^Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of the integrated semiconductor device include a microcontroller, a microprocessor charge coupled device (CCD), a solar cell, and a digital micromirror device (DMD). Semiconductor devices perform many functions, such as high speed computing, transceiving electromagnetic signals, controlling electronics, converting sunlight into electricity, and establishing a video projection of a television display. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor devices are also found in military applications, aerospace vehicles, industrial controllers and office equipment. Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material allows the conductivity doping system to be manipulated into the semiconductor material to manipulate and control the conductivity of the device by applying an electric field or via a doping process. Semiconductor devices contain active and passive electrical structures. Active structure (including bipolar electric, body and field effect transistors) # current flow. The transistor promotes or limits the current flow by changing the tweeting power and applying an electric field or base current. Passive structures (including resistors, capacitors, and inductors) establish the relationship between voltage and current necessary to perform a variety of electrical functions. The passive structure is electrically connected to the active structure to form a circuit, thereby enabling the semiconductor device to perform high speed calculations and other useful functions. Semiconductor devices are typically fabricated using two complex manufacturing processes (i.e., front end manufacturing and back end manufacturing), each of which potentially includes hundreds of steps. Front end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each of the crystal grains is typically identical and contains circuitry formed by electrically connecting the active and passive components. Back end manufacturing involves cutting the finished wafer into individual dies and encapsulating the dies to provide structural support and environmental isolation. Semiconductor manufacturing - the aim is to produce smaller semiconductor devices. Smaller devices typically consume less power, are more efficient, and can be produced more efficiently. Semiconductor devices have a smaller footprint, which is required for smaller end products. The improved front-end process is achieved, resulting in a die with smaller, higher density active and passive components. The back end process can produce a semiconductor device package having a small footprint by modifying electrical, electrical interconnects, and packaging materials. Figure 1 illustrates a conventional semiconductor wafer 10 having a plurality of semiconductor dies 12. The wafer 1G may be made of a semiconductor substrate such as 7, germanium, gallium-consuming, germanium or carbon carbide. Each of the semiconductor dies 12 has active and passive devices, conductive layers and dielectric layers formed in the active surface thereof in accordance with the electrical phase of the ruthenium particles. In an embodiment the semiconductor die contains a base ratio circuit or digital =, such as a digital signal processor (DSp) 'memory or other signal path. + Conductor die 12 may also contain integrated passive devices (IPD) for radio frequency (RF) signal processing [S] 5 201104768, such as inductors, capacitors, and resistors. The semiconductor die 12 has a flip chip type semiconductor device in which a bump pad 14 is formed on an active surface. The bump pads 14 provide electrical interconnections of the conductive layers and active and passive circuit components within the semiconductor die 12. The tan bumps are typically formed on the bump pads 14 to electrically interconnect the semiconductor die 2 with printed circuit boards (PCBs) and other electrical devices after the wafer is single cut. Wafer testing is an important part of the manufacturing process to confirm the continuity of the semiconductor die 12 'electrical parameters and functional operation. This failure is more costly when identifying defective dies at the wafer level and removing them from the manufacturing process to avoid failures in higher-level systems, such as multi-die packages and PCBs. Figure 2 shows a conventional wafer probe test configuration for semiconductor wafer 10. The wafer 1 is fixed to the wafer handler 16 which provides wafer movement in the 乂, 7 and 2 directions for testing purposes. The wafer 1 is manipulated such that the test probe 18 with the finger or stylus 20 electrically contacts the bump pad 14. The computer test system a transmits and receives electrical signals to the bump pads 14 via the test probes 18 and the fingers 20. The computer test system 22 tests the continuity, electrical parameters, and function of the semiconductor die 12 via the bump pads 14 as a computer test to identify a defective semiconductor die and subsequently remove it from the fabrication process. The bump pad 14 has a small area of about 50-500 microns in diameter. The contact 20 typically has a pointed tip to enable reliable electrical connection to the bump 塾μ. #2〇 is known to penetrate the surface and damage the bumps 14. In fact, the 'wafer probe test can include pulling the fingers 20 across the bump pads 14' resulting in scratches on the surface of the bumps. The pin test leaves a finger mark in the bump pad' resulting in subsequent solder bump formation. To avoid the 6201104768 phase-free bump pad 14, the wafer probe test has been performed after the solder bump 24 is formed, as shown in the figure. 3. In most commercial contracts, the wafer foundry is responsible for wafers by its consumers until wafer sorting is completed to ensure adequate yield. The potential for bump pad damage 'Many wafer foundries are formed on bump pads Wafer probing is performed after solder bumps. Wafers can be sold or otherwise transferred after wafer sorting and testing, and wafer sorting tests can be performed until the bumps are formed. However, wafer inspection is required to limit the competition of third-party bump formation service providers after bump formation. If wafer inspection can be performed before the bump formation without damaging the bump pads, the foundry can be sold without The bump wafer and other companies may participate in providing the bump forming service. SUMMARY OF THE INVENTION It is desirable to perform wafer probe testing prior to bump formation without damaging the interconnect bump pads. Thus, in an embodiment, The invention is a method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor wafer comprising a plurality of semiconductor dies, forming a plurality of interconnect bump pads on the semiconductor dies, forming adjacent to the interconnect bumps a plurality of sacrificial bumps, forming a conductive link between each of the interconnect bumps and the adjacent sacrificial bump pads, and forming bumps on the interconnect bump pads, such as by electrical connections Sacrificial bump pad for wafer probing. In another embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer containing a plurality of semiconductor dies and simultaneously on the semiconductor die Forming a plurality of interconnecting bump pads, a plurality of sacrificial bump pads, and a conductive link. The sacrificial bump pads are disposed adjacent to the interconnect pads 201104768. A conductive link causes each interconnect bump pad to be adjacent to the sacrificial The bump pads are electrically connected. The method further includes the step of wafer sensing by electrically contacting the sacrificial bump pads. In another embodiment, the invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer containing a plurality of semiconductor dies, forming an interconnect bump pad in the bump pad array on the semiconductor die to form a sacrificial bump pad in the bump pad array, A bump is formed between the bump pad and the sacrificial bump pad and the wafer is probed by electrically contacting the sacrificial bump. In another embodiment, the invention is a semiconductor wafer comprising a plurality of semiconductor dies, the dies comprising an interconnecting bump pads formed in the array of bump pads on the semiconductor dies. A sacrificial bump pad is formed in the array of bump pads. A conductive link is formed between the interconnect bump pad and the sacrificial bump pad. DETAILED DESCRIPTION OF THE INVENTION The present invention is described in the following description with reference to the drawings, Although the present invention has been described in terms of the best mode of the present invention, it will be understood by those skilled in the art that the present invention is intended to cover alternative modifications that may be included in the spirit and scope of the invention as defined by the appended claims. And equivalents and equivalents thereof as supported by the following disclosure and drawings. Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit " an active device such as a transistor and a diode. The 201104768 component has the ability to control current flow, such as capacitors, inductors. The passive electrical components of the resistors and transformers establish the necessary relationship between voltage and current to perform circuit functions. The passive and active components are formed on the surface of the semiconductor wafer by a series of processing steps including doping, deposition, photolithography, etching, and planarization. The doped system introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process changes the conductivity of the semiconductor material in the active device, thereby converting the semiconductor material into an insulator, a conductor, or dynamically changing the conductivity of the semiconductor material in response to an electric field or base current. The transistor contains regions of varying doping type and extent that are configured as needed to enable the transistor to promote or limit current flow when an electric or base current is applied. Active and passive components are formed from layers of material having different electrical properties. The layers can be formed by a variety of deposition techniques (partly determined by the type of material being deposited). For example, thin film deposition can include chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. The layers are typically patterned to form active components, passive components, or portions of electrical connections between components. The layer can be patterned using photolithography, including depositing a photosensitive material (e.g., photoresist) on the layer to be patterned. Use light to transfer the pattern from the mask onto the photoresist. The portion of the exposed photoresist pattern is removed using a solvent to expose portions of the underlying layer to be patterned. Remove the rest of the photoresist to obtain the patterned layer below it. Alternatively, some types of materials are patterned using techniques such as electroless plating and electrolytic plating by depositing the material directly into regions or voids formed by previous deposition/etch processes. 201104768 Depositing a thin film of material on an existing project will magnify the @ case below and produce a non-uniform flat surface. Active and passive components that produce smaller, denser stacks require a uniform flat surface. Planarization can be used to remove material from the wafer surface and produce a uniform flat surface. Flattening involves polishing the wafer surface with a polishing pad. Abrasive materials and rotted chemicals are added to the wafer surface during polishing. The combination of abrasive mechanical action and chemical corrosive action removes any irregular surface configuration resulting in a uniform flat surface. Back-end manufacturing refers to cutting or simply cutting a finished wafer into individual dies and attaching the dies to isolate the structural building from the environment. This results in a single-cut grain, which is scratched and cut off in this area (called a scribe line or a scribe line). Use the laser cutter 1 53⁄4 1 β 八戈矿 to cut the yen early. After the single cut, the individual dies are fixed to the package substrate, which includes pins or contacts for interconnection with other system components. The contact pads formed on the sheep conductor dies are then joined to the contact pads in the package. The electrical connection may be formed by solder bumps, stud bumps, conductive paste, coal, and a solder wire. A sealant or other forming material is deposited on the seal to provide physical support and electrical insulation. Then, the finished package is packaged into the electrical system and the function of the semiconductor device can be utilized by other system components. FIG. 4 "fills the wafer carrier substrate or PCB 52 having a plurality of semiconductor packages adhered to the surface thereof." 5. Depending on the application, the electronic device: 5 can have one type of semiconductor package or multiple types of semiconductor packages, different types of semiconductor packages are shown in Figure 4 for illustrative purposes. For - use semiconductor package to perform - or a variety of electrical work 10 201104768 month giant system. Or, Lei Zi Meng Pan Yu fk -r recognize X has 4 in 5 can be a sub-component of a larger system. For example In other words, the electronic dream department-Γ, 褒 50 50 is a graphics card that can be inserted into a computer, (4) interface card or other signal processing card. The semiconductor package can include a microprocessor, a memory, a special application integrated circuit ( ASIC), logic circuit, circuit-like RF circuit, discrete device or other semiconductor die or electrical component. - In Figure 4, PCB 52 is provided - a general purpose substrate for structural support and a semiconductor package mounted on the PCB Interconnection. Conductive signal traces are formed on or in one of the surfaces of PCB 52 using steaming, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces are in semiconductor packages, fixed components, and Electrical communication is provided between each of the other external system components. Trace 54 also provides power and ground to each semiconductor package. In some embodiments, a semiconductor device has a two-stage package. The technique of mechanically attaching and electrically attaching the particles to an intermediate carrier. The first level of packaging includes mechanically attaching and electrically attaching the intermediate carrier to the PCB. In other embodiments, the semiconductor device may only have a first level package in which the die Direct mechanical adhesion and electrical adhesion to the pcB. For illustrative purposes 'displays several types of first-level packages on the PCB 52' including the wire bond package 56 and the flip chip 58. In addition, the display* is fixed to the PM 52. Several types of second-level packages, including a ball grid array (BGA) 6〇, a bump wafer carrier (BCC) 62, a dual-row package (Dip) 64, a platform grid array (LGA) 66, Multi-chip module (mcm) 68, four-sided flat = pin package (QFN) 7" and four-sided flat package 72. Depending on system requirements, any combination of semiconductor packages, first and second package types 4 'And σ and other electronic components can be configured to be connected to the PM. In some embodiments, 11 201104768, the electronic device 50 includes a single attached semiconductor package; while other embodiments require multiple interconnect packages. By combining one or more semiconductor packages, manufacturers can incorporate prefabricated components into electronic devices and systems. Since semiconductor packages include complex functions, electronic devices can be fabricated using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, thereby reducing consumer costs. Figures 5a-5C show an exemplary semiconductor package. The figure & further details the DIp 64 fixed on the PCB 52. The semiconductor die Μ includes an active region containing a class of ST::: circuits. The analog circuits or digital circuit lines are used as an active device, a passive skirt, a conductive layer, and a dielectric layer, and are electrically-based according to the electric power of the die. A, 1^.,, Electrical interconnection. For example, a circuit, a transistor, a diode, an inductor, a capacitor, a resistor, and an active contact pad 76 in the active region of the semiconductor die 74 are, for example, Ming (A1) = " . Gold (Au) or silver, tin (Sn), Ni (Ni), to the components of the circuit formed in the semiconductor die 74, and between the electrical connections, using a gold-germanium eutectic layer or such as 埶64 The assembly phase body grains 74 are fixed to the intermediate carrier core resin and the bonding material will be a semiconductive material such as a polymer or H. The cracked body includes an insulating package 74 and a PCB 5 and a bonding wire 82 that are electrically connected to each other between the semiconductor crystals. In order to prevent the environment from being selected, the sealant 84 is deposited on the package, and the granules are wet-rolled and the granules are placed on the cloak. Figure 5b is a + % 々 buckle grain 74 or wire bond 82. The step detail is fixed to Prt5 r with a primer or epoxy dot material 92 to defeat C at 62=62. Put the body 9 on it. The bonding wire 94 is in contact with the center of the core. The conductor crystal f Μ is fixed between the carrier 8 to provide a first level package 12 201104768 interconnection. A molding compound or encapsulant 100 is deposited over the semiconductor die 88 and wire 94 to provide physical support and electrical insulation to the device. Contact pads 102 are formed on one surface of PCB 52 using a suitable metal deposition method such as electrolytic or electroless plating to prevent oxidation. Contact pad 102 is electrically coupled to one or more conductive signal traces 54 in PCB 52. Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52. In Fig. 5c, the semiconductor die 58 is fixed to the intermediate carrier 106 in a face-down manner in a first-stage package. The active region 1 〇 8 of the semiconductor die 58 contains an analog circuit or a digital circuit that is implemented in the form of an active device, a passive device, a conductive layer, and a dielectric layer formed in accordance with the electrical design of the die. For example, a circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components within active region 108. The semiconductor die 58 is electrically and mechanically connected to the carrier 1〇6 via the bump 11〇. The BGA 60 is electrically and mechanically connected to the PCB 52 using bumps 112 in a BGA type second level package. The semiconductor die 58 is electrically coupled to the conductive signal traces 54 in the PCB 52 via bumps 11 , signal lines 114 and bumps 112 . A molding compound or sealant crucible 16 is deposited on the semiconductor die 58 and the carrier 106 to provide physical support and electrical insulation to the device. The flip chip semiconductor device provides a short conductive path from the active device on the semiconductor die 58 to the conductive traces on the pCB 52 to reduce signal propagation distance and reduce road efficiency. In another embodiment, the semiconductor die can be directly mechanically and electrically connected to the PCB 52 using a flip-chip type first-stage package without intermediate carrier core = power. Round & pits contain multiple semiconductor grains
[S 13 201104768 晶圓150可由直徑在150_300毫米（mm)範圍内之半導體 基材製成，諸如矽、鍺、砷化鎵、磷化銦或碳化矽。各半 導體晶粒152在主動表面丨54中具有根據晶粒之電設計所 形成之主動及被動裝置、導電層及介電層。在一實施例中， 半導體晶粒152含有基頻類比電路或數位電路，諸如數位 信號處理器（DSP )、ASIC、記憶體或其他信號處理電路。 半導體晶粒152亦可含有用於RF信號處理之IPD，諸如電 感器、電容器及電阻器。 在一實施例中，半導體晶粒152為覆晶型半導體裝置， 其具有形成於主動表面154上之互連凸塊墊ι6〇β凸塊塾 160係使用PVD、CVD、濺鍵、電解電鑛、無電電錄製程或 其他適合金屬沈積製程進行圖案化並沈積。凸塊墊16〇可 為一或多個Al、Cu、Sn、Ni、Au、Ag或其他適合導電材 料層。凸塊墊160安置於凸塊墊陣列162内以向半導體晶 粒152内之導電層以及主動及被動電路組件提供電互連。 凸塊墊160面積小，直徑為約50-500微米（μηι)。 多個犧牲凸塊墊164形成於主動表面154上。凸塊塾 164係使用PVD、CVD、濺鍍、電解電鍍、無電電鍍製程或 其他適合金屬沈積製程進行圖案化並沈積。凸塊墊丨64可 為一或多個Al、Cu、Sn、Ni、Au、Ag或其他適合導電材 料層。犧牲凸塊墊164可具有小於或大於互連凸塊墊ι6〇 之面積。一般而言，犧牲凸塊墊164直徑約為互連凸塊塾 1 60之直徑或適於晶圓探針測試之直徑。 圖7a-7b說明半導體晶圓150之一部分的俯視圖及橫截 14 201104768 面圖，其進一步詳細展示半導體晶粒丨52之凸塊墊陣列 1 62。犧牲凸塊墊丨64與互連凸塊墊丨6〇之陣列呈間隙安 置。每個互連凸塊墊160存在一個犧牲凸塊墊164。各犧牲 凸塊塾164定位於相應互連凸塊墊16〇鄰近處。在一實施 例中’犧牲凸塊墊1 64安置於相對於相應互連凸塊墊16〇 呈對角偏移之位置’例如一個凸塊墊直徑上方且向右，如 圖6所示。 導電鏈路166係使用PVD、cvd、濺鍍、電解電鍍、 無電電鍍製程或其他適合金屬沈積製程圖案化而形成於主 動表面154上介於互連凸塊墊16〇與犧牲凸塊墊164之間。 導電鏈路166可為一或多個a卜Cu、Sn、Ni、Au、Ag或 其他適合導電材料層。導電鏈路166使互連凸塊墊16〇與 犧牲凸塊墊164電連接。犧牲凸塊墊164及導電鏈路166 可與互連凸塊墊160同時地形成或在凸塊形成期間形成， 從而避免各別加工步驟而簡化製造。 圖8展示半導體晶圓15〇之晶圓級探針測試組態。在 探針測試期間，亦即在單切之前，半導體晶粒152呈晶圓 形式。晶圓級測試確認個別半導體晶粒之連續性、電參數 及功能性。通過晶圓探測之各半導體晶粒152歸類為良裸 晶粒（KGD卜晶圓探測亦可基於測試結果執行修整操作 以調整組件值，例如電阻器修整。晶圓探針測試鑑別的不 良半導體晶粒可在更高層次組裝（例如多 之前自製造製程中移除。 封裝及PCB) 半導體晶圓150在真空廢 畏工歷力下固疋於晶圓操控器170 15 201104768 上。晶圓操控器170提供晶圓在x、乂及z方向上之移動以 達成測試目的。在一實施例中，使用晶圓分類來組織及操 控晶圓以供測試。將多個半導體晶圓150置放於一晶匣上 以供有效處置。 測試探頭172包括PCB，其具有多個自pcB徑向向内 延伸的觸指或觸針174以匹配凸塊墊陣列162之緊密的幾 何形狀觸私1 74典型地由鶴及具有良好電導率及彈性機 械特性之其他金屬製成。觸指174具有2〇_3〇 間距。各 觸指Π4係指向遠端以提供與凸塊墊陣列162上之相關犧 牲凸塊塾164的可菲電連接。測試探頭} 72之包括連 接至觸指174之電跡線，觸指m又連接至電腦測試系統 176。電腦測試系統176產生並接收半導體晶粒之測試 信號以確認其連續性、電參數及電功能性。測試探頭172 可接觸晶圓15G上之-或多個半導體晶粒152。在—實施例 中，測試探帛172接觸一個半導體晶粒152，隨後移動至下 m或者’測試探頭172可接觸所有半導體晶粒152 以測試晶® 150之完整性β電腦測試系统176亦控制晶圓 操控器170之移動。在晶圓分類期間，將晶圓15〇自晶匿 上負載及卸載錢用自動圖案識別進行比對以供測試。 。為進仃曰曰圓分類測試，由電腦測試系统i %操控晶圓 操控器170以使觸指174與犧牲凸塊塾164抵壓嗔合。由 電腦測試系統m產生電測試信號，其經由測試探頭m 及觸才曰174發运至犧牲凸塊墊164。電測試信號亦由導電鍵 路166發送至互連凸塊塾16〇。视所執行之測試而定，半導 16 201104768 體晶粒152在操作溫度範圍内處理電測試信號。測試結果 信號經由互連凸塊墊160、導電鏈路166、犧牲凸塊墊16\、 觸指174及測試探頭172返回電腦測試系統176<1視测試結 果而定，將各半導體晶粒1 52歸類為KGD或鑑別為不良。 若電腦測試系統176偵測到測試故障，則不良半導體晶粒 以墨點標識或記錄於電腦測試系統令以隨後自製造製程中 移除。 觸指174典型地具有尖頭以便使得可靠地電連接至凸 塊墊164。在晶圓探針測試過程中，觸指174已知會穿透表 面且可能損壞凸塊墊。實際上，晶圓探針測試可包括牵引 觸指174橫越凸塊墊164,導致在凸塊墊表面留下擦痕。然 而，由於晶圓探測係在犧牲凸塊墊丨64上進行，因此互連 凸塊墊1 60保持未損壞的最初狀態以供隨後形成凸塊。 在圖9中，犧牲凸塊墊164及導電鏈路166之一部分 視情況藉由濕式蝕刻或乾式蝕刻製程移除。在一實施例 令，在作為形成互連凸塊墊16〇之一部分的蝕刻步驟期間 移除犧牲凸塊墊164及該部分導電鏈路166<>互連凸塊墊 160及導電鏈路166之殘餘戴短部分可供凸塊製程利用。由 於尚未在互連凸塊墊i 6〇上進行晶圓探測，因此該等凸塊 墊處於最初狀態以供形成凸塊。晶圓代工廠可對無凸塊晶 圓執行晶圓分類測試，且出售或以其他方式轉移具有kgd 之，凸塊晶圓的責任。任何第三方凸塊形成服務供應商可 接者在具有由晶圓分類測試鑑別之KGD的無凸塊晶圓上形 成凸塊。 201104768 “導電材料係使用蒸鑛、電解電鑛、&電電鐘、球式滴 落（ball drop)或網版印刷製程沈積於互連凸塊墊16〇上。 導電材料可為A卜Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及 其組合，其視情況含有助熔材料。舉例而言，導電材料可 為共晶Sn/Pb、高&焊料或無紹焊料。^電材料係使用適合 之附著或焊接製程焊接至互連凸塊墊16〇。在一實施例中， 藉由將導電材料加熱至其熔點以上對該材料進行回焊以形 成球形球體或凸塊180。在一些應用中，對凸塊18〇進行二 次回焊以改良與互連凸塊塾16Q《電接觸。亦可將凸塊麼 縮焊接至互連凸塊墊160。凸塊18〇代表—種類型之互連結 構，其可形成於互連凸塊墊丨60上。互連結構亦可使用^ 線、導電膏、柱形凸塊、微凸塊或其他電互連。 圖l〇a-10b說明凸塊18〇形成於互連凸塊墊16〇上之半 導體晶粒152的俯視圖及橫截面圖。導電鏈路166之殘餘 截短部分對凸塊180或互連凸塊墊16〇無電效應。 儘管已詳細說明本發明之一或多個實施例，但熟習此項技 術者應瞭解，可在不違背如以下中請專利範圍中所闡述之本發明範 嘴的情況下對彼等實施例進行修改及改造。 【圖式簡單說明】 圖1說明一具有多個含有凸塊墊之晶粒的習知半導體 晶圓； 圖2為凸塊墊上之習知晶圓探測測試組態； 圖3為焊料凸塊上之習知晶圓探測測試組態； 圖4說明PCB ’其中不同類型之封裝黏著於其表面 18 201104768 圖 5a-5c進一步詳細說明黏著於 體封裝 PCB上之代表性半導 圖6說明-具有多個晶粒的半導體晶圓，該等晶粒含 有經導電鏈路互連之互連凸塊墊與犧牲凸塊墊； 圖以-几進一步詳細說明經導電鏈路互連之互連凸塊 墊與犧牲凸塊墊； 圖8為具有犧牲凸塊墊之半導體晶粒的晶圓探測測試 組態； 圖9說明移除犧牲凸塊塾之後的晶圓；及 圖10a-1 Ob說明移除犧牲凸塊墊之後凸塊形成於互連 凸塊墊上之晶圓。 【主要元件符號說明】 1 〇 :半導體晶圓 12 ： 半導體晶粒 14 ： 凸塊墊 16 ： 晶圓操控器 18 ： 測試探頭 20 : 觸指或觸針 22 ： 電腦測試系統 24 ： 焊料凸塊 50 : 電子裝置 52 ： PCB 54 : 跡線 56 ： 焊線封裝 19 201104768 5 8 :覆晶 60 :球狀栅格陣列 62 :凸塊晶片載體 64 :雙排型封裝 66 :平台柵格陣列 68 :多晶片模組 70 :四邊扁平無引腳封裝 72 :四邊扁平封裝 74 :半導體晶粒 76 :接觸墊 78 :中間載體 80 :導線 82 :焊線 84 :密封劑 88 :半導體晶粒 90 :載體 92 :底膠或環氧樹脂黏合材料 94 :焊線 96 :接觸墊 98 :接觸墊 100 :成型化合物或密封劑 102 :接觸墊 104 :凸塊 106 :載體 20 201104768 108 : 主動區 110: 凸塊 112 ： 凸塊 114 ： 信號線 116: 成型化合物或密封劑 150 ： 半導體晶圓 152 : 半導體晶粒 154 ： 主動表面 160 ： 凸塊墊 162 ： 凸塊墊陣列 164 ： 凸塊墊 166 : 導電鏈路 170 ： 晶圓操控器 172 ： 測試探頭 174 ： 觸指 176 ： 電腦測試糸統 180 ： 球形球體或凸塊 21[S 13 201104768 Wafer 150 may be fabricated from a semiconductor substrate having a diameter in the range of 150-300 millimeters (mm), such as germanium, antimony, gallium arsenide, indium phosphide or tantalum carbide. Each of the semiconductor dies 152 has active and passive devices, conductive layers and dielectric layers formed in the active surface 丨 54 in accordance with the electrical design of the dies. In one embodiment, semiconductor die 152 includes a baseband analog circuit or a digital circuit such as a digital signal processor (DSP), ASIC, memory or other signal processing circuit. Semiconductor die 152 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors. In one embodiment, the semiconductor die 152 is a flip chip type semiconductor device having interconnected bump pads formed on the active surface 154. The bumps are used in PVD, CVD, sputtering, and electrolysis. Patterning and deposition without electro-electric recording or other suitable metal deposition processes. The bump pads 16 can be one or more of Al, Cu, Sn, Ni, Au, Ag or other suitable electrically conductive material layers. Bump pads 160 are disposed within the bump pad array 162 to provide electrical interconnection to the conductive layers within the semiconductor wafer 152 as well as the active and passive circuit components. The bump pad 160 has a small area and a diameter of about 50-500 microns (μηι). A plurality of sacrificial bump pads 164 are formed on the active surface 154. Bumps 164 are patterned and deposited using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The bump pads 64 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The sacrificial bump pads 164 can have an area that is less than or greater than the interconnect bump pads 〇6〇. In general, the sacrificial bump pads 164 are about the diameter of the interconnect bumps 166 or the diameter of the wafer probe test. 7a-7b illustrate a top view of a portion of a semiconductor wafer 150 and a cross-sectional view of a bumper pad array 162 of semiconductor die 丨52. The sacrificial bump pads 64 are spaced apart from the array of interconnect bump pads 6〇. There is one sacrificial bump pad 164 for each interconnect bump pad 160. Each sacrificial bump 164 is positioned adjacent the corresponding interconnect bump pad 16'. In one embodiment, the sacrificial bump pads 1 64 are disposed at a position that is diagonally offset relative to the respective interconnect bump pads 16', such as above a bump pad diameter and to the right, as shown in FIG. The conductive links 166 are formed on the active surface 154 by PVD, cvd, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition process patterning on the interconnect bump pads 16 and sacrificial bump pads 164. between. Conductive link 166 can be one or more layers of Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive link 166 electrically interconnects interconnect bump pads 16A and sacrificial bump pads 164. Sacrificial bump pads 164 and conductive links 166 may be formed simultaneously with interconnect bump pads 160 or during bump formation, thereby avoiding separate processing steps and simplifying fabrication. Figure 8 shows a wafer level probe test configuration for a semiconductor wafer. The semiconductor die 152 is in the form of a wafer during probe testing, i.e., prior to single cut. Wafer level testing confirms the continuity, electrical parameters, and functionality of individual semiconductor dies. Each semiconductor die 152 that is probed by the wafer is classified as a good die (KGD wafer detection can also perform trimming operations based on test results to adjust component values, such as resistor trimming. Wafer probe test identifies poor semiconductors The die can be assembled at a higher level (eg, removed from the manufacturing process before. Packaging and PCB) The semiconductor wafer 150 is fixed on the wafer handler 170 15 201104768 under vacuum waste. The device 170 provides movement of the wafer in the x, 乂, and z directions for testing purposes. In one embodiment, wafer grading is used to organize and manipulate the wafer for testing. A plurality of semiconductor wafers 150 are placed in A wafer is placed for effective disposal. The test probe 172 includes a PCB having a plurality of fingers or styli 174 extending radially inward from the pcB to match the tight geometry of the bump pad array 162. The ground is made of a crane and other metals having good electrical conductivity and elastic mechanical properties. The fingers 174 have a spacing of 2 〇 3 。. Each of the finger Π 4 is directed to the distal end to provide an associated sacrificial convexity with the array of bump pads 162 . Block 塾164 The Philippine electrical connection. The test probe} 72 includes an electrical trace connected to the finger 174, which in turn is coupled to the computer test system 176. The computer test system 176 generates and receives test signals for the semiconductor die to confirm continuity, Electrical parameters and electrical functionality. Test probe 172 can contact - or a plurality of semiconductor dies 152 on wafer 15G. In an embodiment, test probe 172 contacts a semiconductor die 152 and then moves to the next m or ' Test probe 172 can contact all of semiconductor die 152 to test the integrity of Crystal® 150. Computer test system 176 also controls the movement of wafer handler 170. During wafer sorting, wafer 15 is self-embedded and loaded. The unloading money is compared with the automatic pattern recognition for testing. For the rounding classification test, the wafer controller 170 is manipulated by the computer test system i% to press the contact fingers 174 against the sacrificial bumps 164. An electrical test signal is generated by the computer test system m, which is sent to the sacrificial bump pad 164 via the test probe m and the contact 174. The electrical test signal is also sent by the conductive bond 166 to the interconnect bump 塾16. Executed Depending on the test, the semi-conductor 16 201104768 body die 152 processes the electrical test signal over the operating temperature range. The test result signal is via the interconnect bump pad 160, the conductive link 166, the sacrificial bump pad 16\, the contact fingers 174, and the test. The probe 172 returns to the computer test system 176<1 depending on the test result, each semiconductor die 1 52 is classified as KGD or is identified as defective. If the computer test system 176 detects a test failure, the defective semiconductor die is inked. The dot is identified or recorded on the computer test system for subsequent removal from the manufacturing process. The finger 174 typically has a pointed tip to enable reliable electrical connection to the bump pad 164. During wafer probe testing, the fingers 174 are known to penetrate the surface and may damage the bump pads. In effect, the wafer probe test can include pulling the finger 174 across the bump pad 164, resulting in scratches on the surface of the bump pad. However, since the wafer probing is performed on the sacrificial bump pads 64, the interconnect bump pads 160 remain in an undamaged initial state for subsequent bump formation. In Figure 9, one portion of the sacrificial bump pads 164 and conductive links 166 are optionally removed by a wet or dry etch process. In one embodiment, the sacrificial bump pads 164 and the portion of the conductive links 166 are removed during the etch step as part of forming the interconnect bump pads 16 <> interconnect bump pads 160 and conductive links 166 The remaining short portion can be used for the bump process. Since wafer probing has not been performed on the interconnect bump pads 6, the bump pads are in an initial state for forming bumps. Wafer foundries can perform wafer sorting tests on bumpless wafers and sell or otherwise transfer the responsibility of bump wafers with kgd. Any third party bump forming service provider can form bumps on bumpless wafers having KGD identified by wafer classification testing. 201104768 "The conductive material is deposited on the interconnect bump pad 16 using a steamed ore, electrolytic ore, & electric clock, ball drop or screen printing process. The conductive material may be Ab Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, optionally containing a fluxing material. For example, the conductive material may be eutectic Sn/Pb, high & solder or no solder. The material is soldered to the interconnect bump pads 16 using a suitable adhesion or soldering process. In one embodiment, the material is reflowed by heating the conductive material above its melting point to form spherical spheres or bumps 180. In some applications, the bumps 18 are subjected to a second reflow to improve electrical contact with the interconnect bumps 16Q. The bumps may also be soldered to the interconnect bump pads 160. The bumps 18 〇 represent - types An interconnect structure can be formed on the interconnect bump pads 60. The interconnect structure can also be interconnected using wires, conductive paste, stud bumps, microbumps, or other electrical interconnects. 10b illustrates a top view and a cross-sectional view of the semiconductor die 152 formed by bumps 18 on the interconnect bump pads 16A. The residual truncated portion of the conductive link 166 has no electrical effect on the bump 180 or the interconnected bump pad 16. Although one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that Modifications and modifications may be made to the embodiments without departing from the scope of the invention as set forth in the claims below. [Simplified Schematic] FIG. 1 illustrates a die having a plurality of bump pads. Figure 2 is a conventional wafer probing test configuration on a bump pad; Figure 3 is a conventional wafer probing test configuration on a solder bump; Figure 4 illustrates a PCB 'where different types of packages are attached to its surface 18 201104768 Figures 5a-5c further illustrate a representative semi-conductor adhered to a bulk package PCB. Figure 6 illustrates a semiconductor wafer having a plurality of dies having interconnected bump pads interconnected by conductive links. And the sacrificial bump pad; the figure further details the interconnect bump pad and the sacrificial bump pad interconnected by the conductive link; FIG. 8 is a wafer probing test configuration of the semiconductor die with the sacrificial bump pad Figure 9 illustrates removal The wafer after the bump is formed; and FIG. 10a-1 Ob illustrates the wafer on which the bump is formed on the interconnect bump pad after removing the sacrificial bump pad. [Main Component Symbol Description] 1 〇: Semiconductor Wafer 12: Semiconductor die 14 : bump pad 16 : wafer handler 18 : test probe 20 : finger or contact pin 22 : computer test system 24 : solder bump 50 : electronic device 52 : PCB 54 : trace 56 : wire bond Package 19 201104768 5 8 : flip chip 60 : spherical grid array 62 : bump wafer carrier 64 : double row package 66 : platform grid array 68 : multi wafer module 70 : quad flat no lead package 72 : four sides Flat package 74: semiconductor die 76: contact pad 78: intermediate carrier 80: wire 82: bond wire 84: encapsulant 88: semiconductor die 90: carrier 92: primer or epoxy bonding material 94: bonding wire 96: Contact pad 98: contact pad 100: molding compound or sealant 102: contact pad 104: bump 106: carrier 20 201104768 108: active region 110: bump 112: bump 114: signal line 116: molding compound or sealant 150 : Semiconductor Wafer 152: Semiconductor die 154: active surface 160: bump pad 162: bump pad array 164: bump pad 166: conductive link 170: wafer handler 172: test probe 174: contact finger 176: computer test system 180: Spherical sphere or bump 21